JP2004056992A - DC-DC converter - Google Patents

Abstract

An object of the present invention is to provide a highly versatile DC-DC having an excellent response speed by increasing energy efficiency by regenerating energy to an input side in a transient state or a start-up state in which output power rapidly decreases. It is intended to provide a converter.
In a DC-DC converter having a dedicated operation mode (standby operation mode) for reducing power consumption in a light load state such as a standby state, an output upper limit voltage higher by a predetermined voltage than an output target voltage E0. An output power sudden decrease detection circuit that outputs a result of comparison between E1 and the output DC voltage Vo is provided. When the output DC voltage Vo is higher than the output upper limit voltage E1, the standby operation mode is not performed, and the output DC voltage Vo is efficiently output. Is configured to improve the response speed of reaching the output target voltage E0.
[Selection diagram] Fig. 1

Description

【００３１】
実施の形態１のＤＣ−ＤＣコンバータにおいては、検出電圧Ｖｒ２３が基準電圧Ｅｒと等しくなるように制御される。したがって、通常動作状態において、出力直流電圧Ｖｏは次式（２）で表される出力目標電圧Ｅ０に制御される。
【００３２】
【数２】

【００３３】
一方、出力電力急減検出回路１５において比較している、抵抗１２２と抵抗１２３との接続点の電圧と、基準電圧Ｅｒとが等しくなったとき、このときの出力直流電圧Ｖｏである出力上限電圧Ｅ１は次式（３）で表される。
【００３４】
【数３】

【００３５】
次に、基準電圧源１２０の基準電圧Ｅｒが負荷１０等の外部からの信号によって急減した場合の動作について図２及び図３を用いて説明する。図２の（ａ）は基準電圧Ｅｒが急減したときの状態を示す電圧波形である。図２の（ｂ）は、図２の（ａ）のときの出力目標電圧Ｅ０と出力上限電圧Ｅ１と出力直流電圧Ｖｏの関係を示す波形図である。図２の（ｃ）は出力電力負荷急減検出回路１５の比較器１５０から出力される信号Ｖ１５０を示している。図３の（ａ）は基準電圧Ｅｒが急減したときに比較器１５０から出力される電圧波形であり、図３の（ｂ）は比較器１５０から図３の（ａ）に示す信号が出力されたときのインダクタ５に流れる電流波形である。図３の（ｂ）に示す電流波形において、中央部分が連続動作モードであり、その左右部分が不連続動作モードを示している。
【００３６】
実施の形態１のＤＣ−ＤＣコンバータにおいて、負荷１０が同じような軽負荷状態を継続しているとき、軽負荷状態の動作モードである待機動作モードとなっている。この待機動作モードにおいては、軽負荷検出回路１４２が軽負荷状態を検出する。このとき、出力電力急減検出回路１５が出力電力の急減状態を検出しているため、同期スイッチ駆動回路２０は、第２のスイッチ３をオフ状態にする。すなわち、この待機動作モードではＤＣ−ＤＣコンバータは、図３の（ｂ）における左側部分の波形で示す不連続動作モードで動作している。
【００３７】
上記のように待機動作モードでＤＣ−ＤＣコンバータが動作しているとき、例えば負荷１０等からの信号に応じて基準電圧源１２０の基準電圧Ｅｒが下げられると、出力目標電圧Ｅ０及び出力上限電圧Ｅ１も低下する。このとき、出力電力急減検出回路１５の比較器１５０は、検出された電圧が低下した基準電圧Ｅｒより高くなるため“Ｌ”を出力する。この“Ｌ”の信号は、同期スイッチ駆動回路２０に入力される。今、出力電力急減検出回路１５が出力電力の急減状態を検出し、且つ軽負荷検出回路１４２が軽負荷状態を検出しているため、同期スイッチ駆動回路２０は、インバータ１４１の駆動電圧Ｖ１４１をそのまま第２のスイッチ３の駆動電圧Ｖｄ２として出力する。これにより、第２のスイッチ３は第１のスイッチ２と同期してオンオフ動作を行うため、比較器１５０が“Ｌ”の信号を出力している期間、ＤＣ−ＤＣコンバータは待機動作モードで動作せず、連続動作モードで動作する。この連続動作モードは、過渡応答動作モードである。この過渡応答動作モードにおいて電力回生が行われて、出力直流電圧Ｖｏが急激に低下していく。この電力回生動作は、出力直流電圧Ｖｏが出力上限電圧Ｅ１に達して、出力電力急減検出回路１５の比較器１５０が反転するまで継続する。
【００３８】
比較器１５０が反転すると、出力電力急減検出回路１５は出力電力の急減状態を検出しない状態となる。このとき、軽負荷検出回路１４２が軽負荷状態を検出しているため、ＤＣ−ＤＣコンバータは不連続動作モードで動作する。しかし、このとき、誤差電圧Ｖｅが充分に低下していなければ、出力直流電圧Ｖｏは上昇していき比較器１５０がさらに反転し、連続動作モードとなり電力回生を行う。そして、この電力回生動作により、出力直流電圧Ｖｏが低下して比較器１５０がさらに反転して不連続動作モードとなる。このように、連続動作モードと不連続動作モードの動作を繰り返す。その結果、やがて誤差電圧Ｖｅが充分に低下し、出力直流電圧Ｖｏは出力目標電圧Ｅ０に落ち着く。
【００３９】
従来のＤＣ−ＤＣコンバータにおいては、負荷が軽負荷状態の場合、出力目標電圧Ｅ０が急減しても、常に待機動作モードで動作しているため、出力直流電圧Ｖｏが出力目標電圧Ｅ０に達するまで長時間を要していた。
一方、本発明に係る実施の形態１のＤＣ−ＤＣコンバータにおいては、負荷が軽負荷状態の場合、出力目標電圧Ｅ０が急減したとき、待機動作モード（不連続動作モード）で動作せず、過渡応答動作モードで動作して電力回生を行うよう構成されている。したがって、実施の形態１のＤＣ−ＤＣコンバータにおいては、負荷が軽負荷状態において出力目標電圧Ｅ０が急減したときでも、従来の装置に比べて大幅に短縮した応答時間で出力直流電圧を出力目標電圧Ｅ０にすることが可能となる。
【００４０】
なお、実施の形態１においては、同期整流可能な降圧形コンバータを用いて説明したが、本発明のＤＣ−ＤＣコンバータはこのような構成に限定されるものではない。本発明は同期整流可能な降圧型、昇圧型及び昇降圧型の全てのＤＣ−ＤＣコンバータに適用可能である。
また、実施の形態１においては、待機動作モードにおける動作として、不連続動作モードの動作を用いて説明したが、本発明のＤＣ−ＤＣコンバータにおける待機動作モードの動作としてはこれだけに限定されるものではない。ＤＣ−ＤＣコンバータの消費電力を低減する動作を行う待機動作モードの別の動作としては、例えばスイッチング損出等を低減するため、所定の期間、スイッチング動作を停止する期間を設けて間欠的に動作させる間欠動作モード、及びスイッチング周波数を低下させるスイッチング周波数可変動作モードにも本発明の構成が適用可能であることは言うまでもない。
【００４１】
《実施の形態２》
次に、本発明に係る実施の形態２のＤＣ−ＤＣコンバータを添付の図４と図５を用いて説明する。図４は本発明に係る実施の形態２のＤＣ−ＤＣコンバータの構成を示す回路図である。図５は実施の形態２のＤＣ−ＤＣコンバータにおいて、基準電圧Ｅｒが急減したときの各部信号波形を示している。実施の形態２のＤＣ−ＤＣコンバータにおいて、前述の実施の形態１のＤＣ−ＤＣコンバータと実質的に同じ機能、構成を有するものには同じ符号を付しその説明は省略する。
【００４２】
実施の形態２のＤＣ−ＤＣコンバータにおいて、前述の実施の形態１のＤＣ−ＤＣコンバータの構成と異なるところは、誤差増幅回路１２の出力である誤差信号Ｖｅが誤差増幅器１２４の出力に抵抗１２６を介して形成されるよう構成している。また、実施の形態２のＤＣ−ＤＣコンバータには、指示電圧源１７０、抵抗１７１、スイッチ１７２、スイッチ１７３及びインバータ１７４からなる第１の過渡応答動作回路１７が設けられている。
前述の実施の形態１においては、電力回生動作を行うことにより出力直流電圧を低下させるよう構成されている。しかし、出力直流電圧Ｖｏの出力目標電圧Ｅ０への応答速度をさらに向上させるために、実施の形態２のＤＣ−ＤＣコンバータにおいては、誤差電圧Ｖｅを強制的に変更して電力回生動作によって回生される電力を、誤差電圧を強制的に変更しないときの電力回生動作によって回生される電力より大きくしている。
【００４３】
出力目標電圧Ｅ０が負荷等からの指令等により急減した場合、出力直流電圧Ｖｏは出力目標電圧Ｅ０より相対的に急激に高くなる過渡応答状態となる。以下、この過渡応答状態の動作について図５を用いて説明する。
図５は実施の形態２のＤＣ−ＤＣコンバータにおいて、基準電圧Ｅｒが急減したときの各部信号波形を示している。図５において、（ａ）は基準電圧Ｅｒが急減したときの状態を示す電圧波形であり、（ｂ）は（ａ）のときの出力目標電圧Ｅ０と出力上限電圧Ｅ１と出力直流電圧Ｖｏの関係を示す波形図である。図５の（ｃ）は鋸歯状電圧Ｖｔ及び誤差電圧Ｖｅの電圧波形を示している。
【００４４】
出力直流電圧Ｖｏが出力上限電圧Ｅ１より高い期間は、出力電力急減検出回路１５の比較器１５０から出力される駆動電圧Ｖ１５０は“Ｌ”である。このため、スイッチ１７３はオフ状態となる。スイッチ１７３がオフ状態となると、誤差増幅回路１２の出力Ｖ１２は制御回路１４に伝達されない。
また、比較器１５０から出力された駆動電圧Ｖ１５０は、インバータ１７４によって反転されるため、スイッチ１７２をオン状態として、制御回路１４に指示電圧源１７０の指示電圧が抵抗１７１を介して入力される。
【００４５】
抵抗１７１を介して入力された指示電圧Ｖ１７１は、鋸歯状電圧Ｖｔの最小値より少し大きな値となるように設定されている。この動作において、１スイッチング周期において、第１のスイッチ２は僅かな期間だけオン状態、第２のスイッチ３は僅かな期間だけオフ状態となる。この状態は、比較器１５０が反転して、スイッチ１７２がオフ状態、スイッチ１７３がオン状態となるまで継続する。その後は、通常動作モード又は待機動作モードに戻り、やがて出力直流電圧Ｖｏは出力目標電圧Ｅ０に落ち着く。誤差増幅回路１２の抵抗１２６は、第１の過渡応答動作回路１７のスイッチ１７３がオン状態となるとき、位相補償コンデンサ１２５に流れる電流を制限し、検出電圧の変動を抑制する機能を有する。
【００４６】
以上のように、実施の形態２のＤＣ−ＤＣコンバータは、通常動作モードや待機動作モードで動作している場合において、過渡応答状態を検出したとき、出力上限電圧Ｅ１に達するまでは、電力回生動作によって回生される電力が誤差電圧を強制的に変更しない電力回生動作によって回生される電力より大きくなるよう動作する。このため、実施の形態２のＤＣ−ＤＣコンバータは、応答時間を短縮することが可能となる。
なお、実施の形態２のＤＣ−ＤＣコンバータとして、同期整流可能な降圧型コンバータを用いて説明してきたが、本発明のＤＣ−ＤＣコンバータはこの構成に限定されるものではない。本発明は同期整流可能な降圧型、昇圧型及び昇降圧型の全てのＤＣ−ＤＣコンバータにも適用可能である。
【００４７】
《実施の形態３》
次に、本発明に係る実施の形態３のＤＣ−ＤＣコンバータを添付の図６〜図９を用いて説明する。図６は本発明に係る実施の形態３のＤＣ−ＤＣコンバータの構成を示す回路図である。実施の
形態３のＤＣ−ＤＣコンバータにおいて、前述の実施の形態１のＤＣ−ＤＣコンバータと実質的に同じ機能、構成を有するものには同じ符号を付しその説明は省略する。
【００４８】
図６に示すように、実施の形態３のＤＣ−ＤＣコンバータは、入力直流電圧Ｖｉを出力する入力直流電源１を有しており、入力直流電源１の一端には主スイッチである第１のスイッチ２の一端が接続されている。第１のスイッチ２の他端には第２のスイッチ３の一端と、第１のダイオード４のカソードと、インダクタ５の一端が接続されている。第２のスイッチ３の他端と第１のダイオード４のアノードは、入力直流電源１の他端に接続されている。このように接続された第１のスイッチ２及び第２のスイッチ３は、制御部１１からの駆動制御信号によりオンオフ動作が繰り返される。この制御部１１には出力電力が急減した時を検出する出力電力急減検出回路１５が接続されている。
【００４９】
図６に示すように、実施の形態３のＤＣ−ＤＣコンバータには、インダクタ５の一端と接地側とを接続する第３のスイッチ６が設けられており、またインダクタ５の一端と出力コンデンサ９の一端とを接続する第４のスイッチ７が設けられている。この第４のスイッチ７の両端には第２のダイオード８が負荷側へ順方向となるよう並列に接続されている。第３のスイッチ６及び第４のスイッチ７は制御部１１からの駆動制御信号によりオンオフ動作が繰り返される。
また、実施の形態３のＤＣ−ＤＣコンバータには、入出力比較回路１６と第２の過渡応答動作回路１８が設けられている。入出力比較回路１６には入力直流電源１からの入力直流電圧Ｖｉと、出力電力急減検出回路１５に入力される検出信号と同じ検出信号が入力される。第２の過渡応答動作回路１８には出力電力急減検出回路１５からの出力信号と、誤差増幅回路１２からの出力信号が入力されるよう構成されている。
【００５０】
実施の形態３のＤＣ−ＤＣコンバータにおいては、第１のスイッチ２とインダクタ５と第３のスイッチ６が直列に接続されており、第１のスイッチ２と第３のスイッチ６が共にオン状態となると、インダクタ５に入力直流電圧Ｖｉが印加される。また、第２のスイッチ３とインダクタ５と第４のスイッチ７が直列に接続されており、第２のスイッチ３と第４のスイッチ７が共にオン状態となると、インダクタ５の電圧が出力コンデンサ９に印加されるように構成されている。
制御部１１は、誤差増幅回路１２と発振回路１３と制御回路２１４と加算器１４３から構成されている。この制御部１１は、出力直流電圧Ｖｏを制御するため、第１のスイッチ２と第２のスイッチ３と第３のスイッチ６と第４のスイッチ７をそれぞれオンオフ制御する機能を有する。
上記のように構成された実施の形態３のＤＣ−ＤＣコンバータは、昇圧及び降圧コンバータ（昇降圧コンバータ）であり、入力直流電源１の入力直流電圧Ｖｉを所望の直流電圧に形成して出力している。
【００５１】
図７は制御回路２１４の構成を示す回路図である。
図７に示すように、制御回路２１４に入力された誤差電圧Ｖｅは、第２の比較器１４５に入力されており、また加算器１４３を介して第１の比較器１４４に入力されている。加算器１４３は誤差電圧Ｖｅにオフセット電圧Ｖｏｓを加算し、（Ｖｅ＋Ｖｏｓ）の信号を第１の比較器１４４へ出力する。第１の比較器１４４は加算器１４３の出力（Ｖｅ＋Ｖｏｓ）と鋸歯状電圧Ｖｔとを比較する。第２の比較器１４５は誤差電圧Ｖｅと鋸歯状電圧Ｖｔとを比較する。
第１の比較器１４４の出力電圧Ｖｄ１は第１のスイッチ２をオンオフ制御する第１の駆動信号となる。また、第１の比較器１４４の出力は信号を反転させる第１のインバータ１４６を介して第１の同期スイッチ駆動回路４００へ入力される。第１の同期スイッチ駆動回路４００の出力電圧Ｖｄ２が第２のスイッチ３をオンオフ制御する第２の駆動信号となる。
第２の比較器１４５の出力電圧Ｖｄ３は第３のスイッチ６をオンオフ制御する第３の駆動信号となる。また、第２の比較器１４５の出力は信号を反転させる第２のインバータ１４７を介して第２の同期スイッチ駆動回路４０１へ入力される。第２の同期スイッチ駆動回路４０１の出力電圧Ｖｄ４が第４のスイッチ７をオンオフ制御する第４の駆動信号となる。
【００５２】
図７に示すように、第１の軽負荷検出回路１４８には第２のスイッチ３の両端に接続された信号線が入力されており、第２の軽負荷検出回路１４９には第４のスイッチ７の両端に接続された信号線が入力されている。第１の軽負荷検出回路１４８は第２のスイッチ３のオン状態時の抵抗を使用して電流値を検出し、第２の軽負荷検出回路１４９は第４のスイッチ７のオン状態時の抵抗を使用して電流値を検出することにより、これらの電流値に基づいて第１の軽負荷検出回路１４８と第２の軽負荷検出回路１４９は軽負荷状態を検知する。すなわち、オン状態において第２のスイッチ３を流れる電流が予め設定された値を超えた時を、第１の軽負荷検出回路１４８は軽負荷状態と判断する。このとき、出力電力急減検出回路１５が出力電力の急減状態を検出していないため、第１の同期スイッチ駆動回路４００は第２のスイッチ３をオフ状態とする。この動作が待機動作モードの動作の１つである不連続動作モードの動作であり、逆電流を流さないよう制御している。また、第４のスイッチ７を流れる電流が予め設定された値を超えた時を、第２の軽負荷検出回路１４９は軽負荷状態と判断する。このとき、出力電力急減検出回路１５が出力電力の急減状態を検出していないため、第２の同期スイッチ駆動回路４０１は第４のスイッチ７をオフ状態とする。この動作も待機動作モードの動作の１つである不連続動作モードの動作であり、逆電流を流さないよう制御している。
【００５３】
負荷急減検出回路１５は比較器１５０により構成されている。入出力比較回路１６は抵抗１６０、抵抗１６１及び比較器１６２により構成されている。第２の過渡応答動作回路１８は、第１の指示電圧源１８０、抵抗１８１、スイッチ１８２、第２の指示電圧源１８３、抵抗１８４、スイッチ１８５、スイッチ１８６、インバータ１８７及びＮＯＲ回路１８８から構成されている。
【００５４】
次に、以上のように構成された実施の形態３のＤＣ−ＤＣコンバータの動作を説明する。
まず、実施の形態３のＤＣ−ＤＣコンバータにおける重負荷状態の動作モードである通常動作モードについて説明する。
通常動作モードにおいては、制御部１１によって第１のスイッチ２、第２のスイッチ３、第３のスイッチ６及び第４のスイッチ７は、同じスイッチング周期Ｔを有してオンオフ動作を行う。第１のスイッチ２及び第３のスイッチ６の１スイッチング周期におけるオン時間の割合、即ち時比率を、それぞれδ１及びδ２とする。また、第３のスイッチ６がオン状態となる期間は第１のスイッチ２も確実にオン状態となるよう、δ１＞δ２とする。第１のスイッチ２がオン状態のとき第２のスイッチ３はオフ状態となり、第１のスイッチ２がオフ状態のとき第２のスイッチ３はオン状態となる。また、第３のスイッチ６がオン状態のとき第４のスイッチ７はオフ状態となり、第３のスイッチ６がオフ状態のとき第４のスイッチ７はオン状態となる。
【００５５】
まず、第１のスイッチ２と第３のスイッチ６が共にオン状態の時、入力直流電源１の入力直流電圧Ｖｉはインダクタ５に印加される。この期間はδ２・Ｔである。このとき、入力直流電源１からインダクタ５に電流が流れ、インダクタ５に磁気エネルギーが蓄積される。次に、第３のスイッチ６がオフ状態となると、第４のスイッチ７がオン状態となり、インダクタ５には入力直流電圧Ｖｉと出力直流電圧Ｖｏの差Ｖｉ−Ｖｏが印加される。この期間は（δ１−δ２）・Ｔであり、インダクタ５を介して入力直流電源１から出力コンデンサ９へ電流が流れる。最後に、第１のスイッチ２と第３のスイッチ６が共にオフ状態の時、第２のスイッチ３及び第４のスイッチ７が共にオン状態となり、インダクタ５には出力直流電圧Ｖｏが逆方向に印加される。この期間は（１−δ１）・Ｔであり、インダクタ５から出力コンデンサ９へ電流が流れ、蓄積された磁気エネルギーは放出される。
【００５６】
このようにインダクタ５において磁気エネルギーの蓄積と放出の動作が繰り返されることにより、出力コンデンサ９から負荷１０へ電力が供給される。インダクタ５の磁気エネルギーの蓄積と放出が均衡する安定動作状態においては、その電圧時間積の和はゼロであるから、下記式（４）が成り立ち、出力直流電圧Ｖｏは入力直流電圧Ｖｉに対して式（５）という変換特性が得られる。
δ２＝０の場合も同様に、出力直流電圧Ｖｏは式（６）となり、降圧コンバータとして動作する。
また、δ１＝１の場合も同様に、出力直流電圧Ｖｏは式（７）となり、昇圧コンバータとして動作する。また、各スイッチの時比率を制御することにより、δ１／（１−δ２）は０から無限大まで設定可能である。即ち、実施の形態３のＤＣ−ＤＣコンバータは、理論上は任意の入力直流電圧Ｖｉから任意の出力直流電圧Ｖｏを形成することができる昇降圧コンバータとして動作する。
【００５７】
【数４】

【００５８】
【数５】

【００５９】
【数６】

【００６０】
【数７】

【００６１】
誤差増幅回路１２の出力する誤差電圧Ｖｅは、出力直流電圧Ｖｏから検出回路２２による抵抗検出された電圧が、基準電圧源１２０の基準電圧より高くなると低下する。また、抵抗検出された電圧が基準電圧源１２０の基準電圧より低くなると、誤差電圧Ｖｅは上昇する。即ち、入力直流電圧Ｖｉが高くなったり、負荷１０が軽くなって出力直流電圧Ｖｏが上昇しようとすると、誤差電圧Ｖｅは低下する。逆に、入力直流電圧Ｖｉが低くなったり、負荷１０が重くなって出力直流電圧Ｖｏが低下しようとすると誤差電圧Ｖｅは上昇する。
図８は実施の形態３のＤＣ−ＤＣコンバータにおける制御部１１の各部波形図である。図８において、（ａ）は鋸歯状電圧Ｖｔと誤差電圧Ｖｅと加算器１４３の出力電圧（Ｖｅ＋Ｖｏｓ）、（ｂ）は第１の駆動信号Ｖｄ１、（ｃ）は第２の駆動信号Ｖｄ２、（ｄ）は第３の駆動信号Ｖｄ３、（ｅ）は第４の駆動信号Ｖｄ４を示す。図８において、左側部分が、（鋸歯状電圧Ｖｔ）＞（誤差電圧Ｖｅ）の場合であり、中央部分が、鋸歯状電圧Ｖｔと誤差電圧Ｖｅと加算器１４３の出力（Ｖｅ＋Ｖｏｓ）とが交差する場合であり、右側部分が、（鋸歯状電圧Ｖｔ）＜（加算器１４３の出力（Ｖｅ＋Ｖｏｓ））の場合を示す。
【００６２】
次に、実施の形態３のＤＣ−ＤＣコンバータにおける動作を図８を用いて説明する。
まず、入力直流電圧Ｖｉが高く、（鋸歯状電圧Ｖｔ）＞（誤差電圧Ｖｅ）の場合（図８の左側部分）、第２の比較器１４５の出力である第３の駆動信号Ｖｄ３は常時“Ｌ”であり、第３のスイッチ６はオフ状態となる。したがって、第３のスイッチ６の時比率δ２は、δ２＝０である。一方、第１のスイッチ２は、第１の比較器１４４の出力である第１の駆動信号Ｖｄ１によってオンオフ駆動されている。そのときの比率δ１は誤差電圧Ｖｅが低下するほど小さくなる。この場合、ＤＣ−ＤＣコンバータは、その入出力電圧の関係が式（６）で表される降圧コンバータとして動作する。
【００６３】
次に、図８の中央部分に示すように、入力直流電圧Ｖｉが出力直流電圧Ｖｏの近くにあり、鋸歯状電圧Ｖｔと誤差電圧Ｖｅと加算器１４３の出力（Ｖｅ＋Ｖｏｓ）が交差する場合、第１のスイッチ２は第１の比較器１４４の出力である第１の駆動信号Ｖｄ１によってオンオフ駆動され、第３のスイッチ６は第２の比較器１４５の出力である第３の駆動信号Ｖｄ３によってオンオフ駆動される。このとき、時比率δ１及び時比率δ２は誤差電圧Ｖｅが低下するほど小さくなる。この場合、ＤＣ−ＤＣコンバータは、その入出力電圧の関係が式（５）で表される昇降圧コンバータとして動作する。
【００６４】
次に、図８の右側部分に示すように、入力直流電圧Ｖｉが低く、（鋸歯状電圧Ｖｔ）＜（加算器１４３の出力（Ｖｅ＋Ｖｏｓ））の場合（図８の右側部分）、第１の比較器１４４の出力である第１の駆動信号Ｖｄ１は常時“Ｈ”であり、第１のスイッチ２はオン状態となる。したがって、第１のスイッチ２の時比率δ１は、δ１＝１である。一方、第３のスイッチ６は、第２の比較器１４５の出力である第３の駆動信号Ｖｄ３によってオンオフ駆動されている。そのときの比率δ２は誤差電圧Ｖｅが上昇するほど大きくなる。この場合、ＤＣ−ＤＣコンバータは、その入出力電圧の関係が、式（７）で表される昇圧コンバータとして動作する。
以上が本発明の実施の形態３のＤＣ−ＤＣコンバータにおける通常動作モードである。また、抵抗１６０と抵抗１６１の抵抗値をＲ１６０とＲ１６１とすると、比較器１６２は入力直流電圧Ｖｉと出力直流電圧Ｖｏとを比較するので、下記式（８）、（９）の条件を満たす。
【００６５】
【数８】

【００６６】
【数９】

【００６７】
このため、入力直流電圧Ｖｉが出力直流電圧Ｖｏより高いとき、比較器１６２は”Ｈ”を出力する。また、入力直流電圧Ｖｉが出力直流電圧Ｖｏより低いとき、比較器１６２は”Ｌ”を出力する。
【００６８】
次に、実施の形態３のＤＣ−ＤＣコンバータにおける過渡応答時の動作モード（過渡応答動作モード）について図９を用いて説明する。
図９は実施の形態３のＤＣ−ＤＣコンバータにおいて、基準電圧Ｅｒが急減したときの各部信号波形を示している。図９において、（ａ）は基準電圧Ｅｒが急減したときの状態を示す電圧波形であり、（ｂ）は（ａ）のときの出力目標電圧Ｅ０と出力上限電圧Ｅ１と入力直流電圧Ｖｉと出力直流電圧Ｖｏの関係を示す波形図である。図９の（ｃ）は鋸歯状電圧Ｖｔ、誤差電圧Ｖｅ及び加算器１４３の出力（Ｖｅ＋Ｖｏｓ）を示している。
出力直流電圧Ｖｏが出力上限電圧Ｅ１より高い期間は、比較器１５０の駆動電圧Ｖ１５０は“Ｌ”である。また、出力直流電圧Ｖｏより入力直流電圧Ｖｉの方が低いため、比較器１６２の駆動電圧Ｖ１６２は“Ｌ”になる。
【００６９】
比較器１５０の駆動電圧Ｖ１５０と比較器１６２の駆動電圧Ｖ１６２が入力されたＮＯＲ回路１８８は“Ｈ”となり、スイッチ１８２とスイッチ１８５はオン状態となる。ＮＯＲ回路１８８の駆動電圧Ｖ１８８は、インバータ１８７によって反転されるため、スイッチ１８６はオフ状態となる。
スイッチ１８６がオフ状態となると、誤差増幅回路１２の出力Ｖ１２が制御回路２１４に伝達されない状態となる。また、スイッチ１８５がオン状態となると、制御回路２１４に第２の指示電圧源１８３の電圧が抵抗１８４を介して入力される（指示電圧Ｖ１８４）。さらに、スイッチ１８２がオン状態となると、第１の指示電圧源１８０の電圧が抵抗１８１を介して加算器１４３に入力される（指示電圧Ｖ１８１）。加算器１４３の出力は“Ｖ１８４＋Ｖｏｓ＋Ｖ１８１”となる。ここで、指示電圧Ｖ１８４の電圧値は鋸歯状電圧Ｖｔの最小値より少し大きな値となるように設定し、指示電圧Ｖ１８１の電圧値は電圧（Ｖ１８４＋Ｖｏｓ＋Ｖ１８１）が鋸歯状電圧Ｖｔの最大値より大きくなるよう設定する。
【００７０】
上記の動作においては、１スイッチング周期において第１のスイッチ２は常にオン状態であり、第２のスイッチ３は常にオフ状態であり、第３のスイッチ６は僅かな期間だけオン状態であり、第４のスイッチ７は僅かな期間だけオフ状態となる。δ１＝１、δ２は小さな時比率で制御する昇圧形コンバータとして動作する。この状態は、比較器１５０が反転し、スイッチ１８６がオン状態となるまで継続する。その後は通常動作モードまたは待機動作モードに戻り、やがて出力直流電圧Ｖｏは出力目標電圧Ｅ０に落ち着く。抵抗１２６は、スイッチ１８６がオン状態となるときに、位相補償コンデンサ１２５に流れる電流を制限し、検出電圧の変動を抑制する。
【００７１】
以上のように、実施の形態３のＤＣ−ＤＣコンバータは、出力直流電圧Ｖｏが入力直流電圧Ｖｉより高い場合において、出力上限電圧Ｅ１に達するまでは、電力回生動作による電力が誤差電圧を強制的に変更しない電力回生動作による電力より大きくなる動作を継続する。このため、実施の形態３のＤＣ−ＤＣコンバータは、応答時間を短縮することができる。
なお、実施の形態３においては、昇降圧可能なＤＣ−ＤＣコンバータとして４石式の昇降圧コンバータを用いて説明してきたが、本発明のＤＣ−ＤＣコンバータはこのような構成に限定されるものではない。昇降圧可能なＤＣ−ＤＣコンバータとしては、他に図１９に回路図を示すＳＥＰＩＣや図２０に回路図を示すＺｅｔａコンバータが知られている。また、本発明は昇圧コンバータと降圧コンバータとを直列あるいは並列に組み合わせることによっても構成することが可能であり、本発明はこれら全て同期整流可能な昇降圧型のＤＣ−ＤＣコンバータに適用可能である。
さらに、実施の形態３のＤＣ−ＤＣコンバータにおいては、昇降圧動作時には４つのスイッチを駆動制御するが、昇圧動作時には２つのスイッチのみの駆動制御でよいため、スイッチング損失が大幅に減少し高効率なＤＣ−ＤＣコンバータとなる。
【００７２】
《実施の形態４》
次に、本発明に係る実施の形態４のＤＣ−ＤＣコンバータを添付の図１０、図１１を用いて説明する。図１０は本発明に係る実施の形態４のＤＣ−ＤＣコンバータの構成を示す回路図である。実施の形態４のＤＣ−ＤＣコンバータにおいて、前述の実施の形態３のＤＣ−ＤＣコンバータと実質的に同じ機能、構成を有するものには同じ符号を付しその説明は省略する。
実施の形態４のＤＣ−ＤＣコンバータにおいて、図６に示した実施の形態３のＤＣ−ＤＣコンバータの構成と異なるところは、回生スイッチ２１０、抵抗２１１及びＮＯＲ回路２１２からなる高速応答回路２１が設けられていることと、第２の過渡応答動作回路１８が削除されている点である。
【００７３】
上記のように構成された実施の形態４のＤＣ−ＤＣコンバータの過渡応答時の動作モード（過渡応答動作モード）について図１１及び図１２を用いて説明する。図１１において、（ａ）は基準電圧Ｅｒが急減したときの状態を示す電圧波形であり、（ｂ）は（ａ）のときの出力目標電圧Ｅ０と出力上限電圧Ｅ１と入力直流電圧Ｖｉと出力直流電圧Ｖｏの関係を示す波形図である。図１１の（ｃ）は高速応答回路２１における電圧波形（Ｖ２１２）を示している。
図１１の（ａ）の基準電圧Ｅｒの電圧波形は、負荷１０からの指令等によって急激に基準電圧Ｅｒが低下した状態を示している。このときの低下後の基準電圧Ｅｒによる出力上限電圧Ｅ１は、入力直流電圧Ｖｉより高いものとする。基準電圧Ｅｒの変化に伴い、出力目標電圧Ｅ０及び出力上限電圧Ｅ１も変化するが、誤差増幅回路１２の誤差増幅器１２４は即座に応答せず誤差電圧Ｖｅ及び誤差電圧Ｖｅにオフセット電圧Ｖｏｓを加算した電圧（Ｖｅ＋Ｖｏｓ）は緩やかに低下していく。なお、この電圧（Ｖｅ＋Ｖｏｓ）は、加算器１４３において形成され、第１の比較器１４４へ出力されている。
【００７４】
図１１に示した状態において、出力電力急減検出回路１５の比較器１５０は、検出された電圧が基準電圧Ｅｒより高いため”Ｌ”を高速応答回路２１へ出力する。また、入出力比較回路１６の比較器１６２は、入力直流電圧Ｖｉより出力直流電圧Ｖｏの方が高いため、”Ｌ”を高速応答回路２１のＮＯＲ回路２１２へ出力する。したがって、ＮＯＲ回路２１２から出力される回生スイッチ２１０のための駆動信号Ｖ２１２は”Ｈ”となり、回生スイッチ２１０はオン状態となる。この結果、出力コンデンサ９から入力直流電源１へ高速応答回路２１を介して急速に電力回生動作が行われる。回生スイッチ２１０のオン状態は、出力直流電圧Ｖｏが出力上限電圧Ｅ１に達して、比較器１５０が反転するまで継続する。
比較器１５０が反転して回生スイッチ２１０がオフ状態となった後において、誤差電圧Ｖｅが充分に低下していなければ出力直流電圧Ｖｏは上昇し、再び回生スイッチ２１０がオン状態となる。そして、出力直流電圧Ｖｏが低下して再び回生スイッチ２１０がオフ状態となる。このように、回生スイッチ２１０がオンオフ動作を繰り返すことにより、やがて誤差電圧Ｖｅが充分に上昇し、出力直流電圧Ｖｏは出力目標電圧Ｅ０に落ち着く。
【００７５】
図１２は、基準電圧Ｅｒがさらに大きく低下して、基準電圧Ｅｒの低下後の出力上限電圧Ｅ１が入力直流電圧Ｖｉより低いときの状態を示す波形図である。図１２の（ａ）は基準電圧Ｅｒが大きく急減したときの状態を示す電圧波形であり、図１２の（ｂ）は（ａ）のときの出力目標電圧Ｅ０と出力上限電圧Ｅ１と入力直流電圧Ｖｉと出力直流電圧Ｖｏの関係を示す波形図であり、図１２の（ｃ）は高速応答回路２１における電圧波形（Ｖ２１２）を示している。
基準電圧Ｅｒの変化に伴い、出力目標電圧Ｅ０と出力上限電圧Ｅ１も変化するが、誤差増幅器１２４は即座に応答せず誤差電圧Ｖｅ及び誤差電圧Ｖｅにオフセット電圧Ｖｏｓを加算した電圧（Ｖｅ＋Ｖｏｓ）は緩やかに低下していく。
【００７６】
図１２に示した状態において、出力電力急減検出回路１５の比較器１５０は、検出された電圧が基準電圧Ｅｒより高いため”Ｌ”を高速応答回路２１へ出力する。また、入出力比較回路１６の比較器１６２は、入力直流電圧Ｖｉより出力直流電圧Ｖｏの方が高いため、”Ｌ”を高速応答回路２１のＮＯＲ回路２１２へ出力する。したがって、ＮＯＲ回路２１２から出力される回生スイッチ２１０ための駆動信号Ｖ２１２は”Ｈ”となり、回生スイッチ２１０はオン状態となる。この結果、出力コンデンサ９から入力直流電源１へ高速応答回路２１を介して急速に電力回生動作が行われる。回生スイッチ２１０のオン状態は、出力直流電圧Ｖｏが入力直流電圧Ｖｉに達して比較器１５０が反転するまで継続する。
比較器１５０が反転して回生スイッチ２１０のオフ状態となった後において、誤差電圧Ｖｅが充分に低下していなければ出力直流電圧Ｖｏは上昇し、再び回生スイッチ２１０がオン状態となる。そして、出力直流電圧Ｖｏが低下して再び回生スイッチ２１０がオフ状態となる。このように、回生スイッチ２１０がオンオフ動作を繰り返すことにより、やがて誤差電圧Ｖｅが充分に上昇し、出力直流電圧Ｖｏは出力目標電圧Ｅ０に落ち着く。
【００７７】
なお、実施の形態４において、出力上限電圧Ｅ１は出力直流電圧Ｖｏの許容上限値以上で出力目標電圧Ｅ０に近い値に設定するとよい。また、抵抗値Ｒ１６１は回生スイッチ２１０と抵抗２１１での電圧降下を考慮して設定するとよい。
従来のＤＣ−ＤＣコンバータにおいては、誤差増幅器の応答速度で決まる誤差電圧Ｖｅの緩やかな変化に従って出力直流電圧Ｖｏが変化しており、出力直流電圧Ｖｏが出力目標電圧Ｅ０に達するまでの応答速度が非常に遅いものであった。しかし、実施の形態４のＤＣ−ＤＣコンバータは、回生スイッチ２１０を有する高速応答回路２１を設けて急速な電力回生動作を行うことにより、応答時間を大幅に短縮することができる。また、回生スイッチ２１０は、出力直流電圧Ｖｏが出力上限電圧Ｅ１と入力直流電圧Ｖｉの高い方に達するまでがオン状態であり、その後は通常の応答動作に復帰するため、出力直流電圧Ｖｏにはアンダーシュートが発生することがない。
【００７８】
なお、実施の形態４のＤＣ−ＤＣコンバータにおける高速応答回路２１の抵抗２１１は、回生スイッチ２１０による入力直流電源１から出力コンデンサ９への急速な電力回生動作中の回生電流を制限するためのものである。しかし、この抵抗２１１は回生スイッチ２１０自体のオン状態時のインピーダンスで代用することも可能である。また、実施の形態４においては、昇降圧可能なＤＣ−ＤＣコンバータとして４石式の昇降圧コンバータを用いて説明してきたが、本発明のＤＣ−ＤＣコンバータはこのような構成に限定されるものではない。昇降圧可能なＤＣ−ＤＣコンバータとしては、他に図１９に回路図を示すＳＥＰＩＣや図２０に回路図を示すＺｅｔａコンバータが知られている。また、本発明は昇圧コンバータと降圧コンバータとを直列あるいは並列に組み合わせることによっても構成することが可能である。本発明はこれら昇降圧型のＤＣ−ＤＣコンバータにも適用可能である。なお、実施の形態４のＤＣ−ＤＣコンバータは昇降圧型のＤＣ−ＤＣコンバータについて説明したが、実施の形態４の構成は昇圧型のＤＣ−ＤＣコンバータにも適用できる。
【００７９】
《実施の形態５》
次に、本発明に係る実施の形態５のＤＣ−ＤＣコンバータを添付の図１３及び図１４を用いて説明する。図１３は本発明に係る実施の形態５のＤＣ−ＤＣコンバータの構成を示す回路図である。実施の形態５のＤＣ−ＤＣコンバータにおいて、前述の実施の形態１のＤＣ−ＤＣコンバータと実質的に同じ機能、構成を有するものには同じ符号を付しその説明は省略する。
【００８０】
実施の形態５のＤＣ−ＤＣコンバータにおいて、図１に示した実施の形態１のＤＣ−ＤＣコンバータの構成と異なるところは、出力電力急減検出回路（１５）が削除されており、負荷１０等の外部装置から出力電力の急減を知らせる外部信号１９が入力されるよう構成されている点である。実施の形態１においては、出力電力急減検出回路（１５）を用いて出力電力の急減状態を検出する構成であったが、実施の形態５のＤＣ−ＤＣコンバータでは、出力電力の急減を知らせる外部装置からの外部信号１９が制御部１１に入力されて、制御部１１の軽負荷検出回路１４２及び同期スイッチ駆動回路２０において前述の実施の形態１と同じ動作が実施される。したがって、実施の形態５のＤＣ−ＤＣコンバータによれば、回路構成の簡素化が実現可能となる。
【００８１】
また、前述の実施の形態１のように出力電力急減検出回路（１５）を用いることにより、軽負荷の場合、誤差電圧Ｖｅが充分に低下して、出力直流電圧Ｖｏが出力目標電圧Ｅ０に落ち着くまで、連続動作モード（電力回生動作）と不連続動作モードの動作を繰り返すよう構成されているため、出力直流電圧Ｖｏが出力目標電圧Ｅ０に落ち着くまで多少の時間を要した。実施の形態５のＤＣ−ＤＣコンバータにおいては、出力電力の急減を知らせる外部信号１９を用いているため、誤差電圧Ｖｅが充分に低下し、出力直流電圧Ｖｏが出力目標電圧Ｅ０に落ち着くまで、電力回生動作を行うように外部信号１９の入力を継続すれば、応答時間を短縮することが可能となる。
【００８２】
次に、実施の形態５のＤＣ−ＤＣコンバータにおける過渡応答時の動作モード（過渡応答動作モード）について図１４を用いて説明する。図１４の（ａ）は基準電圧Ｅｒが急減したときの状態を示す電圧波形であり、図１４の（ｂ）は（ａ）のときの出力目標電圧Ｅ０と出力直流電圧Ｖｏの関係を示す波形図であり、図１４の（ｃ）は外部信号１９の電圧波形（Ｖ１９）を示している。
まず、負荷１０が常に軽負荷状態であるときについて説明する。
基準電圧Ｅｒが低下する前においても、軽負荷状態であるため、外部信号１９から出力電力の急減状態を知らせる信号が入力されず、且つ軽負荷検出回路１４２が軽負荷状態を検出しているので、同期スイッチ駆動回路２０は第２のスイッチ３をオフ状態にする。このときのＤＣ−ＤＣコンバータは待機動作モードの１つである不連続動作モードで動作している。このとき、すなわち基準電圧Ｅｒが低下する前までの軽負荷状態のとき、外部信号１９は“Ｈ”を出力している。
そして、基準電圧Ｅｒが急減すると、出力目標電圧Ｅ０が低下し、外部信号１９は“Ｌ”となり、出力電力急減を知らせる信号が入力され、且つ軽負荷検出回路１４２は軽負荷を検出している。この結果、同期スイッチ駆動回路２０はインバータ１４１の駆動電圧Ｖ１４１をそのまま第２のスイッチ３の駆動電圧Ｖｄ２として入力する。このように外部信号１９の”Ｌ”が入力されている期間には待機時モードである不連続動作モードとはならず、連続動作モードで動作する。したがって、この期間は電力回生を行うため出力直流電圧Ｖｏが急激に低下する。この電力回生動作は外部信号１９が“Ｈ”になるまで継続する。
【００８３】
以上のように、実施の形態５のＤＣ−ＤＣコンバータにおいては、出力電力の急減を知らせる外部信号１９が入力されるよう構成されているため、誤差電圧Ｖｅが充分に低下し、出力直流電圧Ｖｏが出力目標電圧Ｅ０に落ち着くまで、電力回生動作を行うように外部信号１９の入力を継続するよう構成することにより、応答時間をさらに短縮することが可能となる。
なお、実施の形態５のＤＣ−ＤＣコンバータにおいては、誤差電圧Ｖｅが充分に低下し、出力直流電圧Ｖｏが出力目標電圧Ｅ０に落ち着くまで、外部信号を“Ｌ”に設定するとよい。
また、実施の形態５においては、同期整流可能な降圧形コンバータを用いて説明したが、本発明のＤＣ−ＤＣコンバータはこのような構成に限定されるものではない。本発明は同期整流可能な降圧型、昇圧型及び昇降圧型の全てのＤＣ−ＤＣコンバータに適用可能である。
【００８４】
《実施の形態６》
次に、本発明に係る実施の形態６のＤＣ−ＤＣコンバータを添付の図１５及び図１６を用いて説明する。図１５は本発明に係る実施の形態６のＤＣ−ＤＣコンバータの構成を示す回路図である。前述の実施の形態１のＤＣ−ＤＣコンバータでは、電圧を検出して出力直流電圧を制御する電圧モードと呼ばれる制御方法を本発明に適用した例を用いて説明した。実施の形態６のＤＣ−ＤＣコンバータにおいては、電流を検出して出力直流電圧を制御する電流モードと呼ばれる制御方法を本発明に適用したものである。実施の形態６において、前述の実施の形態１のＤＣ−ＤＣコンバータと実質的に同じ機能、構成を有するものには、同じ符号を付し、その説明は省略する。実施の形態６のＤＣ−ＤＣコンバータにおいて、図１に示した実施の形態１と異なる点は、誤差増幅回路７２と制御回路９１の構成である。
【００８５】
実施の形態６のＤＣ−ＤＣコンバータにおいて、誤差増幅回路７２は、基準電圧源７２０、３つの抵抗７２１，７２２，７２３、誤差増幅器７２４、及び抵抗７２５とコンデンサ７２６との直列回路からなる積分回路を具備している。
誤差増幅回路７２において、出力直流電圧Ｖｏは３つの抵抗７２１，７２２，７２３とにより分圧されて検出される。このうち、抵抗７２１と抵抗７２２との接続点の電圧が誤差増幅器７２４によって基準電圧源７２０の基準電圧Ｅｒと比較される。誤差増幅器７２４は誤差電圧Ｖｅを出力する。誤差増幅器７２４の出力端子には抵抗７２５とコンデンサ７２６との直列回路からなる積分回路が接続され、高周波利得を低減している。抵抗７２１と抵抗７２２との接続点における電圧の分圧比をαとすると、誤差増幅器７２４の反転入力端子に入力される第１の検出電圧は、α・Ｖｏで表される。誤差電圧Ｖｅは、第１の検出電圧α・Ｖｏが基準電圧Ｅｒより大きくなろうとすると低下し、逆に検出電圧α・Ｖｏが基準電圧Ｅｒより小さくなろうとすると上昇する。第１の検出電圧α・Ｖｏと基準電圧Ｅｒが等しい場合、出力直流電圧Ｖｏが所望の電圧値となる。この所望の電圧値である出力目標電圧Ｅ０は下記の式（１０）で表される。
【００８６】
【数１０】

【００８７】
また、抵抗７２２と抵抗７２３との接続点における電圧の分圧比をβとすると、第２の検出電圧はβ・Ｖｏで表される。第２の検出電圧β・Ｖｏは、比較器１５０によって、基準電圧源７２０の基準電圧Ｅｒと比較される。第２の検出電圧β・Ｖｏが基準電圧Ｅｒに等しい場合の出力直流電圧を出力上限電圧Ｅ１とすると、出力上限電圧Ｅ１は下記の式（１１）で表される。出力上限電圧Ｅ１は所望の電圧値である出力目標電圧Ｅ０より大きくなる。
【００８８】
【数１１】

【００８９】
比較器１５０の出力は制御回路９１の同期スイッチ駆動回路９１５に入力される。この同期スイッチ駆動回路９１５の構成は前述の実施の形態１のＤＣ−ＤＣコンバータにおける同期スイッチ駆動回路２０の構成と同様である。
制御回路９１は、電流検出回路９１０、パルス発振回路９１１、比較器９１２、フリップフロップ回路９１３、インバータ９１４、同期スイッチ駆動回路９１５、軽負荷検出回路９１６から構成される。電流検出回路９１０は第１のスイッチ２に流れる電流（以下、スイッチ電流と称する）を検出し、このスイッチ電流に比例した電流検出信号Ｖｓｉを出力する。パルス発振回路９１１はスイッチング周波数ｆのセットパルスを出力する。比較器９１２は誤差増幅回路７２の出力である誤差電圧Ｖｅと電流検出回路９１０からの電流検出信号Ｖｓｉが入力される。比較器９１２は電流検出信号Ｖｓｉが誤差電圧Ｖｅより高くなると、リセットパルスをフリップフロップ回路９１３へ出力する。フリップフロップ回路９１３は、パルス発振回路９１１からのセットパルスが入力されるとハイレベルとなり、比較器９１２からの出力パルスが入力されるとローレベルとなる駆動信号Ｖ９１３を出力する。
【００９０】
図１６に制御回路９１における各部の電圧波形を示す。図１６に示すように、誤差電圧Ｖｅが低くなると、スイッチ電流のピーク値を低減させるため、駆動信号Ｖ９１３のパルス幅が小さくなる。即ち、時比率δが小さくなり、負荷１０への電力供給が抑えられる。逆に、誤差電圧Ｖｅが高くなると、スイッチ電流のピーク値を上昇させるため、駆動信号Ｖ９１３のパルス幅が大きくなる。即ち、時比率δが大きくなり、負荷１０への電力供給が大きくなる。
【００９１】
以上のように、実施の形態６のＤＣ−ＤＣコンバータにおいて、誤差増幅回路７２は、出力直流電圧Ｖｏと出力目標電圧Ｅ０との偏差を増幅した誤差電圧Ｖｅを出力する。実施の形態６のＤＣ−ＤＣコンバータにおいて、誤差電圧Ｖｅを利用して、第１のスイッチ２に流れる電流（スイッチ電流）のピーク値を調整することにより、出力直流電圧Ｖｏは出力目標電圧Ｅ０になるよう制御される。
【００９２】
待機動作モードでＤＣ−ＤＣコンバータが動作しているとき、例えば負荷１０等からの信号に応じて基準電圧源７２０の基準電圧Ｅｒが下げられると、出力目標電圧Ｅ０及び出力上限電圧Ｅ１も低下する。このとき、出力電力急減検出回路１５の比較器１５０は、検出された電圧が低下した基準電圧Ｅｒより高くなるため“Ｌ”を出力する。この“Ｌ”の信号は、同期スイッチ駆動回路９１５に入力される。このとき、出力電力急減検出回路１５が出力電力の急減状態を検出し、且つ軽負荷検出回路９１６が軽負荷状態を検出しているため、同期スイッチ駆動回路９１５はインバータ９１４の駆動電圧Ｖ９１４をそのまま第２のスイッチ３の駆動電圧Ｖｄ２として出力する。これにより、第２のスイッチ３は第１のスイッチ２と同期してオンオフ動作を行うため、比較器１５０が“Ｌ”の信号を出力している期間、ＤＣ−ＤＣコンバータは待機動作モードで動作せず、連続動作モードで動作する。この連続動作モードは、過渡応答動作モードである。
【００９３】
この過渡応答動作モードにおいて電力回生が行われて、出力直流電圧Ｖｏが急激に低下していく。この電力回生動作は、出力直流電圧Ｖｏが出力上限電圧Ｅ１に達して、出力電力急減検出回路１５の比較器１５０が反転するまで継続する。比較器１５０が反転すると、出力電力急減検出回路１５は出力電力の急減状態を検出しない状態となる。このとき、軽負荷検出回路９１６が軽負荷状態を検出しているため、ＤＣ−ＤＣコンバータは不連続動作モードで動作する。しかし、このとき、誤差電圧Ｖｅが充分に低下していなければ出力直流電圧Ｖｏは上昇していく。そして、比較器１５０がさらに反転し、連続動作モードとなり電力回生を行う。この電力回生動作により、出力直流電圧Ｖｏが低下して比較器１５０がさらに反転して不連続動作モードとなる。このように、連続動作モードと不連続動作モードの動作を繰り返して、やがて誤差電圧Ｖｅが充分に低下し、出力直流電圧Ｖｏは出力目標電圧Ｅ０に落ち着く。
【００９４】
前述の実施の形態１においては電圧モードで制御するＤＣ−ＤＣコンバータについて説明したが、実施の形態６においては電流モードで制御するＤＣ−ＤＣコンバータについて説明した。実施の形態６における動作説明から明らかなように、電流モードの制御方法は本発明のＤＣ−ＤＣコンバータに適用可能であり、電圧モードの制御方法と同様の優れた効果を奏する。
実施の形態１から６において説明したように、本発明は出力直流電圧を急減させる場合における応答時間を短縮させるという効果を有する。さらに、本発明は出力目標電圧Ｅ０に対して出力直流電圧Ｖｏが高い場合、その出力直流電圧Ｖｏを入力側へ電力を回生させることにより、出力直流電圧Ｖｏの安定性を高めることができるという効果を有する。このため、本発明のＤＣ−ＤＣコンバータは、出力条件の急変等に伴うオーバーシュートの抑制に有効である。例えば、ＤＣ−ＤＣコンバータの起動時、特に軽負荷時の起動時において、入力直流電圧が印加されて、ＤＣ−ＤＣコンバータが動作を開始するとき、出力直流電圧Ｖｏと基準電圧Ｅｒとの差が大きくなる。この結果、誤差電圧Ｖｅは大きくなり、スイッチ電流のピーク値も大きくなり、出力直流電圧Ｖｏは急激に上昇する。従来のＤＣ−ＤＣコンバータにおいては、出力直流電圧Ｖｏが出力目標電圧Ｅ０に達した後、供給電力を抑制しようとする動作回路の遅延時間の間に、出力直流電圧にオーバーシュートが発生する。特に、軽負荷時の場合、このオーバーシュートが大きくなる。また、出力目標電圧Ｅ０への安定性は負荷に依存するため、出力直流電圧Ｖｏが出力目標電圧Ｅ０に応答するのに時間がかかる。本発明のＤＣ−ＤＣコンバータにおいては、出力直流電圧Ｖｏが出力目標電圧Ｅ０より大きくなり、出力上限電圧を超えたとき、第２のスイッチ３をオンオフ動作させて、電力を回生させるよう構成されている。本発明のＤＣ−ＤＣコンバータは、このように構成されているため出力直流電圧Ｖｏを急減させることができるので、出力目標電圧Ｅ０への応答時間を短縮することができる。
【００９５】
また、実施の形態６においては、同期整流可能な降圧型コンバータを用いて説明したが、本発明のＤＣ−ＤＣコンバータはこのような構成に限定されるものではない。本発明は同期整流可能な降圧型、昇圧型及び昇降圧型の全てのＤＣ−ＤＣコンバータに適用可能である。
また、実施の形態１〜６のＤＣ−ＤＣコンバータにおける制御は、起動時においても適応可能であり、起動時における出力目標電圧Ｅ０への応答時間を短縮することができる。
また、前述の実施の形態１〜６で説明したＤＣ−ＤＣコンバータは、それぞれを組み合わせて各機能を有するよう構成することが可能である。
さらに、前述の実施の形態１〜６で説明したＤＣ−ＤＣコンバータにおける制御部等の各構成部は、それぞれ独立したユニットとして個別に構成して、他の実施の形態に使用することも可能である。
【００９６】
【発明の効果】
以上、実施の形態において詳細に説明したところから明らかなように、本発明のＤＣ−ＤＣコンバータは以下の効果を有する。
本発明のＤＣ−ＤＣコンバータは、出力直流電圧の制御目標となる出力目標電圧に対して所定の電圧だけ高い出力上限電圧を設定し、出力上限電圧と出力直流電圧との比較結果を出力する出力電力急減検出回路を設けることにより、軽負荷状態において出力直流電圧が出力上限電圧より高い場合、待機動作モードを解除して、電力回生動作を行う過渡応答動作モードを実行するよう構成されている。これにより、本発明は、何らかの条件変化によって出力直流電圧が出力目標電圧より高くなっても、負荷の状況に依らず、出力直流電圧が出力目標電圧に効率良く到達する応答速度を大幅に向上させることができるという効果を有する。
【００９７】
また、本発明のＤＣ−ＤＣコンバータは、出力直流電圧の制御目標となる出力目標電圧に対して所定の電圧だけ高い出力上限電圧を設定し、出力上限電圧と出力直流電圧との比較結果を出力する出力電力急減検出ための比較回路を設け、出力直流電圧が出力上限電圧より高い場合、出力直流電圧を低下させるように誤差電圧を強制的に変更して、電力回生動作によって回生される電力がより大きくなる過渡応答動作モードで動作するよう構成されている。このため、本発明のＤＣ−ＤＣコンバータは、応答時間を短縮することができるという優れた効果を奏する。
【００９８】
さらに、本発明のＤＣ−ＤＣコンバータは、出力直流電圧の制御目標となる出力目標電圧に対して所定の電圧だけ高い出力上限電圧を設定し、出力上限電圧と出力直流電圧との比較結果を出力する出力電力急減検出比較回路を設け、出力直流電圧が出力上限電圧より高く、入力直流電圧より出力直流電圧の方が高い場合、出力直流電圧が低下するように誤差電圧及びオフセット電圧を強制的に変更している。このため、本発明のＤＣ−ＤＣコンバータは、電力回生動作によって回生される電力がより大きくなる過渡応答動作モードで動作するため、応答時間を短縮することができる。また、本発明においては、昇降圧可能なＤＣ−ＤＣコンバータを過渡応答動作モードで昇圧動作させることによって、スイッチング損失が減少して高効率となるという効果を奏する。
【００９９】
また、本発明のＤＣ−ＤＣコンバータは、入出力間に回生スイッチを有する高速応答回路を設けて、出力直流電圧が出力上限電圧より高く、出力直流電圧が入力直流電圧より高い場合、回生スイッチをオン状態とすることにより、電力回生動作できないＤＣ−ＤＣコンバータでも適用が可能となり、何らかの条件変化によって出力直流電圧が出力目標電圧より高くなっても、負荷の状況に依らず、出力直流電圧が出力目標電圧に到達する応答速度を大幅に向上させることができる。また、同期整流可能なＤＣ−ＤＣコンバータに高速応答回路を有する本発明のＤＣ−ＤＣコンバータの構成を適用することによって、さらに応答時間を短縮することが可能となる。
【０１００】
また、本発明のＤＣ−ＤＣコンバータは、出力電力の急減を知らせる外部信号が入力されるよう構成されているため、外部信号が入力される期間中においては常に電力回生動作を行うよう構成することにより、応答時間を大幅に短縮することができ、且つ回路の簡素化を達成することができる。
また、本発明は電圧モードで制御するＤＣ−ＤＣコンバータ及び電流モードで制御するＤＣ−ＤＣコンバータに適用可能であり、いずれのモードを適用しても本発明は出力直流電圧を急減させる場合における応答時間を短縮させるという優れた効果を有する。
また、本発明のＤＣ−ＤＣコンバータは、起動時においても適応可能であり、起動時における出力目標電圧への応答時間を短縮することができる。
発明をある程度の詳細さをもって好適な形態について説明したが、この好適形態の現開示内容は構成の細部において変化してしかるべきものであり、各要素の組合せや順序の変化は請求された発明の範囲及び思想を逸脱することなく実現し得るものである。
【図面の簡単な説明】
【図１】本発明に係る実施の形態１のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図２】実施の形態１のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図３】実施の形態１のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図４】本発明に係る実施の形態２のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図５】実施の形態２のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図６】本発明に係る実施の形態３のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図７】実施の形態３のＤＣ−ＤＣコンバータにおける制御部の構成を示す回路図である。
【図８】実施の形態３のＤＣ−ＤＣコンバータにおける制御部の動作を示す波形図である。
【図９】実施の形態３のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図１０】本発明に係る実施の形態４のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図１１】実施の形態４のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図１２】実施の形態４のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図１３】本発明に係る実施の形態５のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図１４】実施の形態５のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図１５】本発明に係る実施の形態６のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図１６】実施の形態６のＤＣ−ＤＣコンバータにおける各部動作を示す波形図である。
【図１７】従来のＤＣ−ＤＣコンバータの構成を示す回路図である。
【図１８】従来のＤＣ−ＤＣコンバータの制御部における各部動作を示す波形図である。
【図１９】昇降圧可能なＤＣ−ＤＣコンバータであるＳＥＰＩＣを示す回路図である。
【図２０】昇降圧可能なＤＣ−ＤＣコンバータであるＺｅｔａコンバータを示す回路図である。
【符号の説明】
１　直流入力電源
２　第１のスイッチ
３　第２のスイッチ
４　整流ダイオード
５　インダクタ
６　第３のスイッチ
７　第４のスイッチ
８　第２のダイオード
９　出力コンデンサ
１０　負荷
１１　制御部
１２　誤差増幅回路
１３　発振回路
１４　制御回路
１５　出力電力急減検出回路
１６　入出力比較回路
１７　第１の過渡応答動作回路
１８　第２の過渡応答動作回路
１９　外部信号
２０　同期スイッチ駆動回路
２１　高速応答回路
２２　検出回路
２３　スイッチ制御回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DC-DC converter that is used in various electronic devices and that receives a DC voltage from a battery or the like and supplies a controlled DC voltage to a load. In particular, the present invention relates to a DC-DC converter capable of rapidly responding to a rapid decrease in output power (output voltage and / or output current).
[0002]
[Prior art]
In a DC-DC converter that receives a DC voltage from a battery or the like as an input DC power supply and controls the DC voltage to step down and supply the load to a load, an operation mode is set according to a load state (light load state or heavy load state). Some are configured to switch. Here, the operation mode in the light load state is, for example, an operation mode when the electronic device is in a standby operation state, and the operation mode in the heavy load state is, for example, an operation mode when the electronic device is in a normal operation state. The reason why the operation mode is switched in accordance with the state of the load is to reduce the power consumption of the DC-DC converter when the load is light such as during standby. A DC-DC converter having such a configuration is disclosed in Japanese Patent Application Laid-Open No. 11-146637.
[0003]
FIG. 17 is a circuit diagram showing a configuration of a conventional DC-DC converter disclosed in Japanese Patent Application Laid-Open No. 11-146637. As shown in FIG. 17, the DC-DC converter to which the input DC power supply 301 for outputting the DC voltage Vi is connected includes an input-side smoothing capacitor 302, a synchronous rectifier circuit 310, and an output-side smoothing capacitor 307. A load 308 is connected to an output terminal of the DC-DC converter.
The synchronous rectifier circuit 310 of the DC-DC converter includes a main switch 303, a synchronous switch 304, a commutation diode 305, an inductor 306, and a control unit 309 that performs on / off control of the main switch 303 and the synchronous switch 304. When the control unit 309 switches the main switch 303 and the synchronous switch 304 in synchronization, the DC-DC converter outputs a predetermined DC voltage to an output terminal connected to the load 308. This DC-DC converter operates in a light load state (standby operation mode) or in a heavy load state (normal operation) depending on the state of the load 308 (light load state or heavy load state) connected to the output terminal. Mode).
[0004]
In the conventional DC-DC converter shown in FIG. 17, a DC voltage Vi of an input DC power supply 301 is input to a synchronous rectifier circuit 310 via an input-side smoothing capacitor 302, and a voltage Vo of an output-side smoothing capacitor 307 is output. The DC voltage is supplied to the load 308. The control unit 309 controls the synchronous switch 304 to be off when the main switch 303 is on, and to control the synchronous switch 304 to be on when the main switch 303 is off.
The DC voltage Vi of the input DC power supply 301 is applied to the inductor 306 when the main switch 303 is on. At this time, current flows from the input DC power supply 301 to the load side via the inductor 306, and magnetic energy is accumulated in the inductor 306. Next, when the main switch 303 is turned off, the synchronous switch 304 is turned on to conduct, a current flows from the inductor 306 to the output-side smoothing capacitor 307 via the synchronous switch 304, and the accumulated magnetic energy is released. You.
[0005]
As described above, in the synchronous rectifier circuit 310, power is supplied from the output-side smoothing capacitor 307 to the load 308 by repeating the operation of storing and releasing magnetic energy.
In the control unit 309 of the conventional DC-DC converter shown in FIG. 17, the output DC voltage Vo can be set from zero to the input voltage Vi by controlling the duty ratio which is the on / off time of the main switch 303 and the synchronous switch 304. It is.
[0006]
Next, an operation of controlling the duty ratio of the main switch 303 and the synchronous switch 304 in the conventional DC-DC converter configured as described above will be described.
FIG. 18 is a voltage waveform diagram at each part in the conventional DC-DC converter. In FIG. 18, Vt is a voltage waveform showing a reference triangular waveform that rises linearly and drops sharply, and is formed by an oscillation circuit in the control unit 309. Ve is an error voltage output from the error amplifier provided in the control unit 309, and indicates a difference between the output voltage Vo and the reference voltage Vref. The first drive signal Vd1 in FIG. 18 is a signal for driving the main switch 303 on and off, and the second drive signal Vd2 is a signal for driving the synchronous switch 304 on and off. When the main switch 303 and the synchronous switch 304 are turned on / off by the first drive signal Vd1 and the second drive signal Vd2, the output DC voltage to be controlled becomes a desired DC voltage. The first drive signal Vd1 and the second drive signal Vd2 are formed by comparing the reference triangular wave voltage Vt and the error voltage Ve in the error amplifier of the control unit 309.
[0007]
The error voltage Ve shown in FIG. 18 decreases when the load 308 is lightened and the output DC voltage Vo tries to increase, and conversely, increases when the load 308 is heavy and the output DC voltage Vo tries to decrease. is there.
The control unit 309 is provided with a reverse current prevention circuit that detects a light load state by detecting a current value flowing when the synchronous switch 304 is on. When the current flowing through the synchronous switch 304 exceeds a preset value, the reverse current prevention circuit determines that the load is light and sets the synchronous switch 304 to the off state.
[0008]
[Patent Document 1]
JP-A-11-146637
[0009]
[Problems to be solved by the invention]
As described above, the conventional DC-DC converter is configured so that the output DC voltage can be appropriately set and changed according to the state of the load. In a DC-DC converter, for example, when a reference voltage of the DC-DC converter is changed by a signal from a load side in order to change an output DC voltage with respect to a DC-DC converter as a DC voltage source. In this case, it is desirable that the output DC voltage promptly reacts with the change of the reference voltage to become a desired DC voltage.
In the conventional DC-DC converter configured as described above, the response speed depends on the change speed of the error signal Ve output from the error amplifier. On the other hand, in order to ensure the stability of the control system in the DC-DC converter, the cutoff frequency of the error amplifier is set to about one-tenth of the switching frequency set to several tens to several hundreds kHz by a phase compensation capacitor or the like. It is general. For this reason, the response time of the conventional DC-DC converter requires several hundred microseconds with respect to the stepped reference voltage, and it is difficult to secure a satisfactory response speed with respect to a load request. Met. In a DC-DC converter having a standby operation mode, even when it is desired to reduce the output DC voltage by changing the reference voltage, the DC-DC converter operates in the standby operation mode in a light load state. For this reason, such a DC-DC converter has a problem that the time for which the output DC voltage drops is dependent on the time for discharging from the output-side smoothing capacitor to the load, and the response time is further delayed.
The present invention provides an excellent response speed by increasing energy efficiency by regenerating energy to an input side in a transient state or a start-up state in which output power is rapidly reduced due to a request for reduction of an output DC voltage from a load or the like. It is an object of the present invention to provide a highly versatile DC-DC converter having:
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a DC-DC converter of the present invention includes an input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A switch control circuit that adjusts an on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and controls driving of the main switch circuit.
A light load detection circuit for detecting that the load is in a light load state,
An output power rapid decrease detection circuit for detecting a rapid decrease in output power,
A DC-DC converter comprising: a synchronous switch drive circuit to which an output of the switch control circuit, an output of the light load detection circuit, and an output of the output power rapid detection circuit are input,
The synchronous switch drive circuit,
(1) the synchronous switch circuit is turned off when the light load detection circuit detects a light load state and the output power sudden decrease detection circuit does not detect the output power rapid decrease state;
(2) the synchronous switch circuit according to the output from the switch control circuit when the light load detection circuit detects a light load state and the output power sudden decrease detection circuit detects a rapid output power decrease state; Is turned on and off, and
(3) when the light load detection circuit does not detect a light load state and the output power rapid decrease detection circuit does not detect a rapid output power decrease state, the synchronous switch circuit is turned on / off according to an output from the switch control circuit; Operating state,
(4) when the light load detection circuit does not detect a light load state and the output power rapid decrease detection circuit detects a rapid output power decrease state, the synchronous switch circuit is turned on / off in response to an output from the switch control circuit; Set to the operating state. The DC-DC converter configured as described above is configured to perform a power regenerating operation when recognizing a sudden decrease in output power. Irrespective of the situation described above, the response speed to reach the output target voltage is greatly improved.
[0011]
In addition, a DC-DC converter according to another aspect of the present invention includes an input DC power supply that supplies an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage to output an error voltage, and adjusts an on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and A control circuit for driving and controlling the switch circuit;
An output power drop detection circuit for detecting a sudden output power drop state;
And a first transient response operation circuit for forcibly changing the error voltage so as to reduce the output power when the output power rapid decrease detection circuit detects a rapid decrease state of the output power. The DC-DC converter configured as described above has a response speed at which the output DC voltage reaches the output target voltage regardless of the load condition, even if the output DC voltage becomes higher than the output target voltage due to some condition change. Can be greatly improved.
[0012]
Further, in the above DC-DC converter, the control circuit has an offset voltage source that outputs an offset voltage,
A transient response operation circuit that forcibly changes the offset voltage so as to reduce the output power when the output power rapid decrease detection circuit detects a rapid decrease state of the output power. Is also good. The DC-DC converter configured as described above has a response speed at which the output DC voltage reaches the output target voltage regardless of the load condition, even if the output DC voltage becomes higher than the output target voltage due to some condition change. Can be greatly improved.
[0013]
In addition, a DC-DC converter according to another aspect of the present invention includes an input DC power supply that supplies an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit for rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage and a reference voltage to output an error voltage, a control circuit that adjusts an on / off period of the main switch circuit based on the error voltage, and controls driving of the main switch circuit;
An output power rapid decrease detection circuit for detecting a rapid decrease in output power,
An input / output comparison circuit for comparing the input DC voltage with the output DC voltage,
A regenerative switch circuit connected in parallel between the input and output of the DC-DC converter, wherein the output DC voltage is higher than the input DC voltage, and the output power rapid decrease detection circuit detects a rapid decrease in output power; A high-speed response circuit that turns on the regenerative switch circuit when responding. The DC-DC converter configured as described above has a response speed at which the output DC voltage reaches the output target voltage regardless of the load condition, even if the output DC voltage becomes higher than the output target voltage due to some condition change. Can be greatly improved.
[0014]
Further, a DC-DC converter according to another aspect of the present invention includes an input DC power supply that supplies an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage and a reference voltage to output an error voltage, and adjusts an on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and controls driving of the main switch circuit. Switch control circuit,
A light load detection circuit for detecting that the load is in a light load state,
A DC-DC converter comprising: an output of the switch control circuit, an output of the light load detection circuit, and a synchronous switch driving circuit to which a signal indicating whether the output power is in a rapidly decreasing state is input,
(1) detecting that the light load detection circuit is in a light load state, and turning off the synchronous switch circuit when the output power is not in a rapidly decreasing state;
(2) detecting that the light load detection circuit is in a light load state, and setting the synchronous switch circuit to an on / off operation state according to an output from the switch control circuit when the output power is in a rapidly decreasing state;
(3) when the light load detection circuit does not detect a light load state and the output power is not in a rapidly decreasing state, the synchronous switch circuit is turned on / off in response to an output from the switch control circuit;
(4) When the light load detection circuit does not detect a light load state and the output power is in a rapidly decreasing state, the synchronous switch circuit is turned on and off according to an output from the switch control circuit. Since the DC-DC converter configured as described above is configured to receive an external signal indicating a sudden decrease in output power, the DC-DC converter is configured to always perform a power regeneration operation during a period in which the external signal is input. By doing so, the response time can be significantly reduced, and the circuit can be simplified.
[0015]
In addition, a DC-DC converter according to another aspect of the present invention includes an input DC power supply that supplies an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A control circuit that adjusts the on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and drives the main switch circuit and the synchronous switch circuit,
And a first transient response operation circuit for forcibly changing the error voltage so as to reduce the output power when a signal indicating a sudden decrease in output power is input from the load side. Since the DC-DC converter configured as described above is configured to receive an external signal indicating a sudden decrease in output power, the DC-DC converter is configured to always perform a power regeneration operation during a period in which the external signal is input. By doing so, the response time can be significantly reduced, and the circuit can be simplified.
[0016]
Further, in the above DC-DC converter, the control circuit has an offset voltage source that outputs an offset voltage,
A second transient response operation circuit for forcibly changing the offset voltage so as to reduce the output power at the time of a transient response in which a signal indicating a rapidly decreasing state of the output power is input from the load side is further provided. You may. Since the DC-DC converter configured as described above is configured to receive an external signal indicating a sudden decrease in output power, the DC-DC converter is configured to always perform a power regeneration operation during a period in which the external signal is input. By doing so, the response time can be significantly reduced, and the circuit can be simplified.
[0017]
In addition, a DC-DC converter according to another aspect of the present invention includes an input DC power supply that supplies an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit for rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A control circuit that adjusts an on / off period of the main switch circuit based on the error voltage, and controls driving of the main switch circuit.
An input / output comparison circuit for comparing the input DC voltage with the output DC voltage,
A regenerative switch circuit connected in parallel between the input and output of the DC-DC converter, wherein the output DC voltage is higher than the input DC voltage, and a signal indicating a rapid decrease in output power is input from the load side. A high-speed response circuit that turns on the regenerative switch circuit when responding. Since the DC-DC converter configured as described above is configured to receive an external signal indicating a sudden decrease in output power, the DC-DC converter is configured to always perform a power regeneration operation during a period in which the external signal is input. By doing so, the response time can be significantly reduced, and the circuit can be simplified.
While the novel features of the invention are the same as those particularly set forth in the appended claims, the invention, both as to its structure and content, together with other objects and features, will be understood by reading the following detailed description, when taken in conjunction with the drawings. Will be better understood and appreciated.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of a DC-DC converter according to the present invention will be described with reference to FIGS. Note that the embodiments described below are preferred specific examples of the present invention, and therefore, various technically preferable limitations are added. However, the scope of the present invention particularly limits the present invention in the following description. The embodiment is not limited to these embodiments unless otherwise described.
[0019]
<< Embodiment 1 >>
FIG. 1 is a circuit diagram showing a configuration of a DC-DC converter according to Embodiment 1 of the present invention. As shown in FIG. 1, an input DC power supply 1 that outputs an input DC voltage Vi is connected to the DC-DC converter according to the first embodiment, and one end of the input DC power supply 1 has a first switch circuit that is a main switch circuit. One end of one switch 2 is connected. The other end of the first switch 2 is connected to one end of a second switch 3 which is a synchronous switch circuit, the cathode of a first diode 4, and one end of an inductor 5. The other end of the second switch 3 and the anode of the first diode 4 are connected to the other end of the input DC power supply 1. The first switch 2 and the second switch 3 connected in this way are repeatedly turned on and off by a control signal from the control unit 11 described later. The control unit 11 is connected to an output power rapid detection circuit 15 for detecting when the output power is rapidly reduced.
[0020]
As shown in FIG. 1, the inductor 5 and the output capacitor 9 are connected in series to form a series circuit, and this series circuit is connected to both ends of the first diode 4 to form a smoothing circuit. This smoothing circuit forms a DC voltage by averaging a rectangular wave voltage generated at both ends of the first diode 4.
A load 10 is connected to the output terminals at both ends of the output capacitor 9 on the output side in the DC-DC converter configured as described above. In the first embodiment, a rectifying / smoothing circuit is configured by the second switch 3, the first diode 4, and the output capacitor 9.
The control unit 11 includes an error amplification circuit 12, an oscillation circuit 13, and a control circuit 14. The control unit 11 controls on / off of the first switch 2 and the second switch 3 to control the output DC voltage Vo output from the DC-DC converter. The control circuit 14 has a synchronous switch drive circuit 20, a switch control circuit 23, and a light load detection circuit 142.
[0021]
The error amplification circuit 12 includes a reference voltage source 120, a detection circuit 22 for detecting the output DC voltage Vo, an error amplifier 124 to which the reference voltage Er of the reference voltage source 120 and the detection voltage from the detection circuit 22 are input, and an error amplifier 124. , And a phase compensation capacitor 125 connected between the input and output. The voltage Er of the reference voltage source 120 is changed by a command from the load 10. The detection circuit 22 is configured by a series circuit of three resistors of a resistor 121, a resistor 122, and a resistor 123. The voltage at the connection point between the resistors 121 and 122 and the reference voltage Er are input to the error amplifier 124. The error amplifier circuit 12 configured as described above outputs the error voltage Ve output from the error amplifier 124 to the control circuit 14.
[0022]
The output power drop detection circuit 15 includes a comparator 150 which receives and compares the voltage at the connection point between the resistors 122 and 123 with the reference voltage Er. The voltage at the connection point of the resistors 121 and 122 and the reference voltage Er are input to the error amplifier 124 of the error amplifier circuit 12, and the case where these voltages are equal is the output target voltage E0. When the voltage at the node between the resistor 122 and the resistor 123 input to the comparator 150 is equal to the reference voltage Er, the output upper limit voltage E1 is higher than the output target voltage E0 by a predetermined voltage. Here, when the output DC voltage Vo becomes higher than the output upper limit voltage E1, the output power is rapidly reduced. The output power sudden decrease state is detected by the comparator 150, and the output power rapid decrease detection circuit 15 outputs a signal indicating the output power rapid decrease state to the synchronous switch drive circuit 20.
[0023]
The oscillation circuit 13 forms a sawtooth voltage Vt, which is a reference triangular wave voltage that repeatedly increases and decreases at a predetermined cycle, and outputs the sawtooth voltage Vt to the control circuit 14. The sawtooth voltage Vt is a triangular waveform having a period of T and an amplitude of ΔVt, and rises linearly and drops sharply.
The switch control circuit 23 of the control circuit 14 includes a comparator 140 for comparing the error voltage Ve and the sawtooth voltage Vt, and an inverter 141 for inverting a signal from the comparator 140. Further, the light load detection circuit 142 of the control circuit 14 detects the value of the current flowing through the second switch 3 in the ON state, and outputs the detection result to the synchronous switch drive circuit 20. The synchronous switch drive circuit 20 operates based on the detection result of the output power sudden decrease detection circuit 15 and the detection result of the light load detection circuit 142. That is, the synchronous switch drive circuit 20 operates as follows.
[0024]
When the signal indicating the light load state is input from the light load detection circuit 142 and the signal indicating the rapid decrease state of the output power is not input from the output power rapid decrease detection circuit 15, the synchronous switch drive circuit 20 A certain second switch 3 is turned off. Further, the synchronous switch drive circuit 20 switches (2) when a signal indicating a light load state is input from the light load detection circuit 142 and a signal indicating a rapid decrease state of the output power is input from the output power rapid decrease detection circuit 15. The second switch 3 is turned on and off according to the output from the control circuit 23. The synchronous switch drive circuit 20 switches (3) when the signal indicating the light load state is not input from the light load detection circuit 142 and the signal indicating the rapid decrease state of the output power is not input from the output power rapid decrease detection circuit 15. The second switch 3 is turned on and off according to the output from the control circuit 23. Further, (4) when the signal indicating the light load state is not input from the light load detection circuit 142 and the signal indicating the rapid decrease state of the output power is input from the output power rapid detection circuit 15 The second switch 3 is turned on and off according to the output from the switch control circuit 23.
[0025]
As shown in FIG. 1, the output voltage Vd1 of the comparator 140 becomes a first drive signal for driving the first switch 2 on and off, and the output voltage Vd2 of the synchronous switch drive circuit 20 drives the second switch 3 on and off. This becomes the second drive signal. Further, the light load detection circuit 142 of the control circuit 14 detects the light load state by detecting the value of the current flowing through the second switch 3 in the ON state using the resistance of the second switch 3 in the ON state. Deciding. That is, the light load detection circuit 142 determines the light load state when the current flowing through the second switch 3 exceeds the preset value by using the resistance of the second switch 3 when the second switch 3 is on. At this time, when the output power rapid decrease detection circuit 15 does not detect the output power rapid decrease state, the synchronous switch drive circuit 20 turns off the second switch 3. This operation is a discontinuous operation mode operation which is an operation in the standby operation mode in the first embodiment. In this standby operation mode, control is performed so that a reverse current does not flow in a light load state.
[0026]
As described above, when the output DC voltage Vo is higher than the output upper limit voltage E1, the DC-DC converter of the present invention performs a power regeneration operation (hereinafter, such a high-speed response operation mode in a transient response is referred to as a transient response operation). Mode), the output DC voltage Vo is reduced to the output target voltage E0.
[0027]
Next, the operation of the DC-DC converter according to the first embodiment configured as described above will be described.
First, a normal operation mode which is an operation mode in a heavy load state in the DC-DC converter of the first embodiment will be described.
In the normal operation mode, the first switch 2 and the second switch 3 are turned on / off by the control unit 11 with the same switching cycle T. In this on / off operation, the second switch 3 is turned off when the first switch 2 is on, and the second switch 3 is turned on when the first switch 2 is off.
[0028]
The input DC voltage Vi of the input DC power supply 1 is applied to the inductor 5 when the first switch 2 is on. At this time, a current flows from the input DC power supply 1 to the load side via the inductor 5, and magnetic energy is accumulated in the inductor 5. Next, when the first switch 2 is turned off, the second switch 3 is turned on. When the second switch 3 is turned on, a current flows from the inductor 5 to the output capacitor 9 via the second switch 3, and the magnetic energy stored in the inductor 5 is released.
As described above, the operation of storing and releasing magnetic energy in the inductor 5 is repeated, so that power is supplied from the output capacitor 9 to the load 10.
As described above, the control section 11 of the DC-DC converter controls the duty ratio, which is the on / off time of the first switch 2 and the second switch 3, to reduce the output DC voltage Vo from zero to the input voltage Vi. Can be set.
[0029]
The above is the normal operation mode in the DC-DC converter according to Embodiment 1 of the present invention. Assuming that the resistance values of the resistance 121, the resistance 122, and the resistance 123 of the detection circuit 22 in the error amplification circuit 12 are R121, R122, and R123, respectively, the detection voltage Vr23 input to the error amplifier 124 is expressed by the following equation (1). You. Vo is an output DC voltage.
[0030]
(Equation 1)

[0031]
In the DC-DC converter of the first embodiment, control is performed such that detection voltage Vr23 becomes equal to reference voltage Er. Therefore, in the normal operation state, the output DC voltage Vo is controlled to the output target voltage E0 represented by the following equation (2).
[0032]
(Equation 2)

[0033]
On the other hand, when the voltage at the connection point between the resistor 122 and the resistor 123 and the reference voltage Er, which are compared in the output power sudden decrease detection circuit 15, become equal to each other, the output upper limit voltage E1 which is the output DC voltage Vo at this time. Is represented by the following equation (3).
[0034]
[Equation 3]

[0035]
Next, the operation when the reference voltage Er of the reference voltage source 120 is rapidly reduced by an external signal such as the load 10 will be described with reference to FIGS. FIG. 2A is a voltage waveform showing a state when the reference voltage Er is rapidly reduced. FIG. 2B is a waveform diagram showing the relationship between the output target voltage E0, the output upper limit voltage E1, and the output DC voltage Vo in the case of FIG. 2A. FIG. 2C shows a signal V150 output from the comparator 150 of the output power load sudden decrease detection circuit 15. FIG. 3A shows a voltage waveform output from the comparator 150 when the reference voltage Er sharply decreases. FIG. 3B shows a signal output from the comparator 150 as shown in FIG. 4 shows a waveform of a current flowing through the inductor 5 when the current flows. In the current waveform shown in FIG. 3B, the central portion is the continuous operation mode, and the left and right portions indicate the discontinuous operation mode.
[0036]
In the DC-DC converter of the first embodiment, when the load 10 keeps the same light load state, it is in the standby operation mode, which is the operation mode in the light load state. In the standby operation mode, the light load detection circuit 142 detects a light load state. At this time, since the output power rapid decrease detection circuit 15 detects the rapid decrease state of the output power, the synchronous switch drive circuit 20 turns off the second switch 3. That is, in this standby operation mode, the DC-DC converter operates in the discontinuous operation mode shown by the waveform on the left side in FIG.
[0037]
When the DC-DC converter is operating in the standby operation mode as described above, for example, if the reference voltage Er of the reference voltage source 120 is reduced according to a signal from the load 10 or the like, the output target voltage E0 and the output upper limit voltage E1 also decreases. At this time, the comparator 150 of the output power drop detection circuit 15 outputs “L” because the detected voltage becomes higher than the lowered reference voltage Er. This “L” signal is input to the synchronous switch drive circuit 20. Now, since the output power sudden decrease detection circuit 15 detects the rapid decrease state of the output power and the light load detection circuit 142 detects the light load state, the synchronous switch drive circuit 20 uses the drive voltage V141 of the inverter 141 as it is. It outputs as the drive voltage Vd2 of the second switch 3. As a result, the second switch 3 performs an on / off operation in synchronization with the first switch 2, so that the DC-DC converter operates in the standby operation mode while the comparator 150 is outputting the “L” signal. Instead, it operates in continuous operation mode. This continuous operation mode is a transient response operation mode. In this transient response operation mode, power regeneration is performed, and the output DC voltage Vo sharply decreases. This power regeneration operation is continued until the output DC voltage Vo reaches the output upper limit voltage E1 and the comparator 150 of the output power sudden decrease detection circuit 15 is inverted.
[0038]
When the comparator 150 is inverted, the output power rapid decrease detection circuit 15 does not detect the output power rapid decrease state. At this time, since the light load detection circuit 142 detects the light load state, the DC-DC converter operates in the discontinuous operation mode. However, at this time, if the error voltage Ve is not sufficiently reduced, the output DC voltage Vo is increased, the comparator 150 is further inverted, and a continuous operation mode is set to perform power regeneration. Then, due to this power regeneration operation, the output DC voltage Vo decreases, and the comparator 150 is further inverted to enter the discontinuous operation mode. As described above, the operations in the continuous operation mode and the discontinuous operation mode are repeated. As a result, the error voltage Ve decreases sufficiently, and the output DC voltage Vo settles to the output target voltage E0.
[0039]
In the conventional DC-DC converter, when the load is in a light load state, the output DC voltage Vo reaches the output target voltage E0 because the converter always operates in the standby operation mode even if the output target voltage E0 suddenly decreases. It took a long time.
On the other hand, in the DC-DC converter according to Embodiment 1 of the present invention, when the load is in a light load state, when the output target voltage E0 sharply decreases, the DC-DC converter does not operate in the standby operation mode (discontinuous operation mode), It is configured to operate in the response operation mode to perform power regeneration. Therefore, in the DC-DC converter according to the first embodiment, even when the output target voltage E0 sharply decreases in a light load state, the output DC voltage is output with the response time greatly shortened compared to the conventional device. E0 can be set.
[0040]
Although the first embodiment has been described using the step-down converter capable of synchronous rectification, the DC-DC converter of the present invention is not limited to such a configuration. The present invention is applicable to all step-down, step-up and step-up / step-down DC-DC converters capable of synchronous rectification.
In the first embodiment, the operation in the standby operation mode is described using the operation in the discontinuous operation mode. However, the operation in the standby operation mode in the DC-DC converter of the present invention is not limited to this. is not. As another operation in the standby operation mode in which the operation of reducing the power consumption of the DC-DC converter is performed, for example, in order to reduce switching loss and the like, a predetermined period and a period in which the switching operation is stopped are provided to operate intermittently. Needless to say, the configuration of the present invention is also applicable to an intermittent operation mode in which the switching frequency is reduced and a switching frequency variable operation mode in which the switching frequency is reduced.
[0041]
<< Embodiment 2 >>
Next, a DC-DC converter according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a circuit diagram showing a configuration of the DC-DC converter according to Embodiment 2 of the present invention. FIG. 5 shows signal waveforms at various points in the DC-DC converter according to the second embodiment when the reference voltage Er sharply decreases. In the DC-DC converter according to the second embodiment, those having substantially the same functions and configurations as those of the DC-DC converter according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0042]
The difference between the DC-DC converter according to the second embodiment and the DC-DC converter according to the first embodiment is that the error signal Ve output from the error amplifier circuit 12 includes a resistor 126 connected to the output of the error amplifier 124. It is constituted so that it may be formed through. The DC-DC converter according to the second embodiment is provided with a first transient response operation circuit 17 including an instruction voltage source 170, a resistor 171, a switch 172, a switch 173, and an inverter 174.
In the first embodiment, the output DC voltage is reduced by performing the power regeneration operation. However, in order to further improve the response speed of output DC voltage Vo to output target voltage E0, in the DC-DC converter of the second embodiment, error voltage Ve is forcibly changed to regenerate by the power regeneration operation. The power regenerated by the power regenerating operation when the error voltage is not forcibly changed is made larger.
[0043]
When the output target voltage E0 is rapidly reduced by a command from a load or the like, the output DC voltage Vo is in a transient response state in which the output DC voltage Vo becomes relatively sharply higher than the output target voltage E0. Hereinafter, the operation in the transient response state will be described with reference to FIG.
FIG. 5 shows signal waveforms at various points in the DC-DC converter according to the second embodiment when the reference voltage Er sharply decreases. In FIG. 5, (a) is a voltage waveform showing a state when the reference voltage Er sharply decreases, and (b) is a relationship between the output target voltage E0, the output upper limit voltage E1, and the output DC voltage Vo in (a). FIG. FIG. 5C shows a voltage waveform of the sawtooth voltage Vt and the error voltage Ve.
[0044]
During a period when the output DC voltage Vo is higher than the output upper limit voltage E1, the drive voltage V150 output from the comparator 150 of the output power sudden decrease detection circuit 15 is "L". Therefore, the switch 173 is turned off. When the switch 173 is turned off, the output V12 of the error amplifier circuit 12 is not transmitted to the control circuit 14.
In addition, since the drive voltage V150 output from the comparator 150 is inverted by the inverter 174, the switch 172 is turned on, and the instruction voltage of the instruction voltage source 170 is input to the control circuit 14 via the resistor 171.
[0045]
The instruction voltage V171 input via the resistor 171 is set to a value slightly larger than the minimum value of the sawtooth voltage Vt. In this operation, in one switching cycle, the first switch 2 is turned on for a short period, and the second switch 3 is turned off for a short period. This state is maintained until the comparator 150 is inverted, the switch 172 is turned off, and the switch 173 is turned on. Thereafter, the mode returns to the normal operation mode or the standby operation mode, and the output DC voltage Vo eventually settles to the output target voltage E0. When the switch 173 of the first transient response operation circuit 17 is turned on, the resistor 126 of the error amplifying circuit 12 has a function of limiting the current flowing through the phase compensation capacitor 125 and suppressing the fluctuation of the detection voltage.
[0046]
As described above, when the DC-DC converter according to the second embodiment operates in the normal operation mode or the standby operation mode, when the transient response state is detected, the power regeneration is performed until the output upper limit voltage E1 is reached. The operation is performed such that the power regenerated by the operation becomes larger than the power regenerated by the power regeneration operation that does not forcibly change the error voltage. Therefore, the DC-DC converter according to the second embodiment can shorten the response time.
Although a step-down converter capable of synchronous rectification has been described as the DC-DC converter of the second embodiment, the DC-DC converter of the present invention is not limited to this configuration. The present invention is also applicable to all the step-down, step-up and step-up / step-down DC-DC converters capable of synchronous rectification.
[0047]
<< Embodiment 3 >>
Next, a DC-DC converter according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a circuit diagram showing a configuration of the DC-DC converter according to Embodiment 3 of the present invention. Implementation
In the DC-DC converter according to the third embodiment, those having substantially the same functions and configurations as those of the DC-DC converter according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0048]
As shown in FIG. 6, the DC-DC converter according to the third embodiment has an input DC power supply 1 that outputs an input DC voltage Vi, and one end of the input DC power supply 1 has a first switch that is a main switch. One end of the switch 2 is connected. The other end of the first switch 2 is connected to one end of the second switch 3, the cathode of the first diode 4, and one end of the inductor 5. The other end of the second switch 3 and the anode of the first diode 4 are connected to the other end of the input DC power supply 1. The ON / OFF operation of the first switch 2 and the second switch 3 connected in this manner is repeated by a drive control signal from the control unit 11. The control unit 11 is connected to an output power rapid detection circuit 15 for detecting when the output power is rapidly reduced.
[0049]
As shown in FIG. 6, the DC-DC converter according to the third embodiment is provided with a third switch 6 for connecting one end of the inductor 5 and the ground side, and one end of the inductor 5 and the output capacitor 9. Is provided with a fourth switch 7 for connecting to one end of the switch. A second diode 8 is connected in parallel to both ends of the fourth switch 7 so that the second diode 8 is directed forward toward the load. The ON / OFF operation of the third switch 6 and the fourth switch 7 is repeated by a drive control signal from the control unit 11.
The DC-DC converter according to the third embodiment includes an input / output comparison circuit 16 and a second transient response operation circuit 18. The input / output comparison circuit 16 receives the input DC voltage Vi from the input DC power supply 1 and the same detection signal as the detection signal input to the output power rapid decrease detection circuit 15. The second transient response operation circuit 18 is configured to receive the output signal from the output power sudden decrease detection circuit 15 and the output signal from the error amplification circuit 12.
[0050]
In the DC-DC converter of the third embodiment, the first switch 2, the inductor 5, and the third switch 6 are connected in series, and both the first switch 2 and the third switch 6 are turned on. Then, the input DC voltage Vi is applied to the inductor 5. Further, the second switch 3, the inductor 5, and the fourth switch 7 are connected in series, and when both the second switch 3 and the fourth switch 7 are turned on, the voltage of the inductor 5 is changed to the output capacitor 9 Is configured to be applied.
The control unit 11 includes an error amplification circuit 12, an oscillation circuit 13, a control circuit 214, and an adder 143. The control unit 11 has a function of controlling on / off of the first switch 2, the second switch 3, the third switch 6, and the fourth switch 7 in order to control the output DC voltage Vo.
The DC-DC converter according to the third embodiment configured as described above is a step-up / step-down converter (step-up / step-down converter), which forms the input DC voltage Vi of the input DC power supply 1 into a desired DC voltage and outputs the desired DC voltage. ing.
[0051]
FIG. 7 is a circuit diagram showing a configuration of the control circuit 214.
As shown in FIG. 7, the error voltage Ve input to the control circuit 214 is input to the second comparator 145, and is also input to the first comparator 144 via the adder 143. The adder 143 adds the offset voltage Vos to the error voltage Ve, and outputs a signal (Ve + Vos) to the first comparator 144. The first comparator 144 compares the output (Ve + Vos) of the adder 143 with the sawtooth voltage Vt. The second comparator 145 compares the error voltage Ve with the sawtooth voltage Vt.
The output voltage Vd1 of the first comparator 144 becomes a first drive signal for controlling the first switch 2 to turn on and off. Further, the output of the first comparator 144 is input to the first synchronous switch driving circuit 400 via the first inverter 146 that inverts the signal. The output voltage Vd2 of the first synchronous switch drive circuit 400 becomes a second drive signal for turning on and off the second switch 3.
The output voltage Vd3 of the second comparator 145 becomes a third drive signal for turning on and off the third switch 6. Further, the output of the second comparator 145 is input to the second synchronous switch driving circuit 401 via the second inverter 147 for inverting a signal. The output voltage Vd4 of the second synchronous switch drive circuit 401 becomes a fourth drive signal for turning on and off the fourth switch 7.
[0052]
As shown in FIG. 7, a signal line connected to both ends of the second switch 3 is input to the first light load detection circuit 148, and the fourth light switch detection circuit 149 is connected to the fourth light switch. 7 are connected to signal lines connected to both ends. The first light load detection circuit 148 detects the current value using the resistance when the second switch 3 is turned on, and the second light load detection circuit 149 detects the resistance when the fourth switch 7 is turned on. , The first light load detection circuit 148 and the second light load detection circuit 149 detect a light load state based on these current values. That is, when the current flowing through the second switch 3 in the ON state exceeds a preset value, the first light load detection circuit 148 determines that the state is the light load state. At this time, the first synchronous switch drive circuit 400 turns off the second switch 3 because the output power rapid decrease detection circuit 15 does not detect the rapid decrease state of the output power. This operation is an operation in the discontinuous operation mode, which is one of the operations in the standby operation mode, and controls so that a reverse current does not flow. When the current flowing through the fourth switch 7 exceeds a preset value, the second light load detection circuit 149 determines that the state is a light load state. At this time, since the output power sudden decrease detection circuit 15 has not detected the rapid decrease state of the output power, the second synchronous switch driving circuit 401 turns off the fourth switch 7. This operation is also an operation in the discontinuous operation mode, which is one of the operations in the standby operation mode, and is controlled so that a reverse current does not flow.
[0053]
The load sudden decrease detection circuit 15 is configured by a comparator 150. The input / output comparison circuit 16 includes a resistor 160, a resistor 161, and a comparator 162. The second transient response operation circuit 18 includes a first command voltage source 180, a resistor 181, a switch 182, a second command voltage source 183, a resistor 184, a switch 185, a switch 186, an inverter 187, and a NOR circuit 188. ing.
[0054]
Next, the operation of the DC-DC converter according to the third embodiment configured as described above will be described.
First, a normal operation mode which is an operation mode in a heavy load state in the DC-DC converter according to the third embodiment will be described.
In the normal operation mode, the first switch 2, the second switch 3, the third switch 6, and the fourth switch 7 are turned on and off with the same switching cycle T by the control unit 11. The ratios of the ON time in one switching cycle of the first switch 2 and the third switch 6, that is, the duty ratios, are δ1 and δ2, respectively. During the period when the third switch 6 is in the ON state, δ1> δ2 is set so that the first switch 2 is also securely turned on. When the first switch 2 is on, the second switch 3 is off, and when the first switch 2 is off, the second switch 3 is on. When the third switch 6 is on, the fourth switch 7 is off, and when the third switch 6 is off, the fourth switch 7 is on.
[0055]
First, when both the first switch 2 and the third switch 6 are on, the input DC voltage Vi of the input DC power supply 1 is applied to the inductor 5. This period is δ2 · T. At this time, a current flows from the input DC power supply 1 to the inductor 5, and magnetic energy is accumulated in the inductor 5. Next, when the third switch 6 is turned off, the fourth switch 7 is turned on, and the difference Vi−Vo between the input DC voltage Vi and the output DC voltage Vo is applied to the inductor 5. This period is (δ1−δ2) · T, and a current flows from the input DC power supply 1 to the output capacitor 9 via the inductor 5. Finally, when both the first switch 2 and the third switch 6 are off, the second switch 3 and the fourth switch 7 are both on, and the output DC voltage Vo is applied to the inductor 5 in the reverse direction. Applied. This period is (1-δ1) · T, a current flows from the inductor 5 to the output capacitor 9, and the stored magnetic energy is released.
[0056]
As described above, the operation of storing and releasing magnetic energy in the inductor 5 is repeated, so that power is supplied from the output capacitor 9 to the load 10. In a stable operation state in which the accumulation and release of the magnetic energy of the inductor 5 are balanced, the sum of the voltage-time products is zero, so that the following equation (4) holds, and the output DC voltage Vo is different from the input DC voltage Vi. The conversion characteristic represented by Expression (5) is obtained.
Similarly, when δ2 = 0, the output DC voltage Vo is given by the equation (6), and operates as a step-down converter.
Similarly, when δ1 = 1, the output DC voltage Vo is given by the equation (7), and operates as a boost converter. By controlling the duty ratio of each switch, δ1 / (1−δ2) can be set from 0 to infinity. That is, the DC-DC converter of the third embodiment theoretically operates as a step-up / step-down converter that can form an arbitrary output DC voltage Vo from an arbitrary input DC voltage Vi.
[0057]
(Equation 4)

[0058]
(Equation 5)

[0059]
(Equation 6)

[0060]
(Equation 7)

[0061]
The error voltage Ve output from the error amplification circuit 12 decreases when the voltage detected by the detection circuit 22 from the output DC voltage Vo is higher than the reference voltage of the reference voltage source 120. When the voltage whose resistance is detected becomes lower than the reference voltage of the reference voltage source 120, the error voltage Ve increases. That is, when the input DC voltage Vi increases or the load 10 becomes lighter and the output DC voltage Vo tries to increase, the error voltage Ve decreases. Conversely, when the input DC voltage Vi decreases or the load 10 becomes heavy and the output DC voltage Vo tries to decrease, the error voltage Ve increases.
FIG. 8 is a waveform diagram of each part of the control unit 11 in the DC-DC converter according to the third embodiment. 8, (a) shows the sawtooth voltage Vt, the error voltage Ve, and the output voltage (Ve + Vos) of the adder 143, (b) shows the first drive signal Vd1, (c) shows the second drive signal Vd2, d) shows the third drive signal Vd3, and (e) shows the fourth drive signal Vd4. In FIG. 8, the left part is a case where (sawtooth voltage Vt)> (error voltage Ve), and the center part is where the sawtooth voltage Vt, error voltage Ve, and output (Ve + Vos) of adder 143 intersect. The right part shows the case where (sawtooth voltage Vt) <(output of adder 143 (Ve + Vos)).
[0062]
Next, the operation of the DC-DC converter according to the third embodiment will be described with reference to FIG.
First, when the input DC voltage Vi is high and (sawtooth voltage Vt)> (error voltage Ve) (the left part of FIG. 8), the third drive signal Vd3 output from the second comparator 145 is always “ L ", and the third switch 6 is turned off. Therefore, the duty ratio δ2 of the third switch 6 is δ2 = 0. On the other hand, the first switch 2 is driven on and off by the first drive signal Vd1 which is the output of the first comparator 144. The ratio δ1 at that time decreases as the error voltage Ve decreases. In this case, the DC-DC converter operates as a step-down converter whose input / output voltage relationship is expressed by Expression (6).
[0063]
Next, as shown in the center part of FIG. 8, when the input DC voltage Vi is near the output DC voltage Vo and the sawtooth voltage Vt, the error voltage Ve, and the output (Ve + Vos) of the adder 143 intersect, The first switch 2 is turned on / off by a first drive signal Vd1 output from the first comparator 144, and the third switch 6 is turned on / off by a third drive signal Vd3 output from the second comparator 145. Driven. At this time, the duty ratio δ1 and the duty ratio δ2 decrease as the error voltage Ve decreases. In this case, the DC-DC converter operates as a step-up / step-down converter whose input / output voltage relationship is expressed by equation (5).
[0064]
Next, as shown in the right part of FIG. 8, when the input DC voltage Vi is low and (sawtooth voltage Vt) <(output (Ve + Vos) of the adder 143) (the right part of FIG. 8), the first The first drive signal Vd1 output from the comparator 144 is always "H", and the first switch 2 is turned on. Therefore, the duty ratio δ1 of the first switch 2 is δ1 = 1. On the other hand, the third switch 6 is turned on and off by a third drive signal Vd3 which is an output of the second comparator 145. The ratio δ2 at that time increases as the error voltage Ve increases. In this case, the DC-DC converter operates as a boost converter whose input / output voltage relationship is expressed by equation (7).
The above is the normal operation mode in the DC-DC converter according to Embodiment 3 of the present invention. When the resistance values of the resistors 160 and 161 are R160 and R161, the comparator 162 compares the input DC voltage Vi with the output DC voltage Vo, and thus satisfies the following equations (8) and (9).
[0065]
(Equation 8)

[0066]
(Equation 9)

[0067]
Therefore, when the input DC voltage Vi is higher than the output DC voltage Vo, the comparator 162 outputs “H”. When the input DC voltage Vi is lower than the output DC voltage Vo, the comparator 162 outputs “L”.
[0068]
Next, an operation mode (transient response operation mode) during a transient response in the DC-DC converter according to the third embodiment will be described with reference to FIG.
FIG. 9 shows signal waveforms of the respective parts when the reference voltage Er sharply decreases in the DC-DC converter according to the third embodiment. In FIG. 9, (a) is a voltage waveform showing a state when the reference voltage Er sharply decreases, and (b) is an output target voltage E0, an output upper limit voltage E1, an input DC voltage Vi, and an output in the case of (a). FIG. 4 is a waveform diagram illustrating a relationship of a DC voltage Vo. FIG. 9C shows the sawtooth voltage Vt, the error voltage Ve, and the output of the adder 143 (Ve + Vos).
While the output DC voltage Vo is higher than the output upper limit voltage E1, the drive voltage V150 of the comparator 150 is “L”. Further, since the input DC voltage Vi is lower than the output DC voltage Vo, the drive voltage V162 of the comparator 162 becomes “L”.
[0069]
The NOR circuit 188 to which the driving voltage V150 of the comparator 150 and the driving voltage V162 of the comparator 162 are input becomes “H”, and the switches 182 and 185 are turned on. Since the drive voltage V188 of the NOR circuit 188 is inverted by the inverter 187, the switch 186 is turned off.
When the switch 186 is turned off, the output V12 of the error amplifier circuit 12 is not transmitted to the control circuit 214. When the switch 185 is turned on, the voltage of the second instruction voltage source 183 is input to the control circuit 214 via the resistor 184 (instruction voltage V184). Further, when the switch 182 is turned on, the voltage of the first instruction voltage source 180 is input to the adder 143 via the resistor 181 (instruction voltage V181). The output of the adder 143 is "V184 + Vos + V181". Here, the voltage value of the command voltage V184 is set to be slightly larger than the minimum value of the sawtooth voltage Vt, and the voltage value of the command voltage V181 is such that the voltage (V184 + Vos + V181) is larger than the maximum value of the sawtooth voltage Vt. Set as follows.
[0070]
In the above operation, in one switching cycle, the first switch 2 is always on, the second switch 3 is always off, and the third switch 6 is on for a short period. The switch 7 of 4 is turned off only for a short period. δ1 = 1, δ2 operate as a boost converter controlled by a small duty ratio. This state continues until the comparator 150 is inverted and the switch 186 is turned on. Thereafter, the mode returns to the normal operation mode or the standby operation mode, and the output DC voltage Vo eventually reaches the output target voltage E0. The resistor 126 limits the current flowing through the phase compensation capacitor 125 when the switch 186 is turned on, and suppresses the fluctuation of the detection voltage.
[0071]
As described above, in the DC-DC converter according to Embodiment 3, when the output DC voltage Vo is higher than the input DC voltage Vi, the power due to the power regeneration operation forcibly sets the error voltage until the output upper-limit voltage E1 is reached. The operation which becomes larger than the power by the power regeneration operation which is not changed to is continued. Therefore, the DC-DC converter according to the third embodiment can shorten the response time.
In the third embodiment, a four-step-up / down converter is described as a DC-DC converter capable of stepping up / down, but the DC-DC converter of the present invention is not limited to such a configuration. is not. Other known DC-DC converters that can be stepped up and down include a SEPIC whose circuit diagram is shown in FIG. 19 and a Zeta converter whose circuit diagram is shown in FIG. The present invention can also be configured by combining a step-up converter and a step-down converter in series or in parallel. The present invention can be applied to a step-up / step-down DC-DC converter capable of synchronous rectification.
Furthermore, in the DC-DC converter according to the third embodiment, four switches are drive-controlled during the step-up / step-down operation. However, only two switches are required to be drive-controlled during the step-up / step-down operation. It becomes a simple DC-DC converter.
[0072]
<< Embodiment 4 >>
Next, a DC-DC converter according to a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a circuit diagram showing a configuration of a DC-DC converter according to Embodiment 4 of the present invention. In the DC-DC converter according to the fourth embodiment, those having substantially the same functions and configurations as those of the DC-DC converter according to the above-described third embodiment are denoted by the same reference numerals, and description thereof is omitted.
The DC-DC converter according to the fourth embodiment differs from the DC-DC converter according to the third embodiment shown in FIG. 6 in that a high-speed response circuit 21 including a regenerative switch 210, a resistor 211, and a NOR circuit 212 is provided. And the second transient response operation circuit 18 is eliminated.
[0073]
An operation mode (transient response operation mode) of the DC-DC converter according to the fourth embodiment configured as described above during a transient response will be described with reference to FIGS. 11 and 12. In FIG. 11, (a) is a voltage waveform showing a state when the reference voltage Er is rapidly reduced, and (b) is an output target voltage E0, an output upper limit voltage E1, an input DC voltage Vi, and an output in the case of (a). FIG. 4 is a waveform diagram illustrating a relationship of a DC voltage Vo. FIG. 11C shows a voltage waveform (V212) in the high-speed response circuit 21.
The voltage waveform of the reference voltage Er in (a) of FIG. 11 shows a state where the reference voltage Er sharply decreases due to a command from the load 10 or the like. At this time, the output upper limit voltage E1 based on the lowered reference voltage Er is higher than the input DC voltage Vi. The output target voltage E0 and the output upper limit voltage E1 change with the change of the reference voltage Er, but the error amplifier 124 of the error amplifier circuit 12 does not immediately respond, and the offset voltage Vos is added to the error voltage Ve and the error voltage Ve. The voltage (Ve + Vos) gradually decreases. This voltage (Ve + Vos) is formed in the adder 143 and output to the first comparator 144.
[0074]
In the state shown in FIG. 11, the comparator 150 of the output power sudden decrease detection circuit 15 outputs “L” to the high-speed response circuit 21 because the detected voltage is higher than the reference voltage Er. The comparator 162 of the input / output comparison circuit 16 outputs “L” to the NOR circuit 212 of the high-speed response circuit 21 because the output DC voltage Vo is higher than the input DC voltage Vi. Therefore, the drive signal V212 for the regenerative switch 210 output from the NOR circuit 212 becomes "H", and the regenerative switch 210 is turned on. As a result, the power regeneration operation is rapidly performed from the output capacitor 9 to the input DC power supply 1 via the high-speed response circuit 21. The ON state of the regenerative switch 210 continues until the output DC voltage Vo reaches the output upper limit voltage E1 and the comparator 150 is inverted.
After the comparator 150 is inverted and the regenerative switch 210 is turned off, if the error voltage Ve is not sufficiently reduced, the output DC voltage Vo is increased, and the regenerative switch 210 is turned on again. Then, the output DC voltage Vo decreases and the regenerative switch 210 is turned off again. As described above, by repeating the on / off operation of the regenerative switch 210, the error voltage Ve eventually rises sufficiently, and the output DC voltage Vo settles to the output target voltage E0.
[0075]
FIG. 12 is a waveform diagram showing a state where reference voltage Er further decreases and output upper limit voltage E1 after reference voltage Er decreases below input DC voltage Vi. FIG. 12A is a voltage waveform showing a state when the reference voltage Er sharply decreases, and FIG. 12B is a diagram showing the output target voltage E0, the output upper limit voltage E1, and the input DC voltage in the case of FIG. FIG. 12C is a waveform diagram showing the relationship between Vi and the output DC voltage Vo. FIG. 12C shows a voltage waveform (V212) in the high-speed response circuit 21.
The output target voltage E0 and the output upper limit voltage E1 also change with the change of the reference voltage Er, but the error amplifier 124 does not immediately respond, and the error voltage Ve and the voltage (Ve + Vos) obtained by adding the offset voltage Vos to the error voltage Ve are: Declines slowly.
[0076]
In the state illustrated in FIG. 12, the comparator 150 of the output power sudden decrease detection circuit 15 outputs “L” to the high-speed response circuit 21 because the detected voltage is higher than the reference voltage Er. The comparator 162 of the input / output comparison circuit 16 outputs “L” to the NOR circuit 212 of the high-speed response circuit 21 because the output DC voltage Vo is higher than the input DC voltage Vi. Therefore, the drive signal V212 for the regenerative switch 210 output from the NOR circuit 212 becomes "H", and the regenerative switch 210 is turned on. As a result, the power regeneration operation is rapidly performed from the output capacitor 9 to the input DC power supply 1 via the high-speed response circuit 21. The ON state of the regenerative switch 210 continues until the output DC voltage Vo reaches the input DC voltage Vi and the comparator 150 is inverted.
After the comparator 150 is inverted and the regenerative switch 210 is turned off, if the error voltage Ve is not sufficiently reduced, the output DC voltage Vo increases and the regenerative switch 210 is turned on again. Then, the output DC voltage Vo decreases and the regenerative switch 210 is turned off again. As described above, by repeating the on / off operation of the regenerative switch 210, the error voltage Ve eventually rises sufficiently, and the output DC voltage Vo settles to the output target voltage E0.
[0077]
In the fourth embodiment, output upper limit voltage E1 may be set to a value equal to or higher than the allowable upper limit value of output DC voltage Vo and close to output target voltage E0. Further, the resistance value R161 may be set in consideration of a voltage drop at the regenerative switch 210 and the resistor 211.
In the conventional DC-DC converter, the output DC voltage Vo changes according to a gradual change of the error voltage Ve determined by the response speed of the error amplifier, and the response speed until the output DC voltage Vo reaches the output target voltage E0 is reduced. It was very slow. However, in the DC-DC converter according to the fourth embodiment, the high-speed response circuit 21 having the regenerative switch 210 is provided to perform a rapid power regeneration operation, so that the response time can be significantly reduced. The regenerative switch 210 is on until the output DC voltage Vo reaches the higher of the output upper limit voltage E1 and the input DC voltage Vi, and thereafter returns to the normal response operation. No undershoot occurs.
[0078]
The resistor 211 of the high-speed response circuit 21 in the DC-DC converter according to the fourth embodiment is used to limit a regenerative current during a rapid power regeneration operation from the input DC power supply 1 to the output capacitor 9 by the regenerative switch 210. It is. However, the resistance 211 can be replaced with the impedance of the regenerative switch 210 itself when it is in the ON state. Further, in the fourth embodiment, a description has been given using a four-step buck-boost converter as the buck-boost DC-DC converter, but the DC-DC converter of the present invention is limited to such a configuration. is not. Other known DC-DC converters that can be stepped up and down include a SEPIC whose circuit diagram is shown in FIG. 19 and a Zeta converter whose circuit diagram is shown in FIG. Further, the present invention can also be configured by combining a step-up converter and a step-down converter in series or in parallel. The present invention is also applicable to these step-up / step-down DC-DC converters. Although the DC-DC converter according to the fourth embodiment has been described as a step-up / step-down DC-DC converter, the configuration according to the fourth embodiment can be applied to a step-up DC-DC converter.
[0079]
<< Embodiment 5 >>
Next, a DC-DC converter according to a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a circuit diagram showing a configuration of a DC-DC converter according to Embodiment 5 of the present invention. In the DC-DC converter according to the fifth embodiment, those having substantially the same functions and configurations as those of the DC-DC converter according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0080]
The DC-DC converter according to the fifth embodiment differs from the configuration of the DC-DC converter according to the first embodiment shown in FIG. 1 in that the output power sudden decrease detection circuit (15) is omitted. The point is that an external signal 19 for notifying a sudden decrease in output power is input from an external device. In the first embodiment, the output power sudden decrease detection circuit (15) is used to detect the rapid decrease state of the output power. However, in the DC-DC converter of the fifth embodiment, an external signal for notifying the rapid decrease of the output power is provided. The external signal 19 from the device is input to the control unit 11, and the same operation as that of the first embodiment is performed in the light load detection circuit 142 and the synchronous switch drive circuit 20 of the control unit 11. Therefore, according to the DC-DC converter of the fifth embodiment, the circuit configuration can be simplified.
[0081]
Also, by using the output power sudden decrease detection circuit (15) as in the above-described first embodiment, the error voltage Ve is sufficiently reduced at a light load, and the output DC voltage Vo is settled at the output target voltage E0. Up to this point, the operation in the continuous operation mode (power regeneration operation) and the operation in the discontinuous operation mode are repeated, so that it takes some time for the output DC voltage Vo to settle to the output target voltage E0. In the DC-DC converter according to the fifth embodiment, since the external signal 19 indicating the sudden decrease of the output power is used, the power is maintained until the error voltage Ve sufficiently decreases and the output DC voltage Vo reaches the output target voltage E0. If the input of the external signal 19 is continued so as to perform the regenerative operation, the response time can be reduced.
[0082]
Next, an operation mode during a transient response (transient response operation mode) in the DC-DC converter of the fifth embodiment will be described with reference to FIG. FIG. 14A is a voltage waveform showing a state when the reference voltage Er sharply decreases, and FIG. 14B is a waveform showing the relationship between the output target voltage E0 and the output DC voltage Vo in FIG. FIG. 14C shows a voltage waveform (V 19) of the external signal 19.
First, a case where the load 10 is always in a light load state will be described.
Even before the reference voltage Er decreases, since the light load state is maintained, a signal for notifying the sudden decrease in output power is not input from the external signal 19, and the light load detection circuit 142 detects the light load state. , The synchronous switch drive circuit 20 turns off the second switch 3. At this time, the DC-DC converter operates in the discontinuous operation mode, which is one of the standby operation modes. At this time, that is, in a light load state before the reference voltage Er decreases, the external signal 19 outputs “H”.
When the reference voltage Er sharply decreases, the output target voltage E0 decreases, the external signal 19 becomes "L", a signal indicating that the output power sharply decreases is input, and the light load detection circuit 142 detects a light load. . As a result, the synchronous switch drive circuit 20 inputs the drive voltage V141 of the inverter 141 as it is as the drive voltage Vd2 of the second switch 3. As described above, during the period in which “L” of the external signal 19 is input, the operation is not in the discontinuous operation mode as the standby mode, but is performed in the continuous operation mode. Therefore, during this period, the output DC voltage Vo drops sharply to perform power regeneration. This power regeneration operation continues until the external signal 19 becomes "H".
[0083]
As described above, in the DC-DC converter according to the fifth embodiment, since the external signal 19 for notifying the rapid decrease of the output power is input, the error voltage Ve sufficiently decreases, and the output DC voltage Vo Is configured such that the input of the external signal 19 is continued so that the power regeneration operation is performed until the output signal reaches the output target voltage E0, whereby the response time can be further reduced.
In the DC-DC converter according to the fifth embodiment, the external signal may be set to “L” until the error voltage Ve sufficiently decreases and the output DC voltage Vo reaches the output target voltage E0.
In the fifth embodiment, a step-down converter capable of synchronous rectification has been described. However, the DC-DC converter of the present invention is not limited to such a configuration. The present invention is applicable to all step-down, step-up and step-up / step-down DC-DC converters capable of synchronous rectification.
[0084]
<< Embodiment 6 >>
Next, a DC-DC converter according to a sixth embodiment of the present invention will be described with reference to FIGS. FIG. 15 is a circuit diagram showing a configuration of the DC-DC converter according to Embodiment 6 of the present invention. In the above-described DC-DC converter according to the first embodiment, the control method called the voltage mode for detecting the voltage and controlling the output DC voltage has been described using the example in which the present invention is applied. In the DC-DC converter according to the sixth embodiment, a control method called a current mode in which a current is detected to control an output DC voltage is applied to the present invention. In the sixth embodiment, components having substantially the same functions and configurations as those of the DC-DC converter of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. The DC-DC converter according to the sixth embodiment differs from the first embodiment shown in FIG. 1 in the configuration of the error amplifier circuit 72 and the control circuit 91.
[0085]
In the DC-DC converter according to the sixth embodiment, the error amplifying circuit 72 includes a reference voltage source 720, three resistors 721, 722, 723, an error amplifier 724, and an integrating circuit including a series circuit of a resistor 725 and a capacitor 726. I have it.
In the error amplifying circuit 72, the output DC voltage Vo is divided and detected by three resistors 721, 722, and 723. The voltage at the connection point between the resistors 721 and 722 is compared with the reference voltage Er of the reference voltage source 720 by the error amplifier 724. Error amplifier 724 outputs error voltage Ve. An output terminal of the error amplifier 724 is connected to an integrating circuit composed of a series circuit of a resistor 725 and a capacitor 726 to reduce high-frequency gain. Assuming that the voltage division ratio at the connection point between the resistor 721 and the resistor 722 is α, the first detection voltage input to the inverting input terminal of the error amplifier 724 is represented by α · Vo. The error voltage Ve decreases when the first detection voltage α · Vo tries to become higher than the reference voltage Er, and conversely increases when the detection voltage α · Vo tries to become lower than the reference voltage Er. When the first detection voltage α · Vo is equal to the reference voltage Er, the output DC voltage Vo has a desired voltage value. The output target voltage E0 that is the desired voltage value is expressed by the following equation (10).
[0086]
(Equation 10)

[0087]
If the voltage division ratio at the connection point between the resistor 722 and the resistor 723 is β, the second detection voltage is represented by β · Vo. The second detection voltage β · Vo is compared by comparator 150 with reference voltage Er of reference voltage source 720. Assuming that the output DC voltage when the second detection voltage β · Vo is equal to the reference voltage Er is the output upper limit voltage E1, the output upper limit voltage E1 is represented by the following equation (11). The output upper limit voltage E1 becomes higher than the output target voltage E0 which is a desired voltage value.
[0088]
[Equation 11]

[0089]
The output of the comparator 150 is input to the synchronous switch driving circuit 915 of the control circuit 91. The configuration of the synchronous switch driving circuit 915 is the same as the configuration of the synchronous switch driving circuit 20 in the DC-DC converter of the first embodiment.
The control circuit 91 includes a current detection circuit 910, a pulse oscillation circuit 911, a comparator 912, a flip-flop circuit 913, an inverter 914, a synchronous switch drive circuit 915, and a light load detection circuit 916. The current detection circuit 910 detects a current flowing through the first switch 2 (hereinafter, referred to as a switch current) and outputs a current detection signal Vsi proportional to the switch current. The pulse oscillation circuit 911 outputs a set pulse of the switching frequency f. The comparator 912 receives the error voltage Ve output from the error amplifier circuit 72 and the current detection signal Vsi from the current detection circuit 910. When the current detection signal Vsi becomes higher than the error voltage Ve, the comparator 912 outputs a reset pulse to the flip-flop circuit 913. The flip-flop circuit 913 outputs a driving signal V913 which becomes high level when a set pulse from the pulse oscillation circuit 911 is input and becomes low level when an output pulse from the comparator 912 is input.
[0090]
FIG. 16 shows the voltage waveform of each part in the control circuit 91. As shown in FIG. 16, when the error voltage Ve decreases, the pulse width of the drive signal V913 decreases in order to reduce the peak value of the switch current. That is, the duty ratio δ becomes small, and power supply to the load 10 is suppressed. Conversely, when the error voltage Ve increases, the peak value of the switch current increases, so that the pulse width of the drive signal V913 increases. That is, the duty ratio δ increases, and the power supply to the load 10 increases.
[0091]
As described above, in the DC-DC converter according to Embodiment 6, the error amplifier circuit 72 outputs the error voltage Ve obtained by amplifying the difference between the output DC voltage Vo and the output target voltage E0. In the DC-DC converter of the sixth embodiment, the output DC voltage Vo is adjusted to the output target voltage E0 by adjusting the peak value of the current (switch current) flowing through the first switch 2 using the error voltage Ve. Is controlled.
[0092]
When the DC-DC converter is operating in the standby operation mode, for example, if the reference voltage Er of the reference voltage source 720 is reduced according to a signal from the load 10 or the like, the output target voltage E0 and the output upper limit voltage E1 also decrease. . At this time, the comparator 150 of the output power drop detection circuit 15 outputs “L” because the detected voltage becomes higher than the lowered reference voltage Er. This “L” signal is input to the synchronous switch driving circuit 915. At this time, since the output power drop detection circuit 15 detects the output power drop state and the light load detection circuit 916 detects the light load state, the synchronous switch drive circuit 915 uses the drive voltage V 914 of the inverter 914 as it is. It outputs as the drive voltage Vd2 of the second switch 3. As a result, the second switch 3 performs an on / off operation in synchronization with the first switch 2, so that the DC-DC converter operates in the standby operation mode while the comparator 150 is outputting the “L” signal. Instead, it operates in continuous operation mode. This continuous operation mode is a transient response operation mode.
[0093]
In this transient response operation mode, power regeneration is performed, and the output DC voltage Vo sharply decreases. This power regeneration operation is continued until the output DC voltage Vo reaches the output upper limit voltage E1 and the comparator 150 of the output power sudden decrease detection circuit 15 is inverted. When the comparator 150 is inverted, the output power rapid decrease detection circuit 15 does not detect the output power rapid decrease state. At this time, since the light load detection circuit 916 detects the light load state, the DC-DC converter operates in the discontinuous operation mode. However, at this time, if the error voltage Ve has not sufficiently decreased, the output DC voltage Vo increases. Then, the comparator 150 is further inverted to enter the continuous operation mode and perform power regeneration. Due to this power regeneration operation, the output DC voltage Vo decreases, and the comparator 150 is further inverted to enter the discontinuous operation mode. As described above, the operation in the continuous operation mode and the operation in the discontinuous operation mode are repeated, and the error voltage Ve eventually decreases sufficiently, and the output DC voltage Vo settles at the output target voltage E0.
[0094]
While the DC-DC converter controlled in the voltage mode has been described in the first embodiment, the DC-DC converter controlled in the current mode has been described in the sixth embodiment. As is clear from the description of the operation in the sixth embodiment, the current mode control method is applicable to the DC-DC converter of the present invention, and has the same excellent effects as the voltage mode control method.
As described in the first to sixth embodiments, the present invention has the effect of shortening the response time when the output DC voltage is rapidly reduced. Further, according to the present invention, when the output DC voltage Vo is higher than the output target voltage E0, the stability of the output DC voltage Vo can be improved by regenerating power to the input side of the output DC voltage Vo. Having. For this reason, the DC-DC converter of the present invention is effective in suppressing overshoot due to a sudden change in output conditions and the like. For example, at the start of the DC-DC converter, particularly at the start of light load, when the input DC voltage is applied and the DC-DC converter starts operating, the difference between the output DC voltage Vo and the reference voltage Er is reduced. growing. As a result, the error voltage Ve increases, the peak value of the switch current also increases, and the output DC voltage Vo sharply increases. In the conventional DC-DC converter, after the output DC voltage Vo reaches the output target voltage E0, an overshoot occurs in the output DC voltage during a delay time of the operation circuit for suppressing the supply power. In particular, when the load is light, the overshoot increases. Further, since the stability to the output target voltage E0 depends on the load, it takes time for the output DC voltage Vo to respond to the output target voltage E0. In the DC-DC converter of the present invention, when the output DC voltage Vo becomes higher than the output target voltage E0 and exceeds the output upper limit voltage, the second switch 3 is turned on and off to regenerate power. I have. Since the DC-DC converter of the present invention is configured as described above, the output DC voltage Vo can be rapidly reduced, so that the response time to the output target voltage E0 can be shortened.
[0095]
In the sixth embodiment, a step-down converter capable of synchronous rectification has been described. However, the DC-DC converter of the present invention is not limited to such a configuration. The present invention is applicable to all step-down, step-up and step-up / step-down DC-DC converters capable of synchronous rectification.
Further, the control in the DC-DC converters of the first to sixth embodiments can be applied even at the time of startup, and the response time to the output target voltage E0 at the time of startup can be shortened.
Further, the DC-DC converters described in the first to sixth embodiments can be configured to have each function by combining them.
Furthermore, each component such as the control unit in the DC-DC converter described in the first to sixth embodiments can be individually configured as an independent unit, and used in another embodiment. is there.
[0096]
【The invention's effect】
As is clear from the above, the DC-DC converter of the present invention has the following effects.
The DC-DC converter of the present invention sets an output upper limit voltage higher by a predetermined voltage than an output target voltage to be a control target of an output DC voltage, and outputs a comparison result between the output upper limit voltage and the output DC voltage. By providing the power sudden decrease detection circuit, when the output DC voltage is higher than the output upper limit voltage in the light load state, the standby operation mode is canceled and the transient response operation mode for performing the power regeneration operation is executed. Thus, the present invention significantly improves the response speed at which the output DC voltage efficiently reaches the output target voltage regardless of the load condition, even if the output DC voltage becomes higher than the output target voltage due to some condition change. It has the effect of being able to.
[0097]
Further, the DC-DC converter of the present invention sets an output upper limit voltage higher by a predetermined voltage than an output target voltage which is a control target of the output DC voltage, and outputs a comparison result between the output upper limit voltage and the output DC voltage. If the output DC voltage is higher than the output upper limit voltage, the error voltage is forcibly changed to lower the output DC voltage, and the power regenerated by the power regeneration operation is reduced. It is configured to operate in a larger transient response operation mode. Therefore, the DC-DC converter of the present invention has an excellent effect that the response time can be shortened.
[0098]
Further, the DC-DC converter of the present invention sets an output upper limit voltage higher by a predetermined voltage than an output target voltage to be a control target of the output DC voltage, and outputs a comparison result between the output upper limit voltage and the output DC voltage. If the output DC voltage is higher than the output upper limit voltage and the output DC voltage is higher than the input DC voltage, the error voltage and the offset voltage are forcibly reduced so that the output DC voltage decreases. Has changed. For this reason, the DC-DC converter of the present invention operates in the transient response operation mode in which the power regenerated by the power regenerating operation is larger, so that the response time can be reduced. Further, in the present invention, by performing the step-up operation of the DC-DC converter capable of stepping up and down in the transient response operation mode, there is an effect that the switching loss is reduced and the efficiency is increased.
[0099]
Also, the DC-DC converter of the present invention is provided with a high-speed response circuit having a regenerative switch between the input and output, and when the output DC voltage is higher than the output upper limit voltage and the output DC voltage is higher than the input DC voltage, the regenerative switch is provided. The on state enables application even to a DC-DC converter that cannot perform power regeneration operation. Even if the output DC voltage becomes higher than the output target voltage due to some condition change, the output DC voltage is output regardless of the load condition. The response speed to reach the target voltage can be greatly improved. Further, by applying the configuration of the DC-DC converter of the present invention having the high-speed response circuit to the DC-DC converter capable of synchronous rectification, the response time can be further reduced.
[0100]
Further, since the DC-DC converter of the present invention is configured to receive an external signal indicating a sudden decrease in output power, the DC-DC converter is configured to always perform a power regeneration operation during a period in which the external signal is input. Accordingly, the response time can be significantly reduced, and the circuit can be simplified.
In addition, the present invention is applicable to a DC-DC converter controlled in a voltage mode and a DC-DC converter controlled in a current mode. It has an excellent effect of shortening the time.
Further, the DC-DC converter of the present invention can be adapted even at the time of startup, and can reduce the response time to the output target voltage at the time of startup.
Although the invention has been described in terms of a preferred form with some detail, the present disclosure of the preferred form should vary in the details of construction, and any combination of elements or change in order will not affect the claimed invention. It can be realized without departing from the scope and spirit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a DC-DC converter according to a first embodiment of the present invention.
FIG. 2 is a waveform chart showing the operation of each unit in the DC-DC converter according to the first embodiment.
FIG. 3 is a waveform chart showing an operation of each unit in the DC-DC converter according to the first embodiment.
FIG. 4 is a circuit diagram showing a configuration of a DC-DC converter according to a second embodiment of the present invention.
FIG. 5 is a waveform chart showing the operation of each part in the DC-DC converter according to the second embodiment.
FIG. 6 is a circuit diagram showing a configuration of a DC-DC converter according to a third embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a control unit in the DC-DC converter according to the third embodiment.
FIG. 8 is a waveform chart showing an operation of a control unit in the DC-DC converter according to the third embodiment.
FIG. 9 is a waveform chart showing the operation of each unit in the DC-DC converter according to the third embodiment.
FIG. 10 is a circuit diagram showing a configuration of a DC-DC converter according to a fourth embodiment of the present invention.
FIG. 11 is a waveform chart showing the operation of each part in the DC-DC converter according to the fourth embodiment.
FIG. 12 is a waveform chart showing the operation of each unit in the DC-DC converter according to the fourth embodiment.
FIG. 13 is a circuit diagram showing a configuration of a DC-DC converter according to a fifth embodiment of the present invention.
FIG. 14 is a waveform chart showing the operation of each part in the DC-DC converter according to the fifth embodiment.
FIG. 15 is a circuit diagram showing a configuration of a DC-DC converter according to a sixth embodiment of the present invention.
FIG. 16 is a waveform chart showing the operation of each part in the DC-DC converter according to the sixth embodiment.
FIG. 17 is a circuit diagram showing a configuration of a conventional DC-DC converter.
FIG. 18 is a waveform chart showing the operation of each unit in a control unit of a conventional DC-DC converter.
FIG. 19 is a circuit diagram showing a SEPIC that is a DC-DC converter capable of stepping up and down.
FIG. 20 is a circuit diagram showing a Zeta converter which is a DC-DC converter capable of stepping up and down.
[Explanation of symbols]
1 DC input power supply
2 First switch
3 Second switch
4 Rectifier diode
5 Inductor
6 Third switch
7 Fourth switch
8 Second diode
9 Output capacitor
10 Load
11 Control part
12 Error amplifier circuit
13 Oscillation circuit
14 Control circuit
15 Output power drop detection circuit
16 I / O comparison circuit
17. First transient response operation circuit
18. Second transient response operation circuit
19 External signal
20 Synchronous switch drive circuit
21 High-speed response circuit
22 Detection circuit
23 Switch control circuit

Claims (12)

An input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A switch control circuit that adjusts an on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and controls driving of the main switch circuit.
A light load detection circuit for detecting that the load is in a light load state,
An output power rapid decrease detection circuit for detecting a rapid decrease in output power,
A DC-DC converter comprising: a synchronous switch drive circuit to which an output of the switch control circuit, an output of the light load detection circuit, and an output of the output power rapid detection circuit are input,
The synchronous switch drive circuit,
(1) the synchronous switch circuit is turned off when the light load detection circuit detects a light load state and the output power sudden decrease detection circuit does not detect the output power rapid decrease state;
(2) the synchronous switch circuit according to the output from the switch control circuit when the light load detection circuit detects a light load state and the output power sudden decrease detection circuit detects a rapid output power decrease state; Is turned on and off, and
(3) when the light load detection circuit does not detect a light load state and the output power rapid decrease detection circuit does not detect a rapid output power decrease state, the synchronous switch circuit is turned on / off according to an output from the switch control circuit; Operating state,
(4) When the light load detection circuit does not detect a light load state and the output power rapid decrease detection circuit detects a rapid decrease in output power, the synchronous switch circuit is turned on / off according to the output from the switch control circuit. A DC-DC converter that is in an operating state. 2. The DC-DC converter according to claim 1, further comprising: a first transient response operation circuit for forcibly changing an error voltage so as to reduce the output power at the time of a transient response in which the output power rapid decrease detection circuit detects a rapid decrease in output power. DC converter. A second transient response forcibly changing the offset voltage so as to reduce the output power when a transient response in which the switch control circuit has an offset voltage source and the output power rapid decrease detection circuit detects a rapid decrease in output power; 3. The DC-DC converter according to claim 1, further comprising an operation circuit. An input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A control circuit that adjusts the on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and drives the main switch circuit and the synchronous switch circuit,
An output power drop detection circuit for detecting a sudden output power drop state;
A first transient response operation circuit that forcibly changes the error voltage so as to decrease the output power during a transient response in which the output power rapid decrease detection circuit detects a rapid decrease in output power;
A DC-DC converter comprising: The control circuit has an offset voltage source that outputs an offset voltage,
5. The circuit according to claim 4, further comprising a second transient response operation circuit for forcibly changing the offset voltage so as to reduce the output power when a transient response in which the output power rapid decrease detection circuit detects a rapid decrease in output power. A DC-DC converter as described. An input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit for rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A control circuit that adjusts an on / off period of the main switch circuit based on the error voltage, and controls driving of the main switch circuit.
An output power rapid decrease detection circuit for detecting a rapid decrease in output power,
An input / output comparison circuit for comparing the input DC voltage with the output DC voltage,
A regenerative switch circuit connected in parallel between the input and output of the DC-DC converter, wherein the output DC voltage is higher than the input DC voltage, and the output power sudden decrease detection circuit detects a rapid decrease in output power. A high-speed response circuit that turns on the regenerative switch circuit when responding;
A DC-DC converter comprising: The output power sudden decrease detection circuit is configured to set an output upper limit voltage higher by a predetermined voltage than an output target voltage that is a control target of the output DC voltage, and compares the output upper limit voltage with the output DC voltage. 7. The circuit according to claim 1, further comprising a comparison circuit configured to detect a period in which the output DC voltage is higher than the output upper limit voltage as the transient response based on an output of the comparison circuit. 8. The DC-DC converter according to any one of the above. The DC-DC converter according to any one of claims 1, 4, 5, and 6, wherein a signal indicating a state of a rapid decrease in output power is input from a load connected to the DC-DC converter. An input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A switch control circuit that adjusts an on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and controls driving of the main switch circuit.
A light load detection circuit for detecting that the load is in a light load state,
A DC-DC converter comprising: an output of the switch control circuit, an output of the light load detection circuit, and a synchronous switch driving circuit to which a signal indicating whether the output power is in a rapidly decreasing state is input,
(1) detecting that the light load detection circuit is in a light load state, and turning off the synchronous switch circuit when the output power is not in a rapidly decreasing state;
(2) detecting that the light load detection circuit is in a light load state, and setting the synchronous switch circuit to an on / off operation state according to an output from the switch control circuit when the output power is in a rapidly decreasing state;
(3) when the light load detection circuit does not detect a light load state and the output power is not in a rapidly decreasing state, the synchronous switch circuit is turned on / off in response to an output from the switch control circuit;
(4) When the light load detection circuit does not detect a light load state, and when the output power is in a rapidly decreasing state, the synchronous switch circuit is turned on / off in response to an output from the switch control circuit. converter. An input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit having a synchronous switch circuit, rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A control circuit that adjusts the on / off period of the main switch circuit and the synchronous switch circuit based on the error voltage, and drives the main switch circuit and the synchronous switch circuit,
A first transient response operation circuit that forcibly changes the error voltage so as to reduce the output power during a transient response in which a signal indicating that the output power is rapidly reduced is input from the load side;
A DC-DC converter comprising: The control circuit has an offset voltage source that outputs an offset voltage,
A transient response operation circuit for forcibly changing the offset voltage so as to reduce the output power when a signal indicating that the output power is rapidly reduced is input from the load side. A DC-DC converter according to claim 10. An input DC power supply for supplying an input DC voltage,
A main switch circuit that receives the input DC voltage and performs a switching operation during a predetermined ON period and OFF period;
An inductor that repeatedly stores and releases magnetic energy by a switching operation of the main switch circuit;
A rectifying and smoothing circuit for rectifying and smoothing the voltage of the main switch circuit or the inductor and supplying an output DC voltage to a load;
An error amplifier circuit that compares the output DC voltage with a reference voltage and outputs an error voltage;
A control circuit that adjusts an on / off period of the main switch circuit based on the error voltage, and controls driving of the main switch circuit.
An input / output comparison circuit for comparing the input DC voltage with the output DC voltage,
A regenerative switch circuit connected in parallel between the input and output of the DC-DC converter, wherein the output DC voltage is higher than the input DC voltage, and a signal indicating that output power is rapidly reduced is input from the load side; A high-speed response circuit that turns on the regenerative switch circuit during a transient response;
A DC-DC converter comprising:

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