JP4576411B2 - Step-up / step-down (buck / boost) switching regulator - Google Patents

Description

  The present invention relates to the field of step-up / step-down switching regulators.

Step-up / step-down switching regulators use pulse width modulation to control energy transfer from the power supply to the load. This control function becomes more complex when the power supply and load voltage ranges overlap, which is a common condition in battery-powered portable devices. Existing technologies exhibit undesirable behavior such as frequency splitting, increased voltage and current ripple, mode hunting, reduced conversion efficiency, increased element stress. As an example, an H-bridge circuit as shown in FIG. 1 is used as a buck-boost DC to DC converter. Such a converter and its method of operation are disclosed in US Pat. No. 6,087,816. This system has a large current ripple. Inductors, capacitors and power switches need to be rated for currents much greater than the load current.
US Pat. No. 6,087,816

  A converter according to the invention is shown in FIG. As shown, in such a converter, switches 1 and 4 are P-channel devices and switches 2 and 3 are N-channel devices. In this regard, in such a converter, switches 2 (N1) and 4 (P2) generally perform a rectification function rather than a control function and can thus be realized as a normal diode, a Schottky diode, or a synchronous rectifier. Techniques for controlling synchronous rectifiers are known in the prior art, and therefore details of the control of switches 2 (N1) and 4 (P2) when using a synchronous rectifier to avoid obscuring the present invention. Is not repeated here. Similarly, if a diode, such as a Schottky diode, is used for switches 2 and 4 on the other hand, the following disclosure will typically ignore the voltage drop across the diode for circuit analysis purposes. The resulting slope of the current waveform will be slightly different and will result in other minor variations that are not essential to an understanding of the present invention, but can still be applied to the description of the operation of the present invention. However, it should be noted that if a diode or synchronous rectifier that suppresses negative current is used, the converter of the present invention requires a minimum load to maintain the regulated value.

  1 and 2 show four switches P1, P2, N1 and N2, such as in a synchronous rectifier. In normal PWM operation of certain preferred embodiments of the present invention, switch N1 is on when switch P1 is off, and switch N1 is off when switch P1 is on, ie, N1 = / P1. (Note: In this specification, “/” means the upper bar). Similarly, when the switch N2 is off, the switch P2 is on, and when the switch N2 is on, the switch P2 is off, that is, P2 = / N2. Thus, the method of the present invention will be described with respect to the control of switches P1 and N2, assuming N1 = / P1, P2 = / N2, unless otherwise noted. However, the present invention is responsive to the current through switches N1 and N2, and therefore, in the preferred embodiment, each of these switches has current sensing circuits CSN1 and CSN2 (generally more common than the current through the respective switch). Supply a proportional current to the controller. In a preferred embodiment, each current sensing circuit is a current mirror so that the current sense signal to the controller is approximately proportional to the current through each switch, even though the voltage across the switch is a non-linear function of the current through that switch. It is a form. Also shown in FIG. 2 as additional inputs to the controller are the feedback FB of the output voltage divided by the voltage dividers R1, R2, and the reference voltage Vref.

  FIG. 1 illustrates three combinations of switch settings for switches P1 and N2 of FIGS. 1 and 2, referred to herein as Φ1, Φ2, Φ3, or phases 1, 2, and 3. Φ1 is identified as “fast L charge” and means increasing the current through the inductor L at high speed. In this current path, the switches P1 and N2 are closed, that is, energized, and are simply indicated by P1N2. Here, the charging speed is di / dt = VIN / L (ignoring the voltage drop of the switch). Since neither switch N1 or P2 is in series with this current path, the use of diodes for switches N1 and P2 does not change this rate of increase of the current in inductor L.

Current path Φ2 is identified as a “slow inductor charge” current path. In this current path, the switch P1 is closed and the switch N2 is open, and will be denoted by P1 / N2 below. In this case, the current accumulation speed of the inductor L is di / dt = (V _in −V _out ) / L. This energization path is expressed as “low speed L charging”. When V _IN = V _out , di / dt passing through the inductor L becomes zero, and when V _IN <V _out , di / dt is actually negative. Note that in the preferred embodiment, it may be negative. When diodes or equivalent synchronous rectifiers are used, the current cannot be negative because they are either blocked by the respective synchronous rectifier being turned off or by the respective diode. Similarly, of course, if the switch P2 is actually a diode, di / dt through the inductor L becomes zero when V _IN -diode voltage drop = V _out .

The third path denoted by Φ3 is denoted as “fast L discharge”. This current path is characterized by both switches P1 and N2 being open, ie / P1 / N2. In this case, the rate of change of current through the inductor L is di / dt = −V _out / L, which can be negative in the preferred embodiment. Again, diodes or equivalent synchronous rectifiers prevent reverse current flow when they are used. In this regard, when switch P2 is a diode, di / dt = − (V _out + diode forward voltage drop) / L. The effect of the forward current drop on the diode, synchronous rectifier, or even switches N1 and P2 can be easily assessed by those skilled in the art, but is further considered for clarity in the following disclosure. No (except for current sensing purposes).

  One aspect of the invention is that the circuit operates in the same mode regardless of whether the input voltage is higher than the output voltage (buck) or the input voltage is lower than the output voltage (boost). These three modes of operation are illustrated in the state diagrams of FIGS. 3a, 4a and 5a. In FIG. 3a, the controller cycles through Φ1, Φ2, Φ3, Φ2, Φ1, Φ2, Φ3, Φ2. The transition from Φ2 to Φ1 and Φ3 to Φ2 is clocked, but the transition from Φ1 to Φ2 occurs when the current IN2 is greater than the current control filter output (FIG. 6) or when the current IN2 is the current control filter output. If the current IN1 is smaller than the current control filter output, or the current IN1 is already smaller than the current control feeder output, the transition from Φ3 to Φ2 and Φ3 occurs Occurs after a minimum time. In these drawings, “/ (tmin) and” means that the second condition has been satisfied or has been satisfied since the minimum time has passed. In this regard, it should be understood that such a relative measure is usually applicable after normalization if the currents are expressed as equal, large and small. As an example, comparators Comp A and Comp B in the current control circuit of FIG. 5 compare the current sense outputs of CSN1 and CSN2, which are proportional to the amplitude of the actual currents of N1 and N2, but far small.

  In FIG. 4a, the controller circulates in the order of Φ1, Φ2, Φ3, Φ1, Φ2, Φ3, Φ1,..., And in FIG. 5a, the controller has Φ3, Φ2, Φ1, Φ3, Φ2, Φ1,. Cycle in order. At the same peak current, the control algorithm of FIG. 4a is more efficient at transmitting a regulated power supply to the output, and therefore this embodiment is an exemplary implementation in the following detailed description of the operation of the present invention. I will use it as a form. However, in all three cases, the algorithm used is fixed regardless of whether the output voltage is lower or higher than the supply voltage.

  Various embodiments of the present invention use current mode correction or current control. A block diagram of the current control used with the preferred embodiment of the present invention is shown in FIG. As shown in this figure, the feedback voltage FB from the voltage dividers R1 and R2 in FIG. 2 is compared with the reference voltage REF (FIG. 6) by the transconductance amplifier E-AMP, and the current output of the transconductance amplifier E-AMP is Filtered by a filter and subsequently coupled to correction circuits COMP A and COMP B. These correction circuits respond to the phase 3 (Φ3) current at N1 and the phase 1 (Φ1) current at N2, respectively, and the outputs of the comparators COMP A and COMP B are supplied to the phase control logic. FIG. 7 shows a filter circuit for the filter of FIG.

  The operation of the circuit of FIG. 2 using the state diagram of FIG. 4a is illustrated in FIGS. 8 and 9 show the respective operations when the input voltage exceeds the output voltage and when the input voltage is smaller than the output voltage. 10 and 11 illustrate the skip capability of the preferred embodiment. Specifically, the entry to the skip mode is illustrated in FIG. 10, and the exit from the skip mode is illustrated in FIG. However, before discussing these figures in detail, it should be noted from FIG. 1 that the current in switch N1 is non-zero only during Φ3 and the current in switch N2 is non-zero only during Φ1. Furthermore, for convenience, in the following description, it is assumed that the currents in the directions indicated by Φ1 and Φ3 are positive.

  The operation of the circuit of FIG. 2 according to the embodiment of FIG. 4a will now be described with reference to FIGS. For operating conditions where the input voltage exceeds the converter output voltage, assume that the circuit is in operation and is in the Φ2 state. In this state, since the input voltage exceeds the output voltage, the current passing through the inductor L increases under low-speed charging conditions. When the Φ3 clock is generated in a time period referred to herein as tmin, the controller changes to the Φ3 mode by turning off the switch P1. This causes energization through switch N1, and the current through the inductor decreases relatively rapidly until it falls below the filter current output, changing the output of comparator COMP A, at which point the controller is connected to switch P1 and Switch to Φ1 mode by turning on both N2. As will be understood hereinafter, when the current of the switch N1 is already lower than the filter output current, the switching from Φ3 to Φ1 occurs after the minimum time tmin. In this regard, tmin is preferably chosen as reasonably short as possible while still allowing the circuit to stabilize in a new state for accurate sensing purposes.

  The Φ1 state continues until the current through switch N2 exceeds the current through the filter and changes the output of comparator COMP B, or the current through switch N2 exceeds the current through the filter in less than tmin. In some cases, it will last for the duration (tmin) of the Φ1 pulse, after which the controller will switch back to Φ2 by turning off switch N2. Again, the inductor L current increases at a slow charge rate until the next Φ3 clock pulse, at which point the cycle is repeated. Thus, there are two decision points: decision A where the current in switch N1 drops and falls below the filter output current, and decision B where the current in switch N2 increases and exceeds the filter output current.

  FIG. 9 illustrates the operation of the controller when the input voltage is lower than the output voltage. Note that the operation is the same in the sense that the phases are similarly arranged, ie, Φ1, Φ2, Φ3, Φ1, Φ2, Φ3, Φ1, etc. The main difference is the waveform and duration of Φ3 and Φ1. Specifically, the current through the inductor L during Φ2 actually decreases, and when switching from Φ2 to Φ3, the current in the switch N1 becomes less than the filter output current. Therefore, the duration of Φ3 is held at tmin, the duration of the subsequent Φ1 operation exceeds tmin, and the current of the switch N2 can be increased to the filter output current.

  At a light load of the converter, as shown in FIG. 10, even if the output voltage of the converter remains above the target adjustment voltage (overvoltage), the current of the switch N1 can become zero during Φ3. At light or no load, the feedback FB (FIG. 6) may exceed the reference voltage REF and produce a negative current output from the filter. Therefore, the current in switch N1 still exceeds the filter output even when that current becomes zero. This “zero cross” is sensed by the controller and the clock oscillator is stopped, otherwise the circuit goes into sleep mode (see Discont signal waveform). In the sleep mode, in a preferred embodiment, switches N1 and N2 are on, switch P2 is off, and return current flow from the load is interrupted. When the output voltage drops below the regulated voltage and the overvoltage condition is eliminated, the clock restarts and begins another Φ1 pulse. However, this pulse is for a fixed time, after which it stays in Φ2 phase until the clock changes phase to Φ3. As illustrated in FIG. 10, the next Φ1, Φ2, Φ3 sequence also produces an output that is higher than the reference voltage REF, the controller senses an overvoltage condition in the middle of the sequence, and the Discount signal is similarly sequenced. The oscillator is stopped at the end of the circuit and the circuit is put into sleep mode until the overvoltage disappears.

  In the light load or no load condition of FIG. 10, each Φ1, Φ2, Φ3 sequence starts with a zero inductor current. When the converter is operating at low or zero inductor current, the controller responds to the output voltage to force initial operation. For example, if a significant load is suddenly applied to the converter during light load (skip) operation (see FIG. 11), the overvoltage condition is eliminated. If this occurs during the Φ1, Φ2, Φ3 sequence, a new sequence will be started. When the Φ1, Φ2, and Φ3 sequences are initiated from a zero inductor current condition, they are forced to the Φ1 phase for a predetermined duration, followed by the Φ2 phase until the next clock pulse. When the threshold inductor current is established, control returns to the control described with respect to FIGS.

  If the output voltage exceeds the input voltage and the overvoltage condition is cleared after skip mode, the long Φ1 and tminΦ3 are imposed first, but the operation is similar, after which the control is described with respect to FIGS. Return to the controlled mode. However, in all cases, the sequence of operations is the same, i.e., Φ1, Φ2, Φ3, Φ1, Φ2, Φ3, Φ1,. In this regard, the foregoing represents the preferred method of skip termination, but other methods are possible.

  The overall operation of the converter of FIG. 4a is shown in the more detailed state diagram of FIG. In this figure, an ON signal in the form of a logic high (LH or “true”) signal turns on the power supply of the converter. When the bias voltage and reference voltage are stable, a fast charge or phase 1 cycle is initiated. Fast charging lasts until the output of COMP B switches (FIG. 7), after which the converter switches to slow charging or phase 2 until the clock signal switches the converter to phase 3. On the other hand, if this clock signal is generated before the fast charge changes the state of the COMP B output, the clock signal will be directly changed from phase 1 to phase 3. As a result, phase 3 persists until COMP A (FIG. 6) changes state to cause the converter to fast charge or return to phase 1. On the other hand, if an overvoltage exists at the end of phase 3, hold is started until such time as the overvoltage condition is cleared, then fast charge or phase 1 is resumed. When exiting the hold condition, it is forced to fast charge or phase 1 state for a fixed or predetermined time interval, followed by phase 2 state, and after a further predetermined time, the clock starts phase 3 state. Exiting from skip or hold mode is the same whether the input voltage is above the output voltage or whether the input voltage is operating below the output voltage. However, if the input voltage is less than the output voltage, fast charge or phase 1 is held for a longer predetermined time before switching to phase 2, which of course will be shortened by the generation of clock pulses. . The goal here is to keep the waveform the same as a conventional PWM controller operating under the same conditions.

  The converter also preferably has a peak current limit in fast charge or phase 1 to slow charge or phase 2 switching. Normally, this peak current is set outside the normal operating range of the converter, but this peak current limit may be reached in the case of an abnormal load such as a short circuit. In the preferred embodiment, the arrival of the peak current starts a timer that essentially gives the system a fixed time to reach the regulation value, after which the system stops until a new start signal is received. Thus, by way of example, in the case of a short circuit, when this peak current is reached at start-up, the circuit will immediately stop again, and the sequence for each successive start signal will continue until it is started after the short circuit has been corrected. repeat. This is just one example of how to handle such abnormal loads without damaging the converter components.

  In the types of circuits described above, there are practical restrictions on the amount of voltage that the input voltage can fall below the output voltage. In battery-operated systems, a particularly low input voltage means that the battery is near full discharge and there is little energy available. Also, if the input voltage drops below the output voltage, the converter needs to stay in fast charge or phase 1 state for most of the time, increasing the ratio of peak current to average output current up to efficiency loss, Limit the average output current of the converter if it should not exceed the peak current. Accordingly, the preferred embodiment includes input voltage sensing and provides an undervoltage lockout (UVLO) to inhibit activation if the supply voltage is too low. The preferred embodiment also includes a soft starting capability by limiting the current in switch P1 to the starting lamp, and in the preferred embodiment, the lamp consists of a small ramp up to the operating current level.

  When the description of the operation of the state diagram of FIG. 4a is complete, the operation of FIGS. 3a and 5a becomes apparent. In this regard, soft start, undervoltage lockout, entering and exiting sleep mode when an overvoltage condition exists after the inductor current goes to zero during phase 3, and predetermined after the inductor current limit is reached The automatic stop when the regulator does not reach the regulation value in time can be the same in all three embodiments. In addition, although clock control between specific phases is illustrated, in some cases, clock control between other phases (other decision points) may be used instead.

Respect Comparison of three methods of operation, FIG. 3b, 4b, 5b presents a comparison in V _out = V _in. This is a convenient comparison point because the present invention often operates near this condition. In all three cases, of course, the current during phase 2 is constant. However, since the method of FIG. 3a goes from phase 3 to phase 2, the current during one of the phase 2 operations is smaller than during the single phase 2 of the method of FIG. 4a. For the same inductance, frequency, peak current, and gate drive, the embodiment of FIG. 4a provides an average current of approximately 16% higher to the load. In the embodiment of FIG. 5a, the converter makes a direct transition from phase 1 to phase 3, eliminating the operation of the second phase 2, which is a highly efficient phase in supplying current to the load in the embodiment of FIGS. 3a, 3b. . Thus, for the same inductance, frequency, peak current, and gate drive, the embodiment of FIGS. 5a and 5b supplies a smaller average current to the load than the embodiment of FIGS. 3a and 3b. However, this embodiment still retains certain advantages of the present invention including, but not limited to, having an input voltage that is higher and lower than the output voltage without changing the mode.

  Thus, the present invention uses a simple control algorithm without mode change, and also provides good transient response, low current ripple over the Vin / Vout range, and low element stress over the Vin / Vout range. can do. While certain preferred embodiments of the invention have been disclosed and described herein for purposes of illustration and not limitation, various changes in form and detail may be made without departing from the spirit and scope of the invention. Those skilled in the art will appreciate the benefits.

It is a figure showing the general purpose H bridge circuit which can be used as a buck boost DC-DC converter. It is a block diagram of the present invention. It is a state diagram of one embodiment of the present invention. FIG. 3b is a diagram illustrating charging supply to the regulator output in one operating cycle according to the state diagram of FIG. 3a operating at an input voltage equal to the output voltage. FIG. 6 is a state diagram of another embodiment of the present invention. FIG. 4b illustrates the charging supply to the regulator output in one operating cycle according to the state diagram of FIG. 4a operating at an input voltage equal to the output voltage. FIG. 6 is a state diagram of still another embodiment of the present invention. FIG. 5b is a diagram illustrating charging supply to the regulator output in one operating cycle according to the state diagram of FIG. 5a operating at an input voltage equal to the output voltage. FIG. 4 is a block diagram of current control used with a preferred embodiment of the present invention. It is a circuit diagram of the filter used in the current control of FIG. 4b illustrates the operation of the embodiment of FIG. 4a when the input voltage exceeds the output voltage. 4b illustrates the operation of the embodiment of FIG. 4a when the input voltage is lower than the output voltage. It is a figure which illustrates approach to skip mode. It is a figure which illustrates leaving from skip mode. FIG. 4b is a more complete state diagram of the embodiment of FIG. 4a.

Explanation of symbols

1, 2, 3, 4 switches

Claims (28)

A control method for a step-up / step-down switching regulator, the regulator comprising:
An inductor with first and second conductors;
A first switch (P1) for controllably coupling the first conductor to a power source;
A second switch (N2) for controllably coupling the second conductor to a circuit ground ;
A third switch (N1) between the first conductor and the circuit ground, for energizing the first conductor from the circuit ground;
A fourth switch (P2) between the second conducting wire and the regulator output unit for energizing current from the second conducting wire to the regulator output unit;
And the third switch is on if the first switch is off and off if the first switch is on, and the fourth switch is the second switch Configured to be on if the switch is off and off if the second switch is on ,
The control method of the regulator is
When the power supply has a voltage that exceeds the regulator output, for step-down, the switches are operated in a sequence including phase 1, phase 2, and phase 3 as elements, and the power supply is connected to the regulator. When having a voltage lower than the output, for the purpose of step-up, the switches include operating the same sequence as described above, including phase 1, phase 2, and phase 3 as elements .
In phase 1 above, both the first and second switches are closed, while in phase 2, the first switch is closed, the second switch is open, and in phase 3 , Both the first and second switches are open ,
Current mode correction, ie
The transition from phase 1 occurs depending on the current of the second switch (N2) and the minimum time of phase 1 ,
The transition from phase 2 is clocked ,
The transition from phase 3 occurs depending on the current of the third switch (N1) and the minimum time of phase 3 ;
A method characterized in that current mode correction is used .   The method of claim 1, wherein the sequence of phases returns to phase 1, phase 2, phase 3, phase 2, then phase 1 and repeats the sequence. The method of claim 2, wherein the phase 2 to phase 3 transition and the phase 2 to phase 1 transition are clocked transitions. The transition from the phase 1 to the phase 2, in that when the current through the second switch exceeds the output of the current-mode filter, occur if already elapsed since the minimum time, the course of the minimum time if current through the second switch before that exceeds the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The transition from the phase 3 to the phase 2, in that when the current through the third switch Tsu falls below the output of the current-mode filter, occur if already elapsed since the minimum time, the minimum time that if prior to the expiration of the current through the third switch falls below the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The method according to claim 3. The phase sequence returns to phase 1, phase 3, phase 2, then back to phase 1 and repeats the sequence;
The method according to claim 1. The transition from phase 2 to phase 1 is a clocked transition,
6. The method of claim 5, wherein: The transition from the phase 1 to the phase 3, the point when the current through the second switch Tsu exceeded the output of the current-mode filter, occur if already elapsed since the minimum time, the minimum time that if current through the second switch before the elapse of that exceeds the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The transition from the phase 3 to the phase 2, in that when the current through the third switch Tsu falls below the output of the current-mode filter, occur if already elapsed since the minimum time, the minimum time that if current prior to the expiration of through the third switch that falls below the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The method according to claim 6. The phase sequence returns to phase 1, phase 2, phase 3, then back to phase 1 and repeats the sequence;
The method according to claim 1. The transition from phase 2 to phase 3 is a clocked transition,
The method according to claim 8, wherein: The transition from the phase 1 to the phase 2, the the point when the current through the second switch Tsu exceeded the output of the current-mode filters, occurs when already after the lapse of a minimum time, the minimum time if current through the second switch before the elapse of that exceeds the output equally Do Rukasono output of the current-mode filter generated in the elapse of the minimum time,
The transition from the phase 3 to the phase 1, the point when the current through the third switch Tsu falls below the output of the current-mode filters, occurs when already after the lapse of a minimum time, minimum time that current through the third switch occurs at the elapse of the current mode the minimum time if Do Rukasono was of the below output equal to the output of the filter before the elapse of
The method of claim 9. The inductor current goes to zero during phase 3, the regulator output exceeds the regulated value, and the regulator is placed in sleep mode until the regulator output falls below the regulated value.
The method according to claim 1. The regulator output, said reduced in the sleep mode than the adjustment value, and the operation of the phase 1 is initiated Ri cotton in a predetermined length of time, changes in the phase 2,
The method according to claim 11, wherein: The method further comprises shutting down the regulator if the regulator output fails to reach a regulated voltage within a predetermined time after a current limit for the current through the inductor is reached. Item 2. The method according to Item 1.   The method of claim 13, further comprising blocking operation of the regulator when the voltage of the power source is lower than a predetermined voltage. A method for controlling a step-up / step-down switching regulator comprising:
The provided inductor having first and second conductors,
Providing a first switch (P1) for controllably coupling the first conductor to a power source;
Providing a second switch (N2) for controllably coupling the second conductor to a circuit ground ;
A third switch (N1) is provided between the first conductor and the circuit ground, and is used to pass current from the circuit ground to the first conductor.
A step of providing a fourth switch (P2) between the second conductor and the regulator output unit for energizing current from the second conductor to the regulator output unit;
The third switch is on if the first switch is off and off if the first switch is on, and the fourth switch is off if the second switch is off. If it is on and the second switch is on, it is off .
When the power supply has a voltage that exceeds the regulator output, for step-down, the switches are operated in a sequence including phase 1, phase 2, and phase 3 as elements, and the power supply is connected to the regulator. When having a voltage lower than the output, for the purpose of step-up, the switches include operating the same sequence as described above, including phase 1, phase 2, and phase 3 as elements .
In phase 1 above, both the first and second switches are closed, while in phase 2, the first switch is closed, the second switch is open, and in phase 3 , Both the first and second switches are open ,
Current mode correction, ie
The transition from phase 1 occurs depending on the current of the second switch (N2) and the minimum time of phase 1 ,
The transition from phase 2 is clocked ,
The transition from phase 3 occurs depending on the current of the third switch (N1) and the minimum time of phase 3 ;
A method characterized in that current mode correction is used .   The method of claim 15, wherein the sequence of phases returns to phase 1, phase 2, phase 3, phase 2, then phase 1, and the sequence is repeated. The method of claim 16, wherein the phase 2 to phase 3 transition and the phase 2 to phase 1 transition are clocked transitions. The transition from the phase 1 to the phase 2, in that when the current through the second switch exceeds the output of the current-mode filter, occur if already elapsed since the minimum time, the course of the minimum time if current through the second switch before that exceeds the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The transition from the phase 3 to the phase 2, in that when the current through the third switch Tsu falls below the output of the current-mode filter, occur if already elapsed since the minimum time, the minimum time that if prior to the expiration of the current through the third switch falls below the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The method according to claim 17, wherein: The phase sequence returns to phase 1, phase 3, phase 2, then back to phase 1 and repeats the sequence;
The method according to claim 15. The transition from phase 2 to phase 1 is a clocked transition,
20. A method according to claim 19, wherein: The transition from the phase 1 to the phase 3, the point when the current through the second switch Tsu exceeded the output of the current-mode filter, occur if already elapsed since the minimum time, the minimum time that if current through the second switch before the elapse of that exceeds the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
The transition from the phase 3 to the phase 2, in that when the current through the third switch Tsu falls below the output of the current-mode filter, occur if already elapsed since the minimum time, the minimum time that if current prior to the expiration of through the third switch that falls below the output equally Do Rukasono output of the current-mode filter, generated in the course time of the minimum time,
21. The method of claim 20, wherein: The phase sequence returns to phase 1, phase 2, phase 3, then back to phase 1 and repeats the sequence;
The method according to claim 15. The transition from phase 2 to phase 3 is a clocked transition,
23. The method of claim 22, wherein: The transition from the phase 1 to the phase 2, the the point when the current through the second switch Tsu exceeded the output of the current-mode filters, occurs when already after the lapse of a minimum time, the minimum time if current through the second switch before the elapse of that exceeds the output equally Do Rukasono output of the current-mode filter generated in the elapse of the minimum time,
The transition from the phase 3 to the phase 1, the point when the current through the third switch Tsu falls below the output of the current-mode filters, occurs when already after the lapse of a minimum time, minimum time that current through the third switch occurs at the elapse of the current mode the minimum time if Do Rukasono was of the below output equal to the output of the filter before the elapse of
24. The method of claim 23. The inductor current goes to zero during phase 3, the regulator output exceeds the regulated value, and the regulator is placed in sleep mode until the regulator output falls below the regulated value.
The method according to claim 15. The regulator output, said reduced in the sleep mode than the adjustment value, and the operation of the phase 1 is initiated Ri cotton in a predetermined length of time, changes in the phase 2,
26. The method of claim 25. 16. The method of claim 15, further comprising shutting down the regulator if the regulator output fails to reach a regulated voltage within a predetermined time after a current limit for the current through the inductor is reached. . 28. The method of claim 27, further comprising blocking operation of the regulator when the voltage of the power source is lower than a predetermined voltage.

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