[go: up one dir, main page]

JP2004055991A - Wiring board - Google Patents

Wiring board Download PDF

Info

Publication number
JP2004055991A
JP2004055991A JP2002214085A JP2002214085A JP2004055991A JP 2004055991 A JP2004055991 A JP 2004055991A JP 2002214085 A JP2002214085 A JP 2002214085A JP 2002214085 A JP2002214085 A JP 2002214085A JP 2004055991 A JP2004055991 A JP 2004055991A
Authority
JP
Japan
Prior art keywords
corner
insulating layer
cavity
via conductor
radius
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002214085A
Other languages
Japanese (ja)
Inventor
Takeshi Ito
伊藤  猛
Shinji Maehara
前原 信治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2002214085A priority Critical patent/JP2004055991A/en
Publication of JP2004055991A publication Critical patent/JP2004055991A/en
Withdrawn legal-status Critical Current

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board in which a via conductor can be easily arranged at the corner of an insulating layer having a cavity whose inside should be mounted with an electronic component. <P>SOLUTION: This wiring board 1 is provided with a plurality of insulating layers 2 to 5 showing almost rectangles from the point of view of flatness, wiring layers 20 formed on surfaces 2a to 5a of the insulating layers 2 to 5, and a cavity 6 formed inside the insulating layers 2 to 4 from the point of view of flatness. In the insulating layer 2 in the uppermost layer, a diameter R of a curvature 7a applied to the internal corner of the cavity 6 adjacent to the corner through which the via conductor V is put is set so as to be larger than a diameter (r) of the curvature 7b applied to the internal corner of the cavity 6 adjacent to the corner through which the via conductor V is not put. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、内側に水晶振動子などの電子部品を実装するキャビティを内設している配線基板に関する。
【0002】
【従来の技術】
図7(A)および(B)に示す配線基板50は、セラミックなどからなる複数の絶縁層51〜54と、これらの表面および層間に形成した図示しない配線層と、最下層の絶縁層54以外の絶縁層51〜53の平面視で内側に形成したキャビティ55と、を備えている。図7(A),(B)に示すように、最上層の絶縁層51におけるキャビティ55の開口部56は、図示で上下方向の幅が絶縁層52,53におけるキャビティ55の開口部57,58よりも大きく、開口部57の上下には第2層目の絶縁層52の表面52aが横長の段部として露出する。
【0003】
開口部56の4カ所の内隅部には、同じ半径Rのアール59が付されている。尚、キャビティ55の底面には、絶縁層54の表面54aが露出する。
また、図7(A),(B)に示すように、絶縁層51〜54における4カ所の出隅部には、同じ半径rである4分の1円形の湾曲面60が垂直方向に連続して形成される。このうち、最下層の絶縁層54における湾曲面60には、湾曲導体62が形成され、これは、当該絶縁層54の表面54aに形成される図示しない配線層と接続され、且つかかる配線層を介してキャビティ55内に実装される図示しない水晶振動子やSAWフィルタなどの底面に位置する端子と導通される。
【0004】
更に、図7(A),(B)に示すように、絶縁層52〜54において対向する上下辺の中間には、平面視が断面半円形の凹溝64とこれらに被覆した凹溝導体66とがそれぞれ形成されている。これらは、絶縁層52,53の表面52aなどに形成される図示しない配線層と接続され、且つこれらの配線層および図示しないワイヤを介して、キャビティ55内に実装される上記SAWフィルタなどの上面に位置する端子と導通される。
図7(A),(B)に示すように、絶縁層51〜53における対角位置のコーナには、複数のビア導体Vが前記開口部56のアール59および前記湾曲面60に挟まれ、且つ垂直方向に連続して形成される。かかるビア導体Vは、絶縁層51〜54の表面51a,52a,54aなどに位置する配線層間を接続する。
【0005】
【発明が解決すべき課題】
ところで、近年の配線基板の小型化の要請により、絶縁層51などの外形は従前よりも小さくされ、一方、実装すべき電子部品のサイズはあまり変化しないため、キャビティ55の開口部56の寸法は従前と変わらない。この結果、最上層の絶縁層51における各コーナの幅Wが狭くなるため、かかるコーナにビア導体Vやこれを形成するためのビアホールを貫通することが困難化している。
本発明は、以上に説明した従来の技術における問題点を解決し、内側に電子部品を実装するためのキャビティを有する絶縁層のコーナにビア導体を容易に配置できる配線基板を提供する、ことを課題とする。
【0006】
【課題を解決するための手段】
本発明は、最上層の絶縁層におけるキャビティの内隅部の半径や出隅部における4分の1円形の湾曲した凹形部の半径を、ビア導体が貫通するコーナと貫通しないコーナとの間で相違させる、ことに着想して成されたものである。
即ち、本発明の第1の配線基板(請求項1)は、平面視でほぼ矩形を呈する複数の絶縁層と、かかる複数の絶縁層の表面および層間の少なくとも一つに形成される配線層と、少なくとも最上層の上記絶縁層の平面視で内側に形成されるキャビティと、を備え、上記最上層の絶縁層において、ビア導体が貫通するコーナに近接する上記キャビティの内隅部に付すアールの径が、上記ビア導体が貫通しないコーナに近接する上記キャビティの内隅部に付すアールの径よりも大きい、ことを特徴とする。
【0007】
これによれば、上記絶縁層においてビア導体が貫通するコーナでは、キャビティの内隅部に付すアールの径が、ビア導体が貫通しないコーナのキャビティの内隅部に付すアールの径よりも大きくされる。このため、ビア導体が貫通するコーナでは、かかるコーナにおける上記絶縁層の幅が、ビア導体が貫通しないコーナにおける当該絶縁層の幅よりも大きくなる。この結果、かかる幅広のコーナにビアホールおよびビア導体を容易に配置した配線基板とすることができる。従って、かかるビア導体が絶縁層の外側に接近または露出しないと共に、複数の絶縁層の表面や層間に形成される配線層間を確実に導通することができる。
尚、上記絶縁層には、セラミック絶縁層のほか、樹脂絶縁層も含まれる。
【0008】
一方、本発明の第2の配線基板(請求項2)は、平面視でほぼ矩形を呈する複数の絶縁層と、かかる複数の絶縁層の表面および層間の少なくとも1つに形成される配線層と、少なくとも最上層の上記絶縁層の平面視で内側に形成されるキャビティと、を備え、上記最上層の絶縁層において、ビア導体が貫通するコーナの出隅部に設ける断面円弧形の凹形部の径が、上記ビア導体が貫通しないコーナの出隅部に設ける断面円弧形の凹形部の径よりも小さい、ことを特徴とする。
これによれば、上記絶縁層においてビア導体が貫通するコーナでは、その出隅部に設ける断面円弧形の凹形部の径が、ビア導体が貫通しないコーナの出隅部に設ける断面円弧形の凹形部の径よりも小さくされる。これによっても、ビア導体が貫通するコーナでは、かかるコーナにおける上記絶縁層の幅が、ビア導体が貫通しないコーナにおける当該絶縁層の幅よりも大きくなる。従って、かかる幅広のコーナにビア導体を容易に配置した配線基板とすることができる。
【0009】
尚、本発明の前記配線基板は、平面視でほぼ矩形を呈する複数の絶縁層と、かかる複数の絶縁層の表面および層間の少なくとも1つに形成される配線層と、少なくとも最上層の上記絶縁層の平面視で内側に形成されるキャビティと、を備え、上記最上層の絶縁層において、ビア導体が貫通するコーナに近接する上記キャビティの内隅部に付すアールの径が、上記ビア導体が貫通しないコーナに近接する上記キャビティの内隅部に付すアールの径よりも大きいこと、および、上記最上層の絶縁層において、ビア導体が貫通するコーナの出隅部に設ける断面円弧形の凹形導体の径が、上記ビア導体が貫通しないコーナの出隅部に設ける断面円弧形の凹形導体の径よりも小さいこと、の少なくとも一方を保有する、とすることも可能である。
これによれば、上記絶縁層においてビア導体が貫通するコーナでは、キャビティの内隅部に付すアールの径が大きくされ、あるいは、かかるコーナの出隅部に設ける断面円弧形の凹形部の径が小さくされる。特に、キャビティの内隅部に付すアールの径を大きくし且つ出隅部に設ける断面円弧形の凹形部の径を小さくした絶縁層のコーナでは、その幅を更に大きくすることが可能となる。
【0010】
また、本発明は、平面視でほぼ矩形を呈する複数の絶縁層と、かかる複数の絶縁層の表面および層間の少なくとも1つに形成される配線層と、少なくとも最上層の絶縁層の平面視で内側に形成されるキャビティと、を備えた配線基板の製造方法であって、追って上記最上層の絶縁層となる複数の製品エリアを有する絶縁シートにおいて、かかるシート内で複数の製品エリアのコーナが隣接する複数のT字形または十字形境界部に対し、円形の貫通孔を形成し、各製品エリアごとに切断して半円形の凹形部、または4分の1円形の凹形部を形成する工程、を含む、請求項1,2の配線基板の製造方法を含むことも可能である。
これによる場合、複数の配線基板における最上層の絶縁層となる絶縁シートにおいて、前記断面円弧形の凹形導体を形成する凹形部を少ない工数により、効率良く製造できる。従って、電子部品を実装するキャビティを有する配線基板を、小型化の要請に応じつつ確実且つ低コストで提供することが可能となる。
尚、上記絶縁シートには、主にセラミックからなるグリーンシートのほか、合成樹脂からなる樹脂シートも含まれる。
【0011】
【発明の実施の形態】
以下において、本発明の実施に好適な形態を図面と共に説明する。
図1(A)は、本発明による第1の配線基板1における複数の絶縁層2〜5およびこれらの内側に形成したキャビティ6を示す平面図であり、図1(B),(C)は、(A)中のB−B線またはC−C線に沿った矢視の断面図である。
配線基板1は、図1(A)〜(C)に示すように、例えばアルミナを主成分とするセラミックからなり且つ平面視で正方形(矩形)を呈する厚みが数100μmの絶縁層2〜5を積層し、最下層の絶縁層5を除く絶縁層2〜4の内側には、平面視でほぼ矩形のキャビティ6が位置する。上記絶縁層2〜4の表面2a〜5aには、後述する配線層が形成されている。
【0012】
図1(A),(C)に示すように、最上層の絶縁層2におけるキャビティ6の開口部7は、図示で上下方向の幅が絶縁層3,4におけるキャビティ6の開口部8よりも大きく、開口部7の上下には第2層目の絶縁層3の表面3aが横長の段部として露出する。但し、図1(A),(B)に示すように、最上層の絶縁層2におけるキャビティ6の開口部7は、図示で左右方向の幅が絶縁層3,4におけるキャビティ6の開口部8と同じである。尚、キャビティ6の底面には、絶縁層5の表面5aが露出している。かかるキャビティ6内には、水晶振動子やSAWフィルタなどの電子部品18が実装される。
【0013】
図1(A)に示すように、絶縁層2〜5における4カ所の出隅部には、平面視で断面が4分の1円形である円弧形の凹形部10が垂直方向に連続して形成され、そのうちで最下層の絶縁層5の凹形部10には、後述する凹形導体12が形成される。また、図1(A)に示すように、絶縁層3〜5において対向する上下辺の中間には、平面視で断面がほぼ半円形の凹溝14とこれらに被覆した後述する凹形導体16とがそれぞれ形成される。尚、凹形導体12,16は、例えばW、Mo、Ni、Ag、またはPd、あるいはこれらの何れかをベースとする合金の焼結体からなる。
【0014】
図1(A)に示すように、最上層の絶縁層2において、左下と右上との各コーナには、直径が約100μmのビア導体Vが貫通して形成され、かかるビア導体Vは下側の絶縁層3,4にも垂直方向に連続して貫通されている。尚、ビア導体Vも前記同様の金属または合金からなる焼結体である。
最上層の絶縁層2において、ビア導体Vが貫通するコーナに近接するキャビティ6の開口部7の内隅部に付したアール7aの半径(径)Rは、ビア導体Vが貫通しないコーナに近接するキャビティ6の開口部7の内隅部に付したアール7bの半径(径)rよりも大きく設定されている。因みに、絶縁層2におけるキャビティ6の開口部7が3.0mm×3.0mmである場合、上記半径Rは0.4〜0.6mmで且つ半径rは0.15〜0.25mmである。このため、絶縁層2において、ビア導体Vが貫通する左下および右上の各コーナの幅は、ビア導体Vが貫通しない左上および右下の各コーナの幅よりも大きくなっている。従って、かかるコーナにビア導体Vを精度良く確実に貫通して配置することができる。
【0015】
図2は、前記配線基板1を形成する絶縁層2〜5の斜視図である。最上層の絶縁層2は、図2に示すように、キャビティ6の開口部7を囲む表面2aの全体を接地用配線層20がベタ状に覆っている。かかる配線層20は、接地回路として機能するほか、キャビティ6内に前記電子部品18を実装した後で、その上に平面視で正方形の図示しない金属枠をロウ付けするためのものでもあり、かかる金属枠の開口部を図示しない蓋板で密閉することにより、実装した電子部品18を密封することができる。また、上記配線層20には、対角位置のビア導体V,Vが接続している。
尚、上記金属枠を省略し、配線層20に直に蓋板をロウ付けしても良い。また、配線層20および以下の各配線層も、前記金属または合金の焼結体である。
図2に示すように、第2層および第3層の絶縁層3,4は、キャビティ6の開口部8の周囲の表面3a,4aに、所定パターンを有する信号用の配線層21〜28,31〜38が形成されている。このうち、配線層23,26,33,36は、それらの外側において、隣接する凹形導体16と個別に接続されている。
【0016】
上記絶縁層3,4における対角位置のコーナには、前記同様のビア導体V,Vが貫通している。このうち、絶縁層3を貫通するビア導体Vは、前記配線層20と配線層34,35とを接続し、絶縁層4を貫通するビア導体Vは、配線層34,35と次述する配線層40の接続部42とを接続する。
図2に示すように、最下層の絶縁層5の表面5aにおける中央付近には、平面視がほぼ矩形で電源用の配線層40がベタ状に形成され、その四隅には、当該絶縁層5における4カ所の出隅部にそれぞれ位置する凹形導体12と個別に接続する接続部42が放射状に形成されている。上記ベタ状の配線層40には、前記電子部品18の底面に位置する端子が図示しないロウ材を介して接続される。
【0017】
前記配線基板1は、次のような工程を経て製造される。
先ず、図3(A)に示すように、例えばアルミナを主成分とし有機バインダを含むグリーンシート(絶縁シート)Sを複数枚用意する。かかるグリーンシートS中の破線は、追って切断するための切断線を示し、1枚のグリーンシートSで、追って前記絶縁層2となる製品エリアsを4個を併有している。
次に、図3(B)に示すように、隣接する複数の製品エリアs,s間におけるT字形境界または十字形境界に対し、各部位ごとに専用の径による円形の貫通孔hを、レーザ加工またはメカニカルパンチにより穿孔する。
次いで、図3(C)に示すように、複数の製品エリアs,sごとにおける所定の位置に上記同様の方法にて、直径が約100μmのビアホールvhを穿孔する。
【0018】
更に、図3(D)に示すように、複数の製品エリアs,sごとにおける中央寄りの位置を所定の断面形状を有する打ち抜き型でパンチングすることにより、追って前記キャビティ6の一部となる開口部7が形成される。この際、かかる開口部7の内隅部に前記半径Rおよび半径rのアール7a,7bが形成されるような打ち抜き型を用いる。
次に、ビアホールvh内にWなどの金属粉末を含む導電性ペーストをマスク印刷により充填した後、製品エリアsの表面全体にも同様のペーストをスクリーン印刷により形成する。この結果、ビアホールvh内にはビア導体Vが、各製品エリアsの表面には配線層20が形成される。
そして、グリーンシートSを破線に沿って切断することにより、図3(E)に示すように、最上層の絶縁層2用のグリーンシートS2が4枚得られる。この際、前記貫通孔hは、かかるシートS2の四隅における4分の1円形の凹形部10、またはシートS2の上下辺の中間に位置する半円形の凹形部14となる。
【0019】
また、前記絶縁層3,4用のグリーンシートS3,4Sも、図3(A)〜(E)の方法と同様にして形成される。尚、シートS3,4Sの凹形部14となる貫通孔hの内壁にも導電性ペーストを形成しておく。
更に、前記最下層の絶縁層5用のグリーンシートS5は、前記グリーンシートSに円形の貫通孔hを穿孔し、その表面に導電性ペーストをスクリーン印刷によりベタ状にして形成した後、前記破線に沿って切断することで得られる。尚、シートS5の凹形部10,14の内壁にも導電性ペーストを形成しておく。
そして、図4(A)〜(C)に示すように、グリーンシートS2〜S5を圧着しつつ積層した後、図示しない焼成炉内に挿入し、800〜1400℃に約0.5〜6時間加熱して焼成する。この結果、図1(A)および図4(A)〜(C)に示すように、前記配線基板1を効率良く確実に得ることができる。
【0020】
図5(A),(B)は、本発明による第2の配線基板1aに関する。尚、以下において、前記の形態と共通する部分や要素には共通する符号を用いる。
配線基板1aも、図5(A),(B)に示すように、絶縁層2〜5を積層し、最下層の絶縁層5を除く絶縁層2〜4の内側には、前記と同じキャビティ6が位置する。上記絶縁層2〜4の表面2a〜5aには、配線層20などが前記同様に形成されている。図5(A)に示すように、最上層の絶縁層2において、ビア導体Vが貫通する左下および右上の各コーナの出隅部に設ける断面が4分の1円形である円弧形の凹形部11の半径(径)dは、ビア導体Vが貫通しない左上および右下の各コーナの出隅部設ける凹形部10の半径(径)Dよりも小さくされている。
因みに、最上層の絶縁層2におけるキャビティ6の開口部7のサイズが3.0mm×3.0mmである場合、上記半径dは0.15〜0.25mmで且つ半径Dは0.3〜0.4mmである。
【0021】
即ち、配線基板1aでは、図5(A)に示すように、最上層の絶縁層2におけるキャビティ6の開口部7における4カ所の内隅部を全て半径rのアール7bとして小さくするが、ビア導体Vが貫通するコーナの出隅部に設ける凹形部11の半径dを小さくすることにより、当該コーナにおける幅を広く確保できる。このため、ビア導体Vを精度良く確実に貫通させることができる。
しかも、配線基板1aによれば、キャビティ6の開口部7をも広く取れるため、第2層の絶縁層2の表面2a上に露出する配線層21〜28の面積を確保できる。この結果、信号用の配線層21〜28とキャビティ6内に実装される電子部品の上面に位置する端子とを接続するワイヤのボンディング操作も容易となる。
【0022】
図6(A),(B)は、配線基板1,1aの応用形態の配線基板1bに関する。
配線基板1bは、図6(A),(B)に示すように、絶縁層2〜5を積層し、最下層の絶縁層5を除く絶縁層2〜4の内側には、前記と同じキャビティ6が位置する。上記絶縁層2〜4の表面2a〜5aには、配線層20,40などが前記同様に形成されている。
図6(A)に示すように、最上層の絶縁層2において、ビア導体Vが貫通する左下と右上とのコーナに近接するキャビティ6の開口部7の内隅部に付したアール7aの半径Rは、ビア導体Vが貫通しないコーナに近接するキャビティ6の開口部7の内隅部に付したアール7bの半径rよりも前記同様に大きくされている。
【0023】
同時に、ビア導体Vが貫通する左下および右上の各コーナの出隅部に設ける断面が4分の1円形である円弧形の凹形部11の半径dは、ビア導体Vが貫通しない左上および右下の各コーナの出隅部設ける凹形部10の半径Dよりも前記同様に小さくされている。
即ち、配線基板1bでは、図6(A)に示すように、最上層の絶縁層2において、ビア導体Vが貫通するコーナに近接するキャビティ6の内隅部の半径Rを大きくし、且つ同じコーナの出隅部に設ける凹形部11の半径dを小さくすることにより、かかるコーナにおける幅を一層大きく取ることができる。このため、そのコーナにおいて、ビア導体Vを容易且つ確実に貫通させ、上下の配線層20などの導通を確実に取ることができる。尚、配線基板1bにおける上述したコーナでは、2つのビア導体Vを平行に貫通させることも可能である。
【0024】
本発明は、以上において説明した各形態に限定されるものではない。
ビア導体Vが貫通するコーナは、前記絶縁層2における対角位置のコーナに限らず、同じ一辺の両端におけるコーナや、3カ所のコーナに配置しても良い。
また、キャビティ6の内隅部に付すアール7a,7bや絶縁層2の出隅部に設ける凹形部10,11の半径R,r,d,Dは、4分の1の円形を描く一定値に限らず、偏平な4分の1の楕円形を描くような変数値にすることも可能である。
更に、前記絶縁層2〜5には、アルミナのほか、チタン酸バリウム、ムライト、窒化アルミニウム、ガラスセラミック、低温焼成セラミックなどのセラミックを適用しても良い。
【0025】
あるいは、前記絶縁層2〜5には、エポキシ、ポリエステル、ポリイミド、ビスマレイミド・トリアジンなどの合成樹脂や、これらにガラスフィラあるいはガラスクロスなどの無機フィラや無機繊維を含有させた複合材を適用しても良い。かかる樹脂や複合材からなる絶縁層2〜5を用いる場合、前記配線層20など、凹形導体12,16、およびビア導体Vは、例えば銅メッキを用いて形成したり、配線パターンを形成するために公知のフォトリソグラフィ技術を用いる。更に、上記樹脂などからなる絶縁層2〜5は、打ち抜き加工を含むプレス加工により所定の形状に成形された後で、接着剤を介して積層される。
加えて、前記キャビティ6内に実装する電子部品は、前記水晶振動子やSAWフィルタに限らず、チップコンデンサ、チップインダクタ、抵抗、フィルタなどの受動部品や、トランジスタ、半導体素子、FET、ローノイズアンプ(LNA)などの能動部品も含まれ、あるいはLCフィルタ、アンテナスイッチモジュール、カプラ、ダイプレクサ、半導体集積回路なども含まれる。しかも、同種または異種の複数の電子部品を前記配線基板の同じキャビティ内に併せて実装することも可能である。
【0026】
【発明の効果】
以上に説明した本発明の配線基板(請求項1,2)によれば、キャビティを内設する最上層の絶縁層において、ビア導体が貫通するコーナでは、かかるコーナにおける上記絶縁層の幅が、ビア導体が貫通しないコーナにおける当該絶縁層の幅よりも大きくなる。従って、かかる幅広のコーナにビア導体を容易に配置した配線基板とすることができる。
【図面の簡単な説明】
【図1】(A)は本発明による第1の配線基板の概略を示す平面図、(B),(C)は(A)中のB−B線またはC−C線に沿った矢視の断面図。
【図2】図1の配線基板の分解斜視図。
【図3】(A)〜(E)は図1の配線基板の製造工程を示す概略図。
【図4】(A)は図3(E)に続く製造工程または得られた図1の配線基板を示す斜視図、(B),(C)は(A)中のB−B線またはC−C線に沿った矢視の断面図。
【図5】(A),(B)は本発明による第2の配線基板を示す平面図または斜視図。
【図6】(A),(B)は図1と図5の配線基板の応用形態を示す平面図または斜視図。
【図7】(A),(B)は従来の配線基板の概略を示す平面図または斜視図。
【符号の説明】
1,1a,1b…………………配線基板
2〜5……………………………絶縁層
2a〜5a………………………表面
6…………………………………キャビティ
7a,7b………………………アール
10,11………………………凹形部
20〜28,31〜38,40…配線層
V…………………………………ビア導体
R,r,D,d…………………半径(径)
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board having a cavity in which an electronic component such as a crystal unit is mounted inside.
[0002]
[Prior art]
The wiring board 50 shown in FIGS. 7A and 7B has a plurality of insulating layers 51 to 54 made of ceramic or the like, a wiring layer (not shown) formed on the surface and between the layers, and a layer other than the lowermost insulating layer 54. And a cavity 55 formed inside the insulating layers 51 to 53 in plan view. As shown in FIGS. 7A and 7B, the opening 56 of the cavity 55 in the uppermost insulating layer 51 has openings 57, 58 of the cavity 55 in the insulating layers 52, 53 in the vertical direction. The surface 52a of the second insulating layer 52 is exposed above and below the opening 57 as a horizontally long step.
[0003]
The four corners of the opening 56 are provided with a radius 59 having the same radius R. The surface 54a of the insulating layer 54 is exposed at the bottom of the cavity 55.
Further, as shown in FIGS. 7A and 7B, a quarter circular curved surface 60 having the same radius r is continuously formed in the four corners of the insulating layers 51 to 54 in the vertical direction. Formed. Among these, a curved conductor 62 is formed on the curved surface 60 of the lowermost insulating layer 54, and is connected to a wiring layer (not shown) formed on the surface 54 a of the insulating layer 54. Conduction is made to the terminal located on the bottom surface of the not-shown quartz oscillator or SAW filter mounted in the cavity 55 through the cavity.
[0004]
Further, as shown in FIGS. 7 (A) and 7 (B), a concave groove 64 having a semicircular cross section in plan view and a concave groove conductor 66 covering them are provided between the upper and lower sides of the insulating layers 52 to 54 facing each other. Are formed respectively. These are connected to wiring layers (not shown) formed on the surfaces 52a and the like of the insulating layers 52 and 53, and the upper surface of the SAW filter and the like mounted in the cavity 55 via these wiring layers and wires (not shown). Is electrically connected to the terminal located at.
As shown in FIGS. 7A and 7B, a plurality of via conductors V are sandwiched between the radius 59 of the opening 56 and the curved surface 60 at diagonal corners of the insulating layers 51 to 53. And it is formed continuously in the vertical direction. The via conductor V connects between wiring layers located on the surfaces 51a, 52a, 54a and the like of the insulating layers 51 to 54.
[0005]
[Problems to be solved by the invention]
By the way, due to the recent demand for miniaturization of the wiring board, the outer shape of the insulating layer 51 and the like is made smaller than before, while the size of the electronic component to be mounted does not change much. Same as before. As a result, the width W of each corner in the uppermost insulating layer 51 is reduced, so that it is difficult to penetrate the via conductor V and the via hole for forming the via conductor V in the corner.
The present invention solves the problems in the conventional technique described above, and provides a wiring board that can easily arrange via conductors in corners of an insulating layer having a cavity for mounting electronic components inside. Make it an issue.
[0006]
[Means for Solving the Problems]
The present invention relates to a method of measuring the radius of the inner corner of the cavity and the radius of the quarter-curved concave portion at the outer corner of the uppermost insulating layer between the corner where the via conductor penetrates and the corner where the via conductor does not penetrate. It is made with the idea of making the difference.
That is, the first wiring board of the present invention (claim 1) includes a plurality of insulating layers having a substantially rectangular shape in a plan view, and a wiring layer formed on at least one of the surfaces and the layers of the plurality of insulating layers. A cavity formed at least inside the uppermost insulating layer in a plan view, and in the uppermost insulating layer, an inner corner of the cavity near a corner through which a via conductor penetrates. The diameter is larger than the diameter of a radius provided at an inner corner of the cavity close to a corner through which the via conductor does not penetrate.
[0007]
According to this, at the corner through which the via conductor penetrates in the insulating layer, the radius of the radius at the inner corner of the cavity is larger than the radius of the radius at the inner corner of the cavity of the corner through which the via conductor does not penetrate. You. For this reason, at the corner through which the via conductor penetrates, the width of the insulating layer at such a corner becomes larger than the width of the insulating layer at the corner where the via conductor does not penetrate. As a result, a wiring board in which via holes and via conductors are easily arranged in such a wide corner can be obtained. Therefore, the via conductor does not approach or be exposed to the outside of the insulating layer, and the conduction between the wiring layers formed on the surfaces of the plurality of insulating layers and between the layers can be ensured.
Note that the insulating layer includes a resin insulating layer in addition to the ceramic insulating layer.
[0008]
On the other hand, a second wiring board (Claim 2) of the present invention includes a plurality of insulating layers having a substantially rectangular shape in a plan view, and a wiring layer formed on at least one of the surfaces and the layers of the plurality of insulating layers. A cavity formed at least inside the uppermost insulating layer in plan view, wherein the uppermost insulating layer has an arc-shaped cross section provided at a protruding corner of a corner through which a via conductor passes. The diameter of the portion is smaller than the diameter of a concave portion having an arc-shaped cross section provided at a protruding corner of a corner through which the via conductor does not penetrate.
According to this, in the corner through which the via conductor penetrates in the insulating layer, the diameter of the concave portion of the circular cross section provided at the protruding corner is smaller than the cross sectional arc provided at the protruding corner of the corner through which the via conductor does not penetrate. The diameter of the concave portion of the shape is made smaller. This also makes the width of the insulating layer at the corner where the via conductor penetrates larger than the width of the insulating layer at the corner where the via conductor does not penetrate. Therefore, it is possible to provide a wiring board in which via conductors are easily arranged in such a wide corner.
[0009]
The wiring board according to the present invention includes a plurality of insulating layers having a substantially rectangular shape in a plan view, a wiring layer formed on at least one of the surfaces and interlayers of the plurality of insulating layers, and at least the uppermost insulating layer. A cavity formed inside the layer in a plan view, wherein, in the uppermost insulating layer, a radius of an inner corner of the cavity adjacent to a corner through which the via conductor penetrates, The diameter is larger than the radius of the radius provided at the inner corner of the cavity adjacent to the corner that does not penetrate, and an arc-shaped recess provided at the outer corner of the corner through which the via conductor penetrates in the uppermost insulating layer. The diameter of the shaped conductor may be smaller than the diameter of the concave conductor having an arc-shaped cross section provided at the corner of the corner where the via conductor does not penetrate.
According to this, at the corner through which the via conductor penetrates in the insulating layer, the radius of the radius provided at the inner corner of the cavity is increased, or the arc-shaped concave portion provided at the outer corner of the corner is formed. The diameter is reduced. In particular, in the corner of the insulating layer in which the radius of the radius provided at the inner corner of the cavity is increased and the diameter of the concave portion having an arc-shaped cross section provided at the protruding corner is reduced, the width can be further increased. Become.
[0010]
The present invention also provides a plurality of insulating layers having a substantially rectangular shape in a plan view, a wiring layer formed on at least one of the surfaces and the interlayers of the plurality of insulating layers, and at least an uppermost insulating layer in a plan view. And a cavity formed on the inside, the method for manufacturing a wiring board comprising: a plurality of product areas to be the uppermost insulating layer in the insulating sheet having a plurality of product area corners in the sheet. Circular through-holes are formed in adjacent T-shaped or cross-shaped boundaries, and cut in each product area to form a semicircular concave portion or a quarter circular concave portion. It is also possible to include the method for manufacturing a wiring board according to claims 1 and 2 including the steps.
In this case, in the insulating sheet serving as the uppermost insulating layer in the plurality of wiring boards, the concave portion forming the concave conductor having the arc-shaped cross section can be efficiently manufactured with a small number of steps. Therefore, it is possible to reliably and inexpensively provide a wiring board having a cavity for mounting an electronic component while meeting a demand for miniaturization.
The insulating sheet includes a green sheet mainly made of ceramics and a resin sheet made of synthetic resin.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.
FIG. 1A is a plan view showing a plurality of insulating layers 2 to 5 and a cavity 6 formed inside the insulating layers 2 to 5 in the first wiring board 1 according to the present invention, and FIGS. FIG. 3 is a cross-sectional view taken along line BB or CC in FIG.
As shown in FIGS. 1 (A) to 1 (C), the wiring board 1 includes insulating layers 2 to 5 having a thickness of several 100 μm, which are made of, for example, a ceramic containing alumina as a main component and have a square (rectangular) shape in plan view. A substantially rectangular cavity 6 in plan view is located inside the insulating layers 2 to 4 except for the lowermost insulating layer 5 which are stacked. On the surfaces 2a to 5a of the insulating layers 2 to 4, a wiring layer described later is formed.
[0012]
As shown in FIGS. 1A and 1C, the opening 7 of the cavity 6 in the uppermost insulating layer 2 has a width in the vertical direction that is larger than the opening 8 of the cavity 6 in the insulating layers 3 and 4. The surface 3a of the second insulating layer 3 is exposed above and below the opening 7 as a horizontally long step. However, as shown in FIGS. 1A and 1B, the opening 7 of the cavity 6 in the uppermost insulating layer 2 has an opening 8 Is the same as The surface 5 a of the insulating layer 5 is exposed at the bottom of the cavity 6. An electronic component 18 such as a quartz oscillator or a SAW filter is mounted in the cavity 6.
[0013]
As shown in FIG. 1A, arc-shaped concave portions 10 each having a quarter-circular cross section in a plan view are continuously formed at four protruding corners of the insulating layers 2 to 5 in the vertical direction. A concave conductor 12 to be described later is formed in the concave portion 10 of the lowermost insulating layer 5 among them. As shown in FIG. 1 (A), in the middle of the upper and lower sides facing each other in the insulating layers 3 to 5, a concave groove 14 having a substantially semicircular cross section in plan view and a concave conductor Are formed respectively. The concave conductors 12, 16 are made of, for example, W, Mo, Ni, Ag, or Pd, or a sintered body of an alloy based on any of these.
[0014]
As shown in FIG. 1A, in the uppermost insulating layer 2, a via conductor V having a diameter of about 100 μm is formed through each of the lower left corner and the upper right corner, and the via conductor V is formed on the lower side. The insulating layers 3 and 4 are continuously penetrated in the vertical direction. The via conductor V is also a sintered body made of the same metal or alloy as described above.
In the uppermost insulating layer 2, the radius (diameter) R of the radius 7a attached to the inner corner of the opening 7 of the cavity 6 close to the corner through which the via conductor V penetrates is close to the corner through which the via conductor V does not penetrate. The radius (diameter) r of the radius 7b provided at the inner corner of the opening 7 of the cavity 6 is set to be larger. Incidentally, when the opening 7 of the cavity 6 in the insulating layer 2 is 3.0 mm × 3.0 mm, the radius R is 0.4 to 0.6 mm and the radius r is 0.15 to 0.25 mm. Therefore, in the insulating layer 2, the width of each of the lower left and upper right corners through which the via conductor V penetrates is larger than the width of each of the upper left and lower right corners through which the via conductor V does not penetrate. Therefore, the via conductor V can be accurately and reliably penetrated through such a corner.
[0015]
FIG. 2 is a perspective view of the insulating layers 2 to 5 forming the wiring board 1. As shown in FIG. 2, the uppermost insulating layer 2 has a ground wiring layer 20 entirely covering the entire surface 2a surrounding the opening 7 of the cavity 6. The wiring layer 20 functions not only as a ground circuit but also for mounting a metal frame (not shown) having a square shape in a plan view thereon after mounting the electronic component 18 in the cavity 6. By sealing the opening of the metal frame with a cover plate (not shown), the mounted electronic component 18 can be sealed. Also, via conductors V, V at diagonal positions are connected to the wiring layer 20.
The metal frame may be omitted, and a cover plate may be directly brazed to the wiring layer 20. The wiring layer 20 and each of the following wiring layers are also sintered bodies of the metal or alloy.
As shown in FIG. 2, the insulating layers 3 and 4 of the second and third layers are provided on the surfaces 3a and 4a around the opening 8 of the cavity 6 on the signal wiring layers 21 to 28 having a predetermined pattern. 31 to 38 are formed. Of these, the wiring layers 23, 26, 33, 36 are individually connected to the adjacent concave conductors 16 on the outside thereof.
[0016]
Via conductors V, V similar to those described above penetrate through the corners of the insulating layers 3, 4 at diagonal positions. Among these, the via conductor V penetrating the insulating layer 3 connects the wiring layer 20 to the wiring layers 34 and 35, and the via conductor V penetrating the insulating layer 4 is the wiring layer 34 and 35 The connection portion 42 of the layer 40 is connected.
As shown in FIG. 2, near the center of the surface 5a of the lowermost insulating layer 5, a wiring layer 40 for power supply having a substantially rectangular shape in a plan view is formed in a solid shape. The connection portions 42 that are individually connected to the concave conductors 12 located at the four protruding corners are formed radially. A terminal located on the bottom surface of the electronic component 18 is connected to the solid wiring layer 40 via a brazing material (not shown).
[0017]
The wiring board 1 is manufactured through the following steps.
First, as shown in FIG. 3A, a plurality of green sheets (insulating sheets) S containing, for example, alumina as a main component and containing an organic binder are prepared. A broken line in the green sheet S indicates a cutting line for subsequent cutting, and one green sheet S has four product areas s to be the insulating layers 2 in succession.
Next, as shown in FIG. 3 (B), a circular through-hole h having a dedicated diameter for each part is formed on a T-shaped boundary or a cross-shaped boundary between a plurality of adjacent product areas s, s by a laser. Drilled by machining or mechanical punch.
Next, as shown in FIG. 3C, a via hole vh having a diameter of about 100 μm is formed at a predetermined position in each of the plurality of product areas s by the same method as described above.
[0018]
Further, as shown in FIG. 3 (D), a position near the center in each of the plurality of product areas s, s is punched by a punching die having a predetermined cross-sectional shape, so that an opening that becomes a part of the cavity 6 is formed. The part 7 is formed. At this time, a punching die is used in which the radiuses 7a and 7b having the radius R and the radius r are formed in the inner corners of the opening 7.
Next, after filling the via hole vh with a conductive paste containing a metal powder such as W by mask printing, a similar paste is formed on the entire surface of the product area s by screen printing. As a result, the via conductor V is formed in the via hole vh, and the wiring layer 20 is formed on the surface of each product area s.
Then, by cutting the green sheet S along the broken line, four green sheets S2 for the uppermost insulating layer 2 are obtained as shown in FIG. At this time, the through hole h becomes a quarter circular concave portion 10 at the four corners of the sheet S2, or a semicircular concave portion 14 located at the middle of the upper and lower sides of the sheet S2.
[0019]
The green sheets S3, 4S for the insulating layers 3, 4 are also formed in the same manner as in the method shown in FIGS. Note that a conductive paste is also formed on the inner wall of the through hole h which becomes the concave portion 14 of the sheets S3 and 4S.
Further, the lowermost green sheet S5 for the insulating layer 5 is formed by forming a circular through hole h in the green sheet S, forming a conductive paste on the surface of the green sheet S by screen printing, and then forming the solid paste by the broken line. It is obtained by cutting along. Note that the conductive paste is also formed on the inner walls of the concave portions 10 and 14 of the sheet S5.
Then, as shown in FIGS. 4A to 4C, the green sheets S2 to S5 are laminated while being pressed, and then inserted into a firing furnace (not shown) at 800 to 1400 ° C. for about 0.5 to 6 hours. Heat and bake. As a result, as shown in FIG. 1A and FIGS. 4A to 4C, the wiring substrate 1 can be efficiently and reliably obtained.
[0020]
FIGS. 5A and 5B relate to a second wiring board 1a according to the present invention. In the following, common reference numerals are used for parts and elements common to the above-described embodiment.
As shown in FIGS. 5A and 5B, the wiring board 1a is also formed by laminating insulating layers 2 to 5, and inside the insulating layers 2 to 4 except for the lowermost insulating layer 5, the same cavity as described above. 6 is located. The wiring layers 20 and the like are formed on the surfaces 2a to 5a of the insulating layers 2 to 4 in the same manner as described above. As shown in FIG. 5A, in the uppermost insulating layer 2, an arc-shaped recess having a cross section of a quarter circle provided at each of the lower left corner and the upper right corner of each of the corners through which the via conductor V passes. The radius (diameter) d of the shape portion 11 is smaller than the radius (diameter) D of the concave portion 10 provided at each of the upper left and lower right corners where the via conductor V does not penetrate.
Incidentally, when the size of the opening 7 of the cavity 6 in the uppermost insulating layer 2 is 3.0 mm × 3.0 mm, the radius d is 0.15 to 0.25 mm and the radius D is 0.3 to 0. 0.4 mm.
[0021]
That is, in the wiring board 1a, as shown in FIG. 5 (A), all four inner corners of the opening 7 of the cavity 6 in the uppermost insulating layer 2 are reduced to radius 7b of radius r, By reducing the radius d of the concave portion 11 provided at the corner of the corner through which the conductor V passes, a wide width at the corner can be secured. Therefore, the via conductor V can be accurately and reliably penetrated.
In addition, according to the wiring board 1a, since the opening 7 of the cavity 6 can be widened, the area of the wiring layers 21 to 28 exposed on the surface 2a of the second insulating layer 2 can be secured. As a result, the bonding operation of the wires connecting the signal wiring layers 21 to 28 and the terminals located on the upper surface of the electronic component mounted in the cavity 6 becomes easy.
[0022]
FIGS. 6A and 6B relate to a wiring board 1b in an application form of the wiring boards 1 and 1a.
As shown in FIGS. 6A and 6B, the wiring board 1b is formed by laminating insulating layers 2 to 5 and inside the insulating layers 2 to 4 except for the lowermost insulating layer 5, the same cavity as described above. 6 is located. On the surfaces 2a to 5a of the insulating layers 2 to 4, wiring layers 20, 40 and the like are formed in the same manner as described above.
As shown in FIG. 6A, in the uppermost insulating layer 2, the radius of the radius 7a provided at the inner corner of the opening 7 of the cavity 6 near the lower left and upper right corners through which the via conductor V passes. R is larger than the radius r of the radius 7b provided at the inner corner of the opening 7 of the cavity 6 near the corner through which the via conductor V does not penetrate as described above.
[0023]
At the same time, the radius d of the arc-shaped concave portion 11 having a cross section of a quarter circle provided at the protruding corners of the lower left and upper right corners through which the via conductor V penetrates, The radius D of the concave portion 10 provided at each of the lower right corners is formed in the same manner as described above.
That is, in the wiring board 1b, as shown in FIG. 6A, in the uppermost insulating layer 2, the radius R of the inner corner of the cavity 6 close to the corner through which the via conductor V passes is increased and the same. By reducing the radius d of the concave portion 11 provided at the corner of the corner, the width at the corner can be further increased. Therefore, in the corner, the via conductor V can be easily and reliably penetrated, and conduction of the upper and lower wiring layers 20 and the like can be ensured. In the above-described corner of the wiring board 1b, two via conductors V can be penetrated in parallel.
[0024]
The present invention is not limited to the embodiments described above.
The corners through which the via conductors V penetrate are not limited to corners at diagonal positions in the insulating layer 2 but may be arranged at corners at both ends of the same side or at three corners.
The radius R, r, d, D of the radius 7a, 7b provided at the inner corner of the cavity 6 or the concave portion 10, 11 provided at the protruding corner of the insulating layer 2 is a constant drawing a quarter circle. Not only the value but also a variable value that draws a flat quarter ellipse can be used.
Further, ceramics such as barium titanate, mullite, aluminum nitride, glass ceramic, and low-temperature fired ceramic may be applied to the insulating layers 2 to 5 in addition to alumina.
[0025]
Alternatively, for the insulating layers 2 to 5, a synthetic material such as epoxy, polyester, polyimide, bismaleimide / triazine, or a composite material containing an inorganic filler such as glass filler or glass cloth or an inorganic fiber is applied. May be. When the insulating layers 2 to 5 made of such a resin or a composite material are used, the concave conductors 12 and 16 and the via conductor V such as the wiring layer 20 are formed by using, for example, copper plating or a wiring pattern. For this purpose, a known photolithography technique is used. Further, the insulating layers 2 to 5 made of the above resin or the like are formed into a predetermined shape by press working including punching, and then laminated via an adhesive.
In addition, the electronic components mounted in the cavity 6 are not limited to the crystal resonator and the SAW filter, but passive components such as a chip capacitor, a chip inductor, a resistor, and a filter, a transistor, a semiconductor element, an FET, a low noise amplifier ( Active components such as LNA) are included, or LC filters, antenna switch modules, couplers, diplexers, semiconductor integrated circuits, and the like are also included. Moreover, it is also possible to mount a plurality of electronic components of the same type or different types together in the same cavity of the wiring board.
[0026]
【The invention's effect】
According to the above-described wiring board of the present invention (claims 1 and 2), in the uppermost insulating layer in which the cavity is provided, at the corner where the via conductor penetrates, the width of the insulating layer in such a corner is The width is larger than the width of the insulating layer at the corner where the via conductor does not penetrate. Therefore, it is possible to provide a wiring board in which via conductors are easily arranged in such a wide corner.
[Brief description of the drawings]
FIG. 1A is a plan view schematically showing a first wiring board according to the present invention, and FIGS. 1B and 1C are views taken along line BB or CC in FIG. 1A. FIG.
FIG. 2 is an exploded perspective view of the wiring board of FIG. 1;
3 (A) to 3 (E) are schematic diagrams showing the steps of manufacturing the wiring board of FIG. 1;
4A is a perspective view showing a manufacturing process subsequent to FIG. 3E or the obtained wiring board of FIG. 1; FIGS. 4B and 4C are BB lines or C in FIG. 3A; Sectional drawing of the arrow taken along the -C line.
FIGS. 5A and 5B are plan views or perspective views showing a second wiring board according to the present invention.
FIGS. 6A and 6B are plan views or perspective views showing application forms of the wiring boards of FIGS. 1 and 5;
7A and 7B are plan views or perspective views schematically showing a conventional wiring board.
[Explanation of symbols]
1, 1a, 1b ... wiring boards 2 to 5 ... insulating layers 2a to 5a ... surface 6 ... ... Cavities 7a and 7b ares 10, 11 are concave portions 20 to 28, 31 to 38, 40 wiring layer V ………………… Via conductors R, r, D, d …………………… Radius (diameter)

Claims (2)

平面視でほぼ矩形を呈する複数の絶縁層と、
上記複数の絶縁層の表面および層間の少なくとも一つに形成される配線層と、
少なくとも最上層の上記絶縁層の平面視で内側に形成されるキャビティと、を備え、
上記最上層の絶縁層において、ビア導体が貫通するコーナに近接する上記キャビティの内隅部に付すアールの径が、上記ビア導体が貫通しないコーナに近接する上記キャビティの内隅部に付すアールの径よりも大きい、
ことを特徴とする配線基板。
A plurality of insulating layers having a substantially rectangular shape in plan view;
A wiring layer formed on at least one of the surface and the interlayer of the plurality of insulating layers,
A cavity formed inside at least the uppermost insulating layer in plan view,
In the uppermost insulating layer, the diameter of the radius of the inner corner of the cavity adjacent to the corner through which the via conductor penetrates is equal to the radius of the radius of the inner corner of the cavity adjacent to the corner through which the via conductor does not penetrate. Larger than the diameter,
A wiring board characterized by the above-mentioned.
平面視でほぼ矩形を呈する複数の絶縁層と、
上記複数の絶縁層の表面および層間の少なくとも一つに形成される配線層と、
少なくとも最上層の上記絶縁層の平面視で内側に形成されるキャビティと、を備え、
上記最上層の絶縁層において、ビア導体が貫通するコーナの出隅部に設ける断面円弧形の凹形部の径が、上記ビア導体が貫通しないコーナの出隅部に設ける断面円弧形の凹形部の径よりも小さい、
ことを特徴とする配線基板。
A plurality of insulating layers having a substantially rectangular shape in plan view;
A wiring layer formed on at least one of the surface and the interlayer of the plurality of insulating layers,
A cavity formed inside at least the uppermost insulating layer in plan view,
In the uppermost insulating layer, the diameter of the concave portion having an arc-shaped cross section provided at the corner of the corner through which the via conductor penetrates has an arc-shaped cross-section provided at the corner of the corner not penetrated by the via conductor. Smaller than the diameter of the concave part,
A wiring board characterized by the above-mentioned.
JP2002214085A 2002-07-23 2002-07-23 Wiring board Withdrawn JP2004055991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002214085A JP2004055991A (en) 2002-07-23 2002-07-23 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002214085A JP2004055991A (en) 2002-07-23 2002-07-23 Wiring board

Publications (1)

Publication Number Publication Date
JP2004055991A true JP2004055991A (en) 2004-02-19

Family

ID=31936502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002214085A Withdrawn JP2004055991A (en) 2002-07-23 2002-07-23 Wiring board

Country Status (1)

Country Link
JP (1) JP2004055991A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224732A (en) * 2008-03-18 2009-10-01 Ngk Spark Plug Co Ltd Manufacturing method of multiple patterning circuit board, and intermediate product of multiple patterning circuit board
WO2016117203A1 (en) * 2015-01-23 2016-07-28 三菱電機株式会社 Ceramic substrate, bonded body, module, and ceramic substrate manufacturing method
CN107426914A (en) * 2011-01-26 2017-12-01 At&S奥地利科技与系统技术股份公司 The intermediate maturity of printed circuit board or printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224732A (en) * 2008-03-18 2009-10-01 Ngk Spark Plug Co Ltd Manufacturing method of multiple patterning circuit board, and intermediate product of multiple patterning circuit board
CN107426914A (en) * 2011-01-26 2017-12-01 At&S奥地利科技与系统技术股份公司 The intermediate maturity of printed circuit board or printed circuit board
WO2016117203A1 (en) * 2015-01-23 2016-07-28 三菱電機株式会社 Ceramic substrate, bonded body, module, and ceramic substrate manufacturing method
JP5980463B1 (en) * 2015-01-23 2016-08-31 三菱電機株式会社 Ceramic substrate, joined body, module, and method for manufacturing ceramic substrate
US10160636B2 (en) 2015-01-23 2018-12-25 Mitsubishi Electric Corporation Ceramic substrate, bonded body, module, and method for manufacturing ceramic substrate

Similar Documents

Publication Publication Date Title
JP5188256B2 (en) Capacitor component manufacturing method
US20080192443A1 (en) Electronic Component Module and Method for Manufacturing the Same
JP2005072095A (en) Electronic circuit unit and manufacturing method thereof
KR20040043736A (en) Ceramic Multilayer Substrate and its Manufacturing Process
US20030075356A1 (en) Electronic device and method of manufacturing the same
KR101973368B1 (en) Collective substrate for resistor devices
EP1330025A2 (en) Saw filter module
JP3928665B2 (en) Chip-type electronic component built-in multilayer substrate and method for manufacturing the same
JP3510971B2 (en) High frequency power amplifier
JP2004056115A (en) Multilayer wiring board
JP2004055991A (en) Wiring board
JP4329762B2 (en) Chip type electronic component built-in multilayer board
JP3855798B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
JP4006686B2 (en) Ceramic multilayer substrate and manufacturing method thereof
JPH06204075A (en) High frequency monolithic ceramic electronic component and manufacturing method thereof
JP2000068149A (en) Laminated electronic component and manufacture therefor
JP5207854B2 (en) Component built-in ceramic substrate and manufacturing method thereof
JP4616016B2 (en) Method for manufacturing circuit wiring board
JP2600620B2 (en) Semiconductor device
TWI496175B (en) Ceramic multilayer component
JP2004128334A (en) High frequency electronic components
JP2002076629A (en) Composite multilayer wiring board
JP4986500B2 (en) Laminated substrate, electronic device and manufacturing method thereof.
JP2004207592A (en) Method of producing multilayer ceramics substrate
JPH05166672A (en) Composite part

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20051004