JP2003303968A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: In a semiconductor device using an SOI substrate, generation of a leakage current depending on a gate voltage is suppressed. The SOI layer has a p-type body region.
A source region (not shown) and a drain layer 15,
Ap ⁺ impurity layer 8 containing a higher concentration of p-type impurities than body region 13 and supplying a voltage to body region 13;
A p ⁻ impurity layer 24 is provided between the body region 13 and the p ⁺ impurity layer 8 and contains a p-type impurity at a concentration higher than the body region 13 and lower than the p ⁺ impurity layer 8. A silicide layer 16 is provided on p ⁺ impurity layer 8. Since the p-type impurity concentration of p ⁻ impurity layer 24 is higher than that of body region 13, the depletion layer generated when a gate voltage is applied is less likely to extend toward p ⁺ impurity layer 8. Therefore, crystal defects generated in p ⁺ impurity layer 8 when silicide layer 16 is formed in the depletion layer are less likely to be taken in.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MIS type transistor formed in an SOI (silicon on insulator) layer.

[0002]

2. Description of the Related Art In recent years, the demand for high speed and low power consumption of LSI has been increasing, and the practical application of SOI (silicon on insulator) device is about to begin. Among SOI devices, a MIS type SOI transistor (hereinafter referred to as an SOI transistor) is a typical element forming an LSI. In the SOI transistor, the body potential is fixed like a transistor formed on a normal silicon substrate by providing a contact reaching the SOI layer (hereinafter, referred to as a body contact type transistor).

FIG. 11 is a plan view showing the structure of a conventional n-channel SOI transistor.

As shown in FIG. 11, the conventional SOI transistor viewed from above has an SOI layer 101 and an SOI layer 1.
Oxide film 1 for insulating 01 from the peripheral region
02 and the gate electrode 1 provided on the SOI layer 101.
03 and a source region 104 provided separately from a portion of the SOI layer 101 located on the side of the gate electrode 103.
And the drain region 105, the source contact 106 in contact with the source region 104, the drain contact 107 in contact with the drain region 105, and the body contact region 1 for controlling the body potential of the SOI transistor.
08 and a body contact 109 in contact with the body contact region 108. In this figure, the wiring layer,
Illustrations of the interlayer insulating film, the metal silicide layer, the gate sidewall, etc. are omitted.

FIG. 12 is a sectional view taken along line XII-XII in FIG. As shown in FIG. 12, in the conventional SOI transistor, an SOI layer 101 is formed on a supporting substrate 110 with a buried oxide film 111 interposed therebetween. SOI layer 101
A gate insulating film 112 and a gate electrode 103 made of polycrystalline silicon doped with an n-type impurity are formed on the above.

Below the gate electrode 103 in the SOI layer 101 is a body region 113 having a p-type impurity concentration of 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . An n ⁻ drain layer 114 having an n-type impurity concentration of 10 ¹⁸ to 10 ²⁰ cm ⁻³ and an n ⁺ drain layer 115 having an n-type impurity concentration of 10 ²⁰ to 10 ²¹ cm ⁻³ are formed on the side of the body region 113. A drain region 105 forming the LDD structure is formed. The source region (not shown) is also formed of the LDD structure.

In the region of the SOI layer 101 which is in contact with the body region 113 and is shielded from the source region and the drain region 105, the p-type impurity concentration is 10 ²⁰ to 10 ²¹ c.
A body contact region 108 of m ⁻³ is formed.

A metal silicide layer 116 for reducing the sheet resistance is formed on the source region, drain region 105 and body region 113 of the SOI layer 101, and the metal silicide layer 1 is also formed on the gate electrode 103.
17 are formed.

The SOI layer 1 is formed on the side surface of the gate electrode 103.
01, the gate sidewall 118 is formed, and the gate electrode 10 is formed on the SOI layer 101.
An interlayer insulating film 119 is formed so as to cover the No. 3 layer. A body contact region 108, a source region (not shown), and a body contact 109 that reaches the drain region 105, a source contact (not shown), and a drain contact 107 are formed through the interlayer insulating film 119. By providing the metal wiring layer 120 in contact with each contact on the interlayer insulating film 119, the body potential can be controlled and the voltage can be applied to the drain region 105 and the like.

[0010]

However, the conventional SOI transistor has the following problems.

A metal silicide layer 1 is formed on the SOI layer 101.
When 16 is formed, a crystal defect layer 121 is generated inside the SOI layer 101 due to a chemical reaction between metal and silicon. The crystal defect layer 121 is mainly used for the SOI layer 10.
It occurs in the portion where the metal silicide layer 116 is formed in the upper part of 1. However, part of the crystal defect layer 121 may be distributed under the gate sidewall 118 or under the edge of the gate electrode 103 in the SOI layer 101.

When a positive voltage is applied to the gate electrode 103,
A depletion layer 122 is formed in a portion of the SOI layer 101 located below the gate electrode 103. The depletion layer 122 is
As the applied voltage (gate voltage) to the gate electrode 103 is increased, the SOI layer 101 extends in the depth direction and the lateral direction. Particularly, in the body contact region 108, the depletion layer extends laterally more than the depth direction due to the influence of the sneak of the electric field from the side wall of the gate electrode 103. Further, when a gate voltage exceeding the threshold value of the transistor is applied, an inversion layer is formed in the portion of the SOI layer 101 located below the gate electrode 103.

Here, the length of the depletion layer 122 is mainly determined by the gate voltage and the impurity concentration of the SOI layer 101. For example,
If the impurity concentration of the region under the gate sidewall 118 in the SOI layer 101 is approximately 10 ¹⁷ cm ⁻³ , the maximum depletion layer width becomes approximately 100 nm in the lateral direction, and part of the crystal defect layer 121 is depleted. Will be incorporated into layer 122.

In this state, when a forward voltage equal to or lower than the built-in voltage of the pn junction is applied between the body region and the source region or between the body region and the drain region, the depletion layer 1
The crystal defect layer taken in 22 becomes a recombination center,
A leakage current more than the current determined by the original recombination current of the pn junction and the diffusion current flows between the body region and the source region and between the body region and the drain region. Moreover, since this leak current changes depending on the size of the depletion layer 122, it changes depending on the gate voltage.

FIG. 13 is a graph showing the gate voltage dependence of the body current in the conventional SOI transistor. Here, Vd, Vs, and Vg are the drain region 105, the source region 104, and the gate electrode 103, respectively.
Vb is the voltage applied to the body contact region 108
Indicates the voltage applied to the body region 113 through. As shown in FIG. 13, if the body current changes depending on the gate voltage, the SOI transistor cannot operate correctly. In particular, when the body potential is changed in the forward direction with respect to the source region or the drain region, an abnormal leak current flows between the body region and the source region and between the body region and the drain region, and the circuit operates normally. It causes a serious malfunction that it does not work.

Also, extracting the SOI transistor model parameter becomes difficult for the following reasons. Generally, as a current component that determines the body potential,
For example, diode current, bipolar operating current, impact ionization current, GIDL (Gate Induced Drain Curre)
nt) is measured. Among these, in the case of an n-channel transistor, the body potential changes from 0 to a positive potential state when the transistor operates, so that the diode current value in the forward direction or lower than the built-in voltage is particularly important.

However, if the above-mentioned leakage current depending on the gate voltage occurs, the parameter of the diode current, which is an important factor for determining the body potential, cannot be accurately extracted. As a result, the operation cannot be simulated, and eventually the circuit design using the SOI transistor cannot be performed.

An object of the present invention is to provide a means for preventing a crystal defect generated at the time of forming a silicide layer from being taken into a depletion layer extending when a gate voltage is applied, so that a leak current depending on the gate voltage is obtained. Low SO
An object is to provide an I-transistor and a manufacturing method thereof.

[0019]

According to a first semiconductor device of the present invention, at least one of a semiconductor layer provided on an insulating film, a gate electrode provided on the semiconductor layer, and the semiconductor layer is provided. A first conductivity type channel region provided below the gate electrode and a first conductive type channel region provided on a side of the channel region in the gate width direction of the gate electrode of the semiconductor layer and having a higher concentration than the channel region. A contact region containing one conductivity type impurity, a contact electrically connected to the contact region for supplying a voltage to the channel region, and interposed between the channel region and the contact region of the semiconductor layer. Provided on the contact region and an impurity layer having a first conductivity type impurity having a concentration higher than that of the channel region and lower than that of the contact region. And a silicide layer.

As a result, the depletion layer generated when the gate voltage is applied reaches the impurity layer having a high first-conductivity-type impurity concentration, so that it is difficult to extend to the contact region. Therefore, it becomes difficult for crystal defects generated in the contact region when forming the silicide to be taken into the depletion layer,
It is possible to prevent crystal defects from becoming recombination centers. Therefore, the leak current depending on the gate voltage can be suppressed.

A second semiconductor device of the present invention is a semiconductor layer provided on an insulating film, a gate electrode provided on the semiconductor layer, and at least a portion of the semiconductor layer below the gate electrode. The first conductivity type channel region provided, the source region and the drain region provided on the side of the channel region in the gate length direction of the gate electrode of the semiconductor layer, and the source region and the drain region. A silicide layer provided apart from the gate electrode by a first distance, a contact region provided on a side of the channel region in the gate width direction of the gate electrode of the semiconductor layer, A silicide layer provided on a part of the contact region so as to be separated from the gate electrode by a second distance longer than the first distance.

Since the silicide layer on the contact region is provided so as to be separated from the gate electrode by the second distance longer than the conventional first distance, the crystal defects generated when the silicide layer is formed are also formed on the gate. It is distributed a second distance from the electrodes. Therefore, when the gate voltage is applied, the number of crystal defects taken in by the depletion layer can be reduced, and the number of crystal defects serving as recombination centers can be reduced. Therefore, the leak current depending on the gate voltage can be suppressed.

Since the depletion layer generated during the operation of the semiconductor device does not reach the position in the semiconductor layer that is located at the second distance from the gate electrode, the depletion layer causes a crystal defect caused when the silicide layer is formed. It is possible not to extend to the region where is distributed.

Since the contact region has a higher concentration of the first conductivity type impurity than the channel region, the contact resistance between the contact region and the silicide layer can be reduced.

Between the channel region and the contact region, since the impurity layer having the first conductivity type impurity whose concentration is higher than that of the channel region and lower than that of the contact region is formed, the gate voltage is increased. Since the depletion layer generated at the time of application reaches the impurity layer and is less likely to extend toward the contact region, it is possible to more reliably prevent the depletion layer from incorporating crystal defects.

The first semiconductor device manufacturing method of the present invention is
A method of manufacturing a semiconductor device, comprising a semiconductor layer provided on an insulating film, the semiconductor layer having a channel region of a first conductivity type and a contact region for supplying a voltage to the channel region, wherein the gate is provided on the semiconductor layer. The step (a) of forming a gate electrode with an insulating film sandwiched between the channel region and the contact region at least in the region between the channel region and the contact region by implanting ions into the semiconductor layer from above the gate electrode. A step (b) of forming an impurity layer containing a higher concentration of the first conductivity type impurity, a step (c) of forming an insulating sidewall on a side surface of the gate electrode, the gate electrode and the insulating property. By implanting ions into the semiconductor layer from above the sidewalls, the concentration of the first conductivity type impurity in the contact region is changed to the impurity layer of the impurity layer. And step (d) of higher than the concentration, and a step (e) to form at least silicide layer on the contact region.

As a result, the depletion layer generated when the gate voltage is applied reaches the impurity layer formed in the step (b), so that it is difficult to extend to the contact region. Therefore, the crystal defects generated in the contact region in step (e) are less likely to be taken into the depletion layer, and the crystal defects can be prevented from becoming recombination centers. Therefore, it is possible to prevent the leak current from changing depending on the gate voltage.

A second semiconductor device manufacturing method of the present invention is
A method for manufacturing a semiconductor device, comprising a semiconductor layer provided on an insulating film, the semiconductor layer having a channel region, a source / drain region, and a contact region for supplying a voltage to the channel region. A step (a) of forming a gate electrode with a gate insulating film interposed therebetween, a step (b) of forming an insulating sidewall on a side surface of the gate electrode, and a step of forming the gate electrode and the insulating sidewall above And (c) forming a source / drain layer separated from the gate electrode by a first distance by injecting a second conductivity type impurity into the semiconductor layer.
A step (d) of forming a protective insulating film on the contact region in a region located at a second distance from the gate electrode; and, after the step (d), the gate on the contact region. A step (e) of forming a silicide layer spaced apart from the electrode by the second distance, and forming a silicide layer spaced apart from the gate electrode by the first distance on the source / drain layer. The second distance is longer than the first distance.

As a result, in step (e), the silicide layer on the contact region is provided apart from the gate electrode by a second distance longer than the conventional first distance, so that it occurs during formation of the silicide layer. Crystal defects are also distributed at a second distance from the gate electrode. Therefore, when the gate voltage is applied, the number of crystal defects taken in by the depletion layer can be reduced, and the number of crystal defects serving as recombination centers can be reduced. Therefore, the leak current depending on the gate voltage can be suppressed.

After the step (b) or the step (c), the method further comprises a step of implanting a first conductivity type impurity into the contact region from above the gate electrode and the insulating sidewall, thereby providing a contact. The contact resistance between the region and the silicide layer can be reduced.

After the step (a), by implanting an impurity of the first conductivity type from above the gate electrode at least between the channel region and the contact region, a depletion layer is formed when the gate voltage is applied. It hardly reaches the impurity layer and extends toward the contact region. Therefore, it is possible to more reliably prevent the crystal defects from being taken into the depletion layer.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below by taking an n-channel type MIS type SOI transistor as an example.

FIG. 1 is a plan view showing the structure of the SOI transistor of the present invention.

As shown in FIG. 1, the SOI transistor of this embodiment viewed from above has an SOI layer (semiconductor layer) 1
A silicon oxide film 2 for insulating the SOI layer 1 from the peripheral region, a gate electrode 3 provided on the SOI layer 1, and a portion of the SOI layer 1 located on the side of the gate electrode 3. A source region 4 and a drain region 5 provided separately from each other, and a source contact 6 in contact with the source region 4.
And a drain contact 7 in contact with the drain region 5,
P ⁺ for controlling the body potential of the SOI transistor
An impurity layer 8 and a body contact 9 in contact with the p ⁺ impurity layer 8 are provided. Here, the silicide layer, the wiring layer,
Illustrations of the interlayer insulating film and the gate sidewalls are omitted.

FIG. 2 is a sectional view taken along line II-II of FIG.

As shown in FIG. 2, in the SOI transistor of this embodiment, an SOI layer 1 of silicon (Si) having a thickness of 150 nm is formed on a supporting substrate 10 with a buried oxide film 11 interposed therebetween. . On top of the SOI layer 1,
Gate oxide film 12 made of a silicon oxide film having a thickness of 3 nm
And a gate electrode 3 having a thickness of 200 nm and made of polycrystalline silicon doped with an n-type impurity.

Below the gate electrode 3 in the SOI layer 1, a body region 13 is formed. The p-type impurity concentration of the body region 13 is usually 10 ¹⁷ to 10 ¹⁸ cm ⁻³ , and this value is SO
It is set to a desired value according to the target threshold voltage of the I transistor. The body region 13 includes a channel region.

On the side of the body region 13 of the SOI layer 1, an n-type impurity concentration of 10 ¹⁸ to 10 ²⁰ cm ^-3 and a depth of 50 n.
m n ^- drain layer 14 and n-type impurity concentration 10 ²⁰ to 1
Since the n ⁺ drain layer 15 having a depth of 0 ²¹ cm ⁻³ and a depth of 150 nm is formed, the drain region 5 has an LDD structure. The source region (not shown) is also L
It has a DD structure.

In the region of the SOI layer 1 on the side of the body region 13 in the gate width direction (hereinafter referred to as the body contact region Rbc), the region is in contact with the body region 13 and cuts off from the source region and the drain region 5. Thus, the p ⁺ impurity layer 8 having a p-type impurity concentration of 10 ²⁰ to 10 ²¹ cm ⁻³ is formed.

A metal silicide layer 16 for reducing the sheet resistance is formed on the source region, the drain region 5 and the body region 13 of the SOI layer 1, and the metal silicide layer 17 is also formed on the gate electrode 3. Are formed.

On the side surface of the gate electrode 3, a gate sidewall 18 made of a silicon oxide film and having a lateral thickness of about 70 nm is formed.

Here, in the portion of the SOI layer 1 extending from below the edge portion of the gate electrode 3 to below the gate sidewall 18, a p-type impurity concentration of 10 ¹⁸ to 10 ²⁰ cm ^-3 and a depth of 70 nm p are formed. ^- impurity layer 24 is provided. Here, the p-type impurity concentration of p ⁻ impurity layer 24 is preferably higher than that of body region 13 and lower than that of p ⁺ impurity layer 8.

The p ^- impurity layer 24 is formed on the gate electrode 3
Is preferably formed so as to extend from below the edge portion to below the gate sidewall 18 and contact the p ⁺ impurity layer 8. However, if the p ⁻ impurity layer 24 is interposed at least between the channel region and the p ⁺ impurity layer 8,
The effect of this embodiment can be obtained.

An interlayer insulating film 19 covering the gate electrode 3 is formed on the SOI layer 1. A body contact 9, a source contact (not shown) and a drain contact 7 which penetrate the interlayer insulating film 19 and reach the p ⁺ impurity layer 8, the source region (not shown) and the drain region 5 are formed. By providing the wiring 20 in contact with each contact on the interlayer insulating film 19, it becomes possible to control the body potential and apply a voltage to the drain region 5 and the like.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 3A to 3D are cross-sectional views taken along the line II-II showing the manufacturing process of the semiconductor device of the first embodiment.

First, in the step shown in FIG. 3A, a buried oxide film 11 and a silicon (Si) film having a thickness of 150 nm are formed on a support substrate 10 according to a general method for manufacturing an MIS transistor having an LDD structure. The SOI layer 1 made of is formed. Then, the body region 13 is formed by ion-implanting boron (B), which is a p-type impurity, into the SOI layer 1 at a dose amount of about 5 × 10 ¹⁷ cm ⁻² .

After that, a gate oxide film 12 made of a silicon oxide film having a thickness of 3 nm and a thickness of 20 are formed on the SOI layer 1.
A gate electrode 3 having a thickness of 0 nm and made of polycrystalline silicon doped with an n-type impurity such as phosphorus (P) is formed.

Next, an n-type impurity 2 such as arsenic (As) is formed in a region (hereinafter referred to as a source / drain formation region) for forming the source / drain region in the SOI layer 1.
1 for acceleration energy of 30 keV, dose of 3 × 10 ¹⁴ c
Ion implantation is performed at m ^-2 . Subsequently, a photoresist 22 is applied on the substrate by photolithography to a thickness of about 1 μm to expose the upper part of the SOI layer 1 on the body contact region Rbc. Then, p-type impurities 23 such as boron ions B ⁺ are implanted with an acceleration energy of 5 keV and a dose of 2 × 10 ¹⁵ cm ^-2 . Here, p-type impurity 2
Boron fluoride ion BF ²⁺ may be used as 3.

Next, in the step shown in FIG.
After removing the digist 22, a short time of 10 seconds at 950 ° C.
Do Neil. As a result, the p-type impurity concentration is 10¹⁸~
10 ²⁰cm^-3And p of 70 nm depth^-An impurity layer 24,
n-type impurity concentration 10¹⁸-10 ²⁰cm^-3At a depth of 50 nm
N^-Source layer (not shown) and n^-Drain layer 14
To form. Where p^-Impurity layers 24, n^-Source
Layers and n^-The drain layer 14 is the gate of the SOI layer 1.
It is preferable that the electrode 3 be formed so as to extend below the edge of the electrode 3.
Yes.

Next, in the step shown in FIG. 3C, a silicon oxide film such as an HTO film or a TEOS film is deposited to a thickness of about 70 nm on the substrate by the CVD method. Then, anisotropic dry etching is performed to form the gate sidewall 18 on the side surface of the gate electrode 3.

Next, by the photolithography method, S
A resist (not shown) is formed on the body contact region Rbc in the OI layer 1. Then, using the resist, the gate electrode 3 and the gate sidewall 18 as a mask, arsenic ions As ⁺ are implanted into the source / drain formation region of the SOI layer 1 at an acceleration energy of 50 keV and a dose of 3 × 10 ¹⁵ cm ⁻² . Then, the resist is removed.

Then, by the photolithography method,
A resist (not shown) is formed on the source / drain formation region of the SOI layer 1. Then, using the resist, the gate electrode, and the gate sidewall 18 as a mask, in the body contact region Rbc of the SOI layer 1,
Boron ions B ⁺ are implanted with an acceleration energy of 10 keV and a dose of 10 ¹⁵ cm ^-2 . Then, the resist is removed.

Then, annealing is performed at 1000 ° C. for a short time of about 10 seconds to form n ⁺ source region (not shown), n ⁺ drain layer 15 and p ⁺ impurity layer 8.

Next, in the step shown in FIG. 3D, a metal such as titanium (Ti) or cobalt (Co) is deposited to a thickness of about 8 nm on the substrate by a sputtering method or the like, and then 5
Annealing is performed at a temperature of 00 ° C. for about 60 seconds. When annealing is performed, the gate sidewall 1 of the SOI layer 1
P ⁺ impurity layers 8 and n, which are regions not covered by
^{On the +} source layer, the n ⁺ drain layer 15 and the gate electrode 3, a silicidation reaction between silicon (Si) and a metal occurs to form metal silicide layers 16 and 17. on the other hand,
Since the silicon oxide and the metal forming the gate sidewall 18 do not cause a silicidation reaction, the metal remains on the gate sidewall 18. This unreacted metal is removed with sulfuric acid or the like.

Then, an interlayer insulating film 19 is deposited on the substrate and contacts 7, 9 penetrating the interlayer insulating film 19 and reaching the metal silicide layers 16, 17 are formed in accordance with a usual MIS transistor manufacturing method. . Then, a wiring 20 made of a metal such as aluminum (Al) and in contact with the contacts 7 and 9 is formed. Through the above steps, the SOI transistor of this embodiment is formed.

The effects obtained in this embodiment will be described below in comparison with the conventional semiconductor device.

When a voltage is applied to the gate electrode 3,
The depletion layer formed in body region 13 tends to extend toward p ⁺ impurity layer 8. However, in the present embodiment, the body region 13 and the p ⁺ impurity layer 8 in the SOI layer 1 are
And the p ⁻ impurity layer 24 is formed between and. here,
Since the p-type impurity concentration of the p ⁻ impurity layer 24 is higher than the p-type impurity concentration of the body region 13, the depletion layer is less likely to be formed in the p ⁻ impurity layer 24, and the length of the depletion layer to be extended becomes shorter.

For example, when the p-type impurity concentration of the p ⁻ impurity layer 24 is 10 ¹⁹ cm ⁻³ , the length of the depletion layer extending in the p ⁻ impurity layer 24 is about 10 nm. Therefore, the possibility that the crystal defect layer accompanying the formation of silicide in the depletion layer is significantly reduced. As a result, a leak current is generated between the body region and the source region or between the body region and the drain region, which is determined by the original recombination current of the clean pn junction and the diffusion current, and the dependency of the leak current on the gate voltage is reduced. From the above, an accurate diode current can be obtained.

FIG. 4 is a graph showing the gate voltage dependence characteristic of the body current in the semiconductor device of the first embodiment. This is a result measured by applying a forward bias between the body region and the source / drain region. Vd,
Vs and Vg are voltages applied to the drain region 5, the source region 4 and the gate electrode 3, respectively, and Vb is a voltage applied to the body region 13 through the p ⁺ impurity layer 8. FIG. 4 showing values of the present embodiment and FIG. 13 showing conventional values.
By comparing with, it can be seen that the gate voltage dependence of the body current is reduced in the present embodiment.

Further, it becomes possible to accurately extract the transistor model parameter of the SOI transistor. In particular, in an LSI such as a logic or memory using an SOI transistor, even when the body potential is changed in the forward direction with respect to the source and drain regions, the body region and the source region, and the body region and the drain region are It is possible to prevent an abnormal leak current from flowing. From this, it becomes possible to obtain a normal circuit function.

When the present embodiment is applied to the CMIS process, the p ⁺ impurity layer 8 and the p ⁻ impurity layer 2 are used.
4 is a p-channel MIS transistor (not shown)
If the p ^- source layer, the p ^- drain layer and the p ⁺ source layer and the p ⁺ drain layer having the LDD structure are simultaneously formed, the process can be simplified.

Further, although the n-channel type transistor has been described as an example in the present embodiment, the present invention can also be applied to a p-channel type transistor to obtain the effect.

(Second Embodiment) The second embodiment of the present invention will be described below.
The embodiment will be described by taking an n-channel type MIS type SOI transistor as an example.

FIG. 5 is a sectional view showing the structure of the SOI transistor of the second embodiment. In addition, in FIG.
2 shows a cross section in the body contact region-gate electrode-drain region in the same manner as the line II-II in FIG.
The same components as those in FIG.

As shown in FIG. 5, in this embodiment, the first
The p-type impurity concentration of the body contact region Rbc shown in the first embodiment is about the same as that of the body region 13, and the p ⁻ impurity layer 24 shown in the first embodiment is not provided. Then, from above the end portion of the gate sidewall 18 to above the body contact region Rbc,
A silicon oxide film pattern (protective insulating film) 42 is formed. A metal silicide layer 41 is formed on a region of the body contact region Rbc that is not in contact with the silicon oxide film pattern 42. Metal silicide layer 4
1 is provided, for example, at a distance of 400 nm from the end of the gate sidewall 18.

Here, the distance between the metal silicide layer 41 and the gate electrode 3 in the body contact region Rbc is dbc.
It is assumed that they are separated by (second distance), and the metal silicide layer 16 and the gate electrode 3 in the source / drain formation region are separated by distance dsd (first distance). Here, it is preferable that the distance dbc is such a distance that a crystal defect generated at the time of forming the metal silicide layer 41 is not taken into the depletion layer extending from the bottom of the gate electrode 3 when the gate voltage is applied. From this, the distance dbc is 200 nm
The above is preferable.

However, even if the distance dbc is 200 nm or less, if the value is larger than the distance dsd, the number of crystal defects taken into the depletion layer can be reduced, and the effect of this embodiment can be obtained. You can

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 6A to 6D are cross-sectional views showing the manufacturing process of the semiconductor device of the second embodiment. 6 (a) to (d)
2 shows a cross section in the body contact region-gate electrode-drain region similarly to the II-II cross section of FIG. 1, and the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals.

First, in the step shown in FIG. 6A, the buried oxide film 11 and the SOI layer 1 are formed on the supporting substrate 1 by the same method as in the first embodiment. Then, after the body region 13 is formed in the SOI layer 1 by the ion implantation method or the like, the gate oxide film 12 and the gate electrode 3 are formed.

Then, n ⁻ source layer (not shown), n ⁻
After forming the drain layer 14 and the gate sidewall 18 on the side surface of the gate electrode 3, an n ⁺ source layer (not shown) and an n ⁺ drain layer 15 are formed. Thus, the source region (not shown) having the LDD structure and the drain region 5 are formed.

Next, in the step shown in FIG. 6B, a silicon oxide film 42a of about 100 nm is formed on the substrate by the CVD method.
Deposit. Then, by the photolithography method,
A photoresist of about 1 μm is applied on the silicon oxide film and patterned. As a result, the photoresist 44 remains on the region within the distance dbc from the gate electrode 3 in the body contact region Rbc.

Next, in the step shown in FIG. 6C, a wet etching method is performed using a dilute solution of hydrofluoric acid, so that the body contact region Rbc is formed on a region within a distance dbc from the gate electrode 3. Silicon oxide film pattern 42
To form.

After that, a metal 43 such as titanium (Ti) or cobalt (Co) is deposited to a thickness of about 8 nm on the substrate by a sputtering method or the like.

Next, in the step shown in FIG. 6D, 500 ° C.
Annealing is performed at the temperature of about 60 seconds. When annealing is performed, a silicide reaction between silicon (Si) and a metal occurs in a region of the SOI layer 1 which is not covered with the gate sidewall 18 and the silicon oxide film pattern 42. As a result, metal silicide layers 41, 16 and 17 are formed on the source region, the drain layer 15 and the gate electrode 3 and on the region of the body contact region Rbc not covered by the silicon oxide film pattern 42. It

On the other hand, since the silicon oxide forming the gate sidewall 18 and the metal do not cause a silicidation reaction, the metal remains on the gate sidewall 18 and the silicon oxide film pattern 42. This unreacted metal is removed with sulfuric acid or the like. At this time, the silicon oxide film pattern 42 may be removed.

Then, according to a usual method for manufacturing a MIS transistor, an interlayer insulating film 19 is deposited on the substrate, and contacts 7 and 9 penetrating the interlayer insulating film 19 and reaching the metal silicide layers 41, 16 and 17 are formed. Form. Then, a wiring 20 made of a metal such as aluminum (Al) and in contact with the contacts 7 and 9 is formed. Through the above steps, the SOI transistor of this embodiment is formed.

The effects obtained in this embodiment will be described below.

When a voltage is applied to the gate electrode 3, the depletion layer formed in the body region 13 extends to the body contact region Rbc. However, in the semiconductor device of this embodiment, the metal silicide layer 42 is not formed on the region within the distance dbc from the gate electrode 3 in the body contact region Rbc.
The crystal defects that occur during the formation of the are not distributed. Therefore, it is less likely that the depletion layer reaches the region of the SOI layer 1 where the crystal defect is formed.

As a result, the possibility that the crystal defects taken into the depletion layer will become recombination centers is reduced, so that a clean pn junction, which is the original recombination between the body region and the source region or between the body region and the drain region, is reduced. A leak current is generated by the coupling current and the diffusion current, and the dependency of the leak current on the gate voltage is reduced.

Although the n-channel type transistor has been described as an example in the present embodiment, the same effect can be obtained by applying the present invention to a p-channel type transistor.

(Third Embodiment) The third embodiment of the present invention will be described below.
The embodiment will be described by taking an n-channel type MIS type SOI transistor as an example.

FIG. 7 is a sectional view showing the structure of the SOI transistor of the third embodiment. In addition, in FIG.
2 shows a cross section in the body contact region-gate electrode-drain region similarly to the line II-II of FIG.
The same components as those in FIG. 2 are designated by the same reference numerals.

As shown in FIG. 7, in the present embodiment, the second
In the body contact region Rbc shown in the above embodiment.
P-type impurity having a concentration higher than that of the region 13⁺
The impurity layer 51 is formed. p⁺P-type of impurity layer 51
Impurity concentration is 10²⁰-10 ^{twenty one}cm^-3Set to about
It The other configuration is the same as that of the second embodiment.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
8A to 8D are cross-sectional views showing the manufacturing process of the semiconductor device of the third embodiment. 8A to 8D, in the same manner as the cross section II-II of FIG.
It shows a cross section in the gate electrode-drain region,
The same components as those in FIGS. 1 and 2 are designated by the same reference numerals.

First, in the step shown in FIG. 8A, the buried oxide film 11 and the SOI layer 1 are formed on the supporting substrate 10 by the same method as in the first embodiment. Then, after the body region 13 is formed in the SOI layer 1 by the ion implantation method or the like, the gate oxide film 12 and the gate electrode 3 are formed.

Then, n ⁻ source layer (not shown), n ⁻
The drain layer 14 is formed, and the gate sidewall 18 is formed on the side surface of the gate electrode 3. Then the SOI layer 1
A resist (not shown) is formed on the body contact region Rbc, and the arsenic ions As are formed using the resist, the gate electrode 3 and the gate sidewall 18 as a mask.
^Implant n-type impurities such as ⁺ .

Thereafter, a photoresist (not shown) is applied on the substrate by photolithography to a thickness of about 1 μm, and the body contact region R of the SOI layer 1 is applied.
Expose the top of bc. And by the ion implantation method,
P-type impurity ions such as boron ions B ⁺ are implanted into the body contact region Rbc at an acceleration energy of 10 keV and a dose of 3 × 10 ¹⁵ cm ^-2 .

After that, annealing at 1000 ° C. for about 10 seconds is performed to form an n ⁺ source layer (not shown), an n ⁺ drain layer 15 and ap ⁺ impurity layer 51.

Next, in the step shown in FIG. 8B, 100 is formed on the substrate by the CVD method by the same method as in the second embodiment.
A silicon oxide film 42a having a thickness of about nm is deposited. Then, a photoresist of about 1 μm is applied and patterned on the silicon oxide film by the photolithography method. As a result, the photoresist 44 remains on the region within the distance dbc from the gate electrode 3 in the body contact region Rbc.

Next, in the step shown in FIG. 8C, a wet etching method is performed using a dilute solution of hydrofluoric acid, so that a portion of the body contact region Rbc located within the distance dbc from the gate electrode 3 is removed. Then, a silicon oxide film pattern 42 is formed.

Then, a metal 43 such as titanium (Ti), cobalt (Co) or the like is deposited on the substrate with a thickness of about 8 nm by a sputtering method or the like.

Next, in the step shown in FIG. 8D, 500 ° C.
Annealing is performed at the temperature of about 60 seconds. When annealing is performed, a silicide reaction between silicon (Si) and a metal occurs in a region of the SOI layer 1 which is not covered with the gate sidewall 18 and the silicon oxide film pattern 42. As a result, metal silicide layers 41, 16 and 17 are formed on the source region, the drain layer 15 and the gate electrode 3 and on the region of the body contact region Rbc not covered by the silicon oxide film pattern 42. It

Then, according to a usual method for manufacturing a MIS transistor, an interlayer insulating film 19 is deposited on the substrate, and contacts 7 and 9 penetrating the interlayer insulating film 19 and reaching the metal silicide layers 41 and 17 are formed. . Then, a wiring 20 made of a metal such as aluminum (Al) and in contact with the contacts 7 and 9 is formed. Through the above steps, the SOI transistor of this embodiment is formed.

In this embodiment, the same effect as in the second embodiment can be obtained. In addition, by forming the p ⁺ impurity layer 51 in the body contact region Rbc, the contact resistance between the metal silicide layer 41 and the SOI layer 1 can be reduced, and the body potential can be controlled more stably. can get.

Although the n-channel transistor has been described as an example in the present embodiment, the same effect can be obtained by applying the present invention to a p-channel transistor.

(Fourth Embodiment) The fourth embodiment of the present invention will be described below.
The embodiment will be described by taking an n-channel type MIS type SOI transistor as an example.

FIG. 9 is a sectional view showing the structure of the SOI transistor of the fourth embodiment. In addition, in FIG.
2 shows a cross section in the body contact region-gate electrode-drain region similarly to the line II-II of FIG.
The same components as those in FIG. 2 are designated by the same reference numerals.

As shown in FIG. 9, in the present embodiment, the third
P ⁺ impurity layer 51 of the SOI layer 1 shown in the embodiment of
And the body region 13 are formed with ap ⁻ impurity layer 61. The p ⁻ impurity layer 61 is the same as the p ⁻ impurity layer 61 shown in the first embodiment, and the p-type impurity concentration is 10 ¹⁸ to 10 ²⁰ cm ⁻³ .

Where p^-P-type impurity concentration of the impurity layer 61
The p-type impurity concentration of the body region 13 is 10 degrees.¹⁷-10¹⁸
cm^-3Higher, p⁺It is the impurity concentration of the impurity layer 51.
10 ²⁰-10^{twenty one}cm^-3Preferred to be lower than
Good

The p ^- impurity layer 61 is formed on the gate electrode 3
Is preferably formed so as to extend from below the edge portion to below the gate sidewall 18 and contact the p ⁺ impurity layer 51. However, if the p ⁻ impurity layer 61 is interposed at least between the channel region and the p ⁺ impurity layer 51, the effect of this embodiment can be obtained.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 10A to 10D are cross-sectional views showing the manufacturing process of the semiconductor device of the fourth embodiment. FIG. 10 (a)-
1D shows a cross section in the body contact region-gate electrode-drain region similarly to the line II-II in FIG. 1, and the same components as those in FIGS. 1 and 2 are designated by the same reference numerals. There is.

First, in the step shown in FIG. 10A, the buried oxide film 11 and the SOI layer 1 are formed on the supporting substrate 10 by the same method as in the first embodiment. Then, after the body region 13 is formed in the SOI layer 1 by the ion implantation method or the like, the gate oxide film 12 and the gate electrode 3 are formed.

Then, the source drain of the SOI layer 1
An n-type impurity is ion-implanted into the ion formation region. Then,
Forming a resist by photolithography and
In the body contact region Rbc of the layer 1, boron ion
B⁺Acceleration energy of 5 p type impurity ions such as
V, dose amount 2 × 10¹⁵cm^-2Inject. After that,
Remove the dys and anneal at 950 ℃ for 10 seconds.
By performing n ^-Source layer (not shown), n^-Do
Rain layer 14 and p^-The impurity layer 61 is formed.

Next, in the step shown in FIG. 10B, CVD
By the method, a silicon oxide film such as an HTO film or a TEOS film is deposited on the substrate to a thickness of about 70 nm.
Then, anisotropic dry etching is performed to form the gate sidewall 18 on the side surface of the gate electrode 3.

Next, arsenic ions As ⁺ are accelerated in the source / drain formation region of the SOI layer 1 at an acceleration energy of 10 ke.
After implantation with V and a dose of 10 ¹⁵ cm ^-2 , boron ions B ⁺ are accelerated in the body contact region Rbc with an acceleration energy of 1
Implantation is performed at 0 keV and a dose of 10 ¹⁵ cm ^-2 .

Then, annealing is performed at 1000 ° C. for a short time of about 10 seconds to form n ⁺ source region (not shown), n ⁺ drain layer 15 and p ⁺ impurity layer 51.

Next, by the same method as in the second embodiment, C
A silicon oxide film 42a of about 100 nm is deposited on the substrate by the VD method. Then, a photoresist of about 1 μm is applied and patterned on the silicon oxide film by the photolithography method. As a result, the photoresist 44 remains on the region within the distance dbc from the gate electrode 3 in the body contact region Rbc.

Next, in the step shown in FIG. 10C, a wet etching method is performed using a diluting solution of hydrofluoric acid to remove the gate electrode 3 in the body contact region Rbc.
A silicon oxide film pattern 42 is formed on a region located within a distance dbc from.

Then, a metal 43 such as titanium (Ti) or cobalt (Co) is deposited to a thickness of about 8 nm on the substrate by a sputtering method or the like.

Next, in the step shown in FIG.
Annealing is performed at a temperature of ° C for about 60 seconds. When annealing is performed, a silicide reaction between silicon (Si) and metal occurs in a region of the SOI layer 1 which is not covered with the gate sidewall 18 and the silicon oxide film pattern 42. As a result, metal silicide layers 41, 16 and 17 are formed on the source region, the drain layer 15 and the gate electrode 3 and on the region of the body contact region Rbc not covered by the silicon oxide film pattern 42. It

After that, according to a normal MIS transistor manufacturing method, an interlayer insulating film 19 is deposited on the substrate, and contacts 7 and 9 penetrating the interlayer insulating film 19 and reaching the metal silicide layers 41, 16 and 17 are formed. To do. And
A wiring 20 made of a metal such as aluminum (Al) and in contact with the contacts 7 and 9 is formed. Through the above steps, the SOI transistor of this embodiment is formed.

In this embodiment, the same effect as that of the third embodiment can be obtained. In addition, p ^{+ of the} SOI layer 1
The p ⁻ impurity layer 6 is formed between the impurity layer 51 and the body region 13.
By interposing 1, the same effect as that of the first embodiment can be obtained. That is, since the electrical resistance of the portion of the SOI layer 1 below the gate sidewall 18 is reduced, the sheet resistance of the body contact region Rbc can be reduced, and thus the body potential can be controlled more stably.

[0113]

According to the present invention, it is possible to reduce the possibility that the crystal defect layer generated during the formation of silicide is incorporated into the depletion layer extending from the channel region under the gate electrode during the operation of the transistor.

Therefore, at the pn junction between the body region and the source region or between the body region and the drain region,
It is possible to suppress an abnormal leak current caused by a crystal defect taken into the depletion layer serving as a recombination center, and an accurate diode current can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing the structure of an SOI transistor of the present invention.

FIG. 2 is a cross-sectional view showing a structure in a II-II cross section of FIG.

3A to 3D are cross-sectional views taken along the line II-II showing the manufacturing process of the semiconductor device of the first embodiment.

FIG. 4 is a graph showing a gate voltage dependence characteristic of a body current in the semiconductor device of the first embodiment.

FIG. 5 is a cross-sectional view showing the structure of the SOI transistor of the second embodiment.

6A to 6D are cross-sectional views showing a manufacturing process of the semiconductor device of the second embodiment.

FIG. 7 is a cross-sectional view showing the structure of the SOI transistor of the third embodiment.

8A to 8D are cross-sectional views showing a manufacturing process of the semiconductor device of the third embodiment.

FIG. 9 is a cross-sectional view showing the structure of the SOI transistor of the fourth embodiment.

10A to 10D are cross-sectional views showing the manufacturing process of the semiconductor device of the fourth embodiment.

FIG. 11 is a plan view showing the structure of a conventional n-channel SOI transistor.

12 is a cross-sectional view showing the structure of the XII-XII cross section of FIG.

FIG. 13 is a graph showing a gate voltage dependence of a body current in a conventional BS transistor.

[Explanation of symbols]

1 SOI Layer 2 Silicon Oxide Film 3 Gate Electrode 4 Source Region 5 Drain Region 6 Source Contact 7 Drain Contact 8 p ⁺ Impurity Layer 9 Body Contact 10 Supporting Substrate 11 Embedded Oxide Film 12 Gate Insulation Film 13 Body Region 14 n ^- Drain Layer 15 n ⁺ drain layer 16 metal silicide layer 17 metal silicide layer 18 gate sidewall 19 interlayer insulating film 20 wiring 21 n-type impurity 22 photoresist 23 p-type impurity 24 p ^- impurity layer 41 metal silicide layer 42 silicon oxide film pattern 43 metal 42a Silicon oxide film 44 Photoresist 51 p ⁺ Impurity layer 61 p ⁻ Impurity layer

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F110 AA06 AA15 CC02 DD13 EE05                       EE09 EE14 EE32 FF02 GG02                       GG12 GG22 GG23 GG24 GG32                       GG34 GG52 GG60 HJ01 HJ13                       HJ23 HK05 HK33 HK40 HL03                       HM15 NN02 QQ11

Claims (9)

[Claims] 1. A semiconductor layer provided on an insulating film, a gate electrode provided on the semiconductor layer, and a first conductivity type provided at least under the gate electrode in the semiconductor layer. A channel region; a contact region provided on a side of the channel region in the gate width direction of the gate electrode in the semiconductor layer, the contact region including a first conductivity type impurity having a higher concentration than that of the channel region; A contact electrically connected to supply a voltage to the channel region and interposed between the channel region and the contact region of the semiconductor layer, higher than the channel region, and higher than the contact region. A semiconductor device comprising: an impurity layer having a low concentration of first conductivity type impurities; and a silicide layer provided on the contact region. 2. A semiconductor layer provided on an insulating film, a gate electrode provided on the semiconductor layer, and a first conductivity type provided at least under the gate electrode in the semiconductor layer. A channel region, a source region and a drain region provided on the side of the channel region in the gate length direction of the gate electrode of the semiconductor layer, and the source region and the drain region on the source region and the drain region. A silicide layer provided apart from each other by a distance of 1, a contact region provided on a side of the channel region in the gate width direction of the gate electrode of the semiconductor layer, and a part of the contact region on the contact region. A silicide layer provided apart from the gate electrode by a second distance longer than the first distance. 3. The semiconductor device according to claim 2, wherein a depletion layer generated during operation of the semiconductor device does not reach a position in the semiconductor layer that is at the second distance from the gate electrode. A semiconductor device characterized by: 4. The semiconductor device according to claim 2, wherein the contact region has a first conductivity type impurity having a higher concentration than that of the channel region. 5. The semiconductor device according to claim 4, wherein between the channel region and the contact region, a first conductivity type impurity having a concentration higher than that of the channel region and lower than that of the contact region. A semiconductor device, wherein an impurity layer having: is formed. 6. A method of manufacturing a semiconductor device, comprising a semiconductor layer provided on an insulating film, the semiconductor layer having a channel region of a first conductivity type and a contact region for supplying a voltage to the channel region. A step (a) of forming a gate electrode with a gate insulating film sandwiched between the layers, and at least a region between the channel region and the contact region by implanting ions into the semiconductor layer from above the gate electrode. A step (b) of forming an impurity layer containing a higher concentration of the first conductivity type impurity than the channel region, a step (c) of forming an insulating sidewall on a side surface of the gate electrode, and the gate By implanting ions into the semiconductor layer from above the electrode and the insulating sidewall, the concentration of the first conductivity type impurity in the contact region is increased. And step (d) of higher than the impurity concentration of the impurity layer, a method of manufacturing a semiconductor device, characterized in that it comprises a step (e) to form at least silicide layer on the contact region. 7. A method of manufacturing a semiconductor device comprising a semiconductor layer provided on an insulating film, the semiconductor layer having a channel region, source / drain regions, and a contact region for supplying a voltage to the channel region. A step (a) of forming a gate electrode on the semiconductor layer with a gate insulating film interposed therebetween, a step (b) of forming an insulating sidewall on a side surface of the gate electrode, the gate electrode and the insulation (C) forming a source / drain layer separated from the gate electrode by a first distance by implanting an impurity of the second conductivity type into the semiconductor layer from above the conductive sidewall; A step (d) of forming a protective insulating film on the contact region in a region located at a second distance, and the contact region after the step (d). The upper,
Forming a silicide layer spaced apart from the gate electrode by the second distance, and forming a silicide layer spaced apart from the gate electrode by the first distance on the source / drain layer; And the second distance is longer than the first distance. 8. The method of manufacturing a semiconductor device according to claim 7, wherein after the step (b) or the step (c), the contact region is formed on the gate electrode and the insulating sidewall. A method of manufacturing a semiconductor device, further comprising the step of implanting a first conductivity type impurity. 9. The method for manufacturing a semiconductor device according to claim 8, wherein after the step (a), the first conductive material is provided on the gate electrode and at least between the channel region and the contact region. A method for manufacturing a semiconductor device, which comprises implanting a type impurity.