JP2002270824A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a complementary MISFET having stabilized characteristics. SOLUTION: After forming a gate electrode 20 and a sidewall spacer, a high-concentration impurity element is ion-implanted and heat-treated to form a high-concentration source / drain diffusion region 25, and after removing the sidewall spacer, a low-concentration impurity element is ionized. LDD diffusion region 2 by implantation and heat treatment
8 and the pocket region 27, and after the surface of the high-concentration source / drain diffusion region 25 is wet-cleaned, the sidewall spacers 31a and 31b are formed.
A silicide 32 is formed on the drain diffusion region 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a MISFET (Metal Insulator
The present invention relates to a technique for stabilizing characteristics such as a threshold value of a lator semiconductor field effect transistor) and a drain current.

[0002]

2. Description of the Related Art As semiconductor integrated circuit devices have become more highly integrated, the size of MISFETs has been reduced. On the other hand, the electric field inside MISFETs has increased due to restrictions on the reduction of the power supply voltage. Is the source / drain junction region near the channel. LDD is generally used as a method for alleviating the increase in the electric field.
(Lightly Doped Drain) structure.

[0003] Taking n-type channel MISFET as an example, n is an LDD region ^- as well as around the diffusion layer, p ^-
By providing a diffusion layer (a so-called pocket structure), a method of further suppressing deterioration of the MISFET characteristics such as a short channel effect by suppressing the spread of a depletion layer of the n ^- diffusion layer.

On the other hand, with the formation of a shallow source / drain junction, the sheet resistance of the source / drain diffusion layer increases,
In order to avoid the problem that the drain current of the MISFET is lowered, the low-resistance silicide layer formed on the diffusion layer by thermally reacting the refractory metal material with the substrate silicon suppresses the increase in the sheet resistance of the diffusion layer. A technique is used.

[0005]

SUMMARY OF THE INVENTION MISF having LDD structure
In the manufacturing process of the ET, taking an n-channel MISFET as an example, an n ⁻ diffusion layer is formed by performing heat treatment after ion implantation of a low-concentration impurity element, and then a side surface is formed by a thermal CVD method involving heating at about 700 ° C. A wall is formed, and a heat treatment is performed after ion implantation of a high-concentration impurity element to form an n ^- diffusion layer. In this step,
n ^- By heating process two more times after the diffusion layer formation is added, n ^- by impurity elements in the diffusion layer is diffused again, n ^- a problem that diffusion occurs the destabilization of such expanding There is.

After this LDD structure is formed, it is necessary to remove the etching stopper film on the substrate surface at the time of ion implantation by wet etching or remove the through oxide film on the substrate surface after ion implantation by wet etching. Therefore, at the same time, the side wall insulating film is also etched and thinned. By reducing the thickness of the sidewall insulating film, a silicide film that is subsequently formed by digging into the substrate in the n ⁺ diffusion layer is formed closer to the end of the n ⁺ diffusion region near the sidewall insulating film. And the n ⁺ diffusion region around the silicide film is substantially reduced.
There is a problem that the drain junction is easily broken and the leak current increases.

As described above, the instability of the n ⁻ diffusion region causes a change in the effective channel length of the MISFET, etc.
The driving capability of the vehicle.

Further, a MISFE having a pocket structure
In the case of T, the above-described effect extends not only to the n ⁻ diffusion layer but also to the p ⁻ diffusion layer (pocket region) around the n ⁻ diffusion layer, so that the influence on the MISFET characteristics is further increased. The problem will get worse.

In a complementary MISFET (CMISFET) having a trench-type element isolation region, the exposed edge portion of the upper part of the insulating film buried in the element isolation region is formed by a wet etching process. Become. Therefore, when the silicide formed in the element isolation region by the salicide method is formed by entering the recess, the silicide is formed deeply on the inner wall of the element isolation region near the end of the source / drain diffusion region. There is also a problem that the silicide comes into direct contact with the substrate silicon (well region) and causes a leakage current at the source / drain junction.

An object of the present invention, after the gate electrode forming the n ^- before the formation of the diffusion layer, by performing the formation of sidewall films formed and the n ⁺ diffusion layer by the thermal CVD method is a heating step, n ^- diffusion It is an object of the present invention to provide a technique capable of preventing re-diffusion of impurities in an LDD region or a pocket region and preventing deterioration of MISFET characteristics by eliminating the above-described two heat treatment steps after forming a layer. .

Another object of the present invention is to provide an etching step for reducing the thickness of a sidewall film before forming silicide on a source / drain diffusion layer, that is, wet etching removal of a through oxide film after ion implantation or removal of an etching stopper film. By eliminating the wet etching removal step, the source / drain diffusion region around the silicide film is substantially reduced due to the thinning of the sidewall film, and the MISFET characteristics are deteriorated due to an increase in the leak current at the source / drain junction. It is an object of the present invention to provide a technology capable of preventing the problem.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

Means for Solving the Problems Of the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the present invention, a high-concentration impurity is formed by forming a first sidewall insulating film after forming a gate electrode, performing ion implantation using the first sidewall insulating film and the gate electrode as a mask, and performing heat treatment. After forming a diffusion region, the first sidewall insulating film is removed, and ion implantation is performed using the gate electrode as a mask.
A low-concentration impurity diffusion region and a pocket region are formed by performing a heat treatment, and a second sidewall insulating film is formed after wet-cleaning the surface of the diffusion region after ion implantation, and is formed on the high-concentration impurity diffusion region. It has a step of forming silicide.

Further, the present invention has a step of forming a sidewall insulating film also in a concave portion formed above the inner wall of the element isolation region when the device has a trench type element isolation region.

According to the present invention, the heating step for forming the high-concentration impurity diffusion region and the sidewall insulating film is performed before the formation of the low-concentration impurity diffusion region. The influence of the heating step during formation does not affect the low-concentration impurity diffusion region, preventing the re-diffusion of the impurities in the low-concentration impurity diffusion region and the pocket region, and the MISFET characteristics such as the threshold fluctuation due to the fluctuation of the effective channel length. Degradation can be prevented.

According to the present invention, when silicide is formed on the high-concentration impurity diffusion region after the formation of the LDD structure, the etching stopper film on the surface of the high-concentration impurity diffusion region is removed by wet etching before silicide formation. By performing the cleaning step before the formation of the sidewall insulating film, the thickness of the sidewall insulating film can be prevented from being reduced by wet etching, and the high-concentration impurity diffusion region around the silicide film is substantially reduced. To prevent the leakage current from rising.
The drive capability of the SFET can be prevented from lowering. At the same time, as a means for preventing the side wall insulating film from being thinned by wet etching, it is possible to form the thermal CVD process of the second side wall insulating film at a lower temperature than the first side wall insulating film. Therefore, re-diffusion of impurities in the low concentration impurity diffusion region and the pocket region can be further prevented.

Further, according to the present invention, the silicide formed on the high-concentration impurity diffusion region is also formed in the concave portion on the inner wall of the trench-shaped element isolation region.
It is possible to prevent an increase in leakage current at the junction near the trench-shaped element isolation region in the high-concentration impurity diffusion region, and to prevent deterioration of complementary MISFET characteristics.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

A MOSFET according to an embodiment of the present invention
(Metal Oxide Semiconductor Field Effect Transisto
r) will be described with reference to FIGS. 1 to 17 as a method of manufacturing a complementary MOSFET (CMOSFET).

First, as shown in FIG.
A semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about Ωcm is thermally oxidized at 800 to 850 ° C., and a silicon oxide film (pad oxide film) is formed on its main surface for the purpose of stress reduction and protection of an active region. After forming the silicon nitride film 2, a silicon nitride film 3 is deposited on the silicon oxide film 2 by a CVD method.

Next, as shown in FIG. 2, after the silicon nitride film 3 and the silicon oxide film 2 in the element isolation region are removed by etching using a photoresist (not shown) as a mask,
As shown in FIG. 3, the semiconductor substrate 1 in the element isolation region has a depth of 350 to
A 400 nm groove 4 is formed. The groove 4 is formed in the semiconductor substrate 1
The side wall of the substrate is tapered by adjusting the composition of the etching gas. By providing the side walls of the groove 4 with a taper, the insulating film can be easily buried inside the groove 4.

The trench 4 can also be formed by sequentially etching the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 in the element isolation region using a photoresist as a mask. When the semiconductor substrate 1 is etched using a photoresist as a mask, the silicon nitride film 3 serving as a mask for thermal oxidation can be prevented from being reduced in thickness, so that the initial thickness of the silicon nitride film 3 can be reduced. After the formation of the groove 4, the inside of the groove 4 is wet-cleaned to remove the etching residue.

Next, as shown in FIG.
Is thermally oxidized at, for example, 950 ° C. to form a silicon oxide film 5 on the inner wall of the groove 4. The silicon oxide film 5 is formed to recover the etching damage caused on the inner wall of the groove 4 and to relieve the stress of the silicon oxide film (6) embedded in the groove 4 in a later step.

Next, as shown in FIG. 6, a silicon oxide film 7 is deposited on the main surface of the semiconductor substrate 1 by a CVD method, so that the silicon oxide film 7 is embedded in the trench 4. The silicon oxide film 7 is made of a silicon oxide material having good fluidity, such as a silicon oxide film formed using ozone (O ₃ ) and tetraethoxysilane ((C ₂ H ₅ ) ₄ Si). use. At this time, prior to the step of depositing the silicon oxide film 7, a thin silicon nitride film 6 may be deposited on the inner wall of the trench 4 by a CVD method as shown in FIG. This silicon nitride film 6 suppresses the growth of the silicon oxide film 5 on the inner wall of the groove 4 on the active region side when the silicon oxide film 7 buried in the groove 4 is sintered (burned) in a later step. Therefore, the silicon oxide film 5 is formed on the semiconductor substrate 1 in the active region.
Can be prevented from forming a leak path due to stress.

Next, sintering (sintering) for improving the film quality of the silicon oxide film 7 buried in the groove 4 is performed by wet oxidizing the semiconductor substrate 1 at a temperature of 1000 ° C. or less, for example, 850 ° C. .

Next, as shown in FIG. 7, the silicon oxide film 7 is polished using, for example, a chemical mechanical polishing (CMP) method to flatten the surface. This polishing uses the silicon nitride film 3 covering the active region as a stopper so that the silicon oxide film 7 remains only inside the trench 4. Thus, the element isolation trench 4 in which the silicon oxide film 7 is embedded is completed.
Thereafter, as shown in FIG. 8, the silicon nitride film 3 covering the active region is removed using an etching solution such as hot phosphoric acid.

The sintering of the silicon oxide film 7 buried in the groove 4 may be performed after the silicon oxide film 7 is polished by a chemical mechanical polishing method and the silicon oxide film 7 is left only inside the groove 4. In this case, the sintering time can be reduced because the silicon oxide film 7 to be sintered is thinner than when sintering is performed before polishing the silicon oxide film 7.

Next, as shown in FIG. 9, an n-type impurity such as P (phosphorus) is ion-implanted into a part of the semiconductor substrate 1, and a p-type impurity such as B (boron) is ion-implanted into another part. After the implantation, the semiconductor substrate 1 is subjected to a heat treatment at a temperature of 1000 ° C. or less, for example, 950 ° C. to extend and diffuse the two kinds of impurities, thereby forming an n-channel MOSF.
A p-type well 8 is formed in an ET formation region, and an n-type well 9 is formed in a p-channel MOSFET formation region. The gate oxide film to be formed later may be formed on the surface of p-type well 8 and n-type well 9 after forming them.

Next, a complementary MOS transistor is formed in the active region of the semiconductor substrate 1 whose periphery is defined by the device isolation groove 4 by the following method.
Form an FET.

First, the silicon oxide film (pad oxide film) 2 remaining on the surface of the active region is removed using a hydrofluoric acid solution or the like. At this time, the silicon oxide film 7 in the element isolation trench 4
Has a convex shape whose upper part protrudes from the surface of the semiconductor substrate 1. For this reason, erosion by the hydrofluoric acid aqueous solution occurs not only from above but also from the lateral direction with respect to the substrate surface at the edge of the convex portion, and the etching proceeds more quickly. Therefore, after the silicon oxide film 2 is removed, the upper portion of the silicon oxide film 7 in the element isolation trench 4 is also etched away, and the shape thereof is such that the concave portion 10 is formed at the edge as shown in FIG. become.

Next, as shown in FIG.
Is thermally oxidized at 800 to 850 ° C. to form a clean gate oxide film 11 on its surface.

Next, P-doped polycrystalline silicon for a gate electrode is deposited by a CVD method, and as shown in FIG. 12, a polycrystalline silicon film is patterned and formed by etching using a photoresist as a mask. On this occasion,
An n-channel MOSFET gate electrode 20 is formed on the p-type well 8, and a p-channel MOSFET gate electrode 21 is formed on the n-type well 9.

Next, as shown in FIG.
An etching stopper film 22 is formed by depositing by CVD method on the entire regions exposed to 0 and 21 and other surfaces. The material of the etching stopper film 22 is made different from each other in order to obtain an etching selectivity with the sidewall spacer 23 when the sidewall spacer 23 is subsequently formed. For example, silicon oxide is used as the etching stopper film 22 and LP
It is formed by deposition by a CVD method. At this time, the etching stopper film 22 may be a silicon nitride film, and the sidewall spacer 23 may be a silicon oxide film.

Next, referring to FIG.
The gate electrode 20 is deposited on the etching stopper film 22 by PCVD and selectively dry-etched.
Then, a sidewall spacer 23 is formed on the side wall of the gate electrode 21 outside the etching stopper film 22. In this case, the sidewall spacers 24 are also formed on the side walls of the recess 10 of the element isolation groove 4.

Next, as shown in FIG.
The spacer 23 and the gate electrodes 20 and 21 are used as a mask.
Then, an n-type impurity such as P (2 × 10¹⁵
cm ^-2) And ion implantation into the n-type well 9
P-type impurities such as (boron) (2 × 10¹⁵cm^-2)
Driving on. Then to activate each impurity
Heat treatment to provide a high concentration of n for n-channel MOSFET
⁺Type diffusion region (source, drain) 25 and p channel
High concentration p for flannel MOSFET⁺Diffusion area (saw
, Drain) 26 are formed.

Next, as shown in FIG. 15, the sidewall spacers 23 made of a silicon nitride film are removed with hot phosphoric acid. Further, using the gate electrodes 20 and 21 surrounded by the etching stopper film 22 as a mask, a p-type impurity such as B is added to the p-type well 8 to form a pocket region 27 of the n-channel MOSFET from the surface of the semiconductor substrate 1 by about For example, ions are implanted to a depth of about 50 to 100 nm as a dose of about 5 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² , and then an n-type impurity such as As is added to the semiconductor substrate 1 to form the LDD region 28. A dose of, for example, 1 × 10 ¹⁴ cm ^{−2 is} implanted as a dose into a depth of about 50 nm from the surface. Further, an n-type impurity such as P is formed in the n-type well at a depth of about 50 to 100 nm from the surface of the semiconductor substrate 1 to form a pocket region 29 of the p-channel MOSFET at a dose of, for example, 5 × 10 ¹² to 5 × 10
Ion implantation is performed at about ¹³ cm ^-2 , and then LDD region 30
For formation, a p-type impurity such as B is dosed at a depth of about 50 nm from the surface of the semiconductor
Implant 10 ¹⁴ cm ^-2 ions. Next, LDD region 2
Heat treatment is performed at a heat treatment temperature of 950 to 1000 ° C. in order to activate 8, 30 and the pocket regions 27 and 29.

Next, as shown in FIG. 16, the etching stopper film 22 made of silicon oxide is removed with a hydrofluoric acid aqueous solution. If the etching stopper film 22 is made of silicon nitride, it is removed with an aqueous solution of hot phosphoric acid or the like. Subsequently, sidewall spacers 31a and 31b are formed on the side walls of the recesses 10 in the gate electrodes 20 and 21 and the element isolation trench 4, respectively. The sidewall spacers 31a and 31b are formed by depositing a silicon oxide film or a silicon nitride film on the semiconductor substrate 1 by a CVD method and patterning the film by anisotropic etching.

[0039] As described above, the formation of the LDD regions 28, 30 and the pocket regions 27, 29, n ⁺ -type diffusion region 25
And after the formation of the p ⁺ type diffusion region 26, L
The respective diffusion layers of the DD regions 28 and 30 and the pocket regions 27 and 29 are not affected by the heating process due to the formation of the n ⁺ -type diffusion region 25 and the p ⁺ -type diffusion region 26 and the formation of the sidewall spacer. Therefore, the LDD regions 28 and 30
Also, the diffusion layer impurities in the pocket regions 27 and 29 do not re-diffuse.

Next, for example, cobalt as a high melting point metal is deposited on the entire surface by a CVD method, and
As shown in FIG. 17, a silicide 32 is selectively formed on the gate electrodes 20 and 21 and in the regions where the source / drain diffusion layers 25 and 26 are exposed.

Since the side wall spacer 31a formed as described above does not become thinner by wet etching, the silicide layer formed by the above-described steps is
Since the source / drain junction is not destroyed near the side wall spacer 31a of the source / drain diffusion regions 25 and 26, the MISFET characteristics do not deteriorate. Further, by forming the sidewall spacer 31b in the concave portion 10 in the element isolation groove 4, the silicide 32 formed on the source / drain diffusion layers 25 and 26 is formed up to the inner wall of the element isolation groove 4. Therefore, the element isolation groove 4 at the source / drain junction
No junction breakdown occurs in the vicinity.

[0042]

The effects obtained by the invention disclosed in the present application will be briefly described as follows.

It is possible to prevent re-diffusion of impurities in the LDD region and the pocket region and prevent deterioration of MISFET characteristics.

Further, even when silicide is formed on the diffusion layer, it is possible to prevent an increase in the leak current of the silicided junction near the sidewall.

Further, even in the case where a trench-shaped element isolation region is provided, it is possible to prevent an increase in leakage current of a silicided junction near the element isolation region.

As a result of obtaining the above effects, the complementary MIS
Deterioration of FET characteristics can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate (wafer) 2 silicon oxide film 3 silicon nitride film 4 element isolation region 5 silicon oxide film 6 silicon nitride film 7 silicon oxide film 8 p-type well semiconductor region 9 n-type well semiconductor region 10 recess 11 gate oxide film 20 gate Electrode 21 Gate electrode 22 Etching stopper film 23 Side wall spacer 24 Side wall spacer 25 n ⁺ type source / drain diffusion region 26 p ⁺ type source / drain diffusion region 27 p ⁻ type pocket diffusion region 28 n ⁻ type LDD diffusion region 29 n ^- -type pocket doped region 30 p ^- -type LDD diffusion regions 31a sidewall spacers 31b sidewall spacers 32 silicide

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 F term (Reference) 5F032 AA39 AA45 AA46 AA70 DA02 DA53 DA74 DA78 5F048 AA04 AA07 AC01 AC03 BA01 BB06 BC06 BD04 BE03 BG14 DA25 5F140 AA21 AA24 AB03 BE03 BE07 BF04 BF11 BF18 BG09 BG12 BG14 BG28 BG37 BG50 BG52 BG54 BH15 BH36 BJ01 BJ08 BK03 BK13 BK20 BK22 BK23 CB04 CB08 CE07 CF04

Claims (5)

[Claims] (A) forming a gate electrode on a semiconductor substrate; (b) forming a first sidewall insulating film on both side walls of the gate electrode; Introducing an impurity element into the semiconductor substrate by ion implantation and performing a first heat treatment to form first diffusion regions on both sides of the first sidewall insulating film; and (c) forming the first diffusion region on both sides of the first sidewall insulating film. (D) thereafter, the second conductive type impurity element having the same conductivity type as the first conductive type impurity element and having a lower concentration than the first conductive type impurity element. Introducing an impurity element into the semiconductor substrate by ion implantation and performing a second heat treatment to form second diffusion regions on both sides of the gate electrode; and (e) forming a second sidewall insulating film. Forming on both side walls of the gate electrode. Method for producing a body integrated circuit device. (A) forming a gate electrode on a semiconductor substrate; (b) forming an etching stopper film on the gate electrode surface and on the semiconductor substrate; and (c) forming a gate electrode on the semiconductor substrate. Forming a first side wall insulating film of a material different from that of the etching stopper film on both side walls outside the etching stopper film; and (d) forming a first side wall using the first side wall insulating film and the gate electrode as a mask. Is introduced into the semiconductor substrate through the etching stopper film by an ion implantation method, and a first heat treatment is performed to form a first diffusion region on both sides of the first sidewall insulating film. (E) selectively removing the first sidewall insulating film; and (f) using the gate electrode covered with the etching stopper film as a mask to form the first conductive type. A second impurity element having the same conductivity type as the impurity element and having a lower concentration than the impurity element of the first conductivity type is introduced into the semiconductor substrate through the etching stopper film by an ion implantation method. , By performing a second heat treatment.
Forming a diffusion region on both sides of the gate electrode, (g) removing the etching stopper film on the first and second diffusion regions, and (h) forming a second sidewall insulating film Forming on both side walls of the gate electrode. 3. A step of forming a gate electrode on a semiconductor substrate, a step of forming an etching stopper film on the surface of the gate electrode and on the semiconductor substrate, and Forming a first sidewall insulating film made of a material different from that of the etching stopper film outside the etching stopper film; and (c) forming a first conductivity type using the first sidewall insulating film and the gate electrode as a mask. Is introduced into the semiconductor substrate through the etching stopper film by an ion implantation method, and a first heat treatment is performed to form first diffusion regions on both sides of the first sidewall insulating film. (D) selectively removing the first sidewall insulating film; and (e) using the gate electrode covered with the etching stopper film as a mask, A second impurity element having the same conductivity type as that of the pure element and having a lower concentration than the impurity element of the first conductivity type is introduced into the semiconductor substrate through the etching stopper film by an ion implantation method. (F) further ionizing a third impurity element having a conductivity type different from the first and second conductivity type impurity elements and having a lower concentration than the first conductivity type impurity element. The second and third diffusion regions corresponding to the second and third ion implantation steps are introduced by penetrating the etching stopper film into the semiconductor substrate by an implantation method and performing a second heat treatment. Forming on both sides of the gate electrode such that the third diffusion region is deeper than the second diffusion region and the second and third diffusion regions are in contact with each other; And the front on the second diffusion region A method of manufacturing a semiconductor integrated circuit device, comprising: a step of removing the etching stopper film; and (h) a step of forming a second side wall insulating film on both side walls of the gate electrode. 4. A step of forming a gate electrode on a semiconductor substrate, a step of forming an etching stopper film on the surface of the gate electrode and on the semiconductor substrate, and Forming a first sidewall insulating film of a different material from the etching stopper film outside the etching stopper film; and (c) removing a first conductivity type impurity element using the first sidewall insulating film as a mask. Introducing the etching stopper film into the semiconductor substrate through the etching stopper film by an ion implantation method and forming a first diffusion region by performing a first heat treatment; (d) forming the first side wall insulating film; (E) using the gate electrode covered with the etching stopper film as a mask and having the same conductivity type as the first conductivity type impurity element, and Introducing a second impurity element having a concentration lower than that of the impurity element into the semiconductor substrate through the etching stopper film by an ion implantation method; and (f) further introducing the first and second conductive elements. A third impurity element having a conductivity type different from that of the first conductivity type and a lower concentration than the first conductivity type impurity element penetrates the etching stopper film by ion implantation into the semiconductor substrate. By introducing and performing a second heat treatment, the second and third diffusion regions corresponding to the second and third ion implantation steps are formed on both sides of the gate electrode, and the third diffusion region is formed by the third diffusion region. Forming the second and third diffusion regions deeper than the second diffusion region and making contact with each other; and (g) removing the etching stopper film on the first and second diffusion regions. And (h) Forming two side wall insulating films on both side walls of the gate electrode; and (i) selectively forming silicide in an exposed region of the first diffusion region. A method for manufacturing a semiconductor integrated circuit device. 5. A step of: (a) forming an element isolation region buried by a first insulating film on a semiconductor substrate; (b) forming a gate electrode on the semiconductor substrate; Forming an etching stopper film on the surface of the gate electrode and on the semiconductor substrate; and (d) first sidewalls made of a material different from the etching stopper film on both side walls of the gate electrode outside the etching stopper film. Forming an insulating film; and (e) using the first sidewall insulating film and the gate electrode as a mask, implanting a first conductivity type impurity element through the etching stopper film by an ion implantation method to form an insulating film in the semiconductor substrate. Forming a first diffusion region on both sides of the first sidewall insulating film by performing a first heat treatment; and (f) selectively removing the first sidewall insulating film. And (g) Using the gate electrode covered by the etching stopper film as a mask, a second impurity having the same conductivity type as the first conductivity type impurity element and a lower concentration than the first conductivity type impurity element. Introducing an element into the substrate through the etching stopper film by ion implantation, and (h) further having a conductivity type different from the first and second conductivity type impurity elements, and A third impurity element having a concentration lower than that of the impurity element of the first conductivity type is introduced into the substrate through the etching stopper film by an ion implantation method, and the second and the second heat treatments are performed by performing a second heat treatment. Third diffusion regions corresponding to the third ion implantation step are formed on both sides of the gate electrode, the third diffusion region is deeper than the second diffusion region, and the second and third diffusion regions are formed. Forming a region so that the regions are in contact with each other; (i) removing the etching stopper film on the first and second diffusion regions; and (j) forming a second sidewall insulating film on the gate electrode. (K) forming the inner wall surface of the element isolation region on the inner wall surface of the element isolation region on the inner wall surface of the element isolation region above the first insulating film; Forming a silicide selectively in the exposed region.