JP2003233351A - Liquid crystal display panel drive - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the frequency transient response characteristic of power save control of a liquid crystal display panel driving device to improve display quality and reduce power consumption. An extended compensation period (Tdc) continuous from a display start portion of an effective display period (T1) to a part of the non-display period (T2) is provided, and the output current capability of the source driver (9) for the non-display period (T3) except the extended compensation period (Tdc). The operation of the output stage amplifier is stopped by the control function and the output is controlled to have a high impedance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a liquid crystal display panel for displaying information used in a notebook personal computer, a portable information terminal or the like, or for displaying an image on a television monitor or the like.

[0002]

2. Description of the Related Art In recent years, as information terminals such as personal computers and mobile phones, and as image display monitors, devices equipped with a liquid crystal display panel having light, thin, short and small characteristics have been increasing. Driving of the liquid crystal display panel will be briefly described.

FIG. 3 is a block diagram of a conventional active matrix type liquid crystal display panel. Here, 6 is an image signal electrode line (Sl to Sm) that supplies a voltage corresponding to a display data signal to a pixel, and 7 is a scanning signal electrode line (Xl to Sm) that supplies a selection scanning signal for performing line sequential scanning. Xn) and 2 are thin film transistors (hereinafter referred to as TF) as switching elements controlled by the selection scanning signal from the scanning signal electrode line 7.
(Abbreviated as T), 3 is a liquid crystal display element as a display material having a pixel electrode, 4 is a storage capacitor for suppressing a decrease in image voltage charged in the liquid crystal display element 3, and 8 is a liquid crystal display element 3.
, A source driver for supplying an image signal voltage to each image signal electrode line 6, and a selection scan 10 for performing line-sequential scanning on each scanning signal electrode line 7. It is a gate driver that supplies a signal.
A timing control signal for performing timing control and an image display signal are input to the logic circuit of the source driver 9, and a timing control signal for performing timing control is also input to the logic circuit of the gate driver 10. It should be noted that one display pixel is formed by the display pixel 1 surrounded by a broken line, each of which is composed of one TFT 2, a liquid crystal display element 3, and a storage capacitor 4, and a large number of display pixels constitute an active matrix type liquid crystal display panel 5. To be done.

Image signal electrode lines 6 and scanning signal electrode lines 7
Are arranged in a matrix, whereas the source terminal of the TFT 2 is the image signal electrode line 6, the gate terminal is the scanning signal electrode line 7, and the drain terminal is the pixel electrode of the liquid crystal display element 3 and the storage capacitor. 4 and the other electrode of the storage capacitor 4 is connected to the counter signal electrode 8.

The counter signal electrode 8 is supplied with a counter voltage Vcom. Depending on the type of driving method of the image signal voltage from the source driver 9, a DC voltage or a voltage whose polarity is inverted every horizontal synchronization period (1H) is supplied. use.

To display an image, the source driver 9 supplies an image signal voltage corresponding to a display data signal to the source terminal (S) of each TFT 2 through each image signal electrode line 6, and In synchronization with this, a selected scanning signal is supplied to the gate terminal (G) of each TFT 2 through the scanning signal electrode line 7 selected by the gate driver 10. This allows
The TFTs 2 on the selected scanning signal electrode lines are simultaneously turned on, and the image signal voltage corresponding to the display data signal supplied from the drain terminal (D) and the counter voltage Vcom supplied to the counter signal electrode 8 are supplied. The potential difference between the liquid crystal display element 3 and each storage capacitor 4 is the image display voltage of the final image information.
Accumulated in. This voltage is retained even after the TFT 2 is turned off for one field period in which the next information is written.

In the liquid crystal display element 3, the twist angle of the liquid crystal molecules corresponding to the accumulated voltage amount is changed to control the transmission amount of the light having the directivity by the polarizing plate, so that the contrast is high and the quality is high. The image of can be displayed.

On the other hand, a basic display drive circuit for driving the liquid crystal display panel has a block circuit configuration as shown in FIG.

In the figure, 5 is a liquid crystal display panel, 11 is an image display signal control circuit for supplying an image display signal to a source driver 9 of the liquid crystal display panel 5, and 12 is a source driver 9 and a gate driver 10 of the liquid crystal display panel 5. A timing control signal generating circuit for supplying a signal for controlling the drive timing to the logic circuit, 13 a liquid crystal display signal source which is a signal source necessary for driving the liquid crystal display panel 5, and 14 a power supply for supplying power to the liquid crystal display device. A circuit, 15 is a counter voltage generating circuit for supplying a counter voltage to the counter signal electrode. The opposite voltage may be either an opposite inversion voltage whose polarity is inverted every horizontal synchronization period or a DC voltage.
Here, the case of the counter inversion voltage is shown.

The signal from the liquid crystal display signal source 13 is the image display signal control circuit 11 and the timing control signal generation circuit 12.
The image signal voltage and the timing control signal necessary for the display operation of the liquid crystal display panel 5 are generated from each of them.
In the liquid crystal display panel 5, various voltages necessary for display drive from the power supply circuit 14, image signal voltage from the image display signal control circuit 11 to the source driver 9, and timing control from the timing control signal generation circuit 12 to the source driver 9 and the gate driver 10 A signal is supplied and a display operation is performed.

By the way, especially in portable devices, low power consumption is important. In order to reduce the driving power, it is necessary to suppress unnecessary power consumption in a so-called non-display period such as a blanking period such as a synchronization signal. For example, when the counter voltage is supplied, the power consumption in the stray capacitance formed by the counter signal electrode 8, the power consumption in the overcharge period in the output stage amplifier of the source driver 9, and the gate supplied from the gate driver 10 For example, the power consumption is due to the floating capacitance formed by the scanning signal electrode line 7 due to the selection scanning signal voltage.

As a measure for reducing these electric powers, firstly,
Stopping the amplitude of the counter voltage, secondly, stopping the operation of the output stage amplifier and increasing the output impedance by suppressing the output current capability of the source driver 9, and third, stopping the gate selection scanning signal voltage from the gate driver 10. This is done by minimizing the power consumption during the non-display period.

FIG. 5 shows a timing chart of typical control signals for driving the liquid crystal display panel with low power consumption. The timing is shown in units of one field (1F), which is the cycle of the vertical synchronizing signal. When the number of horizontal synchronization periods in one field is pH,
The effective display period (T1) of the liquid crystal display panel 5 is 1H to n
H, the non-display period (T2) is divided into (n + 1) H to pH. Here, STV is a vertical start signal for starting selective scanning in synchronization with a vertical synchronizing signal, CKV is a vertical clock signal for performing line sequential scanning, and SV is an image supplied from the image display signal control circuit 11. Display signal VS
Image display output voltage output from the output stage amplifier of the source driver 9, PSC is a power save control signal for controlling the driving of the output stage amplifier of the source driver 9 and making the output high impedance, GSC is the gate The gate selection stop signal for controlling the stop of the selection scanning signal output from the driver 10, VCC is the counter voltage generation circuit 1
A counter voltage control signal VCOM for controlling the stop of the counter voltage amplitude at VCOM is a counter voltage output from the counter voltage generating circuit 15. The control signals STV, CKV, GSV are input to the gate driver 10, and the control signal PSC is input to each logic circuit of the source driver 9. The control signals PSC, G
For SC and VCC, active high (Hi) is a valid operation.

First, for the gate driver 10, the timing control signal generating circuit 12 supplies the gate selection signal voltage to the gate selection stop signal GSC in the non-display period (T2).
And part of the valid display period (T1) is high (Hi)
Then, the gate selection signal voltage is stopped and the non-display period (T
The charge loss due to the floating capacitance of the scanning signal electrode line 7 in 2) is eliminated. In the high (Hi) control for a part of the effective display period (T1), if a delay occurs when the gate selection signal voltage is turned off, an image on the liquid crystal display element 3 is temporarily turned on by the upper and lower TFTs 2 simultaneously. It is provided to prevent signal voltage crosstalk. Next, the counter voltage generating circuit 15 is supplied with a counter voltage from the timing control signal generating circuit 12 which is set to high (Hi) in the non-display period (T2) by the counter voltage control signal VCC and inverted every horizontal period. Only the stop DC voltage (center bias voltage in this figure) is used to suppress the charging / discharging power consumed by the stray capacitance of the counter signal electrode 8.

Further, for the source driver 9, the image display output voltage (VS) from the output stage amplifier is the power save control signal PSC for controlling the output current capability of the source driver 9 from the timing control signal generation circuit 12 is low (Lo). )
Since the output operation is enabled in this state, the power is reduced by cutting off the bias current of the output stage amplifier by setting the entire non-display period (T2) and a part of the effective display period (T1) (Tps1) to high (Hi). The power consumption of the output stage amplifier itself can be reduced by stopping the operation and increasing the output impedance.

The source driver 9, the gate driver 10 and the control of the counter voltage have been described as an example of a measure for lowering the driving power of the liquid crystal panel, but from the viewpoint of the sharing ratio of the driving power, in the output stage amplifier of the source driver 9, The analog drive power tends to occupy a large proportion of about one-half to one-half of the whole. From this point of view, further reduction of the analog drive power of the source driver is desired. The point is the relationship with the charging period of the image signal voltage written in the liquid crystal display element 3 from the source driver 9 within the effective display period (T1). For example, since the image signal voltage of a normally white type liquid crystal display panel which is in a white display state when not driven is the minimum voltage in the white display and the maximum voltage in the black display, the white display is similarly performed during the charging period of the liquid crystal display element 3. The minimum charging period (TW) and the maximum charging period (TB) in black display are required. 1 horizontal synchronization period (1H)
Is TH, the maximum period in which power saving is possible is TpsW = TH-TW in white display and TpsB = TH-T in black display.
It becomes B. FIG. 6 is a graph showing the relationship between the power save period and the analog power of the source driver 9.
The power of the analog system is almost inversely proportional to the power save period, and the power in the white display during the power save period = TpsW is PsaW, and the power in the black display during the power save period = TpsB is PsaB. Normally, when the power save period is set to a fixed value, black display, which requires the maximum charge period, is basically required to secure the display quality. Therefore, the power save period (Tps) of the power save control signal PSC is set.
Has a standard value of TpsB.

[0017]

However, when the power save control is performed under the above conditions, the display of the effective display area is started especially when operating at a low temperature or when the logic circuit system driving voltage of the source driver 9 is lowered. The brightness change phenomenon (black display → gray display) due to insufficient charging appears on the line, which becomes a fatal defect in display quality. To avoid this shortage of charge, set the standard power save period to TpsB.
To Tps1 at which no brightness change occurs. As a result, there is a problem that the driving power increases from PsaB to Psa1.

In view of the above-mentioned problems, in the control of the source driver having the power save control function, by improving the frequency transient response characteristic of the power save control signal, the power reduction and the display of the source driver system within the effective display period are displayed. An object of the present invention is to provide a drive device for a liquid crystal display panel, which can improve the display quality of the start line.

[0019]

SUMMARY OF THE INVENTION The present invention comprises a matrix of electrodes composed of image signal electrode lines and scanning signal electrode lines,
A source driver having an output current capability control function for supplying an image signal voltage to the image signal electrode line, a gate driver supplying a scanning selection voltage to the scanning signal electrode line, and each controlled by the image signal voltage and the scanning selection voltage A liquid crystal display panel including an image display element group (thin film transistor, liquid crystal display element, storage capacitor, etc.) provided in the area of the matrix electrode, and a counter signal electrode commonly connected to one of the liquid crystal display elements, An image signal processing circuit that controls an image signal system, a timing control signal generation circuit that controls a drive timing signal of a liquid crystal display panel, and a counter voltage generation circuit that supplies a counter voltage to a counter signal electrode of the liquid crystal display panel. In the driving device of the liquid crystal display panel described above, one field period (1F) for forming an image display is not represented as an effective display period (T1). When the period (T2) is set, an extended compensation period (Tdc) continuous from the display start portion of the effective display period (T1) to a part of the non-display period (T2) is provided, and the extended compensation period (Tdc) is excluded. In a non-display period (T3), the driving device of the liquid crystal display panel is characterized in that the output current amplifier control function is stopped by the output current capability control function of the source driver and the output is controlled to have a high impedance.

Further, according to the present invention, when one field period (1F) for forming an image display is defined as an effective display period (T1) and a non-display period (T2), one horizontal synchronization period (1H) of the effective display period is set. The device for driving a liquid crystal display panel is characterized in that even during a partial period (Tps2) in (), the operation of the output stage amplifier is stopped by the output current capability control function of the source driver and the output is controlled to have a high impedance.

Further, according to the present invention, the extended compensation period (Tdc) continuous from the display start portion of the effective display period (T1) to a part of the non-display period (T2) is set to one horizontal synchronization period (1H) unit. And a driving device for a liquid crystal display panel.

Further, according to the present invention, a matrix-shaped electrode composed of image signal electrode lines and scanning signal electrode lines, a source driver having an output current capability control function for supplying an image signal voltage to the image signal electrode lines, and a scanning A gate driver that supplies a scan selection voltage to the signal electrode line, and an image display element group (thin film transistor, liquid crystal display element, storage capacitor, etc.) provided in the area of each matrix electrode controlled by the image signal voltage and the scan selection voltage. ) And a counter signal electrode commonly connected to one of the liquid crystal display elements, an image signal processing circuit for controlling an image signal system, and a timing for controlling a drive timing signal of the liquid crystal display panel. Driving device for liquid crystal display panel comprising signal generation circuit and counter voltage generation circuit for supplying counter voltage to counter signal electrode of liquid crystal display panel Therefore, when one field period (1F) for forming an image display is defined as an effective display period (T1) and a non-display period (T2), one horizontal synchronization period of the non-display period (T2) and the effective display period ( 1H), the period of the display start line is set to Tps with respect to the period in which the operation of the output stage amplifier is stopped by the output current capability control function of the source driver and the high impedance control of the output is performed.
3 and the period other than the display start line is Tps2, and 0 ≦ Tps3 <Tps2 is satisfied.

According to the present invention, the frequency transient response of the output current capability control of the source driver can be improved, the influence of the frequency response on the output current capability control period within the effective display period can be eliminated, and the driving power can be reduced. To do.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION The cause of the brightness change phenomenon due to insufficient charging at the display start line of the effective display area will be described. The power save control signal PSC has a valid display period (T
1) and the entire non-display period (T2) are controlled, but from the viewpoint of the operating frequency, the effective display period (T1)
Then, in the horizontal display period (1H) of several tens of KHz, the non-display period (T2) is 60H of one field period (1F).
It is around z. Since the display start line where abnormal display quality occurs is the first line where the operating frequency changes rapidly from 60 Hz to several tens of KHz, the delay in the frequency transient response that changes from the low frequency region to the high frequency region has an effect. It seems that the power saving period is longer than it should be because the delay of low frequency response remains in part despite the period of high frequency response, resulting in insufficient charging and display quality. Will be reduced.
In order to solve this, it is necessary for the frequency response characteristics to be in a state of being capable of coping with a sufficiently high frequency operation at the display start time.

FIG. 1 is an embodiment showing a timing chart of main control signals as a measure for improving the frequency transient response characteristic of the power save control signal PSC for low power driving of the present invention. The difference from the conventional example of FIG. 5 is that the power save control signal PS near the display start line in the effective display period.
The extended control of C was performed. Other control signals and the like are the same as in the conventional example of FIG. Here (A),
(B) Extended control of two types of power save control signals PSC will be described.

In (A), the power save control signal PSC is provided in advance of the effective display period (T1) from the non-display period immediately before the start of the effective display period (T1) by providing the extended compensation period (Tdc).
It is a measure to enter 1). As a result, the apparent non-display period (T3) becomes T3 = T2-Tdc. The figure shows an example in which the extended compensation period (Tdc) is set to one horizontal synchronization period (1H). The extended compensation period (Tdc) corresponds to the time for alleviating the influence of the frequency transient response, and starts the display for the power save period (TpsB = Tps2) in the black display that requires the maximum charging time in the effective display period. The extended compensation period (Td
It may be set as c).

The extended compensation period (Tdc) may be always low (Lo) or may be the same power save period (Tps2) as the effective display period (T1) repeated, but the output stage amplifier of the source driver 9 is in the operating state. However, since the analog system drive power increases during this period, the increase rate (ΔPsaA) is about Tdc / T (Tdc << T1,
In the case of Tdc = 1H, the value is 1 / total number of display lines (n), which is a very small value, and is at a level that causes almost no problem. From the control side, it is easy to set one horizontal synchronization period (1H) unit. On the other hand, in the effective display period (T1), a power with a margin added from the power save period (TpsB) in black display that requires the maximum charging time to avoid insufficient charging of the display start line as in the conventional example. Although the save period (Tps1) is required, in the present invention, the insufficient charge of the display start line is resolved by adding the extended compensation period (Tdc), so the power save period is the original TpsB =
Since the setting can be returned to Tps2 (> Tps1), driving power can be reduced. During this period, the analog system drive power reduction rate (Psa reduction rate) is approximately (Tps1-Tps).
At 2) / 1H, a reduction of about 20% is expected, and the effect is large.

In (B), the power save period (Tps3) of the first line of the display start of the effective display period (T1) is changed to the power save period (Tps) in the other effective display period (T1).
2) It is a measure to set a shorter time (0 ≦ Tps3 <Tps2). Incidentally, this measure is effective when the relaxation time of the frequency transient characteristic is kept within one horizontal synchronization period (1H). In the display start line, the analog system drive power increases during this period, but the increase rate (ΔPsaB) is about (Tsa2-Tsa3) / T1 ((Tsa2-Tsa
3) Since it is a very small value of << T1), it is at a level that causes almost no problem. Power save period other than the display start line (T
ps2) and drive power are the same as in (A).

In FIG. 1, the non-display period (T2)
The power save period is enabled over the entire area of the display and the power save period (Tps2) is provided for each horizontal synchronization period (1H) within the valid display period (T1). Even if the horizontal sync period is shortened due to the frame rate drive and the power save period is not provided within the effective display period and the power save period is applied only in the entire non-display period (T2), it is affected by the above-mentioned frequency transient response. Since there is a possibility that the display quality of the display start line may be degraded, it is needless to say that the extended compensation period (A) is an effective measure from the viewpoint of securing the display quality.

FIG. 2 is a graph showing the degree of improvement of the analog drive power of the source driver 9 in the embodiment of the present invention, which suppresses the influence of the frequency transient response characteristic of the power save control signal PSC on the display effective period. The power save period within one horizontal synchronization period of the effective display period is
As a result of the reduction from ps1 to Tps2 (TpsB), the driving power can be significantly reduced from Psa1 to Psa2 (PsaB).

[0031]

According to the present invention, the control of the power save period performed in the effective display period is started prior to the display start of the non-display period, or the power save period near the display start line is shortened as much as possible. This improves the frequency transient response characteristics when shifting from the non-display period to the effective display period, thereby improving the display quality of the display start line and suppressing the effect of the effective display period on the power save period. It is possible to further lengthen the power save period, and as a result, it is possible to reduce the driving power, and the effect is great.

[Brief description of drawings]

FIG. 1 is a main timing chart of a liquid crystal display device regarding control centered on a power save control signal according to an embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the power save period and the analog power of the source driver in the liquid crystal display panel drive device according to the embodiment of the present invention.

FIG. 3 is a configuration diagram of an active type liquid crystal display panel using general amorphous TFTs.

FIG. 4 is a block circuit diagram of a drive control system in a conventional drive device for an active liquid crystal display panel.

5 is a timing chart of main control signals relating to the driving device of the liquid crystal display panel of FIG.

6 is a graph showing the relationship between the power save period and the analog power of the source driver in the liquid crystal display panel driving device of FIG.

[Explanation of symbols]

5 Liquid crystal display panel 9 Source driver 10 Gate driver 11 Image display signal control circuit 12 Timing control signal generator 15 Opposing voltage generation circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 623D 642 642A F term (reference) 2H093 NA16 NC09 NC16 NC18 NC49 ND34 ND39 5C006 AF42 AF44 AF46 AF51 AF53 AF68 AF69 AF71 AF73 BB16 BC03 BC11 BC16 BC20 BF25 FA47 5C080 AA10 BB05 DD26 FF11 GG07 GG08 JJ02 JJ04

Claims (4)

[Claims] 1. A matrix electrode composed of image signal electrode lines and scanning signal electrode lines, a source driver having an output current capability control function for supplying an image signal voltage to the image signal electrode lines, and the scanning signal electrodes. A gate driver for supplying a scan selection voltage to a line, and an image display element group (thin film transistor, liquid crystal display element, storage capacitor, etc.) provided in a region of each matrix electrode controlled by the image signal voltage and the scan selection voltage. ) And a counter signal electrode commonly connected to one of the liquid crystal display elements, an image signal processing circuit for controlling an image signal system, and a drive timing signal for the liquid crystal display panel. Liquid crystal display composed of a timing control signal generating circuit for controlling the counter voltage and a counter voltage generating circuit for supplying a counter voltage to the counter signal electrode of the liquid crystal display panel. In a panel driving device, when a 1-field period (1F) for forming an image display is defined as an effective display period (T1) and a non-display period (T2), from a display start portion of the effective display period (T1). Non-display period (T2)
Is provided with a continuous extended compensation period (Tdc), and the operation of the output stage amplifier is stopped by the output current capability control function of the source driver for the non-display period (T3) excluding the extended compensation period (Tdc). A drive device for a liquid crystal display panel, which controls output high impedance. 2. A one-field period (1F) for forming an image display is defined as an effective display period (T1) and a non-display period (T1).
2), one horizontal synchronization period (1
2. The liquid crystal display according to claim 1, wherein even during a partial period (Tps2) within H), the operation of the output stage amplifier is stopped by the output current capability control function of the source driver and the output is controlled to have a high impedance. Panel drive. 3. An extended compensation period (T) continuous from a display start portion of the effective display period (T1) to a part of the non-display period (T2).
The liquid crystal display panel drive device according to claim 1, wherein dc) is set in units of one horizontal synchronization period (1H). 4. A matrix-shaped electrode composed of image signal electrode lines and scanning signal electrode lines, a source driver having an output current capability control function for supplying an image signal voltage to the image signal electrode lines, and the scanning signal electrodes. A gate driver for supplying a scan selection voltage to a line, and an image display element group (thin film transistor, liquid crystal display element, storage capacitor, etc.) provided in a region of each matrix electrode controlled by the image signal voltage and the scan selection voltage. ) And a counter signal electrode commonly connected to one of the liquid crystal display elements, an image signal processing circuit for controlling an image signal system, and a drive timing signal for the liquid crystal display panel. And a timing signal generating circuit for supplying a counter voltage to the counter signal electrode of the liquid crystal display panel. And a non-display period (T2) when a one-field period (1F) for forming an image display is defined as an effective display period (T1) and a non-display period (T2). 1 horizontal synchronization period (1
H), the period of the display start line is set to Tps3, and the display start line is set to Tps3 for the period in which the operation of the output stage amplifier is stopped and the output is controlled to have a high impedance by the output current capability control function of the source driver. A driving device for a liquid crystal display panel, characterized in that 0 ≦ Tps3 <Tps2, with a period other than Tps2.