JP2003131630A - Liquid crystal display - Google Patents

Abstract

(57) [Summary] A field-sequential liquid crystal display device does not require a transistor for reset operation. A gate driver (22a) for sequentially and selectively outputting a gate line signal to a pixel unit (21), and a gate driver (22) disposed between the gate driver (22a) and a gate line terminal of the pixel unit (21) to display data in a subfield. Write the write data signal according to the display.
A gate driver output unit 22b that outputs all gate line signals collectively; a drain driver 23a that supplies and drives a write data signal corresponding to display data corresponding to one of the plurality of colors to the drain line; A drain driver output unit 23b is provided between the drain driver 23a and the drain line terminal of the pixel unit 21 and supplies a write data signal of the same potential to all drain lines at the time of resetting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field sequential type liquid crystal display device.

[0002]

2. Description of the Related Art Recently, as a liquid crystal display device for displaying a color image, a liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates having electrodes formed on opposite inner surfaces is used to control light transmission. A liquid crystal display element for displaying an image, a backlight arranged behind the liquid crystal display element for sequentially emitting light of a plurality of colors toward the liquid crystal display element in a predetermined cycle, and displaying one color image For writing a display data corresponding to one of the plurality of colors into the liquid crystal display element for each of a plurality of subfields obtained by dividing one field for the number of colors of light emitted by the backlight. , A control means for causing the backlight to emit light of a color corresponding to the display data, and by combining the displays of a plurality of colors for each of the plurality of subfields,
A method of displaying two color images has been studied.

This system is generally called a field-sequential system. In the conventional field-sequential system liquid crystal display device, light of one color is emitted from the backlight for each of the plurality of sub-fields during the sub-field period. The display data is emitted and the display data corresponding to the one color is written in the liquid crystal display element in that state.

In this field-sequential liquid crystal display device, since the liquid crystal display element is not provided with a color filter, light is not absorbed by the color filter, and 1 is divided by the number of colors of light emitted by the backlight. Since a single color image is displayed by combining bright light of a plurality of colors for each of the plurality of subs, compared to a liquid crystal display device that uses a liquid crystal display element having color filters of a plurality of colors corresponding to a plurality of pixels, respectively. Therefore, a bright and high-definition color image can be displayed.

FIG. 5 shows a general circuit configuration of a conventional field-sequential liquid crystal display device. In the same figure, as the liquid crystal display element, an active matrix type in which thin film transistors (hereinafter referred to as “TFT”) 11a, 11a, ... TFT11
The plurality of gate lines G1 to Gn connected to the gate terminals of a, 11a, ...
A gate driver 12 for supplying a gate signal for turning on a, ... And a plurality of drain lines D1 to Dm connected to the drain terminals of the TFTs 11a, 11a ,. A drain driver 13 for supplying a corresponding write data signal.

At each pixel position of the pixel section 11, the TFT 11 connected to the above gate line and drain line
The source terminal of a is connected to both ends of the liquid crystal capacitance CLC and the auxiliary capacitance CS formed between the pixel electrodes of the liquid crystal, and the other end of the electrostatic capacitance CLC is connected to the common electrode COM with other pixels to the auxiliary capacitance CS. Will be connected to the auxiliary capacitance electrodes CS, respectively.

In addition, the liquid crystal capacitance CLC and the auxiliary capacitance CS
The source terminal of the reset TFT 11b is also connected to one end of the TFT 11a and the source terminal of the TFT 11a. The reset TFT 11b has a drain terminal to which a reset drain signal RED is applied and a gate electrode to which a reset gate signal REG is applied, common to all pixels.

With such a circuit configuration, in the field-sequential liquid crystal display device, "(reset all pixels)" and "(display data)" are performed for each subfield.
The four states of "writing""holding (display data)" and "lighting of backlight (BL while holding display data)" are repeatedly executed. At the time of reset operation, the gate driver 12 and drain are drained. By using the above-mentioned reset drain signal RED and reset gate signal REG as control signals from a location different from the driver 13,
The reset TFTs 11b, 11b, ... Which are provided in parallel with the display TFTs 11a, 11a ,.

[0009]

As described above, in the conventional general field-sequential liquid crystal display device, the TFT 11a for writing the display data and the resetting TFT 11a for each pixel constituting the pixel portion 11 are provided. TFT1
Two TFTs 1b are required, and their control systems are different. These points lead to a decrease in aperture ratio, a complicated wiring layout on the liquid crystal display element panel, an increase in wiring capacitance, and the like. However, there are many problems such as a short circuit between wirings and a factor that reduces the yield of device manufacturing.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the aperture ratio of each pixel by eliminating the need for a transistor for reset operation, and to improve the liquid crystal display panel. An object of the present invention is to provide a field sequential liquid crystal display device capable of simplifying the wiring.

[0011]

The invention according to claim 1 is
A liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates each having electrodes formed on opposite inner surfaces thereof, and arranged on the inner surface of one of the pair of substrates arranged in a matrix in row and column directions. A plurality of pixel electrodes, a plurality of thin film transistors arranged one by one corresponding to the plurality of pixel electrodes respectively, each source electrode being connected to the corresponding pixel electrode, and wiring corresponding to each pixel electrode row. A plurality of gate lines connected to the gate electrodes of the thin film transistors, a plurality of drain lines connected to the pixel electrode columns and connected to the drain electrodes of the thin film transistors, and the other of the pair of substrates. Has an opposite electrode provided on the inner surface of the substrate and facing the plurality of pixel electrodes, and controls light transmission to display an image. A liquid crystal display element and a backlight arranged behind the liquid crystal display element and sequentially emitting light of a plurality of colors toward the liquid crystal display element in a predetermined cycle are provided for displaying one color image. Writing of display data corresponding to one of the plurality of colors into the liquid crystal display element for each of a plurality of subfields obtained by dividing one field by the number of colors of light emitted by the backlight; A liquid crystal display device for displaying one color image by synthesizing display of a plurality of colors for each of the plurality of subfields by causing a backlight to emit light of a color corresponding to the display data. A gate driving means for sequentially and selectively outputting the gate line signals to the display element, and a gate driving means disposed between the gate driving means and the gate line terminal of the liquid crystal display element, In the field, a write data signal corresponding to the display data is written, and a gate output control means for collectively outputting all gate line signals at the time of resetting prior to display writing, and one of the plurality of colors for the drain line, respectively. The drain driving means for supplying and driving the write data signal corresponding to the display data corresponding to one color, and the drain driving means are arranged between the drain driving means and the drain line terminal of the liquid crystal display element. And a drain output control means for supplying a potential write data signal.

With such a configuration, it is possible to eliminate the transistor for the reset operation, improve the aperture ratio of each pixel, and simplify the wiring on the liquid crystal display panel.

According to a second aspect of the present invention, in the first aspect of the present invention, the drain output control means includes a first line for generating a drive voltage signal having an analog value based on the write data from the drain drive means. , A second line for generating a black and white binary drive voltage signal according to the write data from the drain driving means and the first line for color display, while the second line for black and white display.
Switching selection means for selecting the line of (1) to stop the operation of the first line.

According to this structure, in addition to the operation of the invention described in claim 1, for example, D / A is displayed at the time of monochrome display.
By stopping the operation of the analog drive circuit such as the converter or the buffer amplifier, the consumption of the drive power can be suppressed to a low level.

According to a third aspect of the present invention, in the above-mentioned second aspect of the invention, during the black-and-white display, the display is performed in accordance with the display timing of one color of the plurality of subfields, and a plurality of colors are displayed. It is characterized in that the light is emitted at the same time, while the display operation is stopped in the subfields of other colors.

With such a structure, in addition to the operation of the invention described in claim 2, the consumption of the driving power can be further suppressed.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the gate drive means, the gate output control means, the drain drive means, and the drain output control means are applied to the liquid crystal display element for each subfield. It is characterized in that the polarity of the applied voltage is reversed.

With such a configuration, in addition to the operation of the invention described in claim 1, it is possible to prevent the occurrence of flicker and prevent the display quality from being reduced.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a field-sequential liquid crystal display device will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration. In the figure, the liquid crystal display elements include TFTs 21a, 21a ,.
Is used as an active element (pixel driver) for the pixel portion 21 using the active matrix type.
The plurality of gate lines G1 to Gn connected to the gate terminals of T21a, 21a, ...
.. and the TFTs 21a, 21a, ...
Drain lines D1 connected to the drain terminals of the
.. to Dm are provided with a drain driver unit 23 which supplies a write data signal corresponding to display data in synchronization with the gate signal.

At each pixel position of the pixel section 21, the TFT 21 connected to the gate line and the drain line is connected.
The source terminal of a is connected to one end of a liquid crystal capacitor CLC formed between liquid crystal pixel electrodes, the other end of the pixel capacitor CLC is connected to a common electrode COM with another pixel, and one end of the auxiliary capacitor CS is connected to the pixel. One end of the capacitance and the other end are commonly connected to the auxiliary capacitance electrode CS.

However, the gate driver section 22 corresponds to the gate driver 12 shown in FIG. 5, and the gate driver output section 21b arranged between the gate driver 22a and the gate line of the pixel section 21. Composed of and.

FIG. 3A shows the gate driver output section 22.
The circuit configuration provided in b corresponding to each gate line is shown. In FIG. 1A, a shift clock (CLK) synchronized with the scanning timing of the gate line is input to the shift register 41, and the content held in the shift register 41 is given to the AND circuit 42 as a normal scanning selection signal Gout '. .

The AND circuit 42 is also supplied with the all output non-selection control signal D, and its logical output is a buffer amplifier 44 constituted by an FET via an OR circuit 43.
Sent to.

The compulsory all-output selection control signal E is also
It is sent to the buffer amplifier 44 through the OR circuit 43. The buffer amplifier 44 outputs one of the voltage level VGH at the gate line selection output and the voltage level VGL at the non-selection output as described above. The scan selection signal Gout is output to the corresponding gate line in response to the output from the circuit 43.

FIG. 3B shows the signal level "L" of the all output non-selection control signal D and the forced all output selection control signal E.
9 is a table showing the state of the scan selection signal Gout corresponding to “H”.

At the time of resetting, in which all the gate lines of the pixel portion 21 are selected and all the pixels are reset, the forced all-output selection control signal E becomes "H" level, the all-output non-selection control signal D and the scanning selection signal Gout. Regardless of the state of ', the scanning selection signal Gout unconditionally becomes the voltage level VGH at the time of gate line selection output.

Therefore, all the TFTs 21a, 21a, ... Arranged in the pixel section 21 are turned on, and the reset data can be written to all the pixels.

Further, when writing the display data to each pixel, the all-output non-selection control signal D becomes "H" level, the compulsory all-output selection control signal E becomes "L" level, and the scanning selection signal Gout is selected by scanning. It follows the signal Gout 'as it is.

Therefore, as shown in FIG. 3C, when the scanning selection signal Gout 'is at "L" level, the voltage level VGL at the gate line non-selection output and the scanning selection signal Gout' are "H". If it is a level, the voltage level VGH at the same selection output is output to the corresponding gate line as the scanning selection signal Gout, and the display data is written only to the TFTs 21a, 21a, ... Of the selected line. Will be done.

Further, in the display standby state in which all the gate lines of the pixel portion 21 are unselected, both the all-output non-selection control signal D and the forced all-output selection control signal E become "L" level, and the scanning selection signal Gout. Unconditionally becomes the voltage level VGL at the time of gate line non-selected output.

Therefore, all the TFTs 21a, 21a, ... Arranged in the pixel portion 21 are turned off, and the charges of the data written up to that point are held by the liquid crystal capacitance CLC and the auxiliary capacitance CS. .

On the other hand, the drain driver section 23 corresponds to the drain driver 13 shown in FIG. 5, and a drain driver output section arranged between the drain driver 23a and the drain line of the pixel section 21. 23b and.

FIG. 2A shows a circuit configuration mainly provided in the drain driver output section 23b for each drain line. In FIG. 1A, a dot clock (DotCL) synchronized with the drain line scanning timing is used.
K) is input to the shift register 32, and the content held in the shift register 32 is given to the latch circuit 33.

The latch circuit 33 latches and holds, for example, 11-bit display data on the basis of the contents held in the shift register 32, and the contents held therein are D / A as they are.
While being sent to the converter 34, only the most significant bit MSB is sent to the analog switch 35.

The drain line maximum voltage level VDH and the drain line maximum voltage level VDL are applied to the reference driver 31 of the drain driver 23a and the analog switch 36 of the drain driver output section 23b.

The reference driver 31 inverts the polarity by the data output inversion control signal INV, and then applies a voltage of 10 gradations V10 to V0 (V10>) for applying to the drain line by both the applied voltages. V
0) is generated and applied to the D / A converter 34, and only the highest voltage V10 and the lowest voltage V0 are applied to the respective free ends of the analog switch 35.

The analog switch 35 is, for example, a MOS-
One of the voltages is selected by the content "0" or "1" of the most significant bit MSB from the latch circuit 33 and applied to one free end of the analog switch 37.

The analog switch 36 is composed of, for example, a MOS-FET, and either one of the maximum voltage level VDH and the minimum level VDL of the applied drain line is selected according to the output inversion control signal INV. Is selected and applied to the other free end of the analog switch 37.

The analog switch 37 is, for example, a MOS-
The analog switch 3 which is composed of a FET and is applied in accordance with the monochrome reset switching control signal B.
One of the outputs from 5, 36 is selected and applied as a drain output Dout ″ to one free end of the analog switch 39.

The D / A converter 34 is operated by the power save control signal A only when the latch circuit 3 is operated.
The voltage V of 11 gradation levels based on the latch output of 3
The D / A conversion is executed by converting the analog voltage signal into 10 to V0, and the analog voltage signal is output to the buffer amplifier 38.

The buffer amplifier 38 is composed of, for example, an operator amplifier, and only when operating with the power save control signal A, the D / A converter 3 is provided.
Drain output Do by amplifying analog voltage signal from 4
It is applied to the other free end of the analog switch 39 as ut '.

Then, the analog switch 39 is
For example, it is constituted by a MOS-FET, and according to the output mode switching control signal C, one of the drain output Dout ″ which is the output of the analog switch 37 and the drain output Dout ′ output by the buffer amplifier 38 is selected, and is selected as the drain output Dout. Output to drain line.

FIG. 2B shows a drain corresponding to the signal levels "L" and "H" of the output mode switching control signal C, the power save control signal A, the monochrome reset switching control signal B, and the output inversion control signal INV. It is a table showing the state of the output Dout ″.

At the time of resetting, in which all the gate lines of the pixel section 21 are selected and all the pixels are reset, both the output mode switching control signal C and the monochrome reset switching control signal B become "H" level, and the power save control signal A Irrespective of the state, if the output inversion control signal INV is at "L" level, the voltage level VDL is
Is high, the voltage level VDH is output as a drain output Dout from the analog switch 39 to the corresponding drain line via the analog switches 36 and 37. .. are turned on, the drain output Dout is written to all pixels as reset data.

When the display data is written to each pixel by color display, the output mode switching control signal C and the power save control signal A are both at the "L" level, and the output is inverted regardless of the monochrome reset switching control signal B. When the control signal INV is at "L" level, the analog voltage signal of the display data is output to the drain line, and when the output inversion control signal INV is at the "H" level, the analog voltage signal of which the polarity of the display data is inverted is output to the drain line.

Further, when the display data is written in each pixel by the monochrome display, the output mode switching control signal C becomes "H" level, the power save control signal A and the monochrome reset switching control signal B become "L" level, If the output inversion control signal INV is at "L" level, the voltage signal corresponding to the most significant bit MSB of the display data, and if the output inversion control signal INV is at "H" level, the most significant bit of the display data whose polarity is inverted. A voltage signal corresponding to the MSB is output to the drain line.

In the display standby state in which all the drain lines of the pixel portion 21 are unselected, the output mode switching control signal C is at "L" level and the power save control signal A is at "H" in order to save power. And the drain output Dou regardless of the monochrome reset switching control signal B.
By setting t to a low drive current output or a high output impedance state, the power consumption in the drain driver output section 23b is reduced as much as possible.

The gate driver output unit 22b,
The detailed operation of the drain driver output section 23b has been described above, and the overall operation of the above embodiment will be described next.

FIG. 4 exemplifies the signal waveforms in the circuit configurations of FIGS. 1 to 3. Here, the number of gate lines n is “160” and the gate lines G1 to G1.
It is assumed that 60 is sequentially scanned and driven.

As for the television system, it is premised that an NTSC television image generally used in Japan is displayed in full motion. Therefore, in the NTSC system, one screen is displayed in 1/30 second, but one frame image is displayed in two fields for interlaced display, that is, an odd field and an even numbered scan line composed of only odd numbered scan lines. It is assumed that the field is divided into only the odd fields, the odd field is displayed in the first 1/60 second, and then the even field is displayed in the next 1/60 second to interpolate the odd field.

Unlike the display on a CRT, the display of a television image on a liquid crystal display device is basically interpolated by a plurality of fields constituting one frame image due to constraints such as circuit scale and cost. Since a method of sequentially overwriting the image of the next field on the image of one field without displaying such a display, the image of the non-interlaced method is substantially 1/60 seconds.
The operation will be described on the assumption that frames (= 1 field) are sequentially displayed.

[Color display mode] As shown in the vertical synchronizing signal (V-SYNC) in FIG. 4A, 1/60 seconds (16.67 [m] in the field sequential system of this time).
s]), a one-screen color display is performed.

Therefore, as shown in FIG. 4B, the vertical sync signal (V-SYNC) of the subfield is 1/180.
There are color subfield screens that perform time-divisional display in seconds (5.56 [ms]). These color subfield screens are R (red) data screen → G (green) data screen →
It is assumed that the B (blue) data screen is displayed in this order.

In each subfield, the reset gate signal shown in FIG. 4C is output in synchronization with the vertical synchronizing signal, and the reset signal shown in FIG.
As shown in (4) and (5), the gate lines G1 to G are sequentially arranged.
160 is selectively scan driven, and data for display is written from the drain line to each pixel in synchronization with the selective driving.

In the liquid crystal display device, the polarity of the voltage applied to the liquid crystal element is switched at a constant cycle in order to prevent the occurrence of image sticking on the screen, and the electric field vector applied to the liquid crystal element is seen in a long cycle. AC drive for canceling the strength is generally performed. Here, the polarity is inverted in a unit of one field and the polarity inversion is not performed for each subfield in one field, and one subfield is used. The subfield inversion method in which the polarity is inverted every time is adopted.

In the field inversion method, FIG.
As shown in (6), R, G, B constituting one field
The polarities (+/-) of the subfields of each data screen are set to be the same, and the polarities of the subfields are collectively reversed in the next field, which is also shown in FIG. 4 (12). As described above, the polarity of the voltage VCOM, which is the voltage applied to the common electrode that is the counter electrode, is also inverted for each field, and it is possible to suppress the power consumption relatively low, but on the other hand, a liquid crystal material having a low retention rate is used. If used, it has a problem that flicker is likely to occur.

The subfield inversion method is shown in FIG.
As shown in (7), the polarity is inverted in units of subfields. Accordingly, as shown in FIG. 4 (13), the polarity of the voltage VCOM, which is the voltage applied to the common electrode as the counter electrode, is also changed. Since it is inverted every sub-field and the polarity is inverted at a cycle of 1/3 compared to the field inversion method, it is very effective in suppressing the occurrence of flicker without being affected by the liquid crystal material. However, on the other hand, the number of times of charging / discharging the opposite electrode is three times as much as that in the field inversion method per unit time, which causes a problem that power consumption increases. Become.

Therefore, in the following, "(reset of all pixels)" and "(display data) in one subfield period will be described.
The operation in each period of “writing”, “standby (for written data)” and “lighting (of backlight)” will be described.

At the time of "reset", the TFTs 21a, 21a, ... Of all the pixels in the pixel section 21 are turned on, and the reset voltages (VDH, VDL) are written from all the drain lines to the pixel electrodes. Here, the applied voltage is basically a black display state in which the transmittance is minimum when the liquid crystal element is normally white, and a white display state in which the transmittance is maximum when the liquid crystal display element is normally black. It is assumed that the reset voltage is set in advance.

In this reset operation, when the liquid crystal molecules of the liquid crystal layer constituting the liquid crystal element behave by voltage, the behavior of the liquid crystal molecules becomes slow due to the influence of the dielectric constant of the liquid crystal layer which changes according to the behavior of the liquid crystal molecules. In order to avoid the applied voltage range and to make the operation of liquid crystal molecules respond at high speed, and when external light enters the inside of the panel when the backlight is not turned on, the display contrast is lowered due to the increase of the reflected light of the panel. Or to initialize the state when the liquid crystal element has a hysteresis in the voltage-transmittance characteristic.

At the time of "writing", FIG.
As shown in (24), the gate lines are sequentially arranged in FIG.
Data corresponding to the color component shown in 9) is written through the drain line.

In the "standby" mode, after writing the data voltage for each scanning line by the above writing operation, the response time originally possessed by the liquid crystal element corresponds to the target after a predetermined time has elapsed. The gate line G160, which waits until the transmittance state is reached, and in which the write operation is finished at the end.
The period is set to delay the lighting timing of the backlight until the response time of the liquid crystal element of the pixel portion 21 elapses after the selection of (1) is completed.

At the time of "lighting", the LEDs constituting the backlight by the back side of the pixel portion 21, that is, the LEDs-R, L corresponding to the color components of the written image data.
By driving one of the ED-G and the LED-B to light up, an image corresponding to the display data of the color component is displayed on the entire screen at once.

The above operation is repeatedly executed in units of subfields.

[Monochrome (2 gradations) display mode] In the monochrome display mode, the basic flow in one subfield is "reset (for all pixels)" as in the color display mode described above.
Each period of "writing (display data)", "standby (for written data)" and "lighting (backlight)" is executed. In that case, the display data is as described in FIG. Only the most significant bit MSB in the data latched by the latch circuit 33 is used as, so that a white pixel or a black pixel is displayed in each pixel portion without using halftone.

Therefore, the image displayed on the entire screen is 2
Although this is a value image, at the time of this display, the operation of the D / A converter 34 that handles an analog voltage signal by the power save control signal A and the buffer amplifier 38 configured by an operational amplifier are stopped at the drain driver output section 23b. .

Therefore, by stopping the operation of these circuits that consume a large amount of power, the power consumption is greatly reduced as compared with the color display mode. Particularly, in a device using a battery with a limited capacity as a power source. The power consumption can be reduced as much as possible.

In addition to this, when displaying a black-and-white image, the display may be performed only in one of the three subfields forming one field, and may not be performed in the remaining two subfields.

In this case, the RGB constituting one field
For example, assuming that black and white display is performed at the timing of the R (red) subfield located at the beginning of the total of 3 subfields, the following two G (green) and B (blue) subfields are displayed. In the "lighting" period of the subfield in which the display is not performed and the display is performed, not only the backlight (LED) of the color component R corresponding to the subfield but also the backlights (LEDs) of all colors RGB are simultaneously turned on at the same time. It shall be.

In FIG. 4 (8), the write timing in the R subfield is B / Wa, the write timing in the G subfield is B / Wb, and the write timing in the B subfield is B / Wc. The voltage polarity of the written display data is indicated by the sign +/- following the notation. In this case, as a matter of course, the polarity switching timing is synchronized with the inversion timing of the voltage polarity applied to the counter electrode.

One of the write timings in each of the sub-fields shown above is selected, display operations such as writing are not executed in the other sub-fields, and thereafter, a specific color in one field is dealt with. Repeat display in subfields only.

This can contribute to further reduction of power consumption in addition to stopping the circuit operation of the analog output buffer system in the drain driver output section 23b described above.

Since G (green) has the frequency distribution closest to the luminance component in RGB of the primary colors, G
By executing the binary gradation black-and-white display operation based on the display data in the sub-field, the most natural black-and-white display image can be obtained.

As described above, the resetting of the pixel section 21 and the writing of the display data are surely executed even though the resetting TFT is not required only by the display TFT 21a for each pixel of the pixel section 21. In addition to improving the aperture ratio of each pixel, it is possible to prevent the wiring layout from becoming complicated and the wiring capacitance from increasing on the liquid crystal display element panel including the pixel section 21 based on a plurality of control systems. At the same time, it is possible to eliminate a factor such as a short circuit between wirings that lowers the yield of device manufacturing, which can contribute to a large reduction in manufacturing cost.

In addition to this, as the gate driver 22a which constitutes the gate driver portion 22 of the pixel portion 21 and the drain driver 23a itself which constitutes the drain driver portion 23, the conventional general constitution is used as it is, and This can be realized only by adding a relatively small-scale circuit configuration such as the drain driver output unit 23b and the drain driver output unit 23b.

In the above embodiments, the gate driver output section 22b and the drain driver output section 23b have the circuit configurations shown in FIGS. 3 and 2, but the present invention is not limited to this. Of course, other configurations may be used as long as they realize the same function.

In addition, the present invention is not limited to the above-described embodiment, and various modifications can be carried out without departing from the scope of the invention.

Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and it is described in the section of the effect of the invention. When at least one of the effects described above is obtained, a configuration in which this constituent element is deleted can be extracted as an invention.

[0080]

According to the first aspect of the present invention, it is possible to improve the aperture ratio of each pixel and simplify the wiring on the liquid crystal display panel by eliminating the need for a transistor for reset operation. .

According to the invention described in claim 2, in addition to the effect of the invention described in claim 1, for example, when displaying in black and white, for example, D
By stopping the operation of the analog drive circuit such as the / A converter and the buffer amplifier, the consumption of the drive power can be suppressed low.

According to the invention described in claim 3, in addition to the effect of the invention described in claim 2, it is possible to further reduce the consumption of drive power.

According to the invention described in claim 4, in addition to the effect of the invention described in claim 1, it is possible to prevent the occurrence of flicker and prevent the display quality from being reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration for each drain line provided in the drain driver output section of FIG.

FIG. 3 is a block diagram showing a circuit configuration for each gate line provided in the gate driver output section of FIG.

FIG. 4 is a timing chart showing a drive waveform of each signal according to the same embodiment.

FIG. 5 is a diagram showing a circuit configuration of a general field-sequential liquid crystal display device.

[Explanation of symbols]

11 ... Pixel part 11a ... (for display) TFT 11b ... (for reset) TFT 12 ... Gate driver 13 ... Drain driver 21 ... Pixel part 21a ... (for display) TFT 22 ... Gate driver unit 22 22a ... Gate driver 22b ... Gate driver output unit 21b 23 ... Drain driver section 23a ... Drain driver 23b ... Drain driver output section 31 ... Reference driver 32 ... Shift register 33 ... Latch circuit 34 ... D / A converter 35-37 ... Analog switch 38 ... Buffer amplifier 39 ... Analog switch 41 ... Shift register 42 ... AND circuit 43 ... OR circuit 44 ... Buffer amplifier A: Power save control signal B: Monochrome reset switching control signal C ... Output mode switching control signal CLC ... Liquid crystal capacity CS: auxiliary capacity D ... All output non-selection control signal E ... Forced all output selection control signal INV ... Output inversion control signal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 611E 621 621B 624 624B 642 642J 3/34 3/34 JF term (reference) 2H093 NA16 NA65 NB07 NB11 NC02 NC11 NC41 ND22 ND49 NE10 5C006 AA01 AA22 AC09 AC28 AF44 AF69 AF71 AF83 BB16 BC03 BC06 BC11 BC20 BF03 BF04 BF24 BF25 BF26 FA23 FA42 FA43 FA42 FA43 FA22 DD22 FF22 DD26 FF22 DD26 CC22 DD26 CC22 DD26 DD22 CC26 DD26 DD22 FF22 DD26 CC22 DD26 DD22

Claims (4)

[Claims] 1. A liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates each having electrodes formed on opposing inner surfaces, and arranged in a matrix in the row and column directions on the inner surface of one of the pair of substrates. A plurality of pixel electrodes provided by
A plurality of thin film transistors arranged one by one corresponding to the plurality of pixel electrodes, each source electrode being connected to the corresponding pixel electrode, and being wired corresponding to each pixel electrode row, the gate of the thin film transistor A plurality of gate lines connected to the electrodes, a plurality of drain lines connected to the respective pixel electrode columns and connected to the drain electrodes of the thin film transistors,
And a liquid crystal display element that is provided on the inner surface of the other substrate of the pair of substrates and that has a counter electrode that faces the plurality of pixel electrodes and that controls light transmission to display an image, and the liquid crystal display. A backlight arranged behind the element and sequentially emitting light of a plurality of colors toward the liquid crystal display element at a predetermined cycle, and the backlight emits one field for displaying one color image. Write display data corresponding to one of the plurality of colors to the liquid crystal display element and write the display data from the backlight to the plurality of subfields divided by the number of light colors. In a liquid crystal display device that emits light of a corresponding color and displays a single color image by combining displays of a plurality of colors for each of the plurality of subfields, the gate to the liquid crystal display element is provided. A gate drive means for sequentially and selectively outputting a line signal, and a write data signal corresponding to the display data in the subfield, which is arranged between the gate drive means and the gate line terminal of the liquid crystal display element. One of the plurality of colors is output to the drain line and a gate output control unit that collectively outputs all gate line signals at the time of resetting before the display writing.
The drain driving means for supplying and driving the write data signal corresponding to the display data corresponding to one color, and the drain driving means are arranged between the drain driving means and the drain line terminal of the liquid crystal display element, and are connected to all drain lines at the time of the reset. And a drain output control means for supplying a write data signal of a potential. 2. The drain output control means includes a first line for generating a drive voltage signal having an analog value based on the write data from the drain drive means, and a black and white 2 line based on the write data from the drain drive means.
A second line for generating a drive voltage signal having a value and the first line for color display are selected, while the second line for monochrome display is selected to stop the operation of the first line. The liquid crystal display device according to claim 1, further comprising: 3. In the black-and-white display, the display is performed in accordance with the display timing of one color of the plurality of subfields, and the light of a plurality of colors is emitted at the same time, while the subfields of the other colors are displayed. The liquid crystal display device according to claim 2, wherein the display operation is stopped. 4. The gate drive means, the gate output control means, the drain drive means, and the drain output control means,
The liquid crystal display device according to claim 1, wherein the polarity of the voltage applied to the liquid crystal display element is inverted for each subfield.