JP2003229578A - Semiconductor device, display device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT structure for which an OFF-current value is low and an ON-current value is high and to simultaneously provide the TFT structure in which image quality is rarely degradaded by light incident on a semiconductor layer, and an area occupied by a TFT in one pixel is reduced. <P>SOLUTION: By having a multi-gate structure and shortening the width d1 in a channel length direction of a heavily doped region 104 held between two channel formation regions 101 and 102 to the width d2 in the channel length direction in lightly doped regions 106 and 107, the resistance of the entire semiconductor layer in the ON-state of the TFT is reduced, an ON-current is improved, carrier life time by light excitation generated in the heavily doped region is weakened and light sensitivity is lowered. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electro-optical device represented by a liquid crystal display panel and an electronic device in which such an electro-optical device is mounted as a component.

[0002] In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a thin film transistor (TFT) is formed by using a semiconductor thin film (thickness of several to several hundreds nm) formed on a substrate having an insulating surface, and a large area integrated circuit formed by this TFT is formed. The development of the semiconductor device has is progressing. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. In particular, since a TFT having a crystalline silicon film (typically a polysilicon film) as an active layer (hereinafter referred to as a polysilicon TFT) has high field effect mobility, various functional circuits can be formed. Is.

For example, in an active matrix type liquid crystal display device, a pixel circuit for displaying an image in each functional block and a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit and a sampling circuit are controlled. A driving circuit for doing so is formed on one substrate.

In a pixel circuit of an active matrix type liquid crystal display device, a TFT (pixel TFT) is arranged in each of several tens to several millions of pixels, and a pixel electrode is provided in each of the pixel TFTs. . A counter electrode is provided on the counter substrate side with the liquid crystal interposed therebetween, and forms a kind of capacitor using the liquid crystal as a dielectric. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, and the liquid crystal is driven by controlling the charge to this capacitor,
It is designed to display an image by controlling the amount of transmitted light.

The applications of such an active matrix type liquid crystal display device are widespread, and the demand for high definition, high aperture ratio and high reliability is increasing along with the increase in screen area. At the same time, demands for improved productivity and cost reduction are also increasing.

An advantage of the active matrix type display device is that an integrated circuit such as a shift register, a latch or a buffer can be formed by TFTs on the same substrate as a driving circuit for transmitting a signal to the pixel portion.
This makes it possible to significantly reduce the number of contacts with the external circuit, thereby improving the reliability of the display device.

Further, the pixel TFT is composed of an n-channel TFT, and is a switching element which is driven by applying a voltage to the liquid crystal. Since the liquid crystal is driven by alternating current,
A method called frame inversion drive is often used. In this method, in order to keep the power consumption low, the pixel T
For the characteristics required for the FT, it is important that the off current value (drain current flowing when the TFT is in the off operation) be sufficiently low. In addition, sufficiently small characteristics such as gate-drain parasitic capacitance are required. The auxiliary capacitance provided in the pixel is provided to compensate for the small pixel capacitance and insufficient holding operation, and to prevent the influence of the parasitic capacitance.

As a structure of a TFT for reducing the off current value, a lightly doped drain (LDD) is used.
n) The structure is known. In this structure, a region where an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region which is formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling.

Further, as a structure of a TFT for reducing the variation in off current value, a multi-gate structure such as a double gate structure having a plurality of channel forming regions or a triple gate structure is known. As shown in FIG. 27, when two TFTs are simply connected to form a double gate structure, the size of the TFT is increased with respect to one pixel, which leads to a reduction in aperture ratio.

Pixels of the active matrix drive system are
In addition to the pixel electrode that applies a voltage to the liquid crystal, a scanning line (gate line) connected to the gate electrode and a data line connected to the source or drain intersect. Two types of storage capacitors are known: an additional capacitance type in which a pixel electrode and a scanning line (gate line) in the preceding stage are overlapped, and a storage capacitance type in which a dedicated capacitance line is provided. In any case, as the definition of image quality becomes higher, it is inevitable that the size of the TFT or the auxiliary capacitance allowed per pixel is inevitably reduced. Therefore, in order to obtain a high aperture ratio of each pixel within the specified pixel size, it is essential to efficiently lay out the elements necessary for the configuration of these pixels.

In addition, two types of liquid crystal display devices have been developed: a direct view type in which an image displayed on a pixel portion is directly viewed and a projection type in which an image is displayed on a screen using an optical system. Based on the screen size, both are direct view type up to about 30 inch type, and projection type is considered for sizes larger than 30 inch type.

Further, in all liquid crystal display devices, especially liquid crystal display devices for projectors, the TFT characteristics arranged in each pixel vary due to light leak current generated by light incident on the semiconductor layer through various paths, Degradation of image quality (decrease in contrast, flicker, crosstalk, etc.) has been a problem.

[0014]

The above-described conventional pixel structure or TFT structure has a problem that it is difficult to achieve both a high aperture ratio and a reduction in light leakage current, or a high aperture ratio and a reduction in off current value.

[0015] These requirements are demanded for higher definition of liquid crystal display devices.
(Increase in the number of pixels) and miniaturization of each display pixel pitch due to miniaturization are major problems.

Further, the TFT having a multi-gate structure has a low on-current value, which is an obstacle to high-speed driving in a liquid crystal display device.

The present invention provides a TFT structure having a low off-current value and a high on-current value, and at the same time, is resistant to image quality deterioration due to light incident on the semiconductor layer and reduces the area occupied by the TFT in one pixel. A TFT structure is provided.

Further, in the transmissive active matrix type liquid crystal display device, the light shielding layer is a necessary constituent element.
The semiconductor layer has a photoconductive effect in which a resistance value is changed by light irradiation, and off-current is increased by being irradiated with light from a light source. Especially in a projection type display device, a part of light passing through the liquid crystal display device is reflected at the interface between the substrate and the air layer,
The problem is that the light is reflected by the optical system, returned in the opposite direction, and enters the TFT.

In the case of a projection type using a metal halide lamp or the like as a light source, the liquid crystal display device is irradiated with light of 1 to 20 million lux, so the design of the light shielding layer becomes important. On the other hand, it is necessary to suppress the incident light to the TFT to about 100 lux to reduce the off current. Usually TF
Although a light-shielding layer is formed on the upper or lower layer of the T semiconductor layer, about 0.1 to 1% of the incident light (light from the light source) is incident as diffracted light.

The conductivity of the semiconductor layer increases due to the photoconductive effect, which increases the off-current of the TFT, which adversely affects the image display such as reduction of contrast and occurrence of crosstalk. However, in order to block such light, if the light-shielding property is prioritized and the area of the light-shielding layer is increased, the aperture ratio will naturally decrease.

In order to realize a high aperture ratio within a limited pixel size, it is indispensable to efficiently arrange the elements necessary for the construction of the pixel section. An object of the present invention is to provide an active matrix type display device having a pixel structure which realizes a high aperture ratio, by appropriately arranging pixel electrodes, scanning lines (gate lines) and data lines formed in a pixel portion. And

As a means for forming a crystalline silicon film on an insulating surface, laser annealing or an electric heating furnace for an amorphous silicon film is used in addition to the method of directly forming a crystalline silicon film by a low pressure CVD method. A method of crystallizing by heat treatment is adopted. However, even if any of these methods is applied, the field effect mobility of the TFT is the n-channel TFT.
It was possible to obtain a value of about 100 to ²⁰⁰ cm ² / Vsec and a value of about 50 to 100 cm ² / Vsec for the p-channel TFT. The threshold voltage is 3 for n-channel TFT.
Since the V and the subthreshold coefficient (S value) are 300 mV / dec, the driving voltage is 14 V, and it has been a problem to reduce the power supply voltage and the power consumption.

To achieve low voltage and low power consumption,
It is necessary to increase the crystal grain size in the crystalline silicon film, improve the mobility, and reduce the S value. Further, it is necessary to suppress variations in threshold voltage.

The technique for increasing the crystal grain size and its application to TFT are described in, for example, "" Ultra-high Performance Poly-Si
TFTs on a Glass by a Stable Scanning CW Laser Lat
eral Crystallization ", A. Hara, F. Takeuchi, M. Tak
ei, K. Yoshino, K. Suga and N. Sasaki, AMLCD '01 T
ech. Dig., 2001, pp.227-230. ", a TFT using a polycrystalline silicon film crystallized using the second harmonic of a diode-pumped solid-state continuous-wave laser (YVO ₄ ). The prototype was prepared and the improvement of the field effect mobility is described as a result.

However, even if it is possible to increase the grain size of the crystalline silicon film, in the structure in which the above-mentioned light-shielding film and the semiconductor film are provided in an overlapping manner, the light-shielding film is irradiated when the continuous wave laser light is irradiated. Is altered, and the laser light reflected by the light-shielding film formed on the lower layer side of the semiconductor film is irregularly reflected and hinders uniform crystallization. As a result, distortion is accumulated and the threshold voltage fluctuates, which is a problem.

When a continuous wave laser beam is irradiated,
A change in internal stress from the light-shielding film and the insulating film formed on the lower side of the semiconductor film also causes a problem that the threshold voltage changes.

In addition, the present invention has been made in view of the above problems.
It is also an object to reduce the driving voltage of various integrated circuits formed by, and to achieve low power consumption.

[0028]

According to the present invention, a pixel TFT has a multi-gate structure such as a double-gate structure or a triple-gate structure having a plurality of channel formation regions, and a gate electrode is formed between adjacent gate electrodes in one pixel TFT. Is shorter than the width of the low concentration impurity region (LDD region). The low-concentration impurity region is formed between the source region and the channel forming region closest to the source region, and the drain region and the channel forming region closest to the drain region in one multi-gate pixel TFT. It will be installed in two places between and. Since a pixel using liquid crystal is generally driven by an alternating current, the source region and the drain region in the pixel TFT are alternately switched. Therefore,
The width of the low-concentration impurity region provided adjacent to one of the channel formation region and the source region, and the width of the low-concentration impurity region provided adjacent to the other of the channel formation region and the drain region. Equal width.

Further, a region sandwiched between two channel forming regions adjacent to each other in one TFT has a high concentration impurity region containing an impurity element at a concentration equal to or higher than that of the source region or the drain region. Only while reducing the resistance of the entire semiconductor layer in which the TFT is on, the photosensitivity when light is incident on the TFT for some reason is reduced.

That is, according to the present invention, the width in the channel length direction of the high concentration impurity region sandwiched between two adjacent channel formation regions is made shorter than the width in the channel length direction of the low concentration impurity region to form one pixel. To TF
The area of T is reduced to improve the aperture ratio of the pixel. Also,
According to the present invention, by providing a plurality of channel formation regions, even if a defect such as a current leak occurs in one channel formation region, the other channel formation regions operate normally, and abnormal values of off-current are reduced to suppress variations. To be Further, for some reason, the light-shielding property of the pixel TFT is lowered, and even when light is incident on the TFT, the photosensitivity of the off-current value is lowered to suppress display defects.

The configuration (1) of the invention disclosed in this specification is as follows.
What is claimed is: 1. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a plurality of gate electrodes formed on the insulating film. The layer includes a plurality of channel forming regions overlapping the gate electrode with the insulating film sandwiched therebetween, a source region or a drain region, and a low concentration impurity region between the channel forming region and the source region or the drain region. And a gap between two gate electrodes adjacent to each other among the plurality of gate electrodes is shorter than a width of the low concentration impurity region.

The structure (2) of another invention is a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a plurality of gate electrodes formed on the insulating film. And a plurality of channel forming regions overlapping the gate electrode with the insulating film interposed therebetween, a source region or a drain region, and the plurality of channel forming regions. A high-concentration impurity region adjacent to, and a low-concentration impurity region between the channel formation region and the source region or the drain region. In the semiconductor device, the interval is shorter than the width of the low concentration impurity region of the semiconductor layer.

In the above structure (2), if the high concentration impurity region and the source region or the drain region are formed in the same step, the high concentration impurity region has the same impurity concentration as the source region or the drain region. .

In the structure (2), if the high-concentration impurity region and the source region or the drain region are formed in separate steps, the high-concentration impurity region is higher than the source region or the drain region. The impurity concentration can also be used. By increasing the concentration of the high-concentration impurity region as compared with other regions, the resistance of the entire semiconductor layer in the ON state of the TFT is reduced, the ON current is improved, and the photoexcitation generated in the high-concentration impurity region is increased. Can weaken the carrier lifetime and reduce the photosensitivity.

In the structure (2), if the high-concentration impurity region and the source region or the drain region are formed in separate steps, the high-concentration impurity region has a higher impurity concentration than the low-concentration impurity region. The impurity concentration may be lower than that of the source region or the drain region.

Further, in the above structure (2), the width of the high-concentration impurity region is equal to the distance between adjacent gate electrodes.

Further, in the above structure (1), the above structure (2), or each structure, among the plurality of channel formation regions, the interval between the two adjacent channel formation regions is two adjacent gate electrodes. It is characterized by being equal to the interval of.

Further, the present invention is a TFT having a double gate structure.
When applied to, a low-concentration impurity region (LDD region) is provided between one channel formation region and the drain region,
A low concentration impurity region (LDD region) is provided between the other channel formation region and the source region, and a high concentration impurity region is provided between the two channel formation regions to form a TFT structure in which the channel of the high concentration impurity region is formed. The width in the long direction is made shorter than the width of the low concentration impurity region in the channel length direction.

The structure (3) of the other invention is a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a first gate formed on the insulating film. A semiconductor device comprising a TFT including an electrode and a second gate electrode, wherein the semiconductor layer includes a first channel forming region overlapping the first gate electrode with the insulating film interposed therebetween, and the insulating layer. A second channel forming region that overlaps the second gate electrode with a film interposed therebetween; a high-concentration impurity region that is adjacent to both the first channel forming region and the second channel forming region; First contacting the first channel formation region
Low concentration impurity region, a drain region in contact with the first low concentration impurity region, a second low concentration impurity region in contact with the second channel formation region, and a source region in contact with the second low concentration impurity region. And a first gate electrode and a second
The semiconductor device is characterized in that an interval between the gate electrodes is shorter than a width of the first low concentration impurity region.

In the above structure (3), if the high-concentration impurity region and the source region or the drain region are formed in the same process, the high-concentration impurity region has the same impurity concentration as the source region or the drain region. .

In the structure (3), if the high-concentration impurity region and the source region or the drain region are formed in separate steps, the high-concentration impurity region is higher than the source region or the drain region. The impurity concentration can also be used. By increasing the concentration of the high-concentration impurity region as compared with other regions, the resistance of the entire semiconductor layer in the ON state of the TFT is reduced, the ON current is improved, and the photoexcitation generated in the high-concentration impurity region is increased. Can weaken the carrier lifetime and reduce the photosensitivity.

In the structure (3), if the high-concentration impurity region and the source region or the drain region are formed in separate steps, the high-concentration impurity region has a higher impurity concentration than the low-concentration impurity region. The impurity concentration may be lower than that of the source region or the drain region.

Further, in the above configuration (3) or each of the above configurations, the width of the high concentration impurity region is shorter than the width of the first low concentration impurity region.

Further, in the above configuration (3) or each configuration, the width of the high concentration impurity region is shorter than or equal to the width of the second low concentration impurity region.

Further, the present invention has a TFT structure in which a high concentration impurity region is provided between two channel formation regions, and the width of the high concentration impurity region in the channel length direction is defined as the width of the low concentration impurity region in the channel length direction. It may be the same.

The structure (4) of another invention is a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a plurality of gate electrodes formed on the insulating film. And a plurality of channel forming regions overlapping the gate electrode with the insulating film interposed therebetween, a source region or a drain region, and the plurality of channel forming regions. A high-concentration impurity region adjacent to, and a low-concentration impurity region between the channel formation region and the source region or the drain region. In the semiconductor device, the interval is the same as the width of the low concentration impurity region.

In the above structure (4), if the high-concentration impurity region and the source region or the drain region are formed in the same process, the high-concentration impurity region has the same impurity concentration as the source region or the drain region. .

In the structure (4), if the high-concentration impurity region and the source region or the drain region are manufactured in separate steps, the high-concentration impurity region is higher than the source region or the drain region. The impurity concentration can also be used. By increasing the concentration of the high-concentration impurity region as compared with other regions, the resistance of the entire semiconductor layer in the ON state of the TFT is reduced, the ON current is improved, and the photoexcitation generated in the high-concentration impurity region is increased. Can weaken the carrier lifetime and reduce the photosensitivity.

In the structure (4), if the high-concentration impurity region and the source region or the drain region are formed in separate steps, the high-concentration impurity region has a higher impurity concentration than the low-concentration impurity region. The impurity concentration may be lower than that of the source region or the drain region.

Further, in the above constitutions (1) to (4) or each constitution, the TFT is an n-channel type TFT or a p-channel type TFT.

The present invention also has the above structures (1) to (4).
Alternatively, in each of the above structures, a semiconductor device including a pixel electrode electrically connected to the source region or the drain region, typically a liquid crystal display device or a light-emitting device including an EL element. .

In the display device of the present invention, in a semiconductor device (typically a liquid crystal display device) in which a pixel electrode, a thin film transistor, and a capacitor are provided on a substrate, one electrode of the capacitor is The electrode and the conductive film formed in the same layer as the electrode, which is connected to one of the source and the drain of the thin film transistor, extend over the gate electrode of the thin film transistor.

In another structure, in a semiconductor device in which a pixel electrode, a thin film transistor, and a capacitor are provided on a substrate, one electrode of the capacitor is connected to one of a source and a drain of the thin film transistor. The electrode and the light-shielding layer formed of the same layer as the electrode extend over the gate electrode of the thin film transistor and overlap with the light-shielding layer provided thereabove.

In another structure, in a semiconductor device in which a pixel electrode, a thin film transistor, and a capacitor are provided on a substrate, one electrode formed on the insulating layer of the capacitor is the source of the thin film transistor. Alternatively, the drain electrode is connected to one of the drains, the insulating layer covers the gate electrode of the thin film transistor, and one electrode of the capacitor and a light-shielding layer formed in the same layer as the capacitor element extend over the gate electrode of the thin film transistor and are formed on the upper layer thereof. The semiconductor device overlaps with the provided light-shielding layer.

In another structure, the semiconductor layer formed on the substrate, the first light-shielding layer formed between the substrate and the semiconductor layer, and the semiconductor layer formed on the side opposite to the substrate side. A gate electrode, a pixel electrode formed on the upper layer of the gate electrode, a third light-shielding layer formed between the gate electrode and the pixel electrode,
A semiconductor device having a second light-shielding layer formed between a gate electrode and a third light-shielding layer, in which the gate electrode and the first to third light-shielding layers overlap with each other.

In another structure, in a semiconductor device in which a pixel electrode, a thin film transistor and a capacitor are provided on a substrate, a first light shielding layer formed on the substrate and a first light shielding layer formed on the light shielding layer. An insulating layer; a semiconductor layer formed on the first insulating layer; a second insulating layer formed on the semiconductor layer;
A gate electrode formed on the insulating layer, a capacitor wiring, a third insulating layer formed on the gate electrode and the capacitor wiring, and a third insulating layer
A second light-shielding layer formed on the insulating layer, a fourth insulating layer formed on the second light-shielding layer, a source / drain wiring and a source / drain wiring formed on the fourth insulating layer The formed fifth insulating layer, the third light shielding layer formed on the fifth insulating layer, the sixth insulating layer formed on the third light shielding layer, and the pixel formed on the sixth insulating layer. With electrodes,
A semiconductor layer, a second insulating layer, a capacitor wiring, a third insulating layer, a second
A capacitive element is formed in the overlapping portion with the light shielding layer, and the second light shielding layer extends on the gate electrode.

In the above structure, by extending the light shielding layer on the gate electrode, it is possible to prevent the diffracted light from entering the semiconductor layer and prevent the off current of the TFT from being increased by the diffracted light. it can. Further, by efficiently arranging the elements necessary for the configuration of the pixel portion in this manner, a high aperture ratio can be realized within a limited pixel size.

Further, in order to reduce the driving voltage of various integrated circuits formed by TFTs and realize low power consumption, the structure of the present invention has the first crystalline semiconductor film and the second crystalline film on the insulating substrate. The semiconductor film is formed in contact with the first light-shielding film formed between the insulating substrate and the first crystalline semiconductor film, and the gate formed on the side of the second crystalline semiconductor film opposite to the insulating substrate. -A gate electrode, a pixel electrode formed on the upper layer of the gate electrode, a third light-shielding layer formed between the gate electrode and the pixel electrode, a gate electrode and a third light-shielding layer And a second light-shielding layer formed between
It is characterized in that it is larger than the average crystal grain size of the first crystalline semiconductor film.

Further, according to the present invention, a first conductive layer having a light shielding property is formed on an insulating surface, a first insulating layer covering the first conductive layer is formed, and a first amorphous layer is formed on the first insulating layer. A semiconductor film is formed, and the first amorphous semiconductor film is crystallized by heat treatment without being melted to form a first crystalline semiconductor film;
After the second amorphous semiconductor film is formed in contact with the first crystalline semiconductor film and irradiated with laser light to melt part or all of the second amorphous semiconductor film in the irradiation region, A method of manufacturing a semiconductor device having a step of crystallizing is provided.

In the configuration of the above invention, a solid-state laser oscillating device or a gas laser oscillating device is applied as a laser light source. As a solid-state laser oscillator, YA
G laser oscillator, YVO ₄ laser oscillator, YL
One kind selected from F laser oscillator, YAlO ₃ laser oscillator, glass laser oscillator, ruby laser oscillator, alexandrite laser oscillator, and Ti: sapphire laser oscillator is applied, and the laser light is a non-linear optical element. Is preferably converted to the second to third harmonics. As the gas laser oscillator, a kind selected from a continuous oscillation or pulse oscillation excimer laser oscillator, an Ar laser oscillator, a Kr laser oscillator, and a CO ₂ laser oscillator is applied. In addition, as the metal laser oscillator, a helium cadmium laser oscillator, a copper vapor laser oscillator, or a gold vapor laser oscillator may be applied.

After forming the first crystalline semiconductor film, the second crystalline semiconductor film is formed.
By forming an amorphous semiconductor film and crystallizing the film by irradiating laser light, the first crystalline semiconductor film relaxes internal stress from a different film received from the underlying insulating film and the light-shielding film during laser irradiation. Have a function. Further, the first crystalline semiconductor film prevents the light shielding film from being deteriorated by the irradiation of laser light, and the laser reflected by the light shielding film formed on the lower layer side of the first crystalline semiconductor film. The light is prevented from being diffusely reflected, which alleviates the accumulation of distortion,
It is possible to prevent the threshold voltage variation of the FT.

[0062]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) An example of applying Embodiment 1 of the present invention to a TFT having a double gate structure is shown in FIG. 1 and described below.

In FIG. 1, 100 is a substrate, 101 and 102 are channel forming regions, 103 and 105 are source regions or drain regions, 104 is a high-concentration impurity region, 106 and 1
Reference numeral 07 is a low concentration impurity region (LDD region), 108 is a gate insulating film, 109 is a gate electrode, 110 is an interlayer insulating film,
111 and 112 are source electrodes or drain electrodes. Note that FIG. 1A is a top view of the TFT shown in FIG.
A sectional view taken along the dotted line AA ′ in (B) is shown.

The present invention has two channel forming regions 101,
The feature is that the region sandwiched by 102 is only the high concentration impurity region 104. The distance d1 between the gate electrodes 109 adjacent to each other, that is, the width of the high concentration impurity region in the channel length direction is defined as the width d2 of the low concentration impurity regions 106 and 107.
The shorter the distance between the two channel formation regions, the shorter the TF for one pixel.
The area occupied by T can be reduced. Further, since the region sandwiched between the two channel forming regions is the high concentration impurity region, the resistance of the entire semiconductor layer in which the TFT is in the ON state is reduced, and the photosensitivity when light is incident on the TFT for some reason is Reduce.

Conventionally, LDD regions are required on both sides of a channel formation region, and a double gate structure in which two TFTs are simply connected as shown in FIG.
It was a TFT structure (herein referred to as A type) provided with -265940 gazette). Therefore, in this structure (A type), the area occupied by the TFT for one pixel is increased. This TFT structure (A type)
27 shows two channel formation regions 1 as shown in FIG.
Both the low-concentration impurity regions 16 and 17 and the high-concentration impurity regions 14 are formed between the first and the second regions 12, which is a significant difference from the present invention. Also, this structure (A type)
Then, the distance d1 between the adjacent gate electrodes 19 is longer than the width d2 of the low concentration impurity regions 16 and 17, that is, d.
1> d2. In the TFT structure of the present invention, only the high-concentration impurity region is formed between the two channel formation regions, and the on-current value is higher than that of the TFT structure (A type). In FIG. 27, 10 is a substrate, 13 and 15 are source regions or drain regions, 18 is a gate insulating film, 20 is an interlayer insulating film, and 21 and 22 are source electrodes or drain electrodes.

Further, the TFT structures described in JP-A-4-344618 and JP-A-7-263705 are also proposed. The TFT structures described in these publications (referred to as B type here) have only a low-concentration impurity region formed between two channel formation regions, which is a significant difference from the present invention. In the TFT structure of the present invention, 2
Only a high-concentration impurity region is formed between two channel formation regions, and the on-current value is higher than that of the TFT structure (B type). The TFT structure (B type) is d1> d2.

Further, in the TFTs (A type and B type), since the low concentration impurity region is formed between the two channel forming regions, when light is incident between the two channel forming regions, This is a structure in which the TFT characteristics greatly change as compared with the present invention.

Further, a TFT structure (herein referred to as C type) described in JP-A-7-22627 has been proposed. In this TFT structure (C type), only a high-concentration impurity region is formed between two channel forming regions, but a low-concentration impurity region is not provided, while an offset region is formed. It is very different from the present invention. In the TFT structure of the present invention, a low-concentration impurity region is formed between the channel formation region and the source region or the drain region, and the off current value is lower and the on current value is higher than that of the TFT structure (C type). The TFT structure (C type) is d1> d2.

In the TFT (C type), when light is incident on the offset region provided between the channel forming region and the source or drain region,
This is a structure in which the TFT characteristics largely change as compared with the present invention in which a low concentration impurity region is provided between the channel formation region and the source region or the drain region.

Further, according to the present invention, the interval d1 between the gate electrodes 109 adjacent to each other is the low concentration impurity regions 106 and 107.
Of the conventional TFT (A
Type, B type, and C type), it is difficult for light to enter between the two channel formation regions.

Comparative experiments conducted by the inventor and results of the experiments will be shown below.

First, after forming an amorphous silicon film on a substrate having an insulating surface, crystallization is performed to form a silicon film having a crystalline structure, and TF using the silicon film as an active layer.
T was produced and the pixel TFT structure of the present invention, that is, T in which only a high-concentration impurity region was arranged between two channel formation regions
Pixels (23 μm × 23 μm) provided with FT were produced.
The width of each portion in the channel direction is the width of the gate electrode and the channel formation region = 2 μm, and the width of the LDD region d2 =
1.3 μm, the distance d1 between adjacent gate electrodes
To produce pixel TFTs with 1 μm and 2 μm,
The results of measuring the on-current value and the off-current value are shown in FIGS. 3 and 4.

For comparison, a pixel having a TFT corresponding to the above-mentioned type A, that is, a TFT having an LDD region and a high-concentration impurity region sandwiched between the LDD regions is provided between two channel forming regions. Prepared pixels. Regarding the width of each portion in the channel direction, the width of the gate electrode and the channel formation region = 2 μm, and the width of the LDD region d2 = 1.3 μm.
m, and the distance d1 between adjacent gate electrodes is 3 μm (LDD region 1 μm × 2, high-concentration impurity region 1).
.mu.m) pixel TFT, and the on-current value,
The results of measuring the off-current value are shown in FIGS.

For comparison, a pixel having a TFT corresponding to the above-described type B, that is, a pixel having a TFT in which only a low concentration impurity region is arranged between two channel forming regions was manufactured. The widths of the respective parts in the channel direction are the width of the gate electrode and the channel formation region = 2 μm, the width of the LDD region d2 = 1.3 μm, and the distance d1 between adjacent gate electrodes is 1 μm and 2 μm, respectively.
3 and 4 show the results of measuring the on-current value and the off-current value of T produced.

Further, the occurrence rate of the off-current abnormality of each TFT was obtained. For a sample in which 12 × 17 pixels are arranged in a matrix, the ratio of the number of pixels having an off current of more than 100 fA was determined as the generation ratio of pixels having an off current abnormal value, and the present invention was 1.9%. , Type A was 2.7%, and Type C was 23%. The TFT structure of the present invention has the lowest off-current abnormality occurrence rate. That is, the TFT structure of the present invention can reduce the occurrence rate of the off-current abnormality of the TFT, which also leads to an improvement in yield.

The TFT structure of the present invention capable of suppressing deterioration of TFT characteristics with respect to light incident on the TFT due to various factors (natural light, multiple reflection, diffracted light, light from a light source, return light, etc.) It is very useful to apply it to the pixel TFT mounted on the module and the TFT of the driving unit. Further, for the same reason, the TFT structure of the present invention is also very useful when used in a light emitting display device including an EL (Electro Luminescence) element and a contact image sensor.

Although the substrate having the insulating surface is used here, a semiconductor substrate can also be used.

(Second Embodiment) In the first embodiment, d1 <
Although the example of d2 is shown, an example of applying the second embodiment of the present invention in which d1 = d2 to a TFT having a double gate structure is shown in FIG. 2 and will be described below.

In FIG. 2, 200 is a substrate, 201 and 202 are channel forming regions, 203 and 205 are source regions or drain regions, 204 is a high concentration impurity region, and 206 and 2 are.
Reference numeral 07 is a low concentration impurity region (LDD region), 208 is a gate insulating film, 209 is a gate electrode, 210 is an interlayer insulating film,
211 and 212 are source electrodes or drain electrodes. Note that FIG. 2A is a top view of the TFT shown in FIG.
A sectional view taken along the dotted line AA ′ in (B) is shown.

The present invention has two channel forming regions 201,
The feature is that the region sandwiched by 202 is only the high concentration impurity region 204. The distance d1 between the gate electrodes 209 adjacent to each other, that is, the width in the channel length direction of the high-concentration impurity region is defined as the width d2 of the low-concentration impurity regions 206 and 207.
By designing the same length as the above, the distance between the two channel formation regions can be reduced, and the area occupied by the TFT for one pixel can be reduced. Further, since the region sandwiched between the two channel forming regions is the high concentration impurity region, the resistance of the entire semiconductor layer in which the TFT is in the ON state is reduced, and the photosensitivity when light is incident on the TFT for some reason is Reduce.

(Embodiment 3) This embodiment is shown in FIG. A first light shielding layer 1102 is formed on the substrate 1101 so as to match the channel formation region of the semiconductor layer 1105. The first light-shielding layer 1102 is made of W, Ta, Ti, and a heat-resistant non-translucent material such as silicide. This is a material selected in order to maintain stability with respect to a heat treatment step of 500 ° C. or higher performed on a semiconductor layer or the like in a later step. The first insulating layer is formed of a silicon oxynitride film 1103 and a silicon oxide film 1104, and the surface of the silicon oxide film is chemically mechanically polished (CMP).
It may be flattened with.

The semiconductor layer 1105 is formed of a polycrystalline semiconductor layer obtained by crystallizing an amorphous semiconductor layer by heat treatment, and has a thickness of about 30 to 750 nm. Semiconductor layer 11
A second layer of silicon oxide film of 30 to 100 nm is formed on
An insulating film 1106 is formed to reduce the thickness of the capacitor element. Gate electrode 1107, capacitance wiring 11
08 is formed of the same layer, and a third insulating layer 1109 made of a silicon oxide film having a thickness of 150 to 200 nm is formed thereon.

The second light-shielding layers 1111 and 1110 are also electrodes that form contacts with the source and drain, and in particular, the second light-shielding layer 1110 is formed on the capacitor wiring 1108 to form a capacitor element. This second light shielding layer 111
Reference numerals 1 and 1110 extend on the gate electrode 1107 and also function as a light shielding layer. In this case, the third insulating layer 11
By setting 09 to a thickness of 150 to 200 nm, the amount of diffracted light that wraps around and enters the semiconductor layer 1105 is reduced. Further, the capacitance element has an effect of increasing the capacitance.

The channel formation region 1 is formed in the semiconductor layer 1105.
120, source or drain regions 1121, 1122,
The LDD region 1124 is formed. In addition, the semiconductor region 112 extending from the source or drain region 1122
3 functions as one electrode of the capacitive element.

In the structure shown in FIG. 21, the second region is formed on the LDD region 1124 where the change in conductivity is relatively large due to the photoconductive effect.
The light shielding layers 1111 and 1110 are formed to serve as a light shielding layer, and it is possible to almost completely block stray light. A fourth insulating layer 1112, source and drain wirings 111 are formed on the upper layer.
3, 1114, fifth insulating layer 1115, third light shielding layer 111
6, a sixth insulating layer 1117, and a pixel electrode 1118 are formed.

According to the structure of the present invention, it is possible to completely shield stray light including diffracted light, but on the other hand, L
The second light-shielding layer overlaps directly above the DD region 1124, and the LD
It is feared that the electric field distribution of the D region 1124 changes and the characteristics of the TFT are adversely affected.

FIG. 23 shows a result of simulating the lateral electric field intensity distribution in the LDD region in the structure of the present invention having the same structure as that of FIG. FIG. 23A shows the element structure used for the calculation, in which the distance between the first light shielding layer and the LDD region is 580 nm, the thickness of the gate insulating film is 80 nm, and the LD
The distance between the D region and the second light shielding layer is 180 nm. The gate voltage is -8V and the drain voltage is + 5V. Also,
FIG. 24 shows a similar simulation result in the conventional structure without the second light shielding layer directly above the LDD region.

From the comparison between FIG. 23B and FIG. 24B, when the structure of the present invention is adopted, the electric field of the LDD portion at the end of the gate electrode is influenced by the electric field from the second light shielding layer. It can be seen that the strength increases. However, as a result of investigating this effect in a TFT manufactured as a prototype, it was found that the off current hardly increased as shown in FIG. Therefore, it has been confirmed that the structure of the present invention can enhance the light shielding property without deteriorating the characteristics of the TFT.

(Embodiment 4) FIG. 26 shows a sectional structure of a pixel in the present invention, and shows a mode in which a TFT, a pixel electrode connected to the TFT, and a capacitor portion are formed. Board 1
A first light shielding layer 1202 is formed on 201 in accordance with a channel formation region of an active layer formed of a crystalline semiconductor film.

The first light-shielding layer 1202 is made of a heat-resistant non-translucent material such as W, Ta, Ti and silicides thereof. This is a material selected in order to maintain stability with respect to a heat treatment step of 500 ° C. or higher performed on a semiconductor layer or the like in a later step. The first insulating layer is formed of a silicon oxynitride film 1203 and a silicon oxide film 1204,
The surface of the silicon oxide film may be planarized by chemical mechanical polishing (CMP).

The active layer is formed of at least two crystalline semiconductor films, and the first crystalline semiconductor film 1205 is formed by crystallizing an amorphous semiconductor film by heat treatment.
It is formed with a thickness of 00 nm.

Further, an amorphous semiconductor film having a thickness of 30 to 300 nm is formed on the first crystalline semiconductor film 1205, and the amorphous semiconductor film is crystallized by irradiation of laser light to form the second crystalline semiconductor film 120.
6 is formed. A solid-state laser oscillator, a gas laser oscillator, or a metal laser oscillator can be applied to the light source of the laser light. Most preferably, it is a continuous wave solid state laser device, and a continuous wave YAG laser, YV.
O ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser can be applied.

Further, in each of the above structures, it is desirable that the laser light is converted into a harmonic by a non-linear optical element. For example, YAG laser is the fundamental wave,
It is known to emit laser light with a wavelength of 1065 nm. Since the absorption coefficient of the laser light with respect to the semiconductor film is low, it is difficult to crystallize only the amorphous semiconductor film without damaging the insulating film or the substrate formed on the base. The second harmonic (532 nm), the third harmonic (355 nm), the fourth harmonic (2
66 nm) and the fifth harmonic (213 nm) are formed, and by irradiating the laser light of this wavelength, only the amorphous semiconductor film is selectively overheated to crystallize due to the light absorption coefficient of the semiconductor film. Can be converted.

The crystalline semiconductor film formed by such a two-step crystallization treatment has a large grain size and few crystal defects, and the inside of the crystal grain has characteristics similar to a single crystal. Then, when forming the second crystalline semiconductor film, the first crystalline semiconductor film serves as a protective film during laser irradiation and plays a role of relaxing internal stress with the lower heterogeneous film. In addition, the first crystalline semiconductor film and the second
Since the effect of lattice mismatch at the junction of the crystalline semiconductor film is small, even if two layers are stacked to form the active layer of the TFT,
It is not affected by the different layers. This selective crystallization with the first crystalline semiconductor film prevents the light-shielding film from being altered by the irradiation of laser light.
It is possible to prevent irregular reflection of the laser light reflected by the light-shielding film formed on the lower layer side of the crystalline semiconductor film, and to form a crystalline semiconductor film without distortion.

A second insulating film 1207 is formed of a silicon oxide film having a thickness of 30 to 100 nm on the semiconductor layer to reduce the thickness of the capacitive element. Gate electrode 12
08 and the capacitor wiring 1209 are formed in the same layer, and a third insulating layer 12 made of a silicon oxide film having a thickness of 150 to 200 nm is formed thereon.
10 are formed.

The second light-shielding layers 1212 and 1211 also have a function as electrodes for forming contacts with the source and drain, and in particular, the second light-shielding layer 1211 is formed on the capacitor wiring 1209 to form a capacitor element. There is. The second light shielding layers 1212 and 1211 extend on the gate electrode 1208 to enhance the light shielding property. In this case, the third insulating film is
The thickness of 200 nm reduces the amount of diffracted light that wraps around and enters the active layer 1205. In addition, the capacitance portion has the effect of increasing the capacitance.

A channel formation region 1221, source or drain regions 1222 and 1223, and an LDD region 1225 are formed in the active layer. The semiconductor region 1224 extending from the source or drain region 1223 functions as one electrode of the capacitor.

In the structure shown in FIG. 26, the second light-shielding layers 1212 and 1211 are formed on the LDD region 1225 having a relatively large change in conductivity due to the photoelectric effect to form a light-shielding layer, and it is possible to shield stray light almost completely. ing. A fourth insulating layer 1213, a source and drain wiring 121 are formed on the upper layer.
4, 1215, fifth insulating layer 1216, third light shielding layer 121
7, a sixth insulating layer 1218, and a pixel electrode 1219 are formed.

The present invention having the above structure will be described in more detail with reference to the following examples.

(Embodiment) [Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a pixel portion and TFTs (n-channel type TFT and p-type TFT) of a driving circuit provided around the pixel portion are provided on the same substrate.
A method of simultaneously producing channel type TFTs will be described in detail.

First, the base insulating film 3 is formed on the glass substrate 300.
01 is formed and a first semiconductor film having a crystal structure is obtained, and then etching treatment is performed into a desired shape to form island-shaped separated semiconductor layers 302 to 306.

In this embodiment, a two-layer structure is used as the base insulating film 301 provided on the glass substrate, but a single layer film of the insulating film or a structure in which two or more layers are laminated may be used.
As a first layer of the base insulating film 301, a first silicon oxynitride film (composition ratio Si = 32) formed by using a plasma CVD method and using SiH ₄ , NH ₃ , and N ₂ O as reaction gases.
%, O = 27%, N = 24%, H = 17%)
nm. Next, as the second layer of the base insulating film 301, a second silicon oxynitride film (composition ratio Si = 32%, O = 59) formed by using a plasma CVD method using SiH ₄ and N ₂ O as reaction gases. %, N = 7%, H = 2%)
To have a film thickness of 100 nm.

Next, plasma C is formed on the base insulating film 301.
An amorphous silicon film is formed to a thickness of 50 nm by using the VD method. Then, a nickel acetate salt solution containing 10 ppm by weight of nickel is applied by a spinner. Instead of coating, a method of spattering nickel element over the entire surface by a sputtering method may be used.

Next, heat treatment is performed for crystallization to form a semiconductor film having a crystal structure. For this heat treatment, heat treatment of an electric furnace or irradiation of strong light may be used. When it is performed by heat treatment in an electric furnace, it is 4 to 24 at 500 to 650 ° C
You can do it in time. Here, after the heat treatment for dehydrogenation (500 ° C., 1 hour), the heat treatment for crystallization (5
50 ° C., 4 hours) to obtain a silicon film having a crystal structure. Note that here, although crystallization is performed by heat treatment using a furnace, crystallization may be performed by a lamp annealing apparatus.

Then, the first laser beam (XeC) for increasing the crystallization rate and repairing the defects left in the crystal grains is used.
(I: wavelength 308 nm) is performed in the air or in an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of YAG laser are used. In any case, the repetition frequency is 10 to 10
Using a pulsed laser beam of about 00 Hz, the laser beam is focused by an optical system at 100 to 500 mJ / cm ² , and 90 to 9
Irradiation may be performed with an overlap ratio of 5% to scan the surface of the silicon film. Here, the repetition frequency 30
Irradiation with a first laser beam is performed in the atmosphere at a frequency of Hz and an energy density of 476 mJ / cm ² . Note that the irradiation of the first laser light here is performed with a rare gas element (argon here) in the film.
Is very important in eliminating or reducing Then
In addition to the oxide film formed by the irradiation of the first laser light, the surface is treated with ozone water for 120 seconds to give a total of 1 to 5 nm.
Forming a barrier layer made of an oxide film.

Then, a barrier layer is formed on the barrier layer by a sputtering method.
Amorphous silicon containing elemental argon that acts as a tarring site
Forming a film having a thickness of 150 nm. Sputtering of this example
The film forming conditions by the method are as follows: film forming pressure is 0.3 Pa, gas is
(Ar) flow rate is 50 (sccm) and film formation power is 3 kW
And the substrate temperature is 150 ° C. In addition, under the above conditions
Atomic concentration of argon element contained in amorphous silicon film
Is 3 × 10²⁰/ Cm³~ 6 × 10²⁰/ Cm³, The source of oxygen
Child concentration is 1 × 10¹⁹/ Cm³~ 3 x 10¹⁹/ Cm ³And
It Then, using a lamp annealing device at 650 ° C., 3
Gettering is performed by heat treatment for a minute.

Then, the barrier layer is used as an etching stopper to selectively remove the amorphous silicon film containing the argon element which is the gettering site, and then the barrier layer is selectively removed with dilute hydrofluoric acid. In addition, at the time of gettering,
Since nickel tends to move to a region having a high oxygen concentration, it is desirable to remove the barrier layer made of an oxide film after gettering.

Next, the second laser beam is irradiated in a nitrogen atmosphere or in a vacuum to flatten the surface of the semiconductor film. This laser light (second laser light) has a wavelength of 40
Excimer laser light of 0 nm or less, and second and third harmonics of YAG laser are used. Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light. The energy density of the second laser light is
The energy density of the laser beam is set to 30 to 60 mJ / cm ^{2 or} more. Here, irradiation with the second laser light is performed at a repetition frequency of 30 Hz and an energy density of 537 mJ / cm ² , and the PV value of the unevenness on the surface of the semiconductor film becomes 5 nm or less.

Although the second laser beam is applied to the entire surface in this embodiment, the OFF current can be reduced by changing the TF of the pixel portion.
Since T is particularly effective, at least the pixel portion may be selectively irradiated.

Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also referred to as a polysilicon film), a mask made of a resist is formed and an etching treatment is performed to obtain a desired shape. Forming a semiconductor layer separated into islands. After forming the semiconductor layer, the resist mask is removed.

After forming the semiconductor layer, an impurity element imparting p-type or n-type may be added in order to control the threshold value (Vth) of the TFT. The impurity element that imparts p-type conductivity to the semiconductor is boron (B),
Periodic Group 13 elements such as aluminum (Al) and gallium (Ga) are known. Note that an element belonging to Group 15 of the periodic law, typically phosphorus (P) or arsenic (As) is known as an impurity element imparting n-type to a semiconductor.

Then, after removing the oxide film with an etchant containing hydrofluoric acid and simultaneously cleaning the surface of the silicon film,
An insulating film containing silicon as its main component is formed to be the gate insulating film 307. In this embodiment, 11 is formed by the plasma CVD method.
A silicon oxynitride film with a thickness of 5 nm (composition ratio Si = 32
%, O = 59%, N = 7%, H = 2%).

Then, as shown in FIG. 5A, a first conductive film 308a having a film thickness of 20 to 100 nm and a second conductive film 3 having a film thickness of 100 to 400 nm are formed on the gate insulating film 307.
08b and a third conductive film 308 having a film thickness of 20 to 100 nm.
c is laminated. In this embodiment, the gate insulating film 307
A tungsten film with a thickness of 50 nm, an alloy of aluminum and titanium (Al—Ti) film with a thickness of 500 nm, and a thickness of 3
A 0 nm titanium film was sequentially laminated.

As the conductive material for forming the first to third conductive films, an element selected from Ta, W, Ti, Mo, Al and Cu, or an alloy material or a compound material containing the above element as a main component is used. Form. Alternatively, as the first to third conductive films, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. For example, tungsten nitride may be used instead of tungsten of the first conductive film, and an alloy of aluminum and silicon (Al-Si) may be used instead of the alloy of aluminum and titanium (Al-Ti) film of the second conductive film. ) Film may be used, or a titanium nitride film may be used instead of the titanium film of the third conductive film.
The structure is not limited to the three-layer structure, and may be, for example, a two-layer structure of a tantalum nitride film and a tungsten film.

Next, as shown in FIG. 5B, masks 310 to 315 made of resist are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. ICP (In
It is advisable to use an inductively coupled plasma etching method. Using ICP etching method,
Etching conditions (electric power applied to the coil type electrode,
By appropriately adjusting the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc., the film can be etched into a desired tapered shape. As the etching gas, chlorine-based gas represented by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like or CF ₄ , SF ₆ , NF _{3 is used.}
A fluorine-based gas typified by, for example, or O ₂ can be appropriately used.

The etching gas used is not limited,
It is suitable here to use BCl ₃ , Cl ₂ and O ₂ . The gas flow rate ratio of each is 65/10/5 (scc
m) and a pressure of 1.2 Pa is applied to the coil-type electrode 450
RF (13.56 MHz) power of W is supplied to generate plasma and etching is performed for 117 seconds. RF (13.56 MHz) power of 300 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. The Al film and the Ti film are etched under the first etching condition to make the end portion of the first conductive layer into a tapered shape.

After that, the second etching condition is changed to
CF for etching gas_FourAnd Cl₂And O ₂Use and
The gas flow rate ratio of these is 25/25/10 (sccm),
At a pressure of 1 Pa, RF (1
3.56MHz) Power is supplied to generate plasma and
Etching is performed for about 30 seconds. Board side (Sample stay
20W RF (13.56MHz) power is also applied to
Then, a substantially negative self-bias voltage is applied. CF_Four
And Cl₂Under the second etching condition in which
The Ti film and the W film are etched to the same degree. Na
Etching without leaving any residue on the gate insulating film
In order to achieve this, the etching time should be 10-20%.
Should be increased.

In this first etching process, the shape of the mask made of resist is adjusted to
The edges of the first conductive layer, the second conductive layer, and the third conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of this tapered portion is 15 to 45 °. Thus, the first shape conductive layers 317 to 322 (first conductive layers 317a to 32) including the first conductive layer, the second conductive layer, and the third conductive layer are formed by the first etching treatment.
2a, second conductive layers 317b to 322b, and third conductive layers 317c to 322c) are formed. Reference numeral 316 is a gate insulating film, and a region which is not covered with the first shape conductive layers 317 to 322 is etched to a thickness of about 20 to 50 nm to be thinned.

Next, masks 310 to 3 made of resist.
A second etching process is performed as shown in FIG. 5C without removing 15. BCl ₃ and Cl ₂ are used as etching gases, the gas flow rate ratio of each is set to 20/60 (sccm), and the pressure of 1.2 Pa is applied to the coil-type electrode to provide R of 600 W.
F (13.56 MHz) power is supplied to generate plasma for etching. 1 on the substrate side (sample stage)
RF (13.56 MHz) power of 00 W is input. The second conductive layer and the third conductive layer are etched under the third etching condition. In this way, the aluminum film and the titanium film containing a small amount of titanium are anisotropically etched under the third etching condition to perform the second shape conductive layer 324.
˜329 (first conductive layers 324a to 329a, second conductive layers 324b to 329b, and third conductive layers 324c to 32).
9c) is formed. 323 is a gate insulating film,
Areas which are not covered with the conductive layers 324 to 329 of the shape are slightly etched to form thin areas.

Then, the first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1.5 × 10 ¹⁴ atoms / cm ²
And the acceleration voltage is set to 60 to 100 keV. Phosphorus (P) or arsenic (As) is typically used as the impurity element imparting n-type. In this case, the second shape conductive layers 324 to 328 serve as masks for the impurity element imparting n-type, and the first impurity regions 330 to
334 is formed. First impurity regions 330 to 334
Is doped with an impurity element imparting n-type in the concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .

In this embodiment, the first doping process is performed without removing the resist mask, but the first doping process may be performed after removing the resist mask.

Next, after removing the resist mask, resist masks 335 and 336 are formed as shown in FIG. 6A, and a second doping process is performed.
A mask 335 is a mask that protects a channel formation region of a semiconductor layer that forms one of n-channel TFTs of a driver circuit and a peripheral region thereof.
It is a mask that protects the channel formation region of the semiconductor layer forming the FT and the region around it.

The condition of the ion doping method in the second doping process is that the dose amount is 1.5 × 10 ¹⁵ atoms / cm ² and the accelerating voltage is 60 to 100 keV, and phosphorus (P) is doped. Here, the second shape conductive layers 324 to
Impurity regions are formed in the respective semiconductor layers by utilizing the difference in film thickness between 328 and the gate insulating film 323. Of course, the masks 335, 3
No phosphorus (P) is added to the area covered with 36. Thus, second impurity regions 380 to 382 and third impurity regions 337 to 341 are formed. An impurity element imparting n-type conductivity is added to the third impurity regions 337 to 341 within a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . The second impurity region is formed in a lower concentration than the third impurity regions by the thickness difference of the gate insulating film, 1 × 10 ¹⁸ ~
An impurity element imparting n-type is added within the concentration range of 1 × 10 ¹⁹ / cm ³ . In addition, a region serving as a storage capacitor may be covered with a mask.

Note that only the third impurity region is formed in the region between the two channel formation regions of the pixel portion by the second doping process. With such a structure, the resistance of the entire semiconductor layer in the ON state of the TFT is reduced, the ON current is improved, and the carrier lifetime due to the photoexcitation generated in the high concentration impurity region is weakened and the photosensitivity is lowered. be able to.

Next, a mask 335 made of resist,
After removing 336, a new mask 3 made of resist is formed.
42 to 344 are formed and a third doping process is performed as shown in FIG. By this third doping treatment, fourth impurity regions 347 and fifth impurity regions 345, 346 to which an impurity element imparting p-type conductivity is added are formed in a semiconductor layer forming a p-channel TFT. . The fourth impurity region is formed in a region overlapping with the second shape conductive layer and has a size of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3.
The impurity element imparting p-type is added in the concentration range of. Further, an impurity element imparting p-type conductivity is added to the fifth impurity regions 345 and 346 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Although phosphorus (P) was added to the fifth impurity region 346 in the previous step, the concentration of the impurity element imparting p-type conductivity was 1.5 to 3 times that of the conductivity type. Is p-type.

Note that the fifth impurity regions 348 and 349 and the fourth impurity region 350 are formed in a semiconductor layer which forms a storage capacitor in the pixel portion.

By the steps up to this point, each semiconductor layer is n-doped.
An impurity region having a conductivity type of p-type or p-type is formed. The second shape conductive layers 324 to 327 serve as gate electrodes. Further, the second shape conductive layer 328 serves as one electrode which forms a storage capacitor in the pixel portion. Furthermore, the second
The conductive layer 329 having the shape of (5) forms a source wiring in the pixel portion.

Next, an insulating film (not shown) is formed to cover almost the entire surface. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed by the plasma CVD method. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating the back surface with a YAG laser or an excimer laser, a heat treatment using a furnace, or a combination of these methods. By the method. However, in this embodiment, since the material containing aluminum as the main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the activation step.

Simultaneously with the activation treatment, the nickel used as a catalyst during crystallization is gettered to the third impurity regions 337, 339, 340 and the fifth impurity regions 346, 349 containing high concentration phosphorus. The nickel concentration in the semiconductor layer, which mainly serves as the channel formation region, is reduced.
As a result, a TFT having a channel formation region has a low off-state current value, high crystallinity, high field-effect mobility, and favorable characteristics. In addition,
In this example, the first gettering is performed by the method described in Embodiment Mode 1 at the stage of forming the semiconductor layer, so the gettering by phosphorus here is the second gettering. In addition, if the first gettering is sufficient for the gettering, it is not necessary to perform the second gettering.

In this embodiment, an example in which the insulating film is formed before the activation is shown, but after the activation is performed,
It may be a step of forming an insulating film.

Next, a step of hydrogenating the semiconductor layer is performed by forming a first interlayer insulating film 351 made of a silicon nitride film and performing heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). (FIG. 6C) This step is a step of terminating the dangling bond of the semiconductor layer by hydrogen contained in the first interlayer insulating film 351. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. However, in this embodiment, since the material containing aluminum as the main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. Plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation.

Next, a second interlayer insulating film 374 made of an organic insulating material is formed on the first interlayer insulating film 351. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole reaching the source wiring 327 and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed.
In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using an insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). Not etched).

After that, wirings and pixel electrodes are formed using Al, Ti, Mo, W or the like. As a material of these electrodes and pixel electrodes, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component, or a laminated film thereof. Thus, the source or drain wiring 35
3 to 358, the gate wiring 360, the connection wiring 359, and the pixel electrode 361 are formed.

As described above, the n-channel TFT, p
A pixel portion including a driver circuit including a channel TFT and an n-channel TFT and an n-channel TFT and a storage capacitor can be formed over the same substrate. (FIG. 7) In this specification, such a substrate is referred to as an active matrix substrate for convenience. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In FIG. 7, a channel forming region 37 is formed in the pixel TFT (first n-channel TFT) of the pixel portion.
1. A first impurity region 372 formed outside a second shape conductive layer 327 forming a gate electrode and a third impurity region 3 functioning as a source region or a drain region.
73 and 374. Further, phosphorus is added to the region 377 between the two channel formation regions at the same concentration as that of the source region or the drain region. In addition, the area 37
The width of 7 (width in the channel length direction) is narrower than the width of the first impurity region functioning as an LDD region (width in the channel length direction).

A fourth impurity region 376 and a fifth impurity region 377 are formed in the semiconductor layer functioning as one electrode of the storage capacitor. The storage capacitor is formed of the second shape electrode 328 and the semiconductor layer 306 with an insulating film (the same film as the gate insulating film) as a dielectric.

FIG. 8 shows an example of a top view of the pixel.
A cross-sectional view taken along the chain line AA ′ in FIG. 8 corresponds to the chain line AA ′ in FIG. 7, and a cross-sectional view taken along the chain line BB ′ in FIG. Corresponding to the chain line BB ′ of
Further, in FIG. 8, the same reference numerals as those in FIG. 7 are used.

In FIG. 7, the n-channel TFT (second n-channel TFT) of the driving circuit partially overlaps the channel forming region 362 and the second shape conductive layer 324 forming the gate electrode. It has a second impurity region 363 and a third impurity region 364 which functions as a source region or a drain region. In the p-channel TFT, a channel formation region 365 and a fourth impurity region 366 which partially overlaps the second shape conductive layer 325 which forms a gate electrode.
And a fourth impurity region 367 which functions as a source region or a drain region. n-channel type TFT
The channel forming region 3 is formed in the (second n-channel TFT).
68, a second shape conductive layer 326 forming a gate electrode
The second impurity region 369 that partially overlaps with the third impurity region 37 that functions as a source region or a drain region.
Has 0. Such n-channel TFT and p
A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed using channel TFTs.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate of Embodiment 1 will be described below. FIG. 9 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 15, an alignment film is formed on the active matrix substrate of FIG. 15 and rubbing treatment is performed. In this embodiment, before forming the alignment film, the organic resin film such as the acrylic resin film was patterned to form the columnar spacers for holding the substrate distance at desired positions. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light-shielding layer was also provided in the drive circuit portion. A flattening film was provided to cover the color filter and the light shielding layer. Next, a counter electrode made of a transparent conductive film was formed on the flattening film in the pixel portion, an alignment film was formed on the entire surface of the counter substrate, and a rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the drive circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. After that, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, a polarizing plate and the like are appropriately provided by using a known technique. Then, the FPC was attached using a known technique.

The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.

A pixel portion 804 is arranged in the center of the active matrix substrate 801. A source signal line driver circuit 802 for driving a source signal line is arranged above the pixel portion 804. A gate signal line driver circuit 803 for driving a gate signal line is arranged on the left and right of the pixel portion 804. In the example shown in this embodiment,
Although the gate signal line driver circuit 803 is arranged symmetrically with respect to the pixel portion, it may be arranged on only one side and may be appropriately selected by the designer in consideration of the substrate size of the liquid crystal module and the like. However, considering the operational reliability of the circuit, the driving efficiency, etc., the bilaterally symmetrical arrangement shown in FIG. 9 is desirable.

A signal is input to each drive circuit by a flexible print circuit (Flexible Print Circuit: FPC) 8
It starts from 05. The FPC 805 opens a contact hole in the interlayer insulating film and the resin film so as to reach the wiring arranged up to a predetermined position on the substrate 801, and connects the connection electrode 8
After forming 09, it is pressure-bonded through an anisotropic conductive film or the like. In this embodiment, the connection electrode is made of ITO.

A sealant 807 is applied to the periphery of the driving circuit and the pixel portion along the outer circumference of the substrate, and a constant gap is formed by a spacer previously formed on the active matrix substrate (a gap between the substrate 801 and the counter substrate 806). The counter substrate 806 is attached while maintaining After that, a liquid crystal element is injected from a portion where the sealant 807 is not applied and is sealed with a sealant 808. The liquid crystal module is completed through the above steps.

Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as a part of the drive circuits.

In addition, this embodiment is based on Embodiments 1 to 4,
It can be freely combined with any one of the first embodiment.

[Embodiment 3] In this embodiment, EL (Electr
An example of manufacturing a light-emitting display device including an o Luminescence element will be described below.

A substrate having an insulating surface (eg, glass substrate, crystallized glass substrate, or plastic substrate)
Then, a pixel portion, a source side driver circuit, and a gate side driver circuit are formed. These pixel portion and driving circuit can be obtained according to the first embodiment. Further, the pixel portion and the driving circuit portion are covered with a sealing material, and the sealing material is covered with a protective film. Further, it is sealed with a cover material using an adhesive material. The cover material is preferably made of the same material as the substrate, for example, a glass substrate, in order to withstand deformation due to heat or external force. It is desirable to further process to form a recess (depth of 50 to 200 μm) in which a desiccant can be installed. In addition, when manufacturing an EL module by multi-chambering, after bonding the substrate and the cover material, C
O ₂ end surface with a laser or the like may be divided so as to coincide.

The sectional structure will be described below.
An insulating film is provided on the substrate, a pixel portion is provided above the insulating film,
A gate side driver circuit is formed, and a pixel portion is formed by a plurality of pixels including a current control TFT and a pixel electrode electrically connected to its drain. Further, the gate side driver circuit is formed using a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined. These TFTs may be manufactured according to the first embodiment.

The pixel electrode functions as the anode of the EL element. Further, banks are formed at both ends of the pixel electrode, and an EL layer and a cathode of the EL element are formed on the pixel electrode.

As the EL layer, a light emitting layer, a charge transport layer, or a charge injection layer may be freely combined to form an EL layer (a layer for causing light emission and carrier movement for that purpose). For example, a low molecular weight organic EL material or a high molecular weight organic EL material may be used. Further, as the EL layer, a thin film formed of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film formed of a light emitting material (triplet compound) that emits light (phosphorescence) by triplet excitation can be used. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

The cathode also functions as a wiring common to all the pixels, and is electrically connected to the FPC via the connection wiring. Further, all the elements included in the pixel portion and the gate side driving circuit are covered with the cathode, the sealing material and the protective film.

As the sealing material, it is preferable to use a material that is as transparent or semitransparent to visible light as possible. Further, it is desirable that the sealing material is a material that does not allow moisture and oxygen to permeate as much as possible.

After the light emitting element is completely covered with the sealing material, it is preferable to provide a protective film made of at least a DLC film on the surface (exposed surface) of the sealing material. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to take care so that the protective film is not formed on the portion where the external input terminal (FPC) is provided. The protective film may be prevented from being formed by using a mask, or the external input terminal portion may be covered with a tape such as Teflon (registered trademark) used as a masking tape in the CVD device so that the protective film is not formed. Good.

By encapsulating the EL element with the sealing material and the protective film in the above-mentioned structure, the EL element can be completely shielded from the outside, and the EL element such as moisture and oxygen can be shielded from the outside.
It is possible to prevent entry of a substance that promotes deterioration due to oxidation of the layer. Therefore, a highly reliable light emitting device can be obtained.

Further, the pixel electrode may be used as a cathode, the EL layer and the anode may be laminated, and light may be emitted in a direction opposite to the above.

Note that this embodiment can be combined with Embodiment 1 or Embodiments 1 and 2.

[Embodiment 4] In this embodiment, an example of another top gate type TFT, specifically, an active matrix provided with a top gate type TFT in which a gate wiring is provided below a semiconductor layer and used as a light shielding layer. An example of a substrate manufacturing process will be described. Note that FIGS. 10 to 15 which are a top view and a cross-sectional view of part of the pixel portion are used for description.

First, a conductive film is formed on the substrate 401 having an insulating surface, and patterning is performed to scan lines 4
02 is formed. (Fig. 10 (A))

The scanning line 402 also functions as a light-shielding layer that protects an active layer formed later from light. Here, a quartz substrate was used as the substrate 401, and a stacked structure of a polysilicon film (film thickness 50 nm) and a tungsten silicide (W—Si) film (film thickness 100 nm) was used as the scanning line 402. Moreover, the polysilicon film protects the contamination of the substrate from the tungsten silicide. As the substrate 401, a glass substrate or a plastic substrate can be used instead of the quartz substrate. When a glass substrate is used, it may be preliminarily heat-treated at a temperature about 10 to 20 ° C. lower than the glass strain point. Further, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film may be formed on the surface of the substrate 401 on which the TFT is formed in order to prevent diffusion of impurities from the substrate 401. As the scanning line 402, poly-Si or WSi _x (X = 2.
0 to 2.8), a conductive material such as Al, Ta, W, Cr and Mo, and a laminated structure thereof can be used.

Next, an insulating film 403 which covers the scanning lines 402.
a and 403b are formed with a film thickness of 100 to 1000 nm (typically 300 to 500 nm). (FIG. 10B) Here, a 100-nm-thick silicon oxide film formed by a CVD method and a 280-nm-thick silicon oxide film formed by an LPCVD method were stacked.

After forming the insulating film 403b, the surface of the insulating film may be planarized by a process of chemically and mechanically polishing (typically a CMP technique). For example, the maximum height (Rmax) of the surface of the insulating film is 0.5 μm or less, preferably 0.3 μm or less.

Next, an amorphous semiconductor film having a film thickness of 10 to 10 is formed.
It is formed with 0 nm. Here, an amorphous silicon film (amorphous silicon film) having a film thickness of 69 nm was formed by the LPCVD method. Then, as a technique for crystallizing this amorphous semiconductor film, the technique described in JP-A-8-78329 was used for crystallization. The technique described in the publication is to selectively add a metal element that promotes crystallization to an amorphous silicon film, and perform a heat treatment to form a crystalline silicon film that spreads starting from the added region. is there. Here, nickel was used as a metal element that promotes crystallization, and after heat treatment for dehydrogenation (450 ° C., 1 hour), heat treatment for crystallization (600 ° C., 12 hours) was performed. Although the technique described in the above publication was used for crystallization, it is not particularly limited, and a known crystallization treatment (laser crystallization method, thermal crystallization method, etc.) can be used. Then, irradiation with laser light (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in crystal grains is performed.
As the laser light, excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of YAG laser are used.
In any case, a pulsed laser beam with a repetition frequency of about 10 to 1000 Hz is used, the laser beam is condensed to 100 to 400 mJ / cm ² by an optical system, and irradiation is performed with an overlap rate of 90 to 95%. The film surface may be scanned.

Next, from the area to be the active layer of the TFT, N
Getter i. Here, an example of performing a gettering method using a semiconductor film containing a rare gas element is shown.
In addition to the oxide film formed by the irradiation of the laser light,
The surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. Next, an amorphous silicon film containing an argon element, which serves as a gettering site, is formed to a thickness of 150 nm on the barrier layer by a sputtering method. The film forming conditions by the sputtering method of the present embodiment are a film forming pressure of 0.3 Pa, a gas (Ar) flow rate of 50 (sccm), a film forming power of 3 kW, and a substrate temperature of 150 ° C. The atomic concentration of the argon element contained in the amorphous silicon film under the above conditions is 3 × 10 ²⁰ / cm ^{3 to} 6 × 1.
0 ²⁰ / cm ³ , the atomic concentration of oxygen is 1 × 10 ¹⁹ / cm ^{3 to} 3
It is × 10 ¹⁹ / cm ³ . After that, gettering is performed by heat treatment at 650 ° C. for 3 minutes using a lamp annealing device. An electric furnace may be used instead of the lamp annealing device.

Then, the barrier layer is used as an etching stopper to selectively remove the amorphous silicon film containing the argon element which is the gettering site, and then the barrier layer is selectively removed with dilute hydrofluoric acid. In addition, at the time of gettering,
Since nickel tends to move to a region having a high oxygen concentration, it is desirable to remove the barrier layer made of an oxide film after gettering.

Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also referred to as a polysilicon film), a mask made of a resist is formed, and an etching treatment is performed into a desired shape. The island-shaped separated semiconductor layer 404 is formed. After forming the semiconductor layer 404, the resist mask is removed. (Fig. 10
(C1)) Note that FIG. 10C2 is a top view of the pixel after the semiconductor layer 404 is formed. A cross-sectional view taken along dashed line AA ′ in FIG. 10C2 corresponds to FIG. 10C1.

After forming the semiconductor layer, an impurity element imparting p-type or n-type may be added in order to control the threshold value (Vth) of the TFT. The impurity element that imparts p-type conductivity to the semiconductor is boron (B),
Periodic Group 13 elements such as aluminum (Al) and gallium (Ga) are known. Note that an element belonging to Group 15 of the periodic law, typically phosphorus (P) or arsenic (As) is known as an impurity element imparting n-type to a semiconductor.

Next, in order to form a storage capacitor, a mask 405 is formed and part of the semiconductor layer (a region to be a storage capacitor) 406 is doped with phosphorus. (Figure 11 (A))

Next, after removing the mask 405 and forming an insulating film covering the semiconductor layer, a mask 407 is formed to remove the insulating film on the region 406 which is to be the storage capacitor. (Fig. 1
1 (B))

Next, the mask 407 is removed and thermal oxidation is performed to form an insulating film (gate insulating film) 408a. The final thickness of the gate insulating film is 80 n due to this thermal oxidation.
It became m. Note that an insulating film 408b which is thinner than the other regions was formed over the region to be the storage capacitor. (Figure 11 (C1))
A top view of the pixel here is shown in FIG. Figure 11
A cross-sectional view taken along dashed line BB ′ in (C2) corresponds to FIG. 11 (C1).

Then, a channel doping step of adding a p-type or n-type impurity element at a low concentration to the region which will be the channel region of the TFT was performed entirely or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron was added by an ion doping method in which diborane (B ₂ H ₆ ) was plasma-excited without mass separation. Of course, an ion implantation method that performs mass separation may be used.

Next, the insulating film 408a and the insulating film 40
3a and 403b, a mask 409 is formed on the scanning line 40.
A contact hole reaching 2 is formed. (Fig. 12
(A)) Then, after forming the contact hole, the mask is removed.

Next, a conductive film is formed and patterned to form the gate electrode 410 and the capacitor wiring 411. (FIG. 12B) Here, a laminated structure of a phosphorus-doped silicon film (film thickness 150 nm) and tungsten silicide (film thickness 150 nm) was used. In this embodiment, a double gate structure is used, and the distance d1 between adjacent gate electrodes is 1 μm. It should be noted that the storage capacity is equal to
08b is a dielectric and is composed of a capacitor wiring 411 and a part 406 of the semiconductor layer.

Then, phosphorus is added in a low concentration in a self-aligning manner using the gate electrode 410 and the capacitor wiring 411 as a mask. (FIG. 12C1) FIG. 12 is a top view of the pixel here.
It shows in (C2). In FIG. 12 (C2), a dotted line C1-
A cross-sectional view taken along C1 ′ and a cross-sectional view taken along a dotted line C2-C2 ′ correspond to FIG. 12C1. The phosphorus concentration in the region added to this low concentration is 1 × 10 ^{16 to} 5 × 10 ^18.
atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10
Adjust so that it is ¹⁸ atoms / cm ³ .

Next, a mask 412 is formed and phosphorus is added at a high concentration to form a high concentration impurity region 413 which becomes a source region or a drain region. (FIG. 13A) The concentration of phosphorus in this high concentration impurity region is 1 × 10 ²⁰ to 1 × 1.
0 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 ×
10 ²⁰ atoms / cm ³ ). Note that in the semiconductor layer 404, a region overlapping with the gate electrode 410 serves as a channel formation region 414, and a region covered with the mask 412 serves as a low-concentration impurity region 415 and functions as an LDD region. In the TFT of the pixel portion of this embodiment, the mask 412 is not provided between the gate electrodes adjacent to each other, and only the high-concentration impurity region (width 1 μm in the channel length direction) is provided between the two channel formation regions. Form consistently. With this mask 412, the width d2 of the low-concentration impurity region is set to 1.3 to 1.5 μm, and the distance d1 between adjacent gate electrodes is set to 1 μm. However, d1 <d2
If so, it goes without saying that it is not limited to these numerical values. In this embodiment, the TF of the pixel portion is formed on the same substrate.
T and the TFT of the drive circuit are formed, but the TF of the drive circuit
T may be provided with low-concentration impurity regions on both sides of the channel formation region, may be provided with low-concentration impurity regions on one side, or may not be provided with low-concentration impurity regions on both sides. Just design the mask. Then, after adding the impurity element, the mask 412 is removed.

Next, although not shown here, a p-channel type T used for a drive circuit formed on the same substrate as the pixel.
In order to form FT, a mask is used to cover a region to be an n-channel TFT, and boron is added to form a source region or a drain region.

Next, after removing the mask 412, a passivation film 416 covering the gate electrode 410 and the capacitor wiring 411 is formed. Here, a silicon oxide film was formed to a thickness of 70 nm. Next, a heat treatment step for activating the n-type or p-type impurity element added to the semiconductor layer at each concentration is performed. Here 850 ℃, 3
Heat treatment was performed for 0 minutes.

Next, an interlayer insulating film 417 made of an organic resin material is formed. Here, an acrylic resin film having a film thickness of 400 nm was used. Next, after forming a contact hole reaching the semiconductor layer, a drain electrode 418 and a source wiring 419 are formed. In this embodiment, the drain electrode 418
The source wiring 419 is a stacked film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm are successively formed by a sputtering method. (FIG. 13 (B1)) As shown in FIG. 13 (B1),
Light to the semiconductor layer is blocked by the source wiring 419 and the drain electrode 418. The source wiring 419 and the drain electrode 418 block light diffracted at the end of a light shielding layer which will be formed later. Note that a cross-sectional view taken along dashed line DD 'in FIG. 13B2 corresponds to FIG. 13B1.

Then, after hydrogenation is performed, an interlayer insulating film 420 made of acrylic is formed. Next, a conductive film having a light-blocking property of 100 nm is formed over the interlayer insulating film 420 to form a light-blocking layer 421. (FIG. 14 (A)) The cross-sectional view taken along the dotted line EE ′ in FIG. 14 (A) corresponds to FIG. 14 (B).

Then, an interlayer insulating film 422 is formed. Next, a contact hole reaching the drain electrode 418 is formed. Next, after forming a 100-nm transparent conductive film (here, indium tin oxide (ITO) film), patterning is performed to form pixel electrodes 423 and 424. (FIG. 15A) A cross-sectional view taken along the dotted line FF ′ in FIG. 15A corresponds to FIG. 15B.

In this way, in the pixel portion, a pixel TFT made of an n-channel TFT is formed while ensuring an area (aperture ratio 74.5%) of a display region (pixel size 23 μm × 23 μm), and a sufficient storage capacitance ( 55.2 fF) can be obtained.

As described above, the n-channel TFT having the double gate structure and the pixel portion having the storage capacitor, and the driving circuit having the n-channel TFT and the p-channel TFT are formed on the same substrate. be able to.
In this specification, such a substrate is referred to as an active matrix substrate for convenience.

Further, the off current of the pixel TFT thus obtained is small, and it is suitable for the TFT of the pixel portion. In addition, the fluctuation of the TFT characteristics is small.

Needless to say, this embodiment is merely an example and is not limited to the steps of this embodiment. For example, as each conductive film, tantalum (Ta), titanium (Ti),
Molybdenum (Mo), Tungsten (W), Chromium (C
r), an element selected from silicon (Si), or an alloy film in which the above elements are combined (typically, a Mo—W alloy or a Mo—Ta alloy) can be used. As each insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an organic resin material (polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene) film, etc.) film can be used.

Further, in this embodiment, an example in which a transparent conductive film is used for the pixel electrode to manufacture an active matrix substrate for a transmissive display device is shown. However, a reflective material film is used for the pixel electrode for reflection. An active matrix substrate for a mold display device may be manufactured.

Note that this embodiment can be combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, or Embodiment Mode 2.

[Embodiment 5] In Embodiment 1 or Embodiment 2, the high impurity concentration region and the source region (or drain region) have the same impurity concentration. 16 and 17 show examples in which the high-concentration impurity region and the source region (or the drain region) have different concentrations.

In FIG. 16, reference numeral 500 is a substrate, 501 and 502.
Is a channel forming region, 503 and 505 are source regions or drain regions, 504 is a high concentration impurity region, 506,
507 is a low concentration impurity region (LDD region), 508 is a gate insulating film, 509 is a gate electrode, 510 is an interlayer insulating film, and 511 and 512 are source electrodes or drain electrodes.

In this embodiment, the number of doping steps is increased by one so that the impurity concentration of the high concentration impurity region 504 is higher than that of the source or drain regions 503 and 505. In addition, a region 50 sandwiched between two channel forming regions
Since 4 has a higher concentration than the source or drain regions 503 and 505, the resistance of the entire semiconductor layer in which the TFT is in the ON state is reduced, and the photosensitivity when light is incident on the TFT for some reason is reduced.

As in the first embodiment, the region sandwiched between the two channel formation regions 501 and 502 is characterized by only the high-concentration impurity region 504. Further, as in the first embodiment, the distance d1 between the gate electrodes 509 adjacent to each other, that is, the width in the channel length direction of the high concentration impurity region is set to the width d2 of the low concentration impurity regions 506 and 507.
The shorter the distance between the two channel formation regions, the shorter the TF for one pixel.
The area occupied by T can be reduced.

Further, in the TFT structure shown in FIG. 16, as in the second embodiment, the distance d1 between adjacent gate electrodes, that is, the width of the high concentration impurity region in the channel length direction is set to the low concentration impurity region. Even if it is designed to have the same length as the width d2, the effect can be obtained.

In FIG. 17, reference numeral 600 is a substrate, and 601 and 602.
Is a channel formation region, 603 and 605 are source regions or drain regions, 604 is a high concentration impurity region, 606,
Reference numeral 607 is a low-concentration impurity region (LDD region), 608 is a gate insulating film, 609 is a gate electrode, 610 is an interlayer insulating film, and 611 and 612 are source electrodes or drain electrodes.

In this embodiment, the number of doping steps is increased to make the impurity concentration of the high concentration impurity region 604 higher than that of the low concentration impurity regions 606 and 607 and lower than that of the source or drain regions 603 and 605.

As in the first embodiment, the region sandwiched between the two channel forming regions 601 and 602 is characterized by only the high concentration impurity region 604. Further, as in the first embodiment, the distance d1 between the gate electrodes 609 adjacent to each other, that is, the width of the high concentration impurity region in the channel length direction is set to the width d2 of the low concentration impurity regions 606 and 607.
The shorter the distance between the two channel formation regions, the shorter the TF for one pixel.
The area occupied by T can be reduced.

Also in the TFT structure shown in FIG. 17, as in the second embodiment, the distance d1 between adjacent gate electrodes, that is, the width of the high concentration impurity region in the channel length direction is set to the width of the low concentration impurity region. Even if it is designed to have the same length as d2, the effect can be obtained.

The present embodiment is based on Embodiments 1 to 4,
It is possible to freely combine with any one of Embodiments 1 to 4. However, when they are combined, it is necessary to add a doping step for adding an impurity element between the two channel formation regions.

[Embodiment 6] The TFT formed by implementing the present invention can be used in various modules (active matrix type liquid crystal module, active matrix type EL module, active matrix type EC module). That is, the present invention can be applied to all electronic devices in which they are incorporated in the display section.

Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigations, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.). ) And the like. Examples of those are shown in FIGS.

FIG. 18A shows a personal computer, which has a main body 2001, an image input section 2002, and a display section 20.
03, keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 18B shows a video camera, which includes a main body 2101, a display portion 2102, a voice input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
Including 6 etc. The present invention can be applied to the display portion 2102.

FIG. 18C shows a mobile computer (mobile computer), which includes a main body 2201, a camera portion 2202, an image receiving portion 2203, operation switches 2204, a display portion 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 18D shows a goggle type display, which includes a main body 2301, a display portion 2302 and an arm portion 230.
Including 3 etc. The present invention can be applied to the display portion 2302.

FIG. 18E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) in which a program is recorded, and has a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, operation switches 2405 and the like. This player uses a DVD (D
optical Versatile Disc), CD
It is possible to play music, watch movies, play games, and use the internet. The present invention can be applied to the display portion 2402.

FIG. 18F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown) and the like. The present invention can be applied to the display portion 2502.

FIG. 19A shows a front type projector including a projection device 2601, a screen 2602 and the like. The present invention can be applied to the liquid crystal module 2808 which constitutes a part of the projection device 2601.

FIG. 19B shows a rear type projector including a main body 2701, a projection device 2702, and a mirror 270.
3, screen 2704 and the like. The present invention is a projection device 2
The present invention can be applied to the liquid crystal module 2808 which constitutes a part of 702.

Note that FIG. 19C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 19A and 19B. Projection device 2601, 27
02 is a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal module 2808, retardation plate 280.
9, a projection optical system 2810. Projection optical system 28
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG. 19C. Good.

Further, FIG. 19D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 19C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813, and a lens array 2813.
814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 19D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, the projector shown in FIG. 19 shows a case where a transmissive electro-optical device is used, and an application example of a reflective electro-optical device and an EL module is not shown.

FIG. 20A shows a mobile phone, which is a main body 29.
01, voice output unit 2902, voice input unit 2903, display unit 2904, operation switch 2905, antenna 290
6. Image input unit (CCD, image sensor, etc.) 2907
Including etc. The present invention can be applied to the display portion 2904.

FIG. 20B shows a portable book (electronic book) including a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006.
Including etc. The present invention can be applied to the display portions 3002 and 3003.

FIG. 20C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103 and the like.
The present invention can be applied to the display portion 3103. By the way, the display shown in FIG. 20C is a medium-sized or large-sized display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate whose one side is 1 m and perform multi-chambering for mass production.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to the manufacturing methods of electronic devices in all fields. Further, the electronic device of the present embodiment is one of the first, second, third and fourth embodiments, first, second, third, fourth and fifth embodiments. It is also possible to use any one of them and any combination.

[Embodiment 7] In this embodiment, an example of a manufacturing process of an active matrix substrate, which is partially different from that in Embodiment 4, is shown. Since the steps up to the middle are the same as those of the fourth embodiment, detailed description thereof will be omitted here for simplification.

According to the fourth embodiment, an n-type or p-type impurity element is added to the semiconductor layer at each concentration, and then a third insulating layer covering the gate electrode and the capacitor wiring is formed. Here, a silicon oxide film is formed with a thickness of 70 nm. Next, a heat treatment step for activating the n-type or p-type impurity element added to the semiconductor layer at each concentration is performed.
Here, heat treatment is performed at 850 ° C. for 30 minutes.

Then, second light shielding layers 1417 and 1418 are formed. The second light-shielding layer is made of W, Ta, or Ti and is 100 to 1
It is formed with a thickness of 50 nm. This thickness is sufficient to have a light-shielding property, and the thickness is set in consideration of selectivity with the underlying insulating film during etching. That is,
When the light-shielding layer is thick, it is necessary to perform over-etching in consideration of a margin at the time of etching, but in that case, the location where the etching advances quickly is not preferable because the underlying insulating film becomes thin. Further, the second light shielding layer forms a contact with the high concentration impurity region of the semiconductor layer in the opening formed in the insulating film.

Then, after performing hydrogenation treatment, a fourth insulating layer 1419 made of an organic resin material is formed. Here, an acrylic resin film having a film thickness of 400 nm is used. Then
After forming contact holes reaching the second light shielding layers 1417 and 1418, source or drain wirings 1420 and 1
421 is formed. In the present embodiment, these are used as a Ti film.
An aluminum film containing 00 nm and Ti is 300 nm, and a Ti film is 150 nm, which is formed as a three-layer laminated film by a continuous sputtering method.

Next, as shown in FIG. 22A, a fifth insulating layer 1422 made of acrylic is formed. A conductive layer of W, Ta, Ti, or the like is formed to a thickness of 100 nm on the fifth insulating layer 1422 to form a third light-blocking layer 1423. Further, a sixth insulating layer 1424 is formed. Next, a contact hole reaching the drain electrode is formed. After forming a 100 nm transparent conductive film (here, an indium tin oxide (ITO) film), patterning is performed to form a pixel electrode 1425. A cross-sectional view taken along the dotted line FF ′ in FIG. 22B corresponds to FIG.

In this way, in the pixel portion, an n-channel TFT is formed while ensuring the area (aperture ratio 74.5%) of the display region (pixel size 23 μm × 23 μm), and a sufficient storage capacitance (55.2 fF) is formed. Can be obtained.

Further, in this embodiment, an example in which a transparent conductive film is used for the pixel electrode to manufacture an active matrix substrate for a transmissive display device is shown. However, a reflective material film is used for the pixel electrode for reflection. An active matrix substrate for a mold display device may be manufactured.

In addition, this embodiment is based on the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, It can be freely combined with any one of the sixth embodiments.

[Embodiment 8] In this embodiment, Embodiment 4 will be described.
A manufacturing process for forming an active matrix substrate will be described below.

First, similarly to the fourth embodiment, a conductive film is formed on a substrate having an insulating surface and patterned to form a first light shielding layer. This first light shielding layer is a pattern
Formed as a scanning line.

The first light-shielding layer functions as a light-shielding layer that protects the active layer formed later from light. Here, a quartz substrate is used as the substrate, and a polysilicon film is used as the first light shielding layer.
(Film thickness 50 nm) and tungsten silicide (W-Si) film
A laminated structure having a thickness of 100 nm was used. Moreover, the polysilicon film protects the contamination of the substrate from the tungsten silicide. As the substrate, in addition to the quartz substrate, a glass substrate or a plastic substrate can be used. When a glass substrate is used, it is 10 to 20 ° C higher than the glass strain point.
You may heat-process in advance at a low temperature. In addition, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film may be formed on the surface of the substrate on which the TFT is formed in order to prevent diffusion of impurities from the substrate. As the first light-shielding film, polycrystalline silicon doped with an impurity element imparting a conductivity type or WSix (x = 2.0 to 2.
8), a conductive material such as Al, Ta, W, Cr and Mo, and a laminated structure thereof can be used.

Next, an insulating film (first insulating layer) covering the first light shielding layer is formed to a film thickness of 100 to 1000 nm (typically 300 to 50 nm).
0 nm). Here, a film thickness of 10 using the CVD method is used.
Silicon oxide film of 0 nm and film thickness of 280 nm using LPCVD method
Of silicon oxide films are laminated.

[0229] Further, after the insulating film is formed, the insulating surface is chemically and mechanically polished (typically, CMP technique).
For example, it may be flattened. For example, the maximum height (Rmax) of the surface of the insulating film is 0.5 μm or less, preferably 0.3 μm or less.

Then, the first amorphous semiconductor film is formed to a film thickness of 10 to 10.
It is formed at 100 nm. Here, amorphous silicon ((amorphous silicon film)) having a film thickness of 69 nm is formed by using the LPCVD method. As another means, the amorphous silicon film can be formed by a sputtering method, a plasma CVD method or the like. Then, a crystallized first crystalline semiconductor film is formed by using a technique described in Japanese Patent Application Laid-Open No. 8-78329 as a technique for crystallizing the first amorphous semiconductor layer.
By selectively adding a metal element that promotes crystallization to the amorphous silicon film and performing heat treatment, a crystalline semiconductor film that spreads from the addition region as a starting point is formed. Here, nickel is used as a metal element that promotes crystallization, and heat treatment for dehydrogenation (450 ° C., 1 hour) is performed, followed by heat treatment for crystallization (600 ° C., 8 hours). Of course,
The crystallization is not limited to the technique described in the above publication, and a known crystallization treatment can be used.

Next, nickel is gettered from the region which will be the active layer of the TFT. Here, an example in which an amorphous semiconductor film containing a rare gas is used as a gettering method is shown. In addition to the oxide film formed by laser light irradiation, the surface is treated with ozone water for 120 seconds to give a total of 1 to 5 nm.
Forming a barrier layer made of an oxide film. Then, an amorphous silicon film containing an argon element to be a gettering site is formed on the barrier layer by a sputtering method to have a film thickness of 150 nm.
The film forming conditions by the sputtering method of the present embodiment are a film forming pressure of 0.3 Pa, a gas (Ar) flow rate of 50 (sccm), a film forming power of 3 kW, and a substrate temperature of 150 ° C. In addition,
Under the above conditions, the atomic concentration of argon element contained in the amorphous silicon film is 3 × 10 ²⁰ / cm ^{3 to} 6 × 10 ²⁰ / cm ³ , and the atomic concentration of oxygen is 1 × 10 ¹⁹ / cm ^{3 to} 3 ×. It is 10 ¹⁹ / cm ³ . After that, gettering is performed by heat treatment at 650 ° C. for 3 minutes using a lamp annealing device. An electric furnace may be used instead of the lamp anneal device.

Next, as the etching stopper including the barrier layer, the amorphous silicon film containing the argon element which is the gettering site is selectively removed, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with high oxygen concentration, so it is desirable to remove the barrier layer made of an oxide film after gettering.

Next, a second amorphous silicon film is formed to a thickness of 10 to 200 nm on the first crystalline semiconductor film which has undergone the gettering process. The second amorphous silicon film is irradiated with continuous wave laser light to be crystallized. The film crystallized by laser irradiation is a second crystalline semiconductor film.

For example, using the first crystalline semiconductor film, TF
When T is made, the mobility is about 300 cm ² / Vs,
When a TFT is manufactured using the second crystalline semiconductor film, the mobility is significantly improved to about 500 to 600 cm ² / Vs.

Further, the presence of the first crystalline semiconductor film serves as a protective film when the second amorphous silicon film is irradiated with laser, and has an effect of relaxing stress with the base film.

The active layer formed of the laminated structure of the first crystalline semiconductor film and the second crystalline semiconductor film is formed by forming a thin oxide film with ozone water on the surface thereof, and then forming a mask made of resist, and To form an active layer separated into islands. After forming the active layer, the mask made of resist is removed.

In the subsequent steps, the TFT may be formed and the active matrix substrate may be completed according to the first embodiment.

In addition, this embodiment is based on the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, Any one of the sixth embodiment and the seventh embodiment can be freely combined.

[Embodiment 9] In this embodiment, an example in which the first amorphous semiconductor film is crystallized by a method different from that of Embodiment 8 will be described.

According to the eighth embodiment, a first amorphous silicon film is formed on the base insulating film. Then, heat treatment was performed in a nitrogen atmosphere at 600 ° C. for 24 hours. Alternatively, the film can be directly formed by the LPCVD method. The crystalline semiconductor film formed in this example is characterized in that the crystal grain size is smaller than that of the crystalline semiconductor film formed in Example 8.

Then, a second amorphous silicon film is formed to a thickness of 10 to 200 nm on the crystalline semiconductor film. The second amorphous silicon film is crystallized using continuous wave laser light. The film crystallized by laser irradiation is a second crystalline semiconductor film. The crystalline semiconductor film obtained in this example has the same characteristics as the second crystalline semiconductor film of Example 8. Thus, a crystalline semiconductor film which forms a TFT having high electric characteristics can be formed.

In addition, this embodiment is based on the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, Any one of the sixth embodiment and the seventh embodiment can be freely combined.

[0243]

According to the present invention, TF occupying one pixel
The area of T can be reduced to improve the aperture ratio of the pixel. Further, according to the present invention, various factors (natural light,
T due to multiple reflections, diffracted light, light from the light source, return light, etc.
It is possible to suppress the deterioration of the TFT characteristics with respect to the light incident on the FT. Further, according to the present invention, it is possible to advance the miniaturization of each display pixel pitch due to the high definition of the liquid crystal display device (increase in the number of pixels) and the miniaturization.

[Brief description of drawings]

FIG. 1 is a cross-sectional view and a top view of the present invention. (Embodiment 1)

2A and 2B are a cross-sectional view and a top view of the present invention. (Embodiment 2)

FIG. 3 is a graph showing a probability distribution of on-current values.

FIG. 4 is a graph showing a probability distribution of off current values.

FIG. 5 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 6 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 7 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 8 is a diagram showing a top view of a pixel.

FIG. 9 is a diagram showing an appearance of a liquid crystal module.

FIG. 10 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 11 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 12 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 13 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 14 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 15 is a diagram showing a manufacturing process of an active matrix substrate.

FIG. 16 is a diagram showing a cross-sectional view of the present invention. (Example 5)

FIG. 17 is a diagram showing a cross-sectional view of the present invention. (Example 5)

FIG. 18 illustrates examples of electronic devices.

FIG. 19 illustrates an example of an electronic device.

FIG. 20 illustrates an example of an electronic device.

FIG. 21 is a cross-sectional view of a thin film transistor and a pixel structure of Embodiment 3.

FIG. 22 is a diagram showing a manufacturing process of an active matrix substrate. (Example 7)

FIG. 23 is data showing the results of a simulation of the electric field strength distribution in the LDD region in the structure of the present invention.

FIG. 24 is data showing results obtained by simulating electric field strength distribution in an LDD region in a conventional structure.

FIG. 25 is a graph showing static characteristics of a TFT having a structure of the present invention and a TFT having a conventional structure.

FIG. 26 is a cross-sectional view of a thin film transistor and a pixel structure of Embodiment 4.

FIG. 27 is a view showing a conventional example.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/336 H01L 29/78 617N 5G 435 H05B 33/14 616A 612B 619B 627G F term (reference) 2H092 GA59 JA25 JA29 JA38 JA46 JB13 JB23 JB32. BB05 BB06 BB07 DA02 DB02 DB03 DB07 EA16 FA06 FA19 JA01 JA04 5F110 AA09 AA21 AA30 BB02 BB04 BB10 CC02 DD01 DD02 DD03 DD05 DD13 DD14 DD15 DD17 DD25 EE01 GG GGGGEEEEGGEEEE EE23 EE23 EE23 GG36 GG43 GG45 GG47 GG51 GG52 HJ01 HJ04 HJ12 HJ13 HJ23 HL 02 HL03 HL04 HL06 HL08 HL11 HL12 HL23 HM13 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN35 NN42 NN44 NN45 NN46 NN47 NN48 NN73 PP01 PP02 PP03 PP04 PP05 PP13 PP04 PP05 PP13 Q25 QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQAQ LL06 LL07 LL08

Claims (35)

[Claims] 1. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a plurality of gate electrodes formed on the insulating film. Wherein the semiconductor layer has a plurality of channel forming regions overlapping the gate electrode with the insulating film interposed therebetween, a source region or a drain region, and between the channel forming region and the source region or the drain region. A semiconductor device having a low-concentration impurity region, wherein an interval between two gate electrodes adjacent to each other among the plurality of gate electrodes is shorter than a width of the low-concentration impurity region. 2. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a plurality of gate electrodes formed on the insulating film. Wherein the semiconductor layer includes a plurality of channel forming regions overlapping the gate electrode with the insulating film interposed therebetween, a source region or a drain region, a high concentration impurity region adjacent to the plurality of channel forming regions, and A low-concentration impurity region is provided between the channel formation region and the source region or the drain region, and an interval between two gate electrodes adjacent to each other among the plurality of gate electrodes is a low-concentration impurity region of the semiconductor layer. A semiconductor device characterized by being shorter than the width of the region. 3. The semiconductor device according to claim 2, wherein the high concentration impurity region has the same impurity concentration as that of the source region or the drain region. 4. The semiconductor device according to claim 2, wherein the high concentration impurity region has a higher impurity concentration than the source region or the drain region. 5. The semiconductor device according to claim 2, wherein the high concentration impurity region has a higher impurity concentration than the low concentration impurity region and a lower impurity concentration than the source region or the drain region. 6. The semiconductor device according to claim 2, wherein a width of the high concentration impurity region is equal to a distance between adjacent gate electrodes. 7. The method according to claim 1, wherein, in the plurality of channel formation regions, the distance between the two adjacent channel formation regions is equal to the distance between the two adjacent gate electrodes. Characteristic semiconductor device. 8. A semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a first gate electrode and a second gate electrode formed on the insulating film. TF
A semiconductor device comprising T, wherein the semiconductor layer is a first gate electrode overlapping the first gate electrode with the insulating film interposed therebetween.
Of the second gate electrode and the channel formation region of the second gate electrode with the insulating film interposed therebetween.
A high-concentration impurity region adjacent to both the first channel formation region and the second channel formation region, and a first low-concentration impurity region in contact with the first channel formation region. A drain region in contact with the first low concentration impurity region, a second low concentration impurity region in contact with the second channel formation region, and a source region in contact with the second low concentration impurity region, A semiconductor device, wherein a distance between the first gate electrode and the second gate electrode is shorter than a width of the first low concentration impurity region. 9. The semiconductor device according to claim 8, wherein the high concentration impurity region has the same impurity concentration as that of the source region or the drain region. 10. The semiconductor device according to claim 8, wherein the high concentration impurity region has a higher impurity concentration than the source region or the drain region. 11. The semiconductor device according to claim 8, wherein the high concentration impurity region has a higher impurity concentration than the low concentration impurity region and a lower impurity concentration than the source region or the drain region. 12. The semiconductor device according to claim 8, wherein a width of the high concentration impurity region is shorter than a width of the first low concentration impurity region. 13. The semiconductor device according to claim 8, wherein a width of the high concentration impurity region is shorter than a width of the second low concentration impurity region. 14. The semiconductor device according to claim 8, wherein the width of the first low concentration impurity region and the width of the second low concentration impurity region are the same. 15. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a plurality of gate electrodes formed on the insulating film. Wherein the semiconductor layer includes a plurality of channel forming regions overlapping the gate electrode with the insulating film interposed therebetween, a source region or a drain region, a high concentration impurity region adjacent to the plurality of channel forming regions, and A low-concentration impurity region is provided between the channel formation region and the source region or the drain region, and a distance between two adjacent gate electrodes of the plurality of gate electrodes is equal to a width of the low-concentration impurity region. A semiconductor device which is the same as 16. The semiconductor device according to claim 15, wherein the high concentration impurity region has the same impurity concentration as that of the source region or the drain region. 17. The semiconductor device according to claim 15, wherein the high concentration impurity region has a higher impurity concentration than the source region or the drain region. 18. The high concentration impurity region according to claim 15, wherein the high concentration impurity region has a higher impurity concentration than the low concentration impurity region,
A semiconductor device having an impurity concentration lower than that of the source region or the drain region. 19. A semiconductor device according to claim 1, further comprising a pixel electrode electrically connected to the source region or the drain region. 20. In a semiconductor device in which a pixel electrode, a thin film transistor, and a capacitor are provided on a substrate, one electrode of the capacitor is connected to one of a source and a drain of the thin film transistor, and A semiconductor device, wherein the electrode and a conductive film formed in the same layer as the electrode extend over the gate electrode of the thin film transistor. 21. In a semiconductor device having a pixel electrode, a thin film transistor, and a capacitor provided on a substrate, one electrode of the capacitor is connected to one of a source and a drain of the thin film transistor, and A semiconductor device, wherein the electrode and a light-shielding layer formed of the same layer as the electrode extend on the gate electrode of the thin film transistor and overlap with the light-shielding layer provided on the gate electrode. 22. In a semiconductor device having a pixel electrode, a thin film transistor, and a capacitor provided on a substrate, one electrode formed on an insulating layer of the capacitor is a source or a drain of the thin film transistor. Connected to one, the insulating layer covers the gate electrode of the thin film transistor, one electrode of the capacitive element and a light-shielding layer formed in the same layer as the capacitor element, extend over the gate electrode of the thin film transistor, and the upper layer A semiconductor device, characterized in that it overlaps with another light-shielding layer provided in the. 23. The semiconductor device according to claim 22, wherein the light shielding layer has a thickness of 100 to 150 nm. 24. A semiconductor layer formed on a substrate, a first light shielding layer formed between the substrate and the semiconductor layer, and a gate electrode formed on the opposite side of the semiconductor layer from the substrate side. A pixel electrode formed on the gate electrode, a third light-shielding layer formed between the gate electrode and the pixel electrode, and a third light-shielding layer formed between the gate electrode and the third light-shielding layer. A second light-shielding layer, and the gate electrode and the first
To a third light shielding layer are overlapped with each other. 25. In a semiconductor device having a pixel electrode, a thin film transistor, and a capacitor provided on a substrate, a first light shielding layer formed on the substrate, and a first light shielding layer formed on the light shielding layer. An insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, a gate electrode formed on the second insulating layer, and a capacitor wiring, A third insulating layer formed on the gate electrode and the capacitor wiring, a second light shielding layer formed on the third insulating layer, and a fourth insulating layer formed on the second light shielding layer.
A source / drain wiring formed on the fourth insulating layer and a fifth wiring formed on the source / drain wiring.
An insulating layer, a third light shielding layer formed on the fifth insulating layer, and a sixth insulating layer formed on the third light shielding layer,
A pixel electrode formed on the sixth insulating layer, the semiconductor layer, the second insulating layer, the capacitor wiring, the third insulating layer, and the second insulating layer.
A semiconductor device, wherein the capacitive element is formed in an overlapping portion with a light shielding layer, and the second light shielding layer extends on the gate electrode. 26. The semiconductor device according to claim 25, wherein the second light shielding layer has a thickness of 100 to 150 nm. 27. A first conductive layer having a light shielding property is formed on an insulating surface, and a first insulating layer is formed to cover the first conductive layer,
A first amorphous semiconductor film is formed on the first insulating layer, and the first amorphous semiconductor film is crystallized by heat treatment without being melted to form a first crystalline semiconductor film; A second amorphous semiconductor film is formed in contact with one crystalline semiconductor film,
By irradiating a laser beam, the second portion in the irradiation region is irradiated.
A method for manufacturing a semiconductor device, which comprises the step of crystallizing after melting a part or all of an amorphous semiconductor film. 28. A first conductive layer having a light shielding property is formed on an insulating surface, and a first insulating layer is formed to cover the first conductive layer,
A first crystalline semiconductor film is formed on the first insulating layer, a second amorphous semiconductor film is formed on the first crystalline semiconductor film in contact with the first crystalline semiconductor film, and a laser beam is irradiated to expose the irradiated region. After melting a part or all of the second amorphous semiconductor film,
A method for manufacturing a semiconductor device, which has a step of crystallizing. 29. A first conductive layer having a light-shielding property is formed on an insulating surface, and a first insulating layer covering the first conductive layer is formed,
Forming a first amorphous semiconductor film on the first insulating layer and introducing a metal element into the first amorphous semiconductor film; and melting the first amorphous semiconductor film by heat treatment. Without crystallization to form a first crystalline semiconductor film, a second amorphous semiconductor film is formed in contact with the first crystalline semiconductor film, laser light is irradiated, A method of manufacturing a semiconductor device, comprising the step of crystallizing after melting a part or all of the second amorphous semiconductor film. 30. The metal element according to claim 29,
Method for manufacturing a semiconductor device, which is one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au 31. The laser light according to claim 27, wherein the laser light is a continuous oscillation YAG laser or YVO4 laser.
The, YLF laser, YalO3 laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser
A method for manufacturing a semiconductor device, characterized in that the semiconductor device is oscillated from one selected from the above. 32. The laser light according to claim 27, wherein the laser light is one selected from a continuous wave excimer laser, an Ar laser, a Kr laser, and a CO2 laser. A method for manufacturing a semiconductor device, which is oscillated. 33. The laser light according to claim 27, wherein the laser light oscillates from one sleep selected from a continuous wave helium cadmium laser, a copper vapor laser, and a gold vapor laser. And a semiconductor device manufacturing method. 34. A first crystalline semiconductor film and a second crystalline semiconductor film are formed in contact with each other on an insulating substrate, and a first crystalline semiconductor film is formed between the insulating substrate and the first crystalline semiconductor film. A light-shielding film, a gate electrode formed on the side of the second crystalline semiconductor film opposite to the insulating substrate, a pixel electrode formed on the upper layer of the gate electrode, and the gate electrode A third light-shielding layer formed between the gate electrode and the pixel electrode, and a second light-shielding layer formed between the gate electrode and the third light-shielding layer,
The average crystal grain size of the second crystalline semiconductor film is larger than the average crystal grain size of the first crystalline semiconductor film. 35. A display device comprising a pixel electrode, a thin film transistor, and a capacitor provided on an insulating substrate,
A first light shielding layer formed on the insulating substrate, a first insulating layer formed on the light shielding layer, a first crystalline semiconductor film and a second crystal formed on the first insulating layer in contact with each other. Conductive semiconductor film, a second insulating layer formed on the first crystalline semiconductor film and the second crystalline semiconductor film, a gate electrode formed on the second insulating layer, and a capacitor wiring, A third insulating layer formed on the gate electrode and the capacitor wiring, a second light shielding layer formed on the third insulating layer, and a fourth insulating layer formed on the second light shielding layer. A source and drain wiring formed on the fourth insulating layer, a fifth insulating layer formed on the source and drain wiring, and a fifth insulating layer formed on the fifth insulating layer.
3 light-shielding layer, having a sixth insulating layer formed on the third light-shielding layer, and a pixel electrode formed on the sixth insulating layer,
The capacitive element is formed on the second crystalline semiconductor film, the second insulating layer, the capacitor, the third insulating layer, and the second light-shielding layer, and the second light-shielding layer is formed on the gate electrode. A display device characterized by being extended to.