JP2003228345A - Liquid crystal display - Google Patents

Abstract

(57) [Abstract] [Problem] To maintain high-speed response of liquid crystal and at low cost.
A liquid crystal display device having a low horizontal crosstalk level and a low charging error level while maintaining low power consumption is realized. SOLUTION: In addition to adopting a capacitive coupling drive, a binary potential is used as an output of a storage capacitor line driving circuit for controlling a potential of the storage capacitor line, and the storage capacitor line is electrically disconnected from the driving circuit for at least a part of a period. It is configured to be separated and floated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a drive circuit for a storage capacitance line in capacitive coupling drive.

[0002]

2. Description of the Related Art As active matrix type liquid crystal display devices using thin film transistor (TFT) array substrates have become widespread, there has been a general demand for large size, high definition, high image quality, low power consumption and low cost. It is becoming stronger and stronger, and efforts are being made to meet these requirements.

As one of the efforts to improve the overall performance including the cost reduction, it is considered that the driving circuit is built in the substrate by forming the TFT array substrate using low temperature polysilicon instead of the conventional amorphous silicon. ing. In this case, from the viewpoint of process simplification, it is desired to configure a circuit using only p-type or n-type unipolar TFTs. Further, the TFT manufactured by the low temperature polysilicon process has a problem that the operating breakdown voltage is lower than that of a normal single crystal silicon FET, and it is necessary to configure the circuit under these constraint conditions.

In addition, as a driving method of a liquid crystal display device, the response of the liquid crystal is fast, the DC offset applied to the liquid crystal can be accurately compensated and the reliability is excellent, and the required voltage amplitude is small, so that the power consumption is small. There is capacitive coupling drive with many features. In the active matrix type liquid crystal display device, a TFT switch is provided for each pixel, and the scanning pulse supplied to the gate line (scanning line) turns on the switch for a short time (1 horizontal scanning time), and the video signal of the source line during that period. The liquid crystal layer that becomes the pixel is charged through the TFT, and then the switch is opened to hold the voltage of the pixel until the next charging (holding period or vertical scanning period). Further, in the capacitive coupling driving method, The potential of the terminal of the storage capacitor connected in parallel to the liquid crystal layer that is not connected to the switch is changed by a predetermined capacitance during the holding period to compensate for the voltage applied to the liquid crystal layer via the storage capacitor. The features of are realized. One method of changing the voltage of the storage capacitor is to connect one end of the storage capacitor to the gate line in the previous stage. However, if the capacitance load on the gate line is too heavy due to this, the storage capacitor for each scan line It is often the case that the voltage of the storage capacitor is compensated by collectively connecting the storage capacitors for each capacitance to an independent storage capacitance line and driving the storage capacitance line in synchronism with the scanning line.

Conventionally, as a circuit for driving the storage capacitance line, a three-value output circuit as shown in FIG. 7 has been used. Three voltage sources, that is, high level compensation potential signal V
ep, the intermediate level compensation potential signal Vec, and the low level compensation potential signal Vem are supplied to the compensation potential signal output node CC while being switched by the TET switch. FIG. 8 shows a timing chart of the output waveform together with the scanning signal of the gate line. In FIG. 8, Vg (n) and Vg (n +
1) and Vg (n + 2) are the nth, n + 1th, and
Scan signal waveform of the (n + 2) th gate line, CC
(N), CC (n + 1), CC (n + 2) are n
This is the voltage waveform of the storage capacitance line corresponding to the (n + 1) th and (n + 2) th gate lines, that is, the waveform of the compensation potential signal output. A logic chart of the circuit of FIG. 7 is shown in FIG.
Since this circuit uses the compensation potential signal power supply of the intermediate level in addition to the high level and the low level, the current flows only when the compensation potential signal output control signal Q becomes High, that is, the high level compensation potential signal Vep. Alternatively, it is only when the low level compensation potential signal Vem is connected to the compensation potential signal output node CC. In this way, the storage capacitor line drive circuit only needs to supply an output that consumes current only before and after the period in which the corresponding scan signal becomes active, so that the average current flowing through the drive circuit becomes small and the TFTs of the same conductivity type are provided. A circuit with low power consumption can be configured by using only the above.

Incidentally, in FIG. 9, where V is a current, the Vep switch or Vem switch is indicated with (). However, these are respectively Vep output control logical products shown in FIG. This shows that current is consumed in the circuit 1 (2 inputs) 104 and the Vem output control AND circuit 1 (2 inputs) 106.

[0007]

By the way, as the definition of the liquid crystal display device becomes higher, the number of scanning lines increases and the scanning time per one scanning line (horizontal scanning time) becomes shorter. Further, in order to reduce the cost, there is a case in which a multiplexer drive configuration is used in which the number of output terminals of a source line drive circuit for supplying an image signal to a display unit can be reduced to half or more at once. Multiplexer driving is a driving method in which an output from one source line driving circuit output terminal is distributed to a plurality of source lines, and thereby a plurality of source lines are driven by the output of one source line driving circuit output terminal. Therefore, it is possible to reduce the number of output terminals of the source line driving circuit, but on the other hand, since a plurality of source line signals must be written in a plurality of pixels at different timings during one scanning time,
The time available for writing to each pixel becomes shorter.

If the writing time is shortened in this way, various transient phenomena of the matrix array circuit may not be contained at the timing at which the writing must be completed, especially at the moment when the TFT switch is turned off. If a transient phenomenon remains in the storage capacitor line, it causes an error in the voltage applied to the liquid crystal layer, and as a result, image quality problems such as lateral crosstalk become apparent.

This transient phenomenon of the storage capacitance line mainly affects the storage capacitance line when the potential of the source line fluctuates, and the variation affects the storage capacitance line via the cross capacitance between the wirings, whereby the potential of the storage capacitance line fluctuates. Occurs to do. Since the time constant for this transient phenomenon to settle is determined by the product of the capacitance that becomes the load of the storage capacitance line and the wiring resistance, in order to quickly converge the transient phenomenon and avoid the effect on the image quality, reduce the value of the storage capacitance. Therefore, it is effective to reduce the wiring resistance. In order to reduce the wiring resistance, there are process improvements such as changing the wiring material and increasing the thickness. Although it is easier to reduce the storage capacitance, it is necessary to increase the amplitude of the compensation voltage supplied to the storage capacitance line in order to secure the necessary compensation width of the pixel voltage. However, in the conventional ternary output circuit, it is difficult to further increase the amplitude because of the breakdown voltage of the TFT, especially when low temperature polysilicon is used.

The present invention solves the problem of image quality due to the shortened writing time in pixels as described above, and can be used in a low temperature polysilicon process or the like in which a driving circuit can be built in but the withstand voltage is not sufficient. An object of the present invention is to provide a liquid crystal display device using a capacitance line driving method.

[0011]

A liquid crystal display device according to the present invention includes a plurality of source lines for transmitting image signals, a plurality of gate lines provided in a direction intersecting the source lines for transmitting scanning signals, and both lines. The pixel electrodes provided corresponding to the respective intersections, the thin film transistors for writing the image signal to the pixel electrodes, the storage capacitors provided for each pixel electrode, and the storage capacitors common to each row parallel to the gate line. And a storage capacitor line driving circuit for driving the storage capacitor line on an insulating substrate, and a capacitive coupling drive type active matrix liquid crystal that modulates the voltage of the pixel electrode via the storage capacitor. In the display device, the storage capacitance line and the storage capacitance line drive circuit are electrically separated from each other during at least a part of the period in which the image signal written in the pixel electrode is held. It is characterized in. Further, the output of the storage capacitor line drive circuit is binary.

As a result, since the output amplitude can be increased without increasing the power consumed inside the storage capacitor line drive circuit, the storage capacitor can be reduced, and as a result, the liquid crystal display device can be made finer. Even in such a case, the characteristics of the capacitive coupling drive system can be exhibited without impairing the image quality.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) First, a capacitive coupling drive type active matrix array substrate 1 to which the present invention is applied.
0 is shown in FIG. Although not shown in the drawing, a liquid crystal display device is completed by sandwiching and sealing a liquid crystal layer between the array substrate 10 and a counter substrate prepared separately. In each pixel formed in a region divided by a plurality of gate lines 1 and source lines 2, one end of a liquid crystal capacitor Clc connected to a TFT constitutes a pixel electrode 8, and the other end is a common counter for all pixels. It is connected to the electrode 7. This counter electrode 7
May be formed on the counter substrate described above, or may be formed on the array substrate 10. T for each pixel electrode 8
A storage capacitor Cst, which has a function of storing the charge written in FT and a function of modulating the voltage of the pixel electrode by capacitive coupling drive, is connected, and the other end of the series of storage capacitors parallel to the gate line is common. It is connected to the storage capacitance line 3. A gate line drive circuit 4 for driving each gate line 1, a source line drive circuit 5 for driving each source line 2, and a storage capacitance line drive circuit 6 for driving each storage capacitance line 3 are also formed on the array substrate 10. ing. These drive circuits are configured using TFTs formed in the same process as that of forming pixel TFTs.

The present invention relates to the storage capacitance line drive circuit 6 in this array substrate. FIG. 1 shows a main part of the storage capacitor line drive circuit of the present invention. In FIG. 1, Vem and Vep are voltage sources and are supplied to the high level compensation potential signal input node 101 and the low level compensation potential signal input node 103, respectively. And
Vep output switch by various control signals such as compensation potential signal output control positive phase signal Q (n), compensation potential signal output control negative phase signal QB (n), frame switching positive phase signal FR, frame switching negative phase signal FRB Element 1 107,
203 of the Vep output switch element 2, 109 of the Vem output switch element 1, and 204 of the Vem output switch element 2
Is controlled to connect the voltage source as the output CC (n) of the storage capacitor line drive circuit 6 to the compensation potential signal output node 110 which is an output terminal at a predetermined timing. A feature of the storage capacitance line drive circuit of the present invention is that the power consumption of the storage capacitance line drive circuit 6 is reduced by floating the compensation potential signal output node 110 during an unnecessary period, as described later. Further, there is a feature that a large output amplitude can be obtained by changing from the conventional three-value output to a two-value output provided with two voltage sources.

A timing chart of the output obtained from the circuit of FIG. 1 is shown in FIG. 2 together with the timing of the scanning signal Vg (n) of the gate line and other control signals.
The horizontal axis of FIG. 2 is time, and the minimum interval is one horizontal scanning period, V
A period in which a waveform such as g (n) (scan signal of the nth gate line) is repeated is a vertical scanning period (frame period).
Is. In the frame in which the frame switching positive phase signal FR is High, the signal CC (n) of the n-th storage capacitance line is V
After g (n) is turned off, Vem changes to Vep. CC (n) is Vg in the frame where FR is Low
After (n) is turned off, Vep changes to Vem. In the (n + 1) th line, the change of CC (n + 1) is CC
This is the reverse of the change of (n), and the n + 2nd line changes similarly to the nth line with a delay of two horizontal scanning periods. A change in the amplitude of the signal CC (n) on the storage capacitance line modulates or level shifts the terminal voltage of the liquid crystal capacitance Clc via the storage capacitance Cst to compensate the pixel voltage. This example shows an example of so-called 1H inversion in which the image voltage is inverted for each gate line. If the breakdown voltage of the TFTs forming the storage capacitance line drive circuit is the same, the amplitude (Vep-Vem) of the signal CC (n) of the nth storage capacitance line is the same as that of the conventional case shown in FIGS. It will be about twice as large. Amplitude (Ve
P-Vem) changes the pixel electrode potential, that is, the compensation voltage is (Vep-Vem) .Cst / (Cst + Clc)
Therefore, if the amplitude (Vep−Vem) can be increased, the storage capacitance Cst required to secure the same compensation amount may be small. Therefore, it becomes possible to reduce the time constant related to the storage capacitance line, and to reduce lateral crosstalk and TFT.
Therefore, it is possible to solve the image quality problem such as the error due to the insufficient charging of.

Further, in the storage capacitance line drive waveform such as CC (n) in FIG. 2, the portion indicated by the solid line is in the state of being output from the drive circuit, and the portion indicated by the dotted line indicates that the storage capacitance line is electrically connected to the drive circuit. It is in a floating state after being physically separated. As described above, another feature of the present invention is that the potential of the storage capacitance line basically does not change during the period when the signal of the gate line does not change, so that it is not necessary to supply a voltage from the driving circuit. By providing the floating period, the power consumption is reduced.

The relationship between the state of each control signal and the circuit output in the circuit of FIG. 1 is summarized in FIG. Further, the portion surrounded by the dotted line in FIG. 1 is a portion newly added to the conventional circuit configuration (FIG. 7), and therefore a concrete example for realizing the additional switch portion for Vep and the additional switch portion for Vem. Examples of typical circuit configurations are shown in FIGS. 4A and 4B and FIGS. 5A and 5B together with their logic charts.

It should be noted that Vep and Vem are shown in parentheses at the portions where the current is written in FIGS. 3, 4, and 5.
Alternatively, Vep addition SW and Vem addition SW are described, which are respectively the Vep output control AND circuit 2 (3 inputs) 201 and the Vem output control AND circuit 2 (3 inputs) shown in FIG. This indicates that current is being consumed in 202.

Further, in the additional control circuit for Vep and the additional control circuit for Vem shown in FIGS. 4A and 5A, respectively, a TFT in which QB (n) is input to the gate
Even if it does not exist, the current consumption does not increase to the extent that it becomes a problem, so it may be omitted for simplification of the circuit configuration.

In the array substrate shown in FIG. 6,
In the present embodiment, an example is shown in which the source line drive circuit 5, the gate line drive circuit 4, and the storage capacitance line drive circuit 6 are all formed on the substrate by using TFTs formed by the same process as the pixel TFT. Since the source line drive circuit requires a high frequency operation in particular, the capacity of the TFT manufactured by the low temperature polysilicon process may be insufficient. In that case, an external drive circuit IC made of single crystal silicon can be used.

Further, the pixel TFT and the drive circuit T
If the FT is composed of only the p-channel type or the n-channel type, the process is simplified and the cost is reduced. The storage capacitor line drive circuit proposed here is particularly suitable for lowering the power consumption when using such a single conductivity type TFT.

In the present embodiment, the output of the storage capacitance line drive circuit is connected to the storage capacitance line only for about one horizontal scanning period before and after the period when the scanning signal of the associated gate line changes, and the storage capacitance line for the other periods. Is floating. However, when the signal voltage of the source line changes significantly, the potential of the storage capacitance line changes via the cross capacitance of the wiring, which may adversely affect the image quality. When this adverse effect becomes a problem, the storage capacitance line is connected to the storage capacitance line drive circuit for a short period in accordance with the timing of the signal on the source line, and the voltage of Vep or Vem is applied to the storage capacitance line. It is possible to stabilize the potential of the line with a low impedance and avoid adverse effects due to changes in the signal voltage of the source line. This connection period is 1
It is desirable that the period is considerably shorter than the horizontal scanning period. As a signal for controlling this connection, for example, an output enable signal used for generating a gate signal waveform in a gate line driving circuit can be used.

More specifically, this output rice
When the bull signal is used, the period storage capacitor line is driven during one frame period when all gate signals are off or at least one gate signal is on. Can be connected to a circuit. For example, in the case of line inversion drive, when the polarity of the source signal is switched every horizontal period, the switching timing is usually performed in either one of the above two periods. Therefore, the storage capacitance line may be connected to the storage capacitance line drive circuit in accordance with the period corresponding to the switching timing.

Although the case of using the low-temperature polysilicon TFT has been described here, the present invention is not limited to this, and the case of using a TFT composed of amorphous silicon, a silicon-germanium semiconductor, or the like is also applicable. Obviously it applies.

The liquid crystal to be used is not particularly limited, but OCB (optically)
Compensated Birefringenc
e) When combined with a liquid crystal which responds at high speed, such as liquid crystal, the effect is more exerted.

Further, according to the present invention, it becomes easy to introduce a source line multiplexer drive, and a high quality liquid crystal display device can be realized at a lower cost.

[0028]

According to the present invention, since the amplitude of the drive waveform can be increased without increasing the power consumed inside the drive circuit for controlling the potential of the storage capacitance line, the storage capacitance can be reduced, resulting in high speed. While maintaining responsiveness, low cost, and low power consumption, the problem of image quality due to lateral crosstalk, charging error, etc. can be solved, and a liquid crystal display device with high image performance even in high-definition display can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a storage capacitor line drive circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a timing chart of the storage capacitor line drive circuit of FIG.

FIG. 3 is a logic chart illustrating the operation of the storage capacitor line drive circuit of FIG.

FIG. 4 is a detailed diagram and a logic chart of a part of the storage capacitor line drive circuit of FIG.

5 is a detailed diagram and a logic chart of a part of the storage capacitor line drive circuit of FIG.

FIG. 6 is a diagram showing an overall configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional storage capacitance line drive circuit.

FIG. 8 is a timing chart of a conventional storage capacitor line drive circuit.
To

FIG. 9 is a logic chart illustrating the operation of a conventional storage capacitor line drive circuit.

[Explanation of symbols]

1 gate line 2 source line 3 storage capacity line 4 gate line drive circuit 5 source line drive circuit 6 storage capacity line drive circuit 7 counter electrode 8 pixel electrode 10 array substrate 101 high level compensation potential signal (Vep) input node 102 intermediate level compensation Potential signal (Vec) input node 103 Low level compensation potential signal (Vem) input node 104 Vep output control AND circuit 1 (2 inputs) 105 Vec output control logic inverting circuit 106 Vem output control AND circuit 1 (2 Input) 107 Vep output switching element 1 108 Vec output switching element 109 Vem output switching element 1 110 Compensation potential signal output node (nth stage) 111 High level compensation potential signal (Vep) 112 Intermediate level compensation potential signal (Vec) 113 Low Level compensation potential signal (Vem) 1 4 frame switching for positive phase signal (FR) 115 frame reverse phase signal switching (FRB) 116 compensation potential signal output control positive-phase signal 1 (Q
(N): nth stage 117 Compensation potential signal output control anti-phase signal (QB
(N): n-th stage) 201 Vep output control AND circuit 2 (3 inputs) 202 Vem output control AND circuit 2 (3 inputs) 203 Vep output switch element 2 204 Vem output switch element 2 205 Compensation potential signal Output control positive phase signal 2 (Q (n +
1): n + 1st stage) Clc Liquid crystal capacity Cst Storage capacity

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 621 G09G 3/20 621F 623 623Y 624 624B 624Z (72) Inventor Kimura Masanori Osaka Prefecture Kadoma City 1006 Kadoma Matsushita Electric Industrial Co., Ltd. (72) Inventor Katsuhiko Kumagawa 1006 Kadoma, Kadoma City, Osaka Prefecture F-term inside Matsushita Electric Industrial Co., Ltd. (reference) 2H092 GA59 JB13 JB63 JB69 KA04 KA12 KA18 KA22 NA26 NA27 QA06 QA07 2H093 NA NC13 NC18 NC34 NC35 NC49 ND03 ND32 NF04 NF05 5C006 AC11 AC25 AF42 AF50 AF51 AF69 AF71 BB16 BC03 BC06 BC11 BC20 BF24 FA11 FA24 FA37 FA47 5C080 AA10 BB05 DD03 DD07 DD08 DD10 DD26 FF11 JJ03 JJ04

Claims (9)

[Claims] 1. A plurality of source lines for transmitting an image signal, a plurality of gate lines provided in a direction intersecting with the source lines for transmitting a scanning signal, and corresponding to respective intersections of the source lines and the gate lines. A pixel electrode provided for each pixel electrode, a thin film transistor for writing an image signal to the pixel electrode, a storage capacitor provided for each pixel electrode, and the storage capacitor commonly connected to each row parallel to a gate line. An active matrix liquid crystal display device comprising: a storage capacitor line; and a storage capacitor line drive circuit for driving the storage capacitor line on an insulating substrate, wherein the voltage of the pixel electrode is modulated via the storage capacitor. The storage capacitance line and the storage capacitance line drive circuit are electrically separated from each other during at least a part of the period in which the image signal written in the pixel electrode is held. And a liquid crystal display device. 2. The storage capacitance line drive circuit is characterized in that a current flowing from a power supply forming the storage capacitance line drive circuit is cut off at least during a period when a potential is not supplied to the storage capacitance line. Item 2. The liquid crystal display device according to item 1. 3. The liquid crystal display device according to claim 1, wherein the storage capacitance line drive circuit has a binary output. 4. The liquid crystal display device according to claim 1, wherein the storage capacitance line drive circuit is configured by using a thin film transistor made of a low temperature polysilicon semiconductor. 5. The liquid crystal display device according to claim 1, wherein the storage capacitance line drive circuit is composed of a single conductivity type thin film transistor. 6. At least one of a source line driving circuit for supplying an image signal to the source line and a gate line driving circuit for supplying a scanning signal to the gate line is composed of a thin film transistor, and is formed on the insulating substrate. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is provided. 7. The liquid crystal display device according to claim 1, wherein a source line driving circuit that supplies an image signal to the source line is driven by a multiplexer. 8. The storage capacitor line driving circuit stores the storage signal from the storage capacitor line driving circuit during at least a part of a period in which an image signal potential of a source line changes within a period in which an image signal written in the pixel electrode is held. The liquid crystal display device according to claim 1, wherein a potential is supplied to the capacitance line. 9. The switching for supplying a potential from the storage capacitor line drive circuit to the storage capacitor line is performed by using an output enable signal for generating a scanning signal waveform to a gate line. The liquid crystal display device according to claim 8.