JP2005128101A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost liquid crystal display device whose power consumption is low and response is fast and which has a narrow frame, and in which operation response of a storage capacitance line driving circuit can be improved even when a scanning time is reduced with an increase in the load capacitance of a storage capacitance line for the larger screen of a liquid crystal display or increase in display capacitance of a liquid crystal display. <P>SOLUTION: The storage capacitance line driving circuit 1 is equipped with: a transistor 2a where a compensation voltage Vel is applied on its drain electrode and the compensation voltage is inverted and applied on its gate electrode; a transistor 2b where the compensation voltage Vel is applied on its drain electrode and the output voltage of the source electrode of the transistor 2a is inverted and applied on the gate electrode of the transistor 2b; a capacitance 3 disposed between the gate electrode and the source electrode of the transistor 2b; and a transistor 2c where a compensation voltage Veh is applied and the output compensation voltage to be applied on the storage capacitance line is controlled according to an input control signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device using a thin film transistor.

  A structure of a conventional active matrix liquid crystal display device is shown in FIG.

  A storage capacitor 52 and a liquid crystal layer 53 are connected to a drain terminal of a switching element 51 (n-channel MOS transistor) for driving a pixel of the liquid crystal display device, and the other terminal of the storage capacitor 52 and the liquid crystal layer 53 is a liquid crystal layer. It is connected to a common electrode line 56 connected to a counter electrode (not shown) arranged to face the 53 pixel electrodes.

  The scanning line driving circuit 57 outputs a driving voltage for turning on the switching element 51 to the scanning line 55, and the signal line driving circuit 58 outputs a voltage corresponding to the image signal to the signal line 54. Note that the pixel here refers to a minimum unit of an image displayed on the liquid crystal display device.

  The scanning line driving circuit 57 sequentially scans the scanning lines 55 from the top in FIG. 5, applies a driving voltage to turn on the plurality of switching elements 51 connected to the same scanning line to the scanning lines 55, and the signal line driving circuit 58 By applying a voltage corresponding to the image signal to the signal line 54, the storage capacitor 52 and the liquid crystal layer 53 are charged to a desired voltage via the switching element 51.

  Next, when the scanning line driving circuit 57 applies a driving voltage for turning off each switching element 51 on the same scanning line to the scanning line 55, the voltage applied to the storage capacitor 52 and the liquid crystal layer 53 is subjected to the next scanning. Hold up. Thus, the entire screen is displayed by sequentially driving the scanning lines 55.

  FIG. 6 is a diagram showing an electrical equivalent circuit of one display element. The display element is provided with a switching element 51 at the intersection of the scanning line 55 and the signal line 54, a pixel electrode 59 at the drain terminal of the switching element 51, a storage capacitor 52 having a capacitance value Cst, and a liquid crystal layer having a capacitance value Clc. 53 are connected to each other through the common electrode line 56 and connected to the counter electrode. In addition, a parasitic capacitance 60 having a capacitance value of Cgd exists between the gate and drain of the switching element 51.

  FIG. 7 is a diagram showing drive waveforms when the liquid crystal display device constituted by the display elements shown in FIG. 6 is driven by the 1-frame inversion drive method. In FIG. 7, A is a scanning signal Vg transmitted from the scanning line driving circuit 57 to the scanning line, B is an image signal Vs transmitted from the signal line driving circuit 58 to the signal line, C is a potential of the pixel electrode 59, and E is The center value Vsigc of the image signal is shown respectively. In FIG. 7, Vgh is the high potential of the scanning signal Vg, and Vgl is the low potential of the scanning signal Vg. Vsh is the high potential of the image signal Vs, and Vsl is the low potential of the image signal Vs.

  An image signal Vs is written into the pixel electrode 59 when the switching element 51 is ON. However, when the switching element 51 is turned off, the parasitic capacitance 60 existing between the gate and the drain of the switching element 51 generates a punch-through voltage ΔV in the pixel electrode potential C as shown by D, so that the pixel electrode 59 and the opposing electrode are formed. DC voltage component is applied between the two. The punch-through voltage ΔV is given by the following equation.

ΔV = (Vgh-Vgl) × Cgd / Ctot
Here, Ctot = Cgd + Cst + Clc.

  If the counter electrode potential Vcom is set to the center value Vsigc of the image signal ignoring this punch-through voltage ΔV, a potential difference occurs between the high potential side and the low potential side with respect to the voltage applied to the liquid crystal that is AC driven. Flickering and baking will occur.

  In general, in order to compensate the punch-through voltage ΔV, the counter electrode potential Vcom is set to the center value of the image signal−the punch-through voltage (= Vsigc−ΔV), whereby a DC voltage component is applied to the liquid crystal layer. prevent. However, this punch-through voltage ΔV cannot be compensated uniformly over the entire range from white to black because the liquid crystal material has dielectric anisotropy.

  A capacitive coupling driving method is known as a driving method for effectively compensating for such a penetration voltage due to the parasitic capacitance 60 existing between the gate and drain of the switching element 51.

  In addition, liquid crystal display devices for liquid crystal televisions that have been actively developed and commercialized in recent years or for computers having multimedia functions for handling moving image data are strongly required to have high-speed response to support moving image display. It has been. As a method of making liquid crystal respond at high speed, a method of superimposing an overdrive voltage on an image signal is known, but it requires a line memory or complex arithmetic processing to correspond to the moving image data to be displayed in real time. , Leading to higher costs. For this reason, the capacitive coupling driving method is widely used for liquid crystal display devices that require a high-speed response in that a high-speed response can be obtained with an inexpensive configuration.

  FIG. 8 shows a configuration of a liquid crystal display device using a capacitive coupling driving method. As shown in FIG. 8, in the capacitive coupling driving method, the storage capacitor 52 is not connected to the common electrode line, but connected to the storage capacitor line 62. The storage capacitor line driving circuit 61 compensates the penetration voltage. A voltage pulse (compensation voltage) is applied to the storage capacitor line 62.

  Hereinafter, the capacitive coupling driving method will be described with reference to timing charts of FIGS. 9 and 10.

  In the timing chart showing the voltage waveform of FIG. 9, the scanning signal voltage at the n-th scanning line 55 (n is a positive integer) counted from the uppermost stage of FIG. A compensation voltage in the storage capacitor line 62 of the eye is indicated by Vcs (n). FIG. 9 shows scanning lines 55 from the (n−1) th stage to the (n + 1) th stage as an example.

  In each of the scanning signal voltages Vg (n−1) to Vg (n + 1), Vgh and Vgl are voltages that turn the switching element 51 on and off, respectively. A driving voltage for turning on the switching element 51 is applied to a certain scanning line 55, an image signal is written to the pixel electrode 59 through the switching element 51, charging of the pixel electrode 59 is completed after a certain period of time, and the scanning line When the driving voltage for turning OFF is applied to 55, the scanning signal voltage is similarly applied to the scanning line 55 at the next stage. In addition, a driving voltage for turning on each switching element 51 is applied to each scanning line 55 only once per frame. Thus, the scanning signal voltage is sequentially applied to each scanning line 55 from the upper stage.

  In the compensation voltages Vcs (n−1) to Vcs (n + 2), Veh, Vel, and Vec are the positive first compensation voltage, the negative second compensation voltage, and the first applied to the storage capacitor line 62, respectively. The third compensation voltage is an intermediate potential between the compensation voltage and the second compensation voltage.

  In each stage, the first compensation voltage Veh and the second compensation voltage Vel are applied to the storage capacitor line 62 corresponding to the scan line 55 and the scan line 55 before the drive voltage for turning on the switching element 51 is applied to the scan line 55. The voltage is alternately applied to another storage capacitor line 62 adjacent to 55. However, at this stage, since the switching element 51 is not conductive, the compensation voltage is not superimposed on the pixel electrode 59.

  After the period when the switching element 51 is turned on and the pixel electrode 59 is charged with a desired potential, the third compensation is applied to the storage capacitor line 62 connected to the pixel electrode 59 via the storage capacitor 52. Voltage Vec is applied. In this way, the potential difference when changing from the first compensation voltage Veh to the third compensation voltage Vec or the potential difference when changing from the second compensation voltage Vel to the third compensation voltage Vec is superimposed on the potential of the pixel electrode 59. The Further, the first compensation voltage Veh and the second compensation voltage Vel are switched and applied to the same scanning line 55 in synchronization with the polarity of the image signal voltage Vs that is inverted every frame for AC driving of the liquid crystal. The

  By applying the compensation voltage to the pixel electrode 59 in this way, the voltage drop caused by the parasitic capacitance 60 between the gate and the drain of the switching element 51 is eliminated, and the occurrence of the penetration voltage of the pixel electrode potential is prevented. Accordingly, even if the potential center of the image signal voltage Vs and the potential Vcom of the counter electrode are set to the same potential, flicker does not occur.

By driving each pixel, the liquid crystal applied voltage Vlc applied to the liquid crystal of each pixel when the switching element 51 is turned off is:
Vlc (+) = Vs-Vcom + [Cst × (Vec-Vel)-Cgd × (Vgh-Vgl)] / (Cst + Clc + Cgd)
Or
Vlc (-) = Vs-Vcom-[Cst × (Veh-Vec) + Cgd × (Vgh-Vgl)] / (Cst + Clc + Cgd)
Is calculated by

  Here, Cst is the capacitance value of the storage capacitor 52, Cgd is the capacitance value of the parasitic capacitance 60 existing between the gate and drain of the switching element 51, and Clc is the capacitance value of the liquid crystal layer 53. The liquid crystal applied voltage Vlc is two kinds of positive or negative voltage with respect to the polarity inversion of the image signal voltage Vs for each frame. Therefore, the positive side of the counter electrode voltage Vcom is defined as Vlc (+), and the negative side is defined as Vlc (−).

  Here, by setting the first compensation voltage Veh and the second compensation voltage Vel so that the effective values of Vlc (+) and Vlc (−) are equal, the liquid crystal can be AC driven. Further, when the third compensation voltage Vec is increased, the potential difference between the third compensation voltage Vec and the first compensation voltage Veh is reduced, and the potential difference between the third compensation voltage Vec and the second compensation voltage Vel can be adjusted. Therefore, the flicker is effectively removed by adjusting the value of the third compensation voltage Vec so that the DC component generated due to the parasitic capacitance 60 between the gate and drain of the switching element 1 can be removed. can do.

  Next, another form of the compensation voltage applied to the storage capacitor line 62 will be described with reference to the timing chart of FIG.

  In the timing chart showing the voltage waveforms in FIG. 10, for the compensation voltages Vcs (n−1) to Vcs (n + 2), Veh and Vel are the fourth positive compensation voltage applied to the storage capacitor line 62, respectively. This is a negative fifth compensation voltage. The scanning signal voltages Vg (n−1) to Vg (n + 2) are the same as those described with reference to FIG.

  In each stage, the fourth compensation voltage Veh and the fifth compensation voltage Vel are adjacent to the storage capacitor line 62 corresponding to the scanning line 55 and the scanning line 55 before the driving voltage for turning on the scanning line 55 is applied. The fourth compensation voltage Veh and the fifth compensation voltage Vel are applied alternately to the other storage capacitor line 62. However, at this stage, since the switching element 51 is not conductive, each compensation voltage is not superimposed on the pixel electrode 59.

  Then, after the drive voltage for turning on the scanning line 55 is applied, the switching element 51 is turned on, and the voltage of the image signal is written to the pixel electrode 59 to complete the charging of the desired potential, the pixel is The fourth compensation voltage Veh and the fifth compensation voltage Vel are switched and applied to the storage capacitor line 62 connected to the electrode 59 via the storage capacitor 52. In this way, the potential difference when changing from the fourth compensation voltage Veh to the fifth compensation voltage Vel or the potential difference when changing from the fifth compensation voltage Vel to the fourth compensation voltage Veh is superimposed on the potential of the pixel electrode 59. The Further, the fourth compensation voltage Veh and the fifth compensation voltage Vel are applied to the same scanning line 55 every frame in synchronization with the polarity of the image signal voltage Vs that is inverted every frame for AC driving of the liquid crystal. It is applied by switching.

  By applying the compensation voltage to the pixel electrode 59 in this way, the voltage drop caused by the parasitic capacitance 60 between the gate and the drain of the switching element 51 is eliminated, and the occurrence of the penetration voltage of the pixel electrode potential is prevented. Accordingly, even if the potential center of the image signal voltage Vs and the potential Vcom of the counter electrode are set to the same potential, flicker does not occur.

By driving each pixel as described above, the liquid crystal applied voltage Vlc applied to the liquid crystal of each pixel when the switching element 51 is turned off is:
Vlc (+) = Vs-Vcom + [Cst × (Veh-Vel)-Cgd × (Vgh-Vgl)] / (Cst + Clc + Cgd)
Or
Vlc (-) = Vs-Vcom-[Cst × (Veh-Vel) + Cgd × (Vgh-Vgl)] / (Cst + Clc + Cgd)
Is calculated by Here, the liquid crystal can be AC driven by setting the fourth compensation voltage Veh and the fifth compensation voltage Vel so that the effective values of Vlc (+) and Vlc (−) are equal.

  FIG. 11 is a diagram showing how the pixel electrode potential is shifted by the compensation voltage in the capacitive coupling driving method. As shown on the right side of FIG. 11, a positive compensation voltage is applied to the positive pixel electrode 59, and a negative compensation voltage is applied to the negative pixel electrode 59. By superimposing the compensation voltage on the potential of the pixel electrode 59 in this manner, as shown on the left side of FIG. 11, the positive pixel electrode potential is on the positive side and the negative pixel electrode potential is on the negative side. Shift to increase. Accordingly, there is an advantage that the liquid crystal can be AC driven with a low-amplitude image signal even when the potential of the counter electrode is constant.

  In addition, in the capacitive coupling drive method, when the display image changes, the overdrive voltage is automatically increased in the direction to amplify the change by the dynamic behavior of the capacitive coupling voltage due to the dielectric anisotropy of the liquid crystal material. It is applied to the electrode 59, so that high-speed response driving of the liquid crystal can be realized and the moving image visibility of the liquid crystal display device can be improved.

  By the way, with the progress of semiconductor process technology in recent years, it has become possible to form a driving circuit for a liquid crystal display device on the same glass substrate by using the same process for forming a switching element for driving a pixel.

  When the drive circuit of the liquid crystal display device is formed on the same glass substrate, for example, when the circuit is configured by only p-channel transistors, the storage capacitor line drive circuit 61 for realizing the capacitive coupling drive described in FIG. The configuration shown in FIG. 12 was taken.

  The transistor 71 a supplies the compensation voltage Veh to the storage capacitor line 62, and the transistor 71 b supplies the compensation voltage Vel to the storage capacitor line 62. The drain electrodes of the transistors 71a and 71b are connected to the output terminal 73 of the storage capacitor line drive circuit 61, and are connected to the storage capacitor lines 62 from the output terminal 73, respectively.

  Since each of the storage capacitor lines 62 is selectively supplied with either the compensation voltage Veh or the compensation voltage Vel, a signal having the same phase with inverted polarity is applied to the gate electrode of the transistor 71a and the gate electrode of the transistor 71b. Must be entered.

  In the example of FIG. 12, a transistor 71c and a transistor 71d constitute a load MOS inverter, and the inverter output is connected to the gate electrode of the transistor 71a. When the control signal input from the input terminal 72 of the storage capacitor line drive circuit 61 is at a high potential, the compensation voltage Veh is applied to the storage capacitor line 62, and when the control signal is at a low potential, the compensation voltage Vel is applied.

  However, when the liquid crystal display device has a large screen, the load capacity of the storage capacitor line increases, and if the conventional drive circuit is used as it is, the output waveform becomes dull and the response of the circuit becomes slow. In addition, as the display capacity of the liquid crystal display device increases, the number of scanning lines increases and at the same time the number of storage capacitor lines 62 increases, and the scanning time for turning on the scanning lines and the storage capacitor lines is shortened. With respect to the dull output waveform, there is a problem that the scanning period is short and sufficient driving cannot be performed.

  In particular, the above problem is remarkable in the fall time of the waveform of the compensation voltage Vcs shown in FIGS. In capacitive coupling driving, in order to superimpose a sufficient compensation voltage on the pixel electrode 59, it is necessary to set the compensation voltage Vel to a sufficiently low voltage.

  However, when the compensation voltage Vel is a low potential that is close to the low level of the logic operation of the circuit, the on-resistance of the output transistor 71b, which is a p-channel transistor, does not become a sufficiently low resistance. A time constant waveform rounding as shown in FIG. 13 is caused in the voltage waveform. When the waveform rounding is large, the voltage of the storage capacitor line 62 cannot be lowered to the compensation voltage Vel within the scanning period, and a sufficient compensation voltage is not superimposed on the pixel electrode 59. There was a risk of causing abnormal display.

  In order to improve the falling response of the output waveform, the W size of the output transistor 71b is designed to be large and the resistance value at the time of ON is reduced. Each time a transistor with a large size has to be arranged, the layout density on the array substrate is increased, and the frame of the liquid crystal display device has to be enlarged.

  Further, the conventional circuit configuration as shown in FIG. 12 has a problem of increasing power consumption because a current flows through the load MOS inverter when the compensation voltage Veh is output. In order to realize low power consumption without using an inverter, it is necessary to input two in-phase and non-inverted signals to the gate electrodes of the transistors 71a and 71b, which increases the number of signals. There was a problem.

Further, when the capacity of the transistor formed on the glass substrate is insufficient and it is not possible to cope with the charge / discharge of the load capacity of the storage capacitor line 62 to be driven, an IC formed on single crystal silicon having higher driving capacity is used. It has to be mounted on the outside of the glass substrate, leading to an increase in member costs and costs related to mounting.
JP-A 64-88496

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal display device that can apply a desired compensation voltage to a storage capacitor line at high speed.

  In order to achieve the above object, a liquid crystal display device according to a first aspect of the present invention includes a pixel driving switching element provided for each pixel at each intersection of a plurality of signal lines and a plurality of scanning lines. A pixel electrode and a storage capacitor connected to the switching element, a storage capacitor line provided corresponding to each scanning line and connected to the pixel electrode via the storage capacitor, and a compensation voltage applied to the storage capacitor line A storage capacitor line driving circuit for applying a voltage to the storage capacitor line driving circuit, wherein the storage capacitor line driving circuit includes a first transistor having a drain electrode and a gate electrode connected to a compensation voltage source, and the first transistor A second transistor having a source electrode connected to the gate electrode, a drain electrode connected to the compensation voltage source, and a source electrode connected to the storage capacitor line; Wherein the line is connected through the gate electrode and the capacitance of the second transistor.

  Improve the drive capability of the storage capacitor line drive circuit by enabling the desired compensation voltage to be applied to the storage capacitor line at high speed even when the screen size of the liquid crystal display device is increased or the display capacity is increased. In addition, the present invention has an effective effect that a low-power consumption, a narrow frame, a low-cost and high-quality liquid crystal display device can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

<< First Embodiment >>
First, a first embodiment will be described with reference to FIGS. The first embodiment relates to a capacitively coupled drive type liquid crystal display device in which the positive fourth compensation voltage Veh and the negative fifth compensation voltage Vel shown in FIG. 10 are applied to the storage capacitor line. Is.

  FIG. 1 shows the configuration of the storage capacitor line drive circuit 1a provided in the liquid crystal display device according to the first embodiment. The storage capacitor line drive circuit 1a includes transistors 2a, 2b, 2c, and a capacitor 3. The storage capacitor line drive circuit 1a receives a fourth compensation voltage Veh having a positive polarity and a fifth compensation voltage Vel having a negative polarity with respect to a storage capacitor line 14 to be described later. It is a circuit to switch and apply.

  The fifth compensation voltage Vel is applied to the drain and gate electrodes of the transistor 2a and the drain electrode of the transistor 2b. The source electrode of the transistor 2a is connected to the gate electrode of the transistor 2b and one electrode of the capacitor 3. When the transistor 2a is turned on, the fifth compensation voltage Vel is applied to the gate electrode and the capacitor 3 of the transistor 2b. Applied. The source electrode of the transistor 2b is connected to the output terminal 6. When the transistor 2b is turned on, the fifth compensation voltage Vel is applied to the output terminal 6.

  The fourth compensation voltage Veh is applied to the drain electrode of the transistor 2c. Further, the gate electrode of the transistor 2c is connected to the input terminal 5, the source electrode is connected to the output terminal 6, and the fourth compensation voltage Veh is applied to the output terminal 6 when the transistor 2c is turned on.

  The capacitor 3 is a capacitor formed between the output terminal 6 and the gate electrode of the transistor 2b. The capacitor 3 can be easily formed by a cross capacitor in which the source electrode and the gate electrode of the transistor 2b are crossed with an interlayer insulating film interposed therebetween. It can be formed on a glass substrate.

  A signal (voltage) inverted by a negative circuit is applied to the gate electrodes of the transistors 2a, 2b, and 2c.

  Next, FIG. 2 shows a configuration of a capacitively coupled driving type liquid crystal display device including the storage capacitor line driving circuit 1a. The drain terminal of the switching element 10 (n-channel MOS transistor) that drives the pixels of the liquid crystal display device is connected to one pixel electrode of the storage capacitor 11 and the liquid crystal layer 12, and the other pixel electrode of the liquid crystal layer 12 is common. Connected to the electrode wire 13.

  The other terminal of the storage capacitor 11 is connected to the storage capacitor line 14, and a voltage pulse (compensation voltage) for compensating the penetration voltage is applied by the storage capacitor line driving circuit 1a.

  The scanning line driving circuit 15 outputs a driving voltage for turning on the switching element 10 to the scanning line 16, and the signal line driving circuit 17 outputs a voltage corresponding to the image signal to the signal line 18.

  Next, the operation of the storage capacitor line driving circuit 1a shown in FIG. 1 will be described with reference to the timing chart of FIG.

  First, consider a case where the potential of the input terminal 5 changes from a low level potential to a high level potential. When the potential of the input terminal 5 is a low level potential, the transistor 2c is turned on, and the fourth compensation voltage Veh is output to the output terminal 6 of the storage capacitor line driving circuit 1. The transistor 2c is a p-channel pass transistor, and can charge the storage capacitor line 14 to the potential Veh with a sufficient response speed with almost no loss.

  Further, the transistor 2a charges the potential of the gate electrode of the transistor 2b to Vel + Vth, and the transistor 2b is turned off. Here, Vth is a threshold voltage of the transistor.

  Next, when the potential of the input terminal 5 changes from the low level potential to the high level potential, the transistor 2c is turned off, and the potential of the storage capacitor line 14 is gradually discharged toward the fifth compensation voltage Vel. Since the capacitor 3 is connected to the gate electrode of the transistor 2b, the transistor 2a is cut off, and the potential of the gate electrode of the transistor 2a decreases from Vel + Vth to (Vel + Vth) − (Veh−Vel), and the transistor 2b is sufficiently ON with a negative bias voltage. Finally, the voltage level of the output terminal 6 becomes Vel. In this way, the Vel output characteristic of the storage capacitor line driving circuit 1 is improved, and the fall time characteristic is further improved.

  As described above, according to the first embodiment, a desired compensation voltage can be applied to the storage capacitor line 14 at high speed, and the high-quality that can cope with an increase in screen size and an increase in display capacity of the liquid crystal display device. The liquid crystal display device can be realized.

  In addition, since no storage circuit is used in the storage capacitor line drive circuit 1a and no through current path is generated during operation, a liquid crystal display device with low power consumption can be realized without increasing the number of signal lines.

  Further, since the driving capability of the storage capacitor line driving circuit 1a can be improved, the capability necessary for driving the storage capacitor line 14 can be obtained even if the output transistor size is smaller than that of the conventional one. A display device can be realized.

  In addition, a drive circuit can be built in a large-screen liquid crystal display panel with a large load that conventionally requires the use of an external drive driver IC formed of single crystal silicon for driving, A low-cost and high-performance liquid crystal display device can be realized.

<< Second Embodiment >>
Next, a second embodiment will be described with reference to FIG. The same parts as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The second embodiment is a capacitively coupled drive in which the positive first compensation voltage Veh, the negative second compensation voltage Vel, and the intermediate third compensation voltage Vec shown in FIG. 9 are applied to the storage capacitor line. The present invention relates to a liquid crystal display device of the type.

  FIG. 4 shows the configuration of the storage capacitor line driving circuit 1b of the liquid crystal display device according to the second embodiment. The storage capacitor line drive circuit 1b includes transistors 2a, 2b, 2c, 2d, 2e, 2f, and a capacitor 3, and includes a first compensation voltage Veh, a second compensation voltage Vel, and a third compensation applied to the storage capacitor line. This is a circuit for selecting and switching the voltage Vec, and is applied to the liquid crystal display device shown in FIG.

  The second compensation voltage Vel is applied to the drain electrode and the gate electrode of the transistor 2a and the drain electrode of the transistor 2b via the transistor 2d, and the source electrode of the transistor 2a is the gate electrode of the transistor 2b and one electrode of the capacitor 3 And connected to. The source electrode of the transistor 2b and the source electrode of the transistor 2c are connected to the output terminal 6.

  The third compensation voltage Vec is applied to the drain electrode of the transistor 2 c, and the gate electrode is connected to the input terminal 5.

  The transistor 2d is a pass transistor in which the second compensation voltage Vel is applied to the drain electrode and the signal FR is applied to the gate electrode. When the transistor 2d is turned on, the second compensation voltage Vel is applied to the transistor 2a. The voltage is applied to the gate electrode and the drain electrode and the drain electrode of the transistor 2b. The transistor 2e is a pass transistor in which the first compensation voltage Veh is applied to the drain electrode and the signal FRB is applied to the gate electrode. When the transistor 2d is turned on, the first compensation voltage Veh is the transistor. Applied to 2f drain electrode.

  The signal FR and the signal FRB are signals in which the high level and the low level are switched for each frame. Therefore, the transistor 2d and the transistor 2e are alternately switched on and off for each frame.

  The transistor 2 f has a drain electrode connected to the source electrode of the transistor 2 e, a gate electrode connected to the input terminal 5, and a source electrode connected to the output terminal 6.

  The capacitor 3 is a capacitor formed between the output terminal 6 and the gate electrode of the transistor 2b.

  A signal (voltage) inverted by a negative circuit is applied to the gate electrodes of the transistors 2a, 2b, 2c, 2d, 2e, and 2f, respectively.

  Next, the operation of the storage capacitor line drive circuit 1b will be described.

  When the signal FR is at a low level and the signal FRB is at a high level in a certain frame, the circuit configuration of FIG. 4 is equivalent to the circuit configuration of FIG. 1, and is the same as described in the first embodiment. The Vel output characteristic of the storage capacitor line driving circuit is improved.

  In the next frame, when the signal FR changes to the high level and the signal FRB changes to the low level, and the input terminal 5 is at the high level, the first compensation voltage Veh is selected.

  As described above, according to the second embodiment, it is possible to realize the storage capacitor line drive circuit 1b that can alternately apply the compensation voltages Veh and Vel to the storage capacitor line for each frame. Therefore, it is possible to obtain the same effect as the case of using the capacitive coupling driving method in which only the fourth compensation voltage and the fifth compensation voltage described in the first embodiment are applied to the storage capacitor line.

  Further, the first compensation voltage and the second compensation voltage may be applied to the storage capacitor line only by the storage capacitor line corresponding to the scanning line being scanned, and the power consumption of the compensation voltage shift register can be reduced.

  In the present invention, an embodiment in which a p-channel transistor is used for the storage capacitor line driving circuit 1 has been described. However, even if an n-channel transistor is used, the effect of the present invention is the same.

1 is a circuit diagram showing a configuration of a storage capacitor line drive circuit in a first embodiment. FIG. It is a circuit diagram which shows the structure of the liquid crystal display device by a capacitive coupling drive system. It is a drive voltage waveform diagram of the storage capacitor line drive circuit in the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a storage capacitor line driving circuit according to a second embodiment. It is a circuit diagram which shows the structure of the conventional liquid crystal display device. It is an electrical equivalent circuit diagram of the conventional display element. It is a figure which shows the drive waveform in the conventional liquid crystal display device. It is a circuit diagram which shows the structure of the liquid crystal display device by the conventional capacitive coupling drive system. 10 is a timing chart showing voltage waveforms in a scanning line and a storage capacitor line in capacitive coupling driving in which a first compensation voltage, a second compensation voltage, and a third compensation voltage are applied to the storage capacitor line. It is a timing chart which shows the voltage waveform in a scanning line and a storage capacity line in capacitive coupling drive of the form which applies the 4th compensation voltage and the 5th compensation voltage to a storage capacity line. It is a figure for demonstrating the potential shift of the pixel electrode by a capacitive coupling drive system. It is a circuit diagram which shows the structure of the conventional storage capacity line drive circuit. It is a figure which shows the output voltage waveform rounding of the conventional storage capacity line drive circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, b Storage capacity line drive circuit 2a, b, c, d, e, f Transistor 3 Storage capacity 5 Input terminal of storage capacity line drive circuit 6 Output terminal of storage capacity line drive circuit 11 Storage capacity 12 Liquid crystal layer 13 Common electrode Line 14 Storage capacitor line 15 Scan line drive circuit 16 Scan line 17 Signal line drive circuit 18 Signal line 51 Switching element 52 Storage capacitor 53 Liquid crystal layer 54 Signal line 55 Scan line 56 Common electrode line 57 Scan line drive circuit 58 Signal line drive circuit 59 Pixel electrode 60 Gate-drain parasitic capacitance Cgd
61 storage capacitor line drive circuit 71a, b, c, d transistor 72 input terminal of storage capacitor line drive circuit 73 output terminal of storage capacitor line drive circuit A scanning signal Vg
B Image signal Vs
C Pixel electrode potential D Penetration voltage ΔV
E Center value of pixel signal Vsigc

Claims (1)

A switching element for driving a pixel provided for each pixel at each intersection of a plurality of signal lines and a plurality of scanning lines, a pixel electrode connected to the switching element and a storage capacitor, and provided corresponding to each scanning line A storage capacitor line connected to the pixel electrode via the storage capacitor, and a storage capacitor line driving circuit for applying a compensation voltage to the storage capacitor line,
The storage capacitor line driving circuit includes:
A first transistor having a drain electrode and a gate electrode connected to a compensation voltage source;
A second transistor having a source electrode connected to the gate electrode, a drain electrode connected to the compensation voltage source, and a source electrode connected to the storage capacitor line;
Have
The liquid crystal display device, wherein the storage capacitor line is connected to the gate electrode of the second transistor through a capacitor.

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