JP2003203017A - Data processing device that can continue processing with backup data - Google Patents

Abstract

(57) [Summary] [PROBLEMS] Even if a failure occurs in a storage device,
Provided is a processing device capable of continuing the processing without stopping the processing. SOLUTION: After writing data to a flash memory 41 (S1), an SLT 2 transmits the data to an element manager 1 connected by a communication line 5, and the element manager 1 stores the data in a storage device 11 (S2). ). After reading data from the flash memory 41 (S3), the SLT 2 performs a parity check (S3).
4). When a parity error is detected (YE in S5)
S), the SLT 2 transmits a data transmission request to the element manager 1 (S6), and receives from the element manager 1 the same data as the data in which the parity error is detected (S7). After that, the SLT 2 continues the processing based on the received data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, a data storing method, and a data reading method, which can continue processing without stopping even if a failure occurs in a storage device.

[0002]

2. Description of the Related Art In a processing device in which a program stored in a memory, for example, a flash memory is executed by a CPU, the processing device hangs (runaway) due to an error in data (a program instruction or the like) caused by a failure of the flash memory. I have something to do. Therefore, in order to prevent such a hang-up, processing such as stopping the CPU is performed when a failure in the flash memory is detected.

For example, an asynchronous transfer mode (ATM: As)
Subscriber Line Terminal (SLT) that performs communication in the Synchronous Transfer Mode
Stores in the flash memory a backup of operation information relating to the monitoring control of the device and an application program of the CPU (for example, an application program for receiving control from a remote device).

When a failure occurs in this flash memory, the CPU executing the SLT process stops the process. Then, after the flash memory is replaced and the failure is recovered, the processing is restarted.

[0005]

However, if the CPU, that is, the SLT, suspends the processing until the failure is recovered,
The monitoring function stops, and in some cases, the operating / non-operating side of user data (main signal) cannot be switched, which may cause a fatal failure such as a line disconnection.

Further, the SLT cannot be controlled from the remote device, which causes a trouble that the operator cannot see the state of the SLT.

The present invention has been made in view of such a situation, and an object thereof is to provide a processing device which executes processing based on data stored in a storage device (memory), in which the storage device has a failure. Even if it occurs, it is to provide a processing device that can continue its processing without stopping it.

[0008]

In order to achieve the above object, the data processing device according to the first aspect of the present invention is connected to an external data storage device via a communication line, and a predetermined data is stored. A data processing device for performing processing, comprising: storage means for storing data; writing means for writing the data in the storage means; and writing the data before or after writing the data to the storage means by the writing means. Transmission means for transmitting data to the external data storage device via the communication line.

In the data storage method according to the first aspect of the present invention, before or after writing the data in the storage means for storing the data, the data is stored in an external data storage connected via a communication line. When a failure is detected in the storage means, the data is received from the external data storage device via the communication line.

Further, a program according to the first aspect of the present invention causes a computer to execute the data storage method.

According to the first aspect of the present invention, the data is transmitted to the external data storage device via the communication line before or after the data is written to the storage means. The transmitted data is stored in the external data storage device. Therefore, even when a failure occurs in the storage means and the data stored in the storage means cannot be read out correctly or the data cannot be written correctly in the storage means, the data processing device stores the data from the external storage device. Can be received, and processing can be executed according to the received data. As a result, even if a failure occurs in the storage means, the processing can be continued without stopping.

The data processing device according to the second aspect of the present invention is connected via a communication line to an external data storage device in which backup data is stored in advance,
A data processing device for performing a predetermined process on data, comprising storage means for storing the data, and inspection means for inspecting the storage means for a failure when reading the data stored in the storage means. Receiving means for receiving backup data of the read data from the external data storage device via the communication line when a failure is detected by the inspection means.

In the data reading method according to the second aspect of the present invention, an external data storage device in which backup data is stored in advance is connected via a communication line, and a predetermined process is performed on the data. A method of performing data reading of a data processing device, comprising: checking the presence or absence of a failure in the storage means when reading the data stored in the storage means for storing the data; Data for data backup is received from the external data storage device via the communication line.

According to the second aspect of the present invention, when the data stored in the storage means is read, the presence or absence of a failure in the storage means is inspected, and if a failure is detected, backup data for the read data is obtained. Is received from an external data storage device via a communication line. Therefore, the device that receives this data can execute processing according to the received data. Therefore, even if a failure occurs in the storage means, the processing can be continued without stopping.

[0015]

1 is a block diagram showing the configuration of a communication system according to an embodiment of the present invention. This communication system includes an element manager 1, subscriber line terminals (SLT) 2 ₁ and 2 ₂ , and an optical line terminal device (OLT).
ination) 3 _{1 to} 3 ₄ and user terminals 4 ₁ to 4 ₈ .

This communication system includes user terminals 4 ₁ to 4 ₈
Is a data exchange network for switching (exchanging) end user data (user's voice, text data, image data, etc., hereinafter referred to as "user data") that uses.

Here, as an example, two SLTs 2 ₁
Although 2 and ₂ are shown, the number of SLTs may be one or three or more. In addition, OLT is also SL
Although two are shown for each T, other numbers may be used. Further, user terminals other than the number shown may be provided. In the following, "SLT2" will be used unless it is necessary to distinguish between SLT2 ₁ and 2 _2.
Collectively. Similarly, the OLTs 3 _{1 to} 3 ₄ are collectively referred to as the OLT 3, and the user terminals 4 ₁ to 4 ₈ are collectively referred to as the user terminal 4.

The element manager 1 and the SLT 2 are connected by a communication network (eg LAN such as Ethernet (registered trademark)) 5. The element manager 1 and the SLT 2 have identification information (for example, IP address) in the communication network 5, and communicate with each other based on this identification information.

Between SLT2s, and between SLT2 and O
An optical fiber cable is used to connect to LT3,
Between these, asynchronous transfer mode (ATM: Asynchro
data is communicated by nousTransfer Mode). OL
Between T3 and the user terminal 4, depending on the user terminal 4,
It is connected by an optical fiber cable or an electric line, and data is communicated between these by ATM, IP packet or the like according to the user terminal.

The element manager 1 is composed of a computer, a workstation and the like. The element manager 1 sends a program (for example, firmware) required for the SLT 2 to the SLT 2 via the communication network 5
Via SLT2 as described below.
Data such as programs and monitoring information transmitted from the computer via the communication network 5 from a storage device (hard disk,
It is stored in the optical disk, semiconductor memory, etc.) 11 for backup. Then, when a failure occurs in the internal memory of the SLT 2 and the SLT 2 cannot use the data stored in the memory, the element manager 1
The data stored in the storage device 11 for backup is transmitted to the SLT 2.

The user terminal 4 is a terminal used by the end user and is, for example, a telephone, a personal computer or the like. The user terminal 4 transmits the user data to the OLT 3. OL
T3 is the user terminal 4 or SLT2 connected to itself
User data from another user terminal 4 or SLT2
Switch (replace) to. The SLT 2 exchanges the user data transmitted from the user terminal 4 via the OLT 3 with another OLT 3 or another SLT 2.

FIG. 2 is a block diagram showing the detailed structure of the SLT 2. The SLT 2 includes the monitoring device 21 and the switch 2
2, and interface devices 23 to 25.

The interface device 23 is connected to another SLT 2 and the interface devices 24 and 25 are OLTs.
3 is connected. The interface devices 23 to 25 perform mutual conversion of electric signals and optical signals, processing of layer 1 (and 2) communication protocols, and the like. Interface device 23
Two to 25 are provided respectively, and when a failure occurs in one of them, it is switched by the monitoring device 21 and the other is used.

The switch 22 is an interface device 24.
Alternatively, the user data input from the OLT 3 via 25 and the user data input from the other SLT 2 via the interface device 23 are switched, and these user data are output to the other interface device.

The monitoring device 21 monitors the states of the switch 22 and the interface devices 23-24 and switches the interface devices 23-25. FIG. 3 is a block diagram showing a detailed configuration of the monitoring device 21. FIG. 4 is a block diagram showing a detailed configuration of the flash memory unit 36 of the monitoring device 21.

The monitoring device 21 is a LAN (Local Area Net).
work) port 31, CPU 32, boot ROM 33, management information storage EEPROM 34, work SDRAM 3
5, and a flash memory unit 36. The flash memory unit 36 includes four flash memories 41a to 41d and four parity check circuits 42a.
˜42d, and registers 43 and 44.

CPU 32, LAN port 31, boot ROM 33, management information storage EEPROM 34, work SDRAM 35, and flash memory unit 3
6 is a bus (including an address bus and a data bus)
Are connected to each other by.

The LAN port 31 is an interface device for communicating with the element manager 1 via the Internet 5, and mainly executes the processing of communication protocols of layers 1 and 2.

The boot ROM 33 stores a boot program that is started when the SLT 2 (monitoring device 21) is started up. The management information storage EEPROM 34 stores management information such as identification information (IP address, MAC address) of the SLT 2. SDRAM3 for work
Reference numeral 5 denotes a memory used as a work area of the CPU 32, in which a program stored in the flash memory unit 36, data generated by the processing of the CPU 32, and the like are temporarily stored.

The flash memory unit 36 has an SL
Operational information for backup of T2, application programs (firmware), etc. are stored. A plurality of types of application programs may be provided. In this case, the flash memory unit 36 may be provided according to the number of types of application programs.

The flash memories 41a to 41d of the flash memory unit 36 are flash memories having the same structure. Each memory cell of each of the flash memories 41a to 41d has 9 bits as an example.
Data (commands of application programs, operation information, etc.) is stored in 8 bits out of 9 bits, and a parity check bit for 8 bits of data is stored in the remaining 1 bit.

When writing data to the flash memories 41a to 41d, the CPU 32 has an address designating a memory cell to which the data is to be written and data to be written (and a write signal by a signal line (not shown)).
Is output to the flash memories 41a to 41d. The address is simultaneously given to the flash memories 41a to 41d. The data to write is 32 bits.
The 2-bit data is divided into four 8-bit data from the 1st bit to the 32nd bit, and each 8-bit data is given to the flash memories 41a to 41d and stored in the memory cell indicated by the address.

At the time of writing this data, each 8-bit data is also given to the parity check circuits 42a to 42d. The parity check circuits 42a to 42d generate parity bits of each 8-bit data, and the parity bits are used to represent the flash memories 41a to 41d.
The 9th bit of each memory cell 41d is written. The parity bit may be odd parity or even parity.

On the other hand, when reading data from the flash memories 41a to 41d, the CPU 32 sends an address (and a read signal by a signal line (not shown)) designating a memory cell to which data is read.
1a to 41d. Flash memory 41a-4
1d outputs 8-bit data from the memory cell specified by the address. This makes a total of 3
2-bit data is read and given to the CPU 32.

At the time of reading this data, in addition to each 8-bit data from the flash memories 41a to 41d, a parity check bit corresponding to each 8-bit data is generated.
It is given from the flash memories 41a to 41d to the parity check circuits 42a to 42d, respectively.

The parity check circuits 42a to 42d are
A parity check is performed by collating the 8-bit data and the parity check bit provided from each of the flash memories 41a to 41d, and the check result is output to the register 43. The check result is, for example, 1-bit data "1" when a parity error occurs, and 1-bit data "0" when normal (when no parity error occurs).

Register 43 has, for example, 4 bits. Each bit corresponds to the parity check circuits 42a to 42d, and the parity check circuits 42a to 42d, respectively.
Memorize the check result of. Therefore, the flash memory 41 depends on which of the 4 bits is "1".
It is possible to determine which of a-41d is causing the parity error.

The check result stored in the register 43 is read by the CPU 32, and the presence or absence of a parity error is determined by the CPU 32.

The register 44 has, for example, 4 bits,
Each bit stores the presence / absence of output of a busy signal from each of the flash memories 41a to 41d. This busy signal is a signal output from the flash memories 41a to 41d for a predetermined time after writing the data in the flash memories 41a to 41d or erasing the data stored in the flash memories 41a to 41d. Is. While this busy signal is being output, data cannot be written or erased, and even when reading data, the data value is in a toggle state (described later) and is constant during the busy signal output. Since it does not exist, accurate data cannot be read.

The predetermined time for outputting the busy signal is predetermined according to the type of memory circuit (for example, semiconductor chip) used for the flash memories 41a to 41d. Further, the time when the busy signal is output after writing the data and the time when the busy signal is output after erasing the data may be the same or different. In the following, the time when the busy signal is output after erasing data is T1, and the time when the busy signal is output after writing data is T2.

When writing data to the flash memory 41, the data is first written after the data in the memory cell at the address where the data is written is erased.

While the busy signal is being output, the corresponding bit of the register 44 is set to "1", and when the output of the busy signal is stopped, the bit is set to "0".

The 4-bit data stored in the register 44 is read by the CPU 32. CPU32
Measures time T2 after writing the data, for example, with a watchdog timer, and registers register 44 even after the time T2 elapses.
When the value of the bit of "1" is "1", it can be determined that a failure has occurred in the flash memory corresponding to the bit.

Similarly, the CPU 32 measures the time T1 after erasing the data and registers the register 44 even after the time T1 has elapsed.
When the value of the bit of "1" is "1", it can be determined that a failure has occurred in the flash memory corresponding to the bit.

Some flash memories do not have a busy signal output terminal. In this case, the presence or absence of a fault is checked by polling. That is, the CPU 32
Reads the written data at a predetermined time interval after writing the data. During time T2 after writing data,
At least one bit of the read data is in a toggle state in which "0" and "1" are alternately repeated. On the other hand, after the lapse of time T2, if the flash memory is normal, the toggle state is canceled and the written data can be read correctly. When a failure occurs in the flash memory, the toggle state is not resolved and the written data cannot be read correctly.

Therefore, the CPU 32 determines by polling whether the flash memory is in the toggle state or not even after the elapse of the time T2, thereby determining whether the flash memory is normal or has a failure. be able to.

Even after erasing the data, the presence or absence of the failure of the flash memory can be determined by similarly detecting the presence or absence of the toggle state after the lapse of time T1 by polling.

In the communication system having such a configuration,
The flash memories 41a to 41d of the SLT 2 (hereinafter, referred to as "flash memory 4 unless otherwise particularly distinguished.
1 ”. ) In case of failure, C
C for continuing the process without stopping the PU 32
The processing of the PU 32 (SLT2) will be described below.
There are several methods for this processing, so they will be described separately below.

(1) First Method The first method is to receive, from the element manager 1, a portion of data in which a parity error has occurred. FIG. 5 is a flowchart showing the flow of processing according to the first method.

In step S2, the CPU 32 uses, for example, the boot program stored in the boot ROM 33, or the flash memory 41 or the work SDRAM.
This is a process executed when writing data to the flash memory 41 during execution of the application program stored in 35.

When data (for example, monitoring information) is written to the flash memory 41 during execution of the boot program or application program (S
1), the CPU 32, after writing the data to the flash memory 41, transmits the same data to the element manager 1 via the LAN port 31 as a packet (S2).

FIG. 6 shows the data structure of the packet (payload section) transmitted from the SLT 2 to the element manager 1. This packet is, for example, an IP packet, and in FIG. 6, the header portion of the packet is omitted and only the payload portion is shown. The payload portion of the packet includes SLT identification information, flash memory identification information, address, and data.

The "SLT identification information" is the identification information (for example, IP address) of the SLT 2 that transmits the data.

The "flash memory identification information" is information for identifying the flash memory in units of memory circuits (semiconductor chips). For example, in the configuration shown in FIG.
Information for identifying each of the flash memories 41a to 41d becomes flash memory identification information. Further, as described above, when a plurality of flash memory units 36 are provided according to the type of application program, the identification information of each flash memory unit 36 and the identification information of each memory circuit unit inside the flash memory unit 36 are used. is there.

The "address" is the address of the flash memory 41 in which the data is written, and the "data" is the data written in the flash memory 41.

When the packet transmitted from SLT2 is an IP packet, the IP address of SLT2 as the transmission source is included in the header part of the IP packet, and in this case, the "SLT identification information" can be omitted. .

The element manager 1 stores the packet transmitted from the SLT 2 in its own storage device 11.
The data structure stored in the storage device 11 of the element manager 1 is also the same as the data structure of the payload part of the packet shown in FIG.

In this way, the same data as the data written in the flash memory 41 by the CPU 32 is saved in the element manager 1 for backup, and the element manager 1 has the same data as the data stored in the flash memory 41. Have. Note that step S2 may be executed before step S1.

On the other hand, in steps S4 to S7, the CPU 32
Is a process executed when writing data to the flash memory 41 during execution of a boot program or an application program.

When data is read to the flash memory 41 during execution of the boot program or the application program (S3), the CPU 32 reads the data from the flash memory 41 and then reads the contents of the register 43 (S4). . The parity check result of the data read by the CPU 32 is stored in the register 43 by the parity check circuits 42a to 42d.

Subsequently, the CPU 32 determines whether or not a parity error has occurred based on the value of the register 43 (S5). If a parity error has occurred (for example, if at least one of the 4 bits is "1") (YES in S5), the CPU 32 sends a data transmission request for the address in which the parity error has occurred to the packet. Send to element manager 1 (S
6).

This data transmission request packet includes "SLT identification information", "flash memory identification information", and "address" in the payload portion, as in the packet shown in FIG. 6, and the "data" portion. Contains information indicating a data transmission request.

Upon receiving the data transmission request from the SLT 2, the element manager 1 reads the data corresponding to the SLT identification information, the flash memory identification information and the address included in the data transmission request from the storage device 11, and reads the read data. , S that sent the data transmission request
Reply to LT2. As a result, the same data as the data in which the parity error is detected will be the element manager 1
To SLT2.

When the CPU 32 of the SLT 2 receives the returned data, it sends this data to, for example, the work SDR.
It is stored in the AM 35, and thereafter, the processing of the program is continued based on the returned data.

On the other hand, if no parity error has occurred in step S5 (NO in S5), the CPU 3
2 continues the processing of the program based on the read data.

As described above, according to the first method, the CPU 32 saves the data saved for backup in the element manager 1 even if the flash memory 41 fails and accurate data cannot be read. By using it, it is possible to continue executing the program without stopping its operation.

The data received from the element manager 1 in step S7 is the four flash memories 4
It may be 32-bit data read simultaneously from 1a to 41d, or may be 8-bit data (or 16-bit, 24-bit data) portion in which a parity error is detected in the 32-bit data.

The processing of steps S2 and S4 to S7 may be described as program instructions in the boot program or application program, or interrupt the CPU 32 when writing or reading data to or from the flash memory 41. When it is configured so that the above occurs, it may be described as a program for this interrupt processing.

Furthermore, the data stored in the flash memory 41 (for example, application program)
However, if the data is downloaded from the element manager 1, the data is stored in the storage device 11 of the element manager 1 in advance, and therefore, in step S2 executed when writing the data to the flash memory 41. The processing can be omitted.

(2) Second Method In the second method, the transmission of an alarm is added to the first method.

In step S5 of the first method (see FIG. 5), if a parity error occurs, the CPU 32
Sends an alarm to the element manager 1. This alarm can be transmitted together with the data transmission request in step S6, or separately from the data transmission request.
It can also be transmitted before or after the data transmission request.
When sending an alarm with a data transmission request,
Information indicating an alarm is added to the rear part of the data shown in FIG.

Element manager 1 receiving the alarm
Displays an alarm on a display device (CRT display, liquid crystal display, etc.) or stores it in a storage device. As a result, it is possible to notify the operator, administrator, etc. of the element manager 1 that the flash memory 41 needs to be replaced.

Further, the displayed or stored alarm can include the flash memory identification information in which the parity error is detected and the address (for example, 0x100 address) of the flash memory. By this,
You can easily identify the flash memory where the failure is detected,
The time required for repairs and maintenance can be shortened.

When the element manager 1 receives a data transmission request from the SLT 2 without the SLT 2 transmitting such an alarm, the element manager 1 automatically displays / outputs / stores an alarm upon receipt of the data transmission request. You can also do it.

(3) Third Method The third method is SL when a parity error occurs.
T2 receives data from the element manager 1 in units of segments of the flash memory 41 or in units of memory circuits (semiconductor chips) and stores the data in the work SDRAM 35.

A segment is a unit in which a plurality of continuous memory cells of one memory circuit (semiconductor chip) of the flash memory 41 are united. For example, the segment is set in various units such as 1 Kbyte unit and 16 Kbyte unit.

The third method is almost the same as the reading process (S3 to S7) in FIG. 5, but when the data transmission request is transmitted to the element manager 1 in step S6, the element manager 1 will request this data transmission request. All data of the segment or memory circuit including the address contained in SLT2 is transmitted to SLT2.

When the CPU 32 of the SLT 2 receives the data transmitted from the element manager 1, the CPU 32 stores this data in the work SDRAM 35, and thereafter continues the processing of the program.

Subsequent reading / writing of data from the address corresponding to the flash memory 2 is performed by the work SD.
The reading / writing of data from the RAM 35 is performed.

By thus receiving data from the element manager 1 in segment units or memory circuit units, even if a failure (parity error) is detected in different addresses of the same flash memory 41, a data transmission request is issued. And the transmission of the data corresponding to the request from the element manager 1 is omitted. As a result, immediately after the parity error is detected, the communication network 5
Traffic volume temporarily increases, but SLT2
The number of data transmission / reception between the element manager 1 and the element manager 1 decreases. As a result, it is possible to improve the communication quality of the communication network 5 except immediately after the parity error is detected.

(4) Fourth method Data (application program etc.) is stored in advance in the flash memory 41 at the time of factory shipment, and SL
When this data is used when T2 is started up (when power is turned on, at reset, when power is restored after a momentary power failure, etc.) (the data (such as an application program) stored in the flash memory 41 is copied to the work SDRAM 35). (Including the processing to be expanded), the flash memory 4
When a failure is detected in No. 1, all of the data stored in the flash memory 41 may be downloaded from the element manager 1 to the work SDRAM 35 of the SLT 2 and the SLT 2 startup processing may be performed by the downloaded data. it can.

In this case, the same data as the data stored in the flash memory 41 is stored in the storage device 11 of the element manager 1 in advance. In addition, a process of downloading all the data stored in the flash memory 41 from the element manager 1 is incorporated in the boot program when the SLT 2 is started up.

In this download process, the process shown in FIG.
In the read process of step S6, the transmission request in step S6 becomes a transmission request for all data in the flash memory 41, and the data reception in step S7 becomes reception of all data in the flash memory 41.

As a result, the SLT 2 can be started up without stopping the CPU 32 even if a failure occurs in the flash memory 41 after the power is turned on, recovery from a momentary power failure, reset, etc. Operations after startup can also be performed.

(5) Fifth Method The fifth method is a method of detecting a failure in writing data in the flash memory 41 and a coping method when the failure is detected.

FIG. 7 is a flowchart showing the flow of processing when writing data to the flash memory 41.
When writing data to the flash memory 41, the data at the write location is erased before writing. Therefore, first, the CPU 32 erases the data in the memory cell (each memory cell of the four flash memories 41a to 41d) into which the data (32-bit data) in the flash memory 41 is written (S11).

Subsequently, the CPU 32 reads the value of the register 43 after a lapse of a predetermined time T1 after erasing (S1
2). When at least one value of 4 bits of the register 43 is "1", the CPU 32 determines that a failure has occurred in the flash memory 41 (YE in S13).
S), writing of data in the flash memory 41 is stopped, and the data (32-bit data) is transmitted to the element manager 1 (S18). The transmission is performed by the packet shown in FIG.

The element manager 1 stores the received packet in the storage device 11. After that, when the CPU 32 uses this data, the element manager 1
Then, the data is received and used (S19).

On the other hand, when the value of the register 43 is 0 (NO in S13), the CPU 32 causes the flash memory 4
Write data (32-bit data) to 1 (S1
4).

Subsequently, the CPU 32 reads the value of the register 43 after a lapse of a predetermined time T2 after writing (S1
2). When at least one of the 4 bits of the register 43 is "1", the CPU 32 determines that a failure has occurred in the flash memory 41 (YE in S13).
S), the same data as the data written in step S14 is sent to the element manager 1 by the packet shown in FIG.
(S18). Thereafter, the above-mentioned step S19
While the processing of step S16 is executed, the register 4
When the value of 3 is 0 (NO in S16), the CPU 32
Judges that the flash memory 41 has not failed, and therefore the data written in the flash memory 41 is effectively stored in the flash memory 41, and then the written data is stored in the flash memory 4
Read from 1 (S17).

As a result, even if a failure is detected at the time of erasing / writing data in the flash memory 41, the failure can be dealt with without stopping the processing of the SLT 2.

In the same manner as the second method described above,
When a failure is detected at the time of erasing and / or writing, the CPU 32 can also send to the element manager 1 an alarm indicating that a failure has been detected in the flash memory 41.

(6) Other Embodiments A spare flash memory unit having the same structure as the flash memory unit 36 can be provided in the monitoring device 21.

In this case, data may be written in the flash memory of the spare flash memory unit instead of or in addition to the processing of step S2 (see FIG. 5) of the first method described above. it can. Then, instead of the processing of steps S6 and S7,
Data may be read from the flash memory of the spare flash memory unit.

Similarly, in the third method, it is also possible to store data in the spare flash memory unit and read the data from the spare flash memory unit in segment units or memory circuit units.

Also in the fourth method, data such as the application program is stored in the flash memory of the spare flash memory unit, and when a failure is detected in the flash memory 41, the spare flash memory is used. Data can also be read from the unit. In the fourth method, the flash memory 41
When the data is downloaded from the element manager 1 when the failure is detected, the downloaded data can be stored in the flash memory of the spare flash memory unit instead of the work SDRAM.

Further, also in the fifth method, when a failure is detected in the flash memory 41 after erasing or writing, the data is stored in the flash memory of the spare flash memory unit instead of the element manager 1 and then ， Data can also be read from this spare flash memory and used.

When a plurality of flash memory units 36 are provided according to the type of application program, a spare flash memory unit (same capacity as the flash memory) is provided for each of the plurality of flash memory units 36. Can be provided, and one can be provided for a plurality of flash memory units 36.
It is also possible to provide one shared spare flash memory unit. Then, when a failure is detected in any of the plurality of flash memory units 36, data can be stored in this spare flash memory unit.

Furthermore, by providing a plurality of spare flash memory units, when a failure is detected in one spare flash memory unit, data can be stored in another spare flash memory.

(Supplementary Note 1) A data processing device which is connected to an external data storage device through a communication line and performs a predetermined process on data, and which stores the data in the storage means and the storage means. A writing means for writing data, and a transmitting means for transmitting the data to the external data storage device via the communication line before or after writing the data to the storage means by the writing means. Data processing device.

(Supplementary Note 2) In Supplementary Note 1, after writing data in the storage means by the writing means,
It further comprises a first inspection means for inspecting the presence or absence of a failure in the storage means, and the transmission means transmits the data to the external data storage device when a failure is detected by the first inspection means. , Data processing equipment.

(Supplementary Note 3) A data processing device for performing a predetermined process on data, comprising storage means for storing data, auxiliary storage means for storing the data, and writing for writing the data in the storage means. A data processing device comprising: means and auxiliary writing means for writing the data to the auxiliary storage means before or after writing the data to the storage means by the writing means.

(Supplementary Note 4) In Supplementary Note 3, after writing data in the storage means by the writing means,
A first inspection means for inspecting the presence or absence of a failure in the storage means, wherein the auxiliary writing means writes the data in the auxiliary storage means when a failure is detected by the first inspection means; Processing equipment.

(Supplementary Note 5) In Supplementary Note 2 or 4, the storage means is a flash memory, and the first inspection means outputs the data from the flash memory for a predetermined time after writing the data in the flash memory. A data processing device that determines that there is a failure in the flash memory when a busy signal is output for more than the predetermined time.

(Supplementary Note 6) In Supplementary Note 2 or 4, the storage means is a flash memory, and the first inspection means writes the data in the flash memory and then writes the data from the flash memory in a predetermined manner. A data processing device that reads at a time interval, and determines that the flash memory has a failure when the read data changes every time the data is read over a predetermined time.

(Supplementary Note 7) In Supplementary Note 1 or 2, before the data is written into the storage means, an erasing means for erasing at least the data in the storage location of the storage means for storing the data, and the erasing means Second erasing means for inspecting the presence or absence of a fault in the storage means after erasing,
The data processing device, further comprising: a transmission unit that transmits the data to the external data storage device when a failure is detected by the second inspection unit.

(Supplementary Note 8) In Supplementary Note 3 or 4, before writing data in the storage means, erasing means for erasing data in at least a storage location of the storage means for storing the data, Second erasing means for inspecting the presence or absence of a fault in the storage means after erasing,
The data processing device, further comprising: an auxiliary writing unit that writes the data to the auxiliary storage unit when a failure is detected by the second inspection unit.

(Supplementary Note 9) In Supplementary Note 7 or 8, the storage means is a flash memory, and the second inspection means erases the data in the flash memory by the erasing means, and then deletes a predetermined data from the flash memory. A data processing device, which judges that the flash memory has a failure when a busy signal output for a time is output for longer than the predetermined time.

(Supplementary Note 10) In Supplementary Note 7 or 8,
The storage means is a flash memory, and the second inspection means erases the data in the flash memory by the erasing means and then reads the data from the flash memory at a predetermined time interval. If the flash memory changes every time it is read out, it is determined that the flash memory has a failure.
Data processing device.

(Supplementary Note 11) In Supplementary Notes 1, 2, or 7, the external data storage device previously stores the same data as the data stored in the storage means, and the data is read from the storage means. At this time, a third inspection means for inspecting the presence or absence of a failure in the storage means, and when the failure is detected by the third inspection means, the same data as the read data is transmitted via the communication line. A data processing device, further comprising: a receiving unit for receiving from the external data storage device.

(Supplementary Note 12) In Supplementary Note 11, the storage means is a flash memory, and the third checking means performs a parity check on the data read from the flash memory. A data processing device that determines that there is a failure in the flash memory.

(Supplementary Note 13) The data processing apparatus according to Supplementary Note 11 or 12, further comprising auxiliary storage means for storing the data received by the data receiving means.

(Supplementary Note 14) In Supplementary Notes 2, 7, 11, 12 or 13, the data storage device is notified that a failure has been detected in the storage means before or after the transmission of the data by the transmission means or at the same time. A data processing device, further comprising:

(Supplementary Note 15) A data processing device that is connected to an external data storage device in which backup data is stored in advance through a communication line and performs a predetermined process on the data, and stores the data. And a storage means for performing the reading of the data stored in the storage means,
An inspection unit that inspects the storage unit for a failure, and when the inspection unit detects a failure, receives backup data of the read data from the external data storage device via the communication line. A data processing device comprising a receiving means.

(Supplementary Note 16) Before or after writing data in the storage means for storing data, the data is transmitted to an external data storage device connected via a communication line, and the storage means is damaged. A data storage method, which, when detected, receives data from the external data storage device via the communication line.

(Supplementary Note 17) A procedure for transmitting the data to an external data storage device connected via a communication line before or after the data is written to the storage means for storing the data in the computer, and A program for executing a procedure of receiving data from the external data storage device via the communication line when a failure is detected in the storage means.

(Supplementary Note 18) A data reading method of a data processing device, which is connected via a communication line to an external data storage device in which backup data is stored in advance, and which performs a predetermined process on data. When reading the data stored in the storage means for storing data, the storage means is inspected for the presence or absence of a failure, and if a failure is detected by the inspection, the backup data of the read data is transferred to the communication line. A method for reading data, which is received from the external data storage device via

(Supplementary Note 19) A storage device for storing data is connected to an external data storage device in which backup data is stored in advance through a communication line, and performs predetermined processing on the data. When reading stored data, a procedure for inspecting the presence or absence of a fault in the storage means, and a fault detected by the inspection,
A procedure for receiving backup data for the read data from the external data storage device via the communication line.

[0119]

According to the present invention, even if a failure occurs in the storage means (for example, flash memory), the data processing device (for example, SLT monitoring device) can continue the processing without stopping the processing. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a communication system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed internal structure of an SLT.

FIG. 3 is a block diagram showing a detailed configuration of a monitoring device.

FIG. 4 is a block diagram showing a detailed configuration of a flash memory unit of the monitoring device.

FIG. 5: S when a failure is detected in the flash memory
It is a flowchart which shows the flow of a process by the 1st method of LT.

FIG. 6 shows a data structure of a packet transmitted from the SLT to the element manager.

FIG. 7 is a flowchart showing the flow of processing when writing data to the flash memory.

[Explanation of symbols]

1 Element Manager 2 ₁ , 2 ₂ Subscriber Line Terminal (SLT) 21 Monitoring Device 32 CPU 36 Flash Memory Unit 41a-41d Flash Memory 42a-42d Parity Check Circuit 43, 44 Register

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ken Sasaki             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house (72) Inventor Masao Maeda             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house (72) Inventor Kazuma Fujii             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house (72) Inventor Hirokazu Ito             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house F-term (reference) 5B018 GA01 GA04 HA05 HA12 KA01                       KA02 KA22 NA06 QA16                 5K034 DD01 EE10 HH01 HH02 HH26                       HH42 TT01

Claims (5)

[Claims] 1. A data processing device that is connected to an external data storage device via a communication line and performs a predetermined process on data, the storage device storing the data, and the storage device storing the data in the storage device. Data processing comprising writing means for writing, and transmitting means for transmitting the data to the external data storage device via the communication line before or after writing data to the storage means by the writing means apparatus. 2. A data processing device, which is connected via a communication line to an external data storage device in which backup data is stored in advance, and which performs predetermined processing on the data, and which stores the data. Means, an inspection means for inspecting the presence or absence of a failure in the storage means when reading the data stored in the storage means, and a backup data of the read data when the failure is detected by the inspection means And a receiving unit that receives the data from the external data storage device via the communication line. 3. Before or after writing the data in the storage means for storing the data, the data is transmitted to an external data storage device connected via a communication line, and a failure is detected in the storage means. Then, a data storage method of receiving data from the external data storage device via the communication line. 4. A procedure for transmitting the data to an external data storage device connected via a communication line before or after writing the data to the storage means for storing the data in the computer, and the storage means. And a procedure for receiving data from the external data storage device via the communication line when a failure is detected in the program. 5. A data reading method of a data processing device, which is connected via a communication line to an external data storage device in which backup data is stored in advance, and which performs predetermined processing on the data, comprising: When the data stored in the storage means for storing the data is read, the presence or absence of a failure in the storage means is inspected, and when the failure is detected by the inspection, the backup data of the read data is transferred via the communication line. A data read method for receiving data from the external data storage device.