JP2000047896A - Device for setting device-specific information - Google Patents

Abstract

(57) [Summary] [Problem] A maintenance device to be replaced while maintaining security when a failure occurs in a device that performs data processing based on retained device unique information with respect to a device for setting device unique information. The device-specific information is transferred to and can be set. SOLUTION: In a data processing device including a central processing unit and a writable and readable nonvolatile memory holding device-specific information, a connector connecting a bus line and a power supply line, and an external device having the same configuration as the device are provided. A transfer unit that outputs the address of the non-volatile memory on the bus, reads device-specific information from the non-volatile memory, and writes the read information to the non-volatile memory, and connects the data processing devices having the above configuration with the connector, The data processing device on the power-on side is configured to read the device-specific information stored in the non-volatile memory of the connection destination data processing device, store it in the non-volatile memory of its own device, and set it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory capable of writing and reading device-specific information [hereinafter referred to as NVRA.
M (NON VOLATILE RANDOM ACCESS MEMORY)]
A computer device that identifies the device by storing the
The present invention relates to a device-specific information setting device capable of automatically setting device-specific information in the NVRAM of a maintenance board while maintaining security when a failure occurs on a board (such as a motherboard) on which the NVRAM is mounted and the board is replaced with a maintenance board.

[0002]

2. Description of the Related Art FIG.
Is a diagram illustrating an example of a motherboard. The unique information of the device, for example, a global MAC address and a serial number in network communication are written and held in the NVRAM as nonvolatile information, and a program such as a firmware or an operating system executes a predetermined process using the unique information. As shown in FIG. 6, the NVRAM includes a central processing unit CPU3, a BOOT for performing initial program loading, and the like.
ROM 4 in which program 7 is stored, program,
It is mounted on a motherboard 1 on which a memory MEM2 or the like in which data and the like are mounted is mounted in a detachable manner by a socket 6. If a failure occurs in the motherboard 1, the NVRAM 5 of the motherboard 1 is replaced with the same function. By replacing it with another motherboard (maintenance board) that has it, the identity of the device is maintained.

According to this method, when an accident such as breaking of a pin of the NVRAM 5 occurs when the NVRAM 5 is mounted on the motherboard 1, the inherent information for maintaining the identity of the device is lost, and the device does not operate. I will.

For this recovery, a new NVRAM 5 in which device-specific information is written is prepared at a factory or the like, and work such as sending it to a user occurs, so that the device does not operate for a long time.

Since the unique information is a problem relating to the security of the apparatus, it is not desirable that the user input a command to rewrite the information. The present invention has been made in view of the above circumstances, and has as its object to provide a simple device-specific information setting device that automatically sets device-specific information in a memory on a maintenance board using a simple method while maintaining security.

[0006]

In order to solve the above-mentioned problems, a device for setting device-specific information according to the present invention is provided in a first data processing device or a second data processing device in the principle diagram of FIG. As shown in FIG. (First invention) A first invention is directed to a data processing device including a central processing unit 3 and a readable / writable nonvolatile memory 5a for holding device-specific information (the first data processing device and the second data processing device shown in FIG. 1). The data processing device has the same configuration, but only the nonvolatile memory is distinguished), a bus line 14 between the central processing unit 3 and the nonvolatile memory 5a, and a power supply line 27 for supplying power to an external device. Connector 21
And a separation mechanism 26 that enables access to the nonvolatile memory 5b from the connector 21 when the power is turned off.
And outputs the address of the non-volatile memory 5b including the address specifying the external device having the same configuration as the data processing device onto the bus, reads the device-specific information from the non-volatile memory 5b, and reads the non-volatile memory of the own device. 5a, a transfer unit 23 for writing data is provided, the data processing devices having the above configuration are connected by a connector 21, and the transfer unit 23 of the first data processing device on the power-on side is connected to the non-volatile memory of the connected second data processing device. The device-specific information stored in the volatile memory 5b is directly read, and stored in the non-volatile memory 5a of the own device and set.

With the above configuration, for example, if the transfer unit 23 is activated by turning on the power, when the failed device is replaced with the maintenance device, the failed device and the maintenance device are connected by the connector 21. Then, it is possible to transfer and set the device-specific information from the failed device to the maintenance device only by turning on the power to the maintenance device.

Therefore, it is not necessary to replace the NVRAM 5, so that troubles such as breakage of the pins of the NVRAM 5 can be avoided. Information can be set.

(Second Invention) According to a second invention, in the first invention, the transfer unit 23 confirms that the content of the nonvolatile memory 5a of the own device is a predetermined pattern, and then transmits the predetermined pattern from the connection destination device. Reads device-specific information and stores its own nonvolatile memory
After writing to 5a and confirming the completion of normal writing, the nonvolatile memory 5b of the connection destination device is cleared.

As described above, after the transfer, the device-specific information on the faulty device side is deleted, so that security can be more reliably maintained.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. Note that the same reference numerals represent the same object throughout the drawings.

FIG. 2 is a block diagram of the embodiment, FIG. 3 is a connection diagram, FIG. 4 is a diagram showing an example of a connection state at the time of setting, and FIG. 5 is an operation flowchart. The device for setting device-specific information according to the present invention includes:
In the present embodiment, a central processing unit CPU, a writable and readable non-volatile memory NVR for storing device-specific information
Motherboard with AM (first or second in FIG. 1)
). However, CP
Even if U and NVRAM are mounted on separate boards, they can of course be incorporated into either board or another board as long as they are connected to each other by an external bus.

In FIG. 2, reference numeral 2 denotes a memory MEM which stores programs, data, and the like from a disk device or the like (not shown). Reference numeral 3 denotes a central processing unit CPU,
Then, predetermined processing is performed according to programs, data, and the like stored in MEM2. 4 is a read-only memory RO
In M, a BOOT program 7 for loading an initial program and the like, and a transfer program (transfer unit in FIG. 1) 23 for transferring the device-specific information of the present invention are stored in advance.

5 is a writable and readable nonvolatile memory N
Device specific information is set in the VRAM, and read out and used by an operating system or the like. This NV
The RAM 5 stores the NVRAM SEL signal CS generated on the own board or the selection signal CS-EXT from the external board.
A write mode (“1”) or a read mode (“0”) is set by a WR signal or a WR-IN signal input from an external board, respectively, selected by IN.

An OR circuit 8 performs an OR operation on the WR signal output from the CPU 3 of the own board and the WR-IN signal input from the connector 21. The OR circuit is in a state where the power supply of the apparatus is turned off. In this case, the WR signal is set to be "0". Fault board and maintenance board are connectors
When the connection is made at 21 and the device-specific information is transferred, the power supply on the faulty board is turned off and the power supply on the maintenance board is turned on. The reading mode will be determined.

Reference numeral 9 denotes an OR circuit, which is a decoder DE on its own board.
The CS signal generated in C10 and the CS-EXT-IN signal input from the connector 21 are ORed. The faulty board side (the side where power is cut off and read) is set to "0". You. This allows the maintenance board to select the NVRAM 5 of its own board or the NVRAM of the external board.
Chip select control for selecting the RAM 5 is performed.

Reference numeral 10 denotes a decoder DEC for decoding a predetermined upper address of the addresses output from the CPU 3 and outputting select signals SEL and CS of each memory chip and an NVRAM select signal CS-EXT @ IN of an external board. .

24 is a status register STS REG
Stores the state of whether or not the connector 21 is connected to the other party. When connected, the other party's STS OUT
When the signal is not connected to “0”, and when not connected, “1” is set by the pull-up resistor R, this state is confirmed. The illustrated board also outputs an STS OUT signal to the other party.

Reference numeral 25 denotes a gate, which electrically insulates the upper bus from the lower bus when power is not supplied. D is a diode for matching. On a board where the power supply of the device is off, the power supply Vc-IN from the connector 21 is NVR.
It is designed to be applied only to the access element (including ORs 8 and 9) of the AM5.

Reference numeral 21 denotes a connector to which the control signal lines shown in the figure are connected in addition to the address bus 12 and the data bus 13. twenty three
Is a transfer program, which is started when power is turned on, and NVR
If the device-specific information is not set in the AM 5, a process of setting the device-specific information by transfer from an external device described later is performed.

When the motherboard 1 in which the device-specific information is set as described above is incorporated in the device and, for example, provided with a function of performing a communication process, when the power is turned on, the BOOT program 7 is started. A communication control program is loaded from a disk (not shown) into the MEM 2, and a predetermined communication process is performed by the CPU 3 with reference to the MAC address and the like.

When a failure occurs in this board, as shown in FIG. 4, the failure board 1b (in the following description, the maintenance board is identified by adding a suffix a to the code, and the failure board is identified by the suffix b. Is removed from the device 20 and the maintenance board 1a
Is attached to the device 20, but the NVRAM of the maintenance board 1a is
5 is connected by a cable 22 in order to transfer the device-specific information of the faulty board 1b to the device 5, and then the device 20 is turned on.

It is assumed that a predetermined pattern, for example, "5" is written in the NVRAM 5a of the maintenance board 1a. FIG. 3 is a block diagram showing a case where the faulty board 1b removed from the device 20 and the maintenance board 1a attached to the device 20 are connected by a cable 22, as shown in FIG.

On the left side of the figure is a failure board 1b, and the power supply Vc-IN is supplied from the maintenance board 1a via a diode Da.
Since the power supply Vcb of the faulty board is 0 V, the power supply Vc-IN is prevented from being supplied to other elements by the diode Db.
It is supplied only to the elements required for accessing the NVRAM 5b from the maintenance board 1a, such as the NVRAM 5b, OR 8b, OR 9b.

When the power supply Vcb on the faulty board 1b side is zero, CSb is designed to be "0" and WRb is designed to be "0". When the OR function is configured by an AND circuit, the reverse is of course the case.

With the above configuration, when the power supply Vca is applied to the maintenance board 1a mounted on the device 20, the maintenance board 1a
1a is supplied with power to the entire device and the device itself becomes operable, and the NVRAM 5b of the faulty board 1b can be directly accessed via the buses 14a and 14b (including the address bus 12 and the data bus 13). Configuration.

The operation of setting the device-specific information will be described below with reference to FIG. The ROM 4a stores a BOOT program 7a and a transfer program 23a. When the power is supplied to the maintenance board 1a, the transfer program 23a is started. (1) In the transfer program 23a, first, the NVR of the own board 1a
Read the contents of AM5a and check the contents. If a specific pattern, in this case, “5” is not written, it is determined that the device-specific information has already been set and the BO
Transfer control to OT program 7a, if it is a specific pattern,
Proceed to the next step. (2) Next, verify the contents of the status register STS REG,
It is verified whether or not the external motherboard 1b is connected via the connector 21. If it is "1", it is not connected and issues an alarm. This alarm provides a display prompting connection if the display unit is connected. If "0", the connection is established, and the process proceeds to the next step. (3) The address of the NVRAM 5b on the faulty board 1b is
a, and as a result, the contents of the data output to the bus 14a via the bus 14b are read, and the NV of the own board 1a is read.
The data is written to the same address in the RAM 5a. Note that this transfer is performed after NVRAM is temporarily transferred to MEM2a.
It may be stored in M5a, or as shown in (3 ') of FIG. 5, it can be directly executed by an instruction between memories (between NVRAMs). (4) After the transfer of the predetermined device-specific information is completed, normal transfer is confirmed by comparing and matching. If the transfer is normal, the process proceeds to the next step. (5) After confirming the normal transfer, the contents of the NVRAM 5b of the faulty board 1b are cleared. By this clearing, even if the content of the NVRAM 5b remaining on the faulty board 1b is read, the security can be further maintained because the device-specific information has disappeared. (6) After the above operation steps are completed, an end message is displayed.

Then, after the power is turned off, the connector 21 is removed, and the power of the apparatus is turned on again, the step
As a result of (1), the BOOT program 7a operates and the device 20 enters the operating state.

As described above, the NVRAM of the faulty board 1b
There is no need to remove 5b from the socket 6b, without operator input and setting, and while ensuring security, it is possible to automatically transfer and set device-specific information from the faulty board to the maintenance board on site while ensuring security. it can.

In the above embodiment, the NVRAM is described as an example of the writable and readable nonvolatile memory. However, the same function as that of the NVRAM, for example, EPROM,
Of course, the present invention can be applied to an EPROM, an SRAM backed up by a battery, and the like.

As a device for setting device-specific information, a CP
This board has been described as applied to a data processing unit (board) containing U, but this board is used not only for so-called computers such as personal computers, workstations, and mainframes, but also for processing devices other than computers such as exchanges and LAN routers. Needless to say, this is also used.

[0032]

As described above, according to the present invention,
A mechanism has been provided to transfer the device-specific information recorded on the faulty board to the maintenance board and to set the device-specific information. Therefore, the device-specific information can be easily set on the maintenance board at the site, and the nonvolatile memory can be replaced. In addition to the above, the setting can be easily performed without any problem, and the non-volatile memory in which the failure has occurred is cleared, so that the effect of maintaining security can be obtained.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 Connection diagram

FIG. 4 is a diagram showing an example of a connection state at the time of setting;

FIG. 5 is an operation flowchart.

FIG. 6 is a diagram illustrating an example of a motherboard.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Motherboard, data processing device 1a Maintenance board 1b Faulty board 2, 2a, Memory MEM3, 3a, 3b Central processing unit CPU 4, 4, a, 4b Read-only memory ROM 5, 5, a, 5b Writable and readable nonvolatile memory NVRA
M 6,6a, 6b Socket 7 BOOT Program 8,8a, 8b, 9,9a, 9b OR circuit OR 10,10a, 10b
Decoder DEC 12 Address bus 13 Data bus 14a, 14b Bus 20 Device 21, 21a, 21b Connector 22 Cable 23, 23a, 23b Transfer unit, transfer program 24, 24a Status register STS REG 25, 25a, 25b Gate R, Ra resistance D , Da, Db diode

Claims (2)

[Claims] 1. A data processing device including a central processing unit and a readable and readable nonvolatile memory for holding device-specific information, comprising: a bus line between the central processing unit and the nonvolatile memory; A connector connected to a power supply line for supplying power, a separation mechanism between an element that enables access to the nonvolatile memory from the connector when the power is turned off, and another element, and the same configuration as the data processing device A transfer unit that outputs an address of a non-volatile memory including an address designating the external device to the bus, reads device-specific information from the non-volatile memory, and writes the device-specific information to the non-volatile memory of the own device. The data processing devices of the configuration are connected by the connector, and the transfer unit of the first data processing device on the power-on side is connected to the second data processing device of the connection destination. An apparatus for setting device-specific information, which is configured to read device-specific information from a non-volatile memory and store and set the device-specific information in a non-volatile memory of the device itself. 2. The transfer unit, after confirming that the content of the non-volatile memory of the self-device is a predetermined pattern, reads the device-specific information from the connection destination device, writes the device-specific information in the non-volatile memory of the self-device, and performs normal writing. 2. The device unique information setting device according to claim 1, wherein the device clears the non-volatile memory of the connection destination device after confirming the completion.