JP2003274290A - Solid-state imaging device and driving method thereof - Google Patents

Abstract

[PROBLEMS] To increase the dynamic range of a MOS solid-state imaging device and reduce the voltage. SOLUTION: Each pixel of the solid-state imaging device includes a photodiode PD, an FD section, a transfer transistor (transfer gate) T
r1, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4. When reading an image, the transfer gate Tr1
The output signal of the amplifying transistor Tr3 is taken into the CDS circuit of the subsequent stage in a state where is turned on. As a result, the voltage of the FD section can be increased by using the capacitive coupling between the transfer gate Tr1 and the FD section, and the voltage in the pixel can be reduced accordingly. In addition, by using the FD section, the channel of the transfer gate Tr1, and the photodiode PD as receivers of signal charges, the number of electrons handled can be increased, and the dynamic range can be expanded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS sensor type solid-state image pickup device having a photoelectric conversion element and a readout circuit for each pixel constituting an image pickup area portion, and a driving method thereof.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram showing a structural example of a main part in a MOS sensor type solid-state image pickup device. Pixel 1
A large number of 0s are arranged in a two-dimensional array in the image pickup region, and each pixel has a photodiode PD as a photoelectric conversion element and four MOSs constituting a readout circuit thereof.
Transistors Tr1 to Tr4 are provided. The photodiode PD is for generating a signal charge according to the amount of light received, and is a transfer transistor (transfer gate means) Tr.
1 transfers the signal charge of the photodiode PD to the floating diffusion (FD) section based on the transfer pulse. The reset transistor (reset means) Tr2 periodically resets the voltage of the FD section to the power supply voltage Vdd based on the reset pulse.
The FD section is connected to the gate of the amplification transistor (amplification means) Tr3, and outputs an output signal according to the voltage fluctuation of the FD section. Select transistor Tr4
Is a vertical signal line (output signal line) 1 which outputs an output signal of the amplification transistor Tr3 based on a selection pulse for selecting a pixel row.
2 is output.

The vertical signal line 12 is provided for each pixel column, and one end thereof is Lo as a constant current source outside the imaging region.
It is connected to the ad transistor Tr5. The other end of the vertical signal line 12 is connected to a signal processing circuit provided for each pixel column outside the imaging area. This signal processing circuit is provided in the next stage of the image pickup area and performs various signal processing on pixel signals. This signal processing circuit has a CDS (Correlated Double Samplin) as shown in FIG.
g) Includes circuitry. This CDS circuit is
An orrelated Double Sampling circuit is a circuit that inputs two signals in time series and outputs a signal proportional to the difference. Specifically, the transistors Tr6, Tr7, T
It has r8, capacitors Cs and Cr, and a differential amplifier 14.

Then, the transistor Tr6 is turned on by the timing signal SHS at the time when the signal charge of the photodiode PD is accumulated in the FD section, and the output signal is held by the capacitor Cs.
Timing signal SHR at the time when the FD section is reset
By turning on the transistor Tr7 by, the output signal is held by the capacitor Cr. Then, the levels held in these two capacitors Cs and Cr are compared by the differential amplifier 14 to obtain the difference between the two,
This difference value is transferred to the horizontal signal line 1 via the transistor Tr8.
Output to 6.

FIG. 11 is a timing chart showing a conventional operation example in the solid-state image pickup device having such a configuration, and FIG. 12 is a potential diagram showing transition of signal charges during the operation shown in FIG. Note that FIG. 11 and FIG.
It is assumed that the numbers indicating timings in 2 correspond.
First, during timing 0, photoelectrons are accumulated in the photodiode PD. Then, at timing 1, when the selection transistor Tr4 is turned on, the amplification transistor Tr3 of the pixel is connected to the vertical signal line 12. Then L
The constant current determined by the open transistor Tr5 changes from Vdd (power supply voltage terminal) to the amplification transistor Tr5.
It flows in the path of 3 → vertical signal line 12 → Load transistor Tr5. Since the amplification transistor Tr3 and the load transistor Tr5 form a source follower, the gate voltage of the amplification transistor Tr3, that is, the voltage corresponding to the voltage of the FD portion appears on the vertical signal line 12. This continues for as long as the selection transistor Tr4 is turned on.

Next, with a reset pulse at timing 2,
Reset the FD section. Immediately after this, the potential at timing 3 is as shown in (3) of FIG.
As shown in the figure, photoelectrons are accumulated in the photodiode PD at this time, and the FD portion is in a state immediately after reset. It should be noted that the voltage of the FD portion is assumed to be substantially equal to Vdd in order to facilitate understanding of the description hereafter. At timing 3, since the voltage (reset level) corresponding to the potential of the FD portion appears on the vertical signal line 12, SH
By inputting the R pulse, this is sampled and held in the capacitor Cr of the CDS circuit.

Next, with the pulse of timing 4, the photoelectrons of the photodiode PD are transferred to the FD section. Immediately after this, the potential at timing 5 is as shown in (5) of FIG. As shown in the figure, the potential of the FD section is shifted to the minus side by the amount of photoelectrons. And this F
Since the voltage (signal level) corresponding to the potential of the D section appears on the vertical signal line 12, by inputting the SHS pulse, this is sampled and held in the capacitor Cs of the CDS circuit. The differential amplifier 14 of the CDS circuit outputs a voltage proportional to the difference between the signal level held in each of the capacitors Cs and Cr and the reset level as described above. Next, at timing 6, the selection transistor Tr4 is turned off to disconnect the amplification transistor Tr3 from the vertical signal line 12. After that, the output of the differential amplifier 14 of the CDS circuit is read to the horizontal signal line 16 by controlling the transistor Tr8 from the H selection means (horizontal scanner circuit).

[0008]

However, the above-mentioned conventional techniques have the following problems. (1) It is difficult to reduce the voltage. That is, since the FD section can actually be reset only at a voltage lower than Vdd,
Since the source follower must operate stably after taking the signal voltage amplitude from the reset voltage, when considering the reset voltage drop, the signal amplitude, the operating voltage of the source follower, and their margins, the peripheral circuit Can reduce the voltage, but the operating voltage of the pixel regulates the power supply voltage, so that the voltage cannot be reduced.

(2) The dynamic range is narrow because the capacity of the photodiode cannot be increased. In other words, if the capacity of the photodiode is increased, the capacity of the FD section must also be increased to increase the photoelectrons of the photodiode.
There is a problem that the portion D cannot be received and electrons remain in the photodiode. However, increasing the capacity of the FD portion lowers the efficiency of converting charges into voltage, which is a factor of reducing sensitivity. Moreover, the pixel area is also increased. Therefore, the capacity of the photodiode cannot be increased, and it becomes difficult to expand the dynamic range.

Therefore, an object of the present invention is to provide a solid-state image pickup device capable of expanding the dynamic range and reducing the voltage, and a driving method thereof.

[0011]

In order to achieve the above-mentioned object, the present invention comprises a semiconductor substrate provided with an image pickup area section comprising a plurality of pixels and a peripheral circuit section for controlling the image pickup area section. Each pixel in the imaging region section generates a photoelectric charge according to the amount of received light, a photoelectric conversion element, a transfer gate unit that transfers the signal charge generated by the photoelectric conversion element to a floating diffusion section, and the floating diffusion. In the solid-state imaging device configured to include an amplifying unit that outputs an electric signal corresponding to the voltage of the unit to an output signal line and a reset unit that resets the voltage of the floating diffusion unit, the transfer gate unit is turned on. In this state, the electric signal output to the output signal line is taken in by the signal processing circuit provided in the peripheral circuit section, and the electric signal is taken in. And generates an image signal from the item.

Further, according to the present invention, a semiconductor substrate is provided with an image pickup area portion composed of a plurality of pixels and a peripheral circuit portion for controlling the image pickup area portion, and each pixel of the image pickup area portion receives a light receiving amount. , A transfer gate means for transferring the signal charge generated by the photoelectric conversion element to the floating diffusion portion, and an electric signal corresponding to the voltage of the floating diffusion portion are output. In a method for driving a solid-state imaging device, which comprises an amplifying means for outputting to a signal line and a resetting means for resetting a voltage of the floating diffusion part, the output signal line in a state where the transfer gate means is turned on. The electric signal output to the device is captured by the signal processing circuit provided in the peripheral circuit section, and an image pickup signal is generated from the captured signal. And wherein the Rukoto.

In the solid-state image pickup device and the driving method thereof according to the present invention, the electric signal output to the output signal line in the state where the transfer gate means is turned on is taken in by the signal processing circuit provided in the peripheral circuit section, and the taken signal is taken. The imaging signal is generated from the. Therefore, the voltage of the floating diffusion portion can be increased by using the capacitive coupling between the transfer gate means and the floating diffusion portion, and the voltage in the pixel can be reduced accordingly. Moreover, since the floating diffusion portion, the channel of the transfer gate means and the photoelectric conversion element can be used as a tray for receiving the signal charges, the number of handled electrons can be increased and the dynamic range can be expanded.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a solid-state image pickup device and a driving method thereof according to the present invention will be described below. The present embodiment provides a method for driving a CMOS sensor type solid-state image pickup device in a wide dynamic range at a low voltage, and turns on the transfer gate means of each pixel when reading each pixel signal of the CMOS sensor. By reading the voltage of the output signal line of the pixel signal as it is, the voltage can be lowered by the amount of capacitive coupling, and by increasing the amount of charge handled, saturation shortage can be resolved and the dynamic range expanded. It was done.

FIG. 1 is a schematic plan view showing an example of the overall structure of a MOS sensor type solid-state image pickup device according to this embodiment. This solid-state image pickup device includes an image pickup pixel section 112 formed on a semiconductor chip 110, a V selection unit 114, an H selection unit 116, a timing generator (TG) 118, and a C.
It includes a DS section 120, a constant current section 122, a horizontal signal line 124, an output section 126 and the like.

The image pickup pixel section 112 constitutes the above-mentioned image pickup area, and a large number of pixels are arranged in a two-dimensional matrix, and each pixel has a photodiode similar to that shown in FIG. A PD, an FD section, a transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, a selection transistor Tr4 and the like are provided. In addition, in the following description, the reference numerals shown in FIG. Further, each pixel of the image pickup pixel unit 112 is sequentially selected in the vertical direction in units of horizontal lines (pixel rows) in the vertical direction, and various pulse signals from the timing generator 118 are applied to the MOS of each pixel.
By controlling the transistors, each pixel signal is read out to the CDS unit 120 for each pixel column through the vertical signal line.

The CDS section 120 is provided with the above-described CDS circuit shown in FIG. 10 for each pixel column of the image pickup pixel section 112, and for the pixel signals read from each pixel row of the image pickup pixel section 112. , CDS processing, and outputs the pixel signal to the output unit 126 via the horizontal signal line 124. The output unit 126 provides automatic gain conversion (AGC) and analog / digital (A / D) for pixel signals from the CDS circuit.
Each circuit is provided for performing processing such as conversion and amplification.
Further, the H selection means 116 selects the pixel signal output from the CDS section 120 in the horizontal direction, and selects it as the horizontal signal line 12.
4 is output.

The constant current section 122 supplies a constant current source to the above-described image pickup pixel section 112 for each pixel column. Also, the timing generator 118
Supplies various timing signals to each part of the imaging pixel unit 112 other than each pixel. Also, the output unit 1
26 outputs a digital signal sent from the horizontal signal line 124 to an external terminal of the semiconductor chip 110. Note that such a configuration itself is basically the same as the conventional one, and the present invention is characterized by the driving method described below.

FIG. 2 is a timing chart showing a first operation example (first embodiment) of the solid-state image pickup device according to the present embodiment, and FIG. 3 is an operation time of the first embodiment shown in FIG. 6 is a potential diagram showing a transition of signal charges in FIG. Note that the numbers indicating the timings in FIGS. 2 and 3 correspond to each other. In this example, the timing 2 of FIG.
During the period when the selection transistor Tr4 is turned on in ~ 6,
As in the conventional example, the voltage corresponding to the potential of the FD section is output to the vertical signal line. However, in FIG. 2, the FD unit is reset by the reset pulse at timing 2 (first reset pulse). At timing 3, the transfer gate Tr1 is turned on and the transistor T of the CDS circuit is turned on.
The SHS pulse is input to r6 and the voltage (signal level) of the vertical signal line 12 is taken into the capacitor Cs of the CDS circuit. Here, the photoelectrons of the photodiode PD are transferred to the FD section, and the potential is in the state shown in (3) of FIG.

Here, the difference from the conventional example is that (1) the transfer gate Tr1 receives a high-level gate signal, so that the voltage is high even under the channel of the transfer gate Tr1. ) Photoelectrons exist in the FD section, but due to capacitive coupling between the transfer gate Tr1 and the FD section,
That is, photoelectrons are accumulated from a voltage higher than the reset voltage (here, about Vdd). In this example, the latter is particularly important. As a result, the driving voltage of the pixel can be lowered. The capacitive coupling between the transfer gate Tr1 and the FD section is about 0.5 V with respect to the power supply voltage of 2.5 V, and plays an important role in lowering the voltage.

Next, returning to FIG. 2 and continuing the explanation, after the transfer pulse is made to fall after the above-mentioned timing 3, the FD section is reset by the second reset pulse at timing 4 and the transfer pulse is again made. Start up, at timing 5,
The SHR pulse is input to the transistor Tr7, and the voltage (reset level) of the vertical signal line 12 is input to the capacitor Cr of the CDS circuit. The potential at this point is in the state shown in (5) of FIG. Here, due to capacitive coupling between the transfer gate Tr1 and the FD section, the FD section has a voltage higher than the reset voltage (approximately Vdd). This amount contributes to lowering the voltage as described above. After that, the differential amplifier 14 of the CDS circuit outputs a signal proportional to the difference between the signal level and the reset level, and then the transfer gate Tr1 and the selection gate Tr4 are closed to complete the operation of the pixel.

In the image pickup pixel section 112, the pixels 10 are arranged in a matrix form, all the pixels for one row are simultaneously driven by this scanning, and the pixel signals for one row are arranged in a CDS in which CDS circuits are arranged. It is simultaneously read out and held in the unit. Then, the photoelectron accumulation period starts. Although not shown in FIG. 2, the H selection means 116 is operated during this period, and the output of the CDS circuit is sequentially guided to the horizontal signal line 116 and output. After that, if the next row is selected by the V selection means 114 and the same operation is performed, the signal of the next row is read out. Then, the signals of all rows can be read by sequentially scanning with the V selection means 114. In this way, a low-voltage, wide dynamic range solid-state imaging device can be realized.

Next, a second operation example (second embodiment) will be described. In the second embodiment, the photodiode PD
The purpose is to cope with the case where the potential well is deep or the capacity is large and the FD portion cannot receive photoelectrons. FIG. 4 is a timing chart showing the operation in the second embodiment, and FIG. 5 is a potential diagram showing the transition of signal charges during the operation of the second embodiment shown in FIG. Note that the numbers indicating the timings in FIGS. 4 and 5 correspond to each other. First, after turning on the selection transistor Tr4, a reset pulse (first reset pulse) is input and then the transfer gate Tr1 is turned on, and at timing 3, the vertical signal line 12 is turned on by the SHS pulse.
The voltage (signal level) of is taken into the capacitor Cs is the same as in the first embodiment. At this time, if the FD portion cannot receive the photoelectrons, the photoelectrons exist even in the channel of the transfer gate Tr1 and the photodiode PD as shown in (3) of FIG. Since the signal is output in this state, all the photoelectron signals can be read, unlike the case where the conventional transfer gate Tr1 is turned off and the photodiode PD and the FD portion are separated.

FIG. 6 is an explanatory diagram showing the relationship between the amount of received light and the amount of output signal in the photodiode. As shown in the figure, when the light amount is small, the FD portion can receive the photoelectrons, and therefore the slope of the light amount-output curve is relatively large. Further, when the amount of light increases, the light is received by the channel of the FD section and the transfer gate Tr1, so that the inclination becomes gentle. When the amount of light further increases, photoelectrons also remain in the photodiode PD, so that the inclination becomes gentler. As described above, even when the FD unit cannot receive photoelectrons, it is possible to increase the number of photoelectrons handled by increasing the sensitivity in dark areas and decreasing the sensitivity in bright areas. Next, when the reset gate Tr2 is also turned on (activated), both the FD section and the photodiode PD are reset. Particularly, the FD section is reset to the voltage of approximately Vdd. Then, at timing 4, the transfer gate Tr1
When is turned off, the voltage of the FD section tends to decrease due to capacitive coupling, but since the reset gate Tr2 is turned on (activated), the potential of the FD section is still maintained at about Vdd.
This order is different from the first embodiment shown in FIG. 2, and if the order is reversed, the photoelectrons remaining in the photodiode PD will not be reset.

Then, when the reset gate Tr2 is turned off (deactivated) and then the transfer gate Tr1 is turned on, at timing 5, the same state as in the first embodiment is restored. The voltage (reset level) of the vertical signal line 12 at this time is set to SH.
It is the same as in the first embodiment that the transfer gate Tr1 and the selection transistor Tr4 are turned off by taking in the capacitor Cr for processing by the R pulse. Thus, even when the photodiode PD has a large number of saturated electrons and cannot be received by the FD portion, the dark area has a high sensitivity, the bright area has a low sensitivity, and an output with a large number of handled photoelectrons is possible. Further, it is clear that the effect of lowering the voltage by using the capacitive coupling between the transfer gate Tr1 and the FD portion is the same as that of the first embodiment. Of course, if the photodiode PD has a small number of saturated photoelectrons and the FD portion can fully receive it, there is no problem even if this operation is performed.

Next, a third operation example (third embodiment) will be described. The third embodiment provides a driving method capable of further expanding the dynamic range. FIG. 7 is a timing chart showing the operation in the third embodiment. Further, the potential diagram in the third embodiment is common to that in FIG. 5, and therefore will be described with reference to this. Note that the numbers indicating the timings in FIGS. 7 and 5 correspond to each other. The third embodiment differs from the operation of the second embodiment in that there is no reset pulse immediately after turning on the select transistor Tr4 shown in FIG. When the amount of light is large, electrons overflow from the photodiode PD to the FD portion during the photoelectron accumulation period of timing 0, and photoelectrons are also accumulated in the FD portion.
Then, the photoelectrons transferred from the photodiode PD are added without resetting them (see FIG. 5).

The subsequent operation is the same as in the second embodiment.
Therefore, in the third embodiment, the amount of charge handled increases to the sum of the saturation amount of the photodiode PD and the saturation amount of the FD portion, instead of the saturation amount of the photodiode PD, while maintaining the same effect as in the second embodiment. . However, in the third embodiment, the dark charge (noise component generated regardless of light) accumulated in the FD portion during the period of timing 0 is also read out, which is disadvantageous in terms of noise. . Therefore, it is preferable to appropriately select and adopt the driving method of the second embodiment capable of reducing the noise and the driving method of the third embodiment capable of expanding the dynamic range according to the application of the solid-state imaging device. .

Next, a fourth operation example (fourth embodiment) will be described. The fourth embodiment provides a driving method that saves operating time while expanding the dynamic range. FIG. 8 is a timing chart showing the operation in the fourth embodiment, and FIG. 9 is a potential diagram showing the transition of signal charges during the operation in the fourth embodiment shown in FIG. Note that the numbers indicating the timings in FIGS. 8 and 9 correspond to each other. In this fourth embodiment,
The fact that there is no reset pulse immediately after the selection transistor Tr4 is turned on is the same as in the third embodiment. Next, the transfer gate Tr1 is turned on at the timing 2, and the SHS pulse is input at the timing 3 to capture the signal level in the capacitor Cs. Then, it is reset at the timing 4, and the SHR pulse is input at the timing 5 to capture the reset level in the capacitor Cr. In this case, the potentials at timing 3 and timing 5 are as shown in (3) and (5) of FIG.

Further, even when the FD section is reset, the transfer gate Tr1 is turned on.
The reset voltage of the section has no increase effect by the coupling capacitance so far, and is about Vdd in this case. Further, at timing 3, the photoelectrons are transferred to the FD portion, but the photoelectrons are accumulated from the voltage as in (3) of FIG. 5 described above. Therefore, there is no effect of lowering the voltage. However, the handling charge amount is the sum of the saturation amount of the photodiode PD and the saturation amount of the FD portion, and the dynamic range is widened, as in the third embodiment, and the effect of widening the dynamic range can be obtained. And this fourth
In the embodiment, since the driving pulse is simple, it is effective when it is desired to save the operation time.

The four examples of the present embodiment have been described above, but any of them can be provided with an electronic shutter function. Further, although the transistor of the pixel is the NMOS, the same applies when the polarity of the voltage is switched by using the PMOS as the PMOS. Further, the photoelectric conversion element may not be a photodiode, but may be, for example, a photogate or the like. Further, the driving method can be variously modified within a range that does not change the gist of the present invention, for example, a case where one reset pulse is used in the above-mentioned example, and a plurality of pulses are executed.

In the above example, the pixel outputs the voltage to the vertical signal line, but the output signal line may be a horizontal wiring, and the output signal is a current signal. Is also good. Further, the pixel structure is not limited to the one configured by four transistors as described above.
Further, the CDS circuit is taken as an example of the signal processing circuit of the next stage, but it may be an A / D converter having a CDS effect, for example, or a circuit that merely holds the reset level and the signal level. , CDS may be arranged further downstream. As described above, the present invention can be implemented in various configurations.

[0032]

As described above, according to the solid-state image pickup device of the present invention, the electric signal output to the output signal line with the transfer gate means turned on is captured by the signal processing circuit provided in the peripheral circuit section. , Since the imaging signal is generated from the captured signal, the voltage of the floating diffusion portion can be increased by using the capacitive coupling between the transfer gate means and the floating diffusion portion,
It is possible to reduce the voltage in the pixel. Moreover, since the floating diffusion portion, the channel of the transfer gate means, and the photoelectric conversion element can be used as a tray for receiving the signal charge,
The number of handled electrons can be increased and the dynamic range can be expanded.

Similarly, according to the driving method of the solid-state image pickup device of the present invention, the electric signal output to the output signal line with the transfer gate means turned on is captured by the signal processing circuit provided in the peripheral circuit section. , Since the image pickup signal is generated from the captured signal, the voltage of the floating diffusion portion can be increased by using the capacitive coupling between the transfer gate means and the floating diffusion portion, and the voltage in the pixel can be reduced accordingly. Can be achieved. Moreover, since the floating diffusion portion, the channel of the transfer gate means and the photoelectric conversion element can be used as a tray for receiving the signal charges, the number of handled electrons can be increased and the dynamic range can be expanded.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an overall configuration example of a MOS sensor type solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the first embodiment of the present invention.

FIG. 3 is a potential diagram showing transition of signal charges during the operation of the first embodiment shown in FIG.

FIG. 4 is a timing chart showing an operation in the second embodiment of the present invention.

FIG. 5 is a potential diagram showing transition of signal charges during operation of the second embodiment shown in FIG.

FIG. 6 is an explanatory diagram showing the relationship between the amount of received light and the amount of output signal of the photodiode in the second to fourth examples of the present invention.

FIG. 7 is a timing chart showing an operation in the third embodiment of the present invention.

FIG. 8 is a timing chart showing an operation in the fourth embodiment of the present invention.

FIG. 9 is a potential diagram showing transition of signal charges during operation of the fourth embodiment shown in FIG.

FIG. 10 is a circuit diagram showing a configuration example of an output main part in a conventional MOS sensor type solid-state imaging device.

11 is a timing chart showing an operation example of the solid-state imaging device shown in FIG.

12 is a potential diagram showing transition of signal charges during the operation shown in FIG.

[Explanation of symbols]

110 ... Semiconductor chip, 112 ... Imaging pixel unit, 11
4 ... V selecting means, 116 ... H selecting means, 118 ...
Timing generator (TG), 120 ... CDS
Part, 122 ... Constant current part, 124 ... Horizontal signal line, 12
6 ... Output section.

Claims (12)

[Claims] 1. A semiconductor substrate is provided with an image pickup area section including a plurality of pixels, and a peripheral circuit section for controlling the image pickup area section. Each pixel of the image pickup area section is a signal corresponding to a light receiving amount. A photoelectric conversion element that generates electric charges, a transfer gate unit that transfers the signal charges generated by the photoelectric conversion element to a floating diffusion portion, and an electric signal that corresponds to the voltage of the floating diffusion portion is output to an output signal line. In the solid-state imaging device configured to have an amplifying unit for resetting and a reset unit for resetting the voltage of the floating diffusion unit, an electric signal output to the output signal line in a state where the transfer gate unit is turned on is output. A signal processing circuit provided in the peripheral circuit section captures the signal, and an image pickup signal is generated from the captured signal. Body imaging device. 2. The signal processing circuit resets the floating diffusion part by the reset signal and the signal level when the signal charge generated by the photoelectric conversion element is transferred to the floating diffusion part by the transfer gate means. And the signal level when the transfer gate means is turned on,
The solid-state imaging device according to claim 1, wherein a signal according to the difference value is output. 3. The transfer gate means after the first reset pulse is input to the reset means, the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit. Is turned off, then a second reset pulse is input to the reset means, the transfer gate means is turned on, and the electric signal output to the output signal line in this state is taken into the signal processing circuit. The solid-state imaging device according to claim 2. 4. After inputting a first reset pulse to the reset means, the transfer gate means is turned on, and in that state, the electric signal output to the output signal line is taken into the signal processing circuit and then the reset means is turned on. After activating and turning off the transfer gate means and then deactivating the reset means, the transfer gate means is turned on and the electric signal output to the output signal line in that state is taken into the signal processing circuit. The solid-state imaging device according to claim 2. 5. The transfer gate means is turned on after the reset means is inactivated, the electric signal output to the output signal line in that state is taken into the signal processing circuit, and then the reset means is activated and transferred. Turn off the gate means, then
3. The solid-state imaging device according to claim 2, wherein after the reset means is inactivated, the transfer gate means is turned on and the electric signal output to the output signal line in that state is taken into the signal processing circuit. 6. The transfer gate means is turned on, after the electric signal output to the output signal line in that state is taken into the signal processing circuit, a reset pulse is input to the reset means, and the output signal line in that state is input. The solid-state imaging device according to claim 2, wherein the electric signal output to the signal processing circuit is taken into the signal processing circuit. 7. A semiconductor substrate is provided with an image pickup area section composed of a plurality of pixels and a peripheral circuit section for controlling the image pickup area section, and each pixel of the image pickup area section outputs a signal corresponding to a light receiving amount. A photoelectric conversion element that generates electric charges, a transfer gate unit that transfers the signal charges generated by the photoelectric conversion element to a floating diffusion portion, and an electric signal that corresponds to the voltage of the floating diffusion portion is output to an output signal line. In the method for driving a solid-state imaging device, the method includes: an amplifying unit that resets the voltage of the floating diffusion unit, and a reset unit that resets the voltage of the floating diffusion unit. The feature is that an electric signal is captured by a signal processing circuit provided in the peripheral circuit section, and an image pickup signal is generated from the captured signal. A method of driving a solid-state image pickup device. 8. The signal processing circuit resets the floating diffusion portion by the signal level when the signal charges generated by the photoelectric conversion element are transferred to the floating diffusion portion by the transfer gate means and by the reset means. And the signal level when the transfer gate means is turned on,
The solid-state imaging device driving method according to claim 7, wherein a signal corresponding to the difference value is output. 9. The transfer gate means after the first reset pulse is input to the reset means, the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit. Is turned off, then a second reset pulse is input to the reset means, the transfer gate means is turned on, and the electric signal output to the output signal line in this state is taken into the signal processing circuit. The method for driving a solid-state imaging device according to claim 8. 10. The reset gate is turned on after the first reset pulse is input to the reset means, the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit. After activating, turning off the transfer gate means, then deactivating the reset means,
9. The method for driving a solid-state imaging device according to claim 8, wherein the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit. 11. After deactivating said reset means,
The transfer gate means is turned on, the electric signal output to the output signal line in that state is taken into the signal processing circuit, the reset means is activated, the transfer gate means is turned off, and then the reset means is deactivated. 9. After that, the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit.
A method for driving the solid-state imaging device according to claim 1. 12. The transfer gate means is turned on, and after the electric signal output to the output signal line in that state is taken into the signal processing circuit, a reset pulse is input to the reset means and the output signal line is kept in that state. 9. The method for driving a solid-state image pickup device according to claim 8, wherein the electric signal output to the device is taken into the signal processing circuit.