JP2001218112A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device that can pick up an object having a wide luminance range from a high luminance to a low luminance with high accuracy. SOLUTION: A photocurrent (electric signal) generated from a photodiode PD onto which a light is made incident changes a gate voltage of a MOS transistor(TR) T2, a current in response to the gate voltage flows to a capacitor C via the TR T2 to change a voltage at a connection node (a). In this case, when the MOS TR T1 is operated in a sub-threshold region whose value is less than a threshold, the voltage at the connection node (a) natural- logarithmically changes with the photocurrent. Furthermore, turning off the MOS TR T1 linearly changes the voltage at the connection node (a) with respect to the photocurrent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device in which pixels are two-dimensionally arranged.

[0002]

2. Description of the Related Art Pixels each including a photoelectric conversion element (photosensitive element) such as a photodiode and a means for extracting photocharges generated by the photoelectric conversion element to an output signal line are arranged in a matrix. Two-dimensional solid-state imaging devices are used for various purposes. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. C
The CD type is designed to transfer a photocharge while accumulating it in a potential well, and has a drawback that a dynamic range is narrow. On the other hand, in the MOS type, the charge accumulated in the pn junction capacitance of the photodiode is directly read out through a MOS transistor.

Here, one of the conventional MOS-type solid-state imaging devices is described.
The configuration per pixel will be described with reference to FIG. In the figure, PD is a photodiode whose cathode is M
The gate of the OS transistor T1 and the MOS transistor T
2 sources. MOS transistor T1
Is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line Vou.
Connected to t. The DC voltage VPD is applied to the drain of the MOS transistor T1 and the drain of the MOS transistor T2, and the DC voltage VPS is applied to the anode of the photodiode.

When light enters the photodiode PD,
Photocharge is generated, and the charge is stored in the gate of the MOS transistor T1. Here, the MOS transistor T3
When the MOS transistor T3 is turned on by applying a pulse signal φV to the gate of the MOS transistor T1, a current proportional to the charge of the gate of the MOS transistor T1 is led out to the output signal line through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read. After the signal is read, the MOS transistor T3 is turned off and the MO
By turning on the S transistor T2, the gate voltage of the MOS transistor T1 can be initialized.

[0005]

As described above, the conventional M
The OS-type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and stored in the gate of the MOS transistor as it is, so the dynamic range is narrow, and therefore, the exposure amount must be precisely controlled. In addition, even if the exposure amount is precisely controlled, dark portions are blackened and bright portions are saturated. On the other hand, the present applicant has disclosed a photosensitive means capable of generating a photocurrent corresponding to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias means for biasing the MOS transistor to a state in which a subthreshold current can flow. Prepared,
A solid-state imaging device in which a photocurrent is subjected to logarithmic compression conversion has been proposed (see Japanese Patent Application Laid-Open No. 3-192664).

[0006] Although such a solid-state imaging device has a wide dynamic range, it has a problem that the characteristics and S / N ratio in the case of low luminance are not sufficient. Although such a solid-state imaging device has a wide dynamic range, the threshold characteristics of MOS transistors provided for each pixel may be different, and the sensitivity may be different for each pixel. Therefore, it is necessary to take measures such as holding the output obtained by previously irradiating bright light (uniform light) with uniform luminance as correction data for correcting the output of each pixel when the subject is imaged. .

However, there are problems that it is complicated for the operator to irradiate each pixel using an external light source, and that the exposure cannot be uniformly performed well. Further, when the uniform light irradiation mechanism is provided in the imaging device, there is a problem that the configuration of the imaging device becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a solid-state imaging device capable of imaging a wide range of objects from high luminance to low luminance with high definition. It is another object of the present invention to provide a solid-state imaging device capable of switching between a wide dynamic range state and a narrow dynamic range state using the same photoelectric conversion means. Another object of the present invention is to provide a solid-state imaging device capable of accurately obtaining correction data for correcting the output of each pixel at the time of imaging a subject without previously irradiating uniform light. . Still another object of the present invention is to provide a solid-state imaging device in which the initial state of each pixel is made substantially the same, thereby suppressing the variation in sensitivity of each pixel.

[0009]

According to a first aspect of the present invention, there is provided a solid-state imaging device comprising: a photoelectric conversion unit having a photoelectric conversion element for generating an electric signal corresponding to an amount of incident light; A plurality of pixels each including a lead-out path for leading an output signal of the unit to an output signal line, wherein an operation state of the photoelectric conversion unit is a first state in which the electric signal is linearly converted, and a natural logarithmic conversion is performed. And a detecting means for detecting a variation in the sensitivity of each of the pixels.

According to the solid-state imaging device having such a configuration,
By switching the operation state of the photoelectric conversion means according to the luminance state of the subject and the environment at the time of imaging, it is possible to appropriately change the dynamic range to the optimal dynamic range. Also, when any output state is selected, variations in sensitivity of each pixel can be detected, and high-quality imaging can be performed. As the detecting means, a means including a current source and a switch for electrically connecting and disconnecting the current source and the photoelectric conversion means can be used.

According to a third aspect of the present invention, there is provided a solid-state imaging device, comprising: a photoelectric conversion unit having a photoelectric conversion element for generating an electric signal according to the amount of incident light; and an output signal of the photoelectric conversion unit is led to an output signal line. In a two-dimensional solid-state imaging device in which pixels having lead-out paths are arranged in a matrix, the photoelectric conversion unit includes a photoelectric conversion element having a DC voltage applied to a second electrode, a first electrode and a second electrode. An electrode and a control electrode;
An electrode includes a first transistor connected to a first electrode of the photoelectric conversion element, a first electrode, a second electrode, and a control electrode. A DC voltage is applied to the first electrode, and the control electrode is connected to the first electrode. Connected to the second electrode of the first transistor,
A second transistor that outputs an electric signal from the electrode, a current source having a DC voltage applied to one end, and one end connected to the other end of the current source, and the other end connected to the second electrode of the first transistor. And a switch connected to a connection node of a control electrode of the second transistor. By changing a voltage applied to a control electrode of the first transistor, the operation state of the photoelectric conversion unit is changed by the electric signal. It is possible to switch between a first state for linear conversion and a second state for natural logarithmic conversion, and when performing an imaging operation,
The switch is turned off, and the switch is turned on when detecting a variation in the sensitivity of each pixel.

According to the solid-state imaging device having such a configuration,
The dynamic range can be changed according to the luminance state of the subject and the environment at the time of imaging. For example, in the case where a photocharge generated by a photodiode is converted by using a MOS transistor, when this MOS transistor is operated in a sub-threshold region equal to or less than a threshold, a logarithmic conversion state (second state) is obtained and a large dynamic range can be obtained. However, when imaging a moving subject at low brightness,
In the logarithmic conversion operation, an afterimage easily occurs.

In the logarithmic conversion operation, the electrical signal generated by the photodiode is logarithmically converted in real time and output from the MOS transistor when the MOS transistor is in the ON state. This is because the charge stored in the parasitic capacitance of the photodiode connected to is not discharged, and the previous information remains. This is particularly noticeable when the brightness is low. In logarithmic conversion, since the conversion output is generally small, the S / N ratio (signal / noise ratio) is poor.

On the other hand, the MOS transistor is
In the linear conversion state (first state) in the F state, the dynamic range is narrow, but the signal output from the photoelectric conversion means is large, so that the S / N ratio is good.

Therefore, to image a subject over a wide range from low luminance to high luminance, the photoelectric conversion means is switched to the second state (logarithmic conversion) and used to image a low-luminance object or a narrow-luminance object. It is preferable that the photoelectric conversion means be switched to the first state (linear conversion) before use.

On the other hand, the solid-state imaging device repeatedly performs an imaging operation and a reset operation as in an imaging device for a video movie, for example, to capture a moving image even when light is incident on the photoelectric conversion element. By turning on the switch connected to the current source, the voltage applied to the first or second transistor can be made less susceptible to light incident on the photoelectric conversion element, and the sensitivity variation of each pixel can be reduced. It can be detected quickly. Therefore, in order to obtain correction data for correcting the output of each pixel at the time of imaging the subject, it is not necessary to irradiate uniform light as in the related art, and it is obtained when irradiating uniform light. There is no need to keep recording correction data.

Further, as in the solid-state image pickup device according to the fourth aspect, the switch is turned on, and the current source and the first
By connecting to the second electrode of the transistor of
A variation in sensitivity of each pixel is detected, and an output signal at the time of imaging is corrected using the signal obtained at this time.

Further, when the photoelectric conversion means operates in the first state, the switch is turned on and the control electrode of the second transistor is set at a constant level for all pixels. By applying a reset voltage that is a voltage value, variations in the sensitivity of each pixel are detected,
Further, when the photoelectric conversion means operates in the second state, the switch is turned on, and the current flowing through the first transistor by the current source is set to a constant current value for all pixels. Detect sensitivity variations. At this time, the voltage applied to the current source is changed when the photoelectric conversion unit is operated in the first state and when the photoelectric conversion unit is operated in the second state.

Further, as described in claim 6, the switch is a transistor, and a signal is applied to a control electrode of the switch to turn on / off the connection between the first transistor and the current source.

Further, as in the solid-state imaging device according to claim 7, each of the pixels has an amplifying transistor for amplifying an output signal of the photoelectric conversion means, and the output signal of the amplifying transistor is derived. When the signal is output to the output signal line via the path, the signal from each pixel is read in a large and stable state.

Further, as set forth in claim 8, in the solid-state image pickup device according to claim 7, the solid-state imaging device may include a load resistor or a constant current source connected to the output signal lines, the total number of which is less than the total number of pixels. It may be a solid-state imaging device. By providing the load resistance or the constant current source, a current signal output from each pixel can be read as a voltage signal. In such a solid-state imaging device, claim 9
As described in the above, the load resistor or the constant current source has a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control electrode connected to a DC voltage. It may be a transistor.

[0022] In the solid-state imaging device according to claim 9,
When the amplifying transistor is an N-channel MOS transistor, a DC voltage applied to a first electrode of the amplifying transistor may be:
The potential may be higher than a DC voltage connected to the load resistor or the second electrode of the transistor serving as a constant current source.
When the amplifying transistor is a P-channel MOS transistor, a DC voltage applied to a first electrode of the amplifying transistor is used as the load resistance or a constant current source. The potential may be lower than the DC voltage connected to the second electrode of the transistor.

Further, in the solid-state imaging device according to any one of claims 3 to 11, as described in claim 12, a predetermined one is sequentially selected from all pixels in the lead-out path. By providing a switch for leading a signal amplified from a selected pixel to an output signal line, a signal output from each pixel to the output signal line can be sequentially read and output as serial data.

The solid-state imaging device according to the present invention is: (1) In a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode, a first electrode, a second electrode, and a gate electrode. A first MOS transistor to which an electric signal output from the photodiode is input to a second electrode, a second MOS transistor having a gate electrode connected to a second electrode of the first MOS transistor, and a DC voltage at one end. An applied current source; one end of the current source; a second electrode of the first MOS transistor;
A switch connected between the gate electrode of the MOS transistor, and a natural logarithmic conversion of an electric signal output from the photodiode to output from the second electrode of the second MOS transistor. The first M
After the OS transistor is operated in a sub-threshold region equal to or less than the threshold value and an electric signal is output, the switch is turned on, and a constant current is caused to flow through the first MOS transistor by the current source. When detecting a variation in sensitivity of a pixel due to a voltage and linearly converting an electric signal output from the photodiode to output from a second electrode of the second MOS transistor, a gate electrode of the first MOS transistor is used. The first MOS transistor is turned off by switching the level of the voltage input to the first MOS transistor, and after outputting the electric signal, the switch is turned on to apply the voltage applied to the current source to the gate of the second MOS transistor. It is characterized in that it is applied to an electrode and reset.

In such a solid-state imaging device, (2)
The switch is a transistor, and a signal is supplied to a control electrode of the switch to turn on / off the connection between the first MOS transistor and the current source. (3) The switch is connected to the first electrode of the first MOS transistor. The first MOS transistor is connected to a connection node between a second electrode and a gate electrode of the second MOS transistor, the second electrode being a MOS transistor connected to the current source, and applying a signal to a control electrode of the MOS transistor. A connection node between the second electrode and the control electrode of the second MOS transistor is turned ON / OFF with the current source.

In the solid-state imaging device according to any one of (1) to (3), (4) the pixel has a first electrode connected to a DC voltage and a gate electrode connected to a second electrode of the second MOS transistor. A configuration may be employed in which a third MOS transistor is connected and amplifies the output signal output from the second electrode of the second MOS transistor.
In the solid-state imaging device having such a configuration, (5) the pixel has a first electrode connected to a second electrode of the third MOS transistor, a second electrode connected to an output signal line, and a gate electrode connected to a row selection line. Is provided, and this fourth MOS transistor can be used as a switch for row selection.

In the solid-state imaging device according to (4) or (5), (6) the pixel has one end connected to the second electrode of the second MOS transistor and the other end connected to the second electrode of the first MOS transistor. And a capacitor that is connected to the first signal line and reset via the second MOS transistor when a reset voltage is applied to the first electrode of the second MOS transistor. With such a configuration, the signal output from the pixel becomes a signal once integrated by the capacitor.
Fluctuation components of the light source and high frequency noise are absorbed and removed by the capacitor. Further, by applying a reset voltage to a first electrode of the second MOS transistor,
The charge in the capacitor is released through the MOS transistor and reset.

In the solid-state imaging device having such a configuration,
(7) The second MOS transistor may be a MOS transistor having a polarity opposite to that of the first MOS transistor.

(8) In the pixel, the second M
A first electrode of the OS transistor is connected to a DC voltage, and a first electrode is connected to a second electrode of the second MOS transistor.
Fifth M having an electrode connected and a DC voltage connected to the second electrode
One end is connected to an OS transistor and a second electrode of the second MOS transistor, and the other end is connected to a signal line connected to a second electrode of the first MOS transistor, and a reset voltage is applied to a gate electrode of the fifth MOS transistor. And a capacitor that is reset via the fifth MOS transistor when is supplied. With such a configuration, the signal output from the pixel becomes a signal once integrated by the capacitor, so that the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor. Further, by applying a reset voltage to the gate electrode of the fifth MOS transistor,
The charge in the capacitor is released through the fifth MOS transistor and reset.

In the solid-state imaging device having such a configuration,
(9) The second and fifth MOS transistors are connected to the first MOS transistor.
The MOS transistor may have a polarity opposite to that of the MOS transistor.

(1) The solid-state imaging device according to any one of (1) to (9), further including a MOS transistor forming a load resistor or a constant current source connected to the pixel via the output signal line. It is characterized by.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <Example of Pixel Configuration> FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. In the figure, G11 to Gm
n indicates pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, and rows (lines) 4-1 and 4
.., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 to 6-2,.
.. The photoelectric conversion signals derived in 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. Also, the constant current sources 9-1, 9-2,..., 9-m are connected to the pixel G11 via the current supply lines 8-1, 8-2,. ~ G1n, G21 ~ G2n, ..., Gm1 ~ Gmn
To supply current. Line 7 to which DC voltage VPS is supplied
, 7-2,..., 7-n are connected to pixels G11 to Gm1, G12 to Gm2,. For each pixel, the lines 4-1 and 4-2.
, 4-n and lines 7-1, 7-2, ..., 7-n
, 6-m, the current supply lines 8-1, 8-2,..., 8-m, the power supply line 5, and other lines (for example, , Clock lines and bias supply lines) are also connected, but these are omitted in FIG.

The output signal lines 6-1, 6-2,.
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. Output signal line 6-1
The gate of the MOS transistor Q1 is connected to the DC voltage line 11, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '. On the other hand, MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 10, and the gate is connected to the horizontal scanning circuit 3.
It is connected to the.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. FIG. 2A shows the connection between the MOS transistor Ta and the MOS transistor Q1. This MO
The S transistor Ta corresponds to the fifth MOS transistor T5 in the first to third embodiments, and corresponds to the second MOS transistor T2 in the fourth embodiment. Where MOS
DC voltage VPS 'connected to the source of transistor Q1
And the DC voltage VPD 'connected to the drain of the MOS transistor Ta is VPD'> VPS ', and the DC voltage VPS' is, for example, a ground voltage (ground). In this circuit configuration, a signal is input to the gate of the upper MOS transistor Ta, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower MO
The S transistor Q1 is equivalent to a resistor or a constant current source,
The circuit in FIG. 2A is a source follower type amplifier circuit. In this case, what is amplified and output from the MOS transistor Ta may be a current.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, an N-channel fourth MOS transistor T4 for switching is also provided in the pixel of each of the embodiments shown in FIGS. If this MOS transistor T4 is also included, the circuit of FIG. 2A is exactly as shown in FIG. 2B. That is, the MOS transistor T4 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T4 selects a row, and the MOS transistor Q2 selects a column. The configuration shown in FIGS. 1 and 2 is a configuration common to the first to fourth embodiments described below.

With the configuration as shown in FIG. 2, a large signal gain can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the output signal lines 6-1, 6-2,... To which a plurality of pixels arranged in the column direction are connected without providing the MOS transistor Q1 constituting the load resistance portion of the amplifier circuit in the pixel. The provision of each 6-m can reduce the number of load resistances or constant current sources, and reduce the area occupied by the amplifier circuit on the semiconductor chip.

<First Embodiment> A first embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 3 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment.

In FIG. 3, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The cathode of the photodiode PD is connected to a first MOS transistor T1.
And the gate of the second MOS transistor T2. The drain of the third MOS transistor T3 and the fifth MOS transistor are connected to the source of the MOS transistor T2.
The gate of the transistor T5 is connected. This MO
The drain of the fourth MOS transistor T4 is connected to the source of the S transistor T5, and the source of the MOS transistor T4 is connected to the output signal line 6 (this output signal line 6 is
1, 6-2,..., 6-m). The MOS transistors T1 to T5 are N-channel MOS transistors, and have a back gate grounded.

Further, a DC voltage VPS is applied to the anode of the photodiode PD. On the other hand, M
The DC voltage VPD is applied to the drain of the OS transistor T1, and the signal φVPG is applied to the gate. M
The source of the OS transistor T2 has a DC voltage VPS at the other end.
Is connected to one end of a capacitor C to which is applied, and this connection node is defined as a. The DC voltage VPD is applied to the drain of the MOS transistor T2. The signal φV is input to the gate of the MOS transistor T4. Furthermore, MO
DC voltage V RB is applied to the source of S transistor T3, and signal φVRS is applied to its gate. M
DC voltage VD is applied to the drain of OS transistor T5. Then, a connection node b between the source of the MOS transistor T1 and the cathode of the photodiode PD and a constant current source 9 (the constant current sources 9 are 9-1, 9-2,...
, 9-m). Further, a signal φVSS is applied to the constant current source 9.

In this embodiment, the voltage value of the signal φVPG is switched to turn on / off the MOS transistor T1.
By doing so, the output signal led out to the output signal line 6 in a single pixel is natural logarithmic with respect to an electric signal (hereinafter, referred to as “photocurrent”) output by the photodiode PD in accordance with the incident light. The case where the conversion is performed and the case where the conversion is performed linearly can be realized. Hereinafter, each of these cases will be described.

The voltage of the signal φVPG for operating the MOS transistor T1 in the sub-threshold region is a first voltage, and the voltage of the signal φVPG for turning off the MOS transistor T1 is a second voltage. As for the signal φVSS applied to the constant current source 9, the voltage of the signal φVSS for flowing a current to the MOS transistor T1 when detecting pixel variation is the third voltage, and the gate voltage of the MOS transistor T2 when resetting is performed. Signal φV for raising
The voltage of SS is defined as a fourth voltage.

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, the voltage of the signal φVSS is set to the third voltage. (1-a) Imaging Operation First, using the signal φVPG as the first voltage, the MOS transistor T1 is operated in the sub-threshold region, the switch SW is turned off, and the constant current source 9
The state is not connected to the connection node b between the source of the transistor T1 and the cathode of the photodiode PD. At this time, when light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T1 and the gate of the MOS transistor T2. appear. At this time, since the negative photocharge generated in the photodiode PD flows into the source of the MOS transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which changes in a natural logarithm with respect to the photocurrent appears at the gate of the MOS transistor T2, a high-level signal φVRS is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3. Then, the voltages of the capacitor C and the connection node a are reset. At this time, the voltage of the connection node a is reset to a voltage lower than the surface potential determined by the gate voltage of the MOS transistor T2 so that the MOS transistor T2 can operate. Next, the signal φV
Set RS to low level to turn off MOS transistor T3
After that, the signal φV is set to the high level to turn on the MOS transistor T4.

When the voltage at the connection node a is reset by the MOS transistor T3, the MOS transistor T2 operates, and the voltage obtained by sampling the surface potential determined by the gate voltage of the MOS transistor T2 is applied to the gate of the MOS transistor T5. Given. Therefore, the gate voltage of the MOS transistor T5 becomes a value proportional to the value obtained by logarithmically converting the amount of incident light.
When the S transistor T4 is turned on, a current having a value obtained by natural logarithmically converting the photocurrent is led to the output signal line 6 via the MOS transistors T4 and T5. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(1-b) Sensitivity Variation Detection FIG. 4 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. As described above, after the pulse signal φVRS is supplied to the gate of the MOS transistor T3 to reset the voltage of the connection node a, the pulse signal φV is supplied to the gate of the MOS transistor T4, and the output signal is read. First, the switch SW is turned on to connect the constant current source 9 to the connection node b.
Note that, as described above, the signal φVSS is set to the third voltage so that a large current flows from the MOS transistor T1 to the constant current source 9. In this case, the MOS transistor T1
In order for a large current to flow from the
The voltage can be lower than the DC voltage VPS.

At this time, since the current flowing through the constant current source 9 is sufficiently larger than the photocurrent generated by the photodiode PD, the current flowing through the MOS transistor T1 is substantially equal to the current flowing through the constant current source 9. It can be. Therefore, the voltage appearing at the connection node b at this time is determined by the current flowing through the constant current source 9 and becomes a voltage corresponding to the variation in the threshold value of the MOS transistor T1 of each pixel. Then, a pulse signal φVRS is supplied to the gate of the MOS transistor T3 to reset the voltage of the connection node a. Thereafter, a pulse signal φV is supplied to the gate of the MOS transistor T4, and the output signal amplified by the MOS transistor T5 is read.

At this time, the output signal read out is an output signal in a state where the intense light artificially generated by the constant current source 9 is incident.
Since the signal flows through the OS transistor T1, the signal indicates a variation in sensitivity. Then, when the operation of detecting the variation in sensitivity is completed, finally, the next imaging operation can be performed.
Turn off the switch SW. The signal obtained by the detection of the variation in sensitivity is stored as correction data in a memory such as a line memory, and for each pixel, the output signal at the time of actual imaging is corrected using this correction data, thereby obtaining an output signal. , Components due to pixel variations can be removed.

Further, as described above, by operating each MOS transistor for each pixel, the MOS
When a signal at the time of resetting the gate voltage of the transistor T1 is output to the output signal line 6, the signal at the time of resetting is output serially and stored in a subsequent circuit in a memory as correction data for each pixel. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal.

(2) When the photocurrent is linearly converted and output. At this time, the signal φVPG is always set to the second voltage, and the MOS transistor T1 is always turned off.
The MOS transistor T2 serves as a signal amplification transistor. The voltage of the signal φVSS is set to the fourth voltage.

(2-a) Imaging Operation First, the switch SW is turned off, and the constant current source 9
The state is not connected to the connection node b between the gate of the S transistor T2 and the cathode of the photodiode PD. At this time, when a photocurrent flows through the photodiode PD, the gate voltage of the MOS transistor T2 changes. That is, a negative photocharge is given from the photodiode PD to the gate of the MOS transistor T2,
The gate voltage of the transistor T2 becomes a value linearly changed with respect to the photocurrent. At this time, the negative photocharge generated in the photodiode PD is transferred to the MOS transistor T2.
Flows into the gate, the more the strong light is incident, the more MO
The gate voltage of S transistor T2 decreases.

When a voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T2, a high-level signal φVRS is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3.
Then, the voltages of the capacitor C and the connection node a are reset. At this time, the voltage of the connection node a is set so that the MOS transistor T2 can operate.
Is reset to a voltage lower than the surface potential determined by the gate voltage of. Next, after the signal φVRS is set to the low level to turn off the MOS transistor T3, the signal φV is set to the high level to set the MOS transistor T3.
Turn 4 ON.

When the voltage at the connection node a is reset by the MOS transistor T3, the MOS transistor T2 operates, and the voltage obtained by sampling the surface potential determined by the gate voltage of the MOS transistor T2 is applied to the gate of the MOS transistor T5. Given. Therefore, since the gate voltage of the MOS transistor T5 becomes a value proportional to the value obtained by integrating the amount of incident light, when the MOS transistor T4 is turned on, the current that becomes a value obtained by linearly converting the photocurrent is the MOS transistor T4. ,
It is led to the output signal line 6 via T5. When a signal (output current) proportional to the value of the amount of incident light is read in this way, the MOS transistor T4 is turned off.

(2-b) Reset Operation FIG. 5 shows a timing chart of each signal when the reset operation of each pixel is performed. As described above, the pulse signal φ
After VRS is applied to the gate of MOS transistor T3 to reset the voltage at connection node a, pulse signal φV
Is supplied to the gate of the MOS transistor T4, and the output signal is read out. First, the switch SW is turned on to connect the constant current source 9 to the connection node b. When the switch SW is turned on, the signal φ is applied to the gate of the MOS transistor T2 via the constant current source 9 and the switch SW.
VSS is applied, and the gate voltage of MOS transistor T2 is reset. At this time, as described above,
In order to reset the gate voltage of the MOS transistor T2 to a high voltage, the signal φVSS is set to a fourth voltage higher than the DC voltage VPS.

Next, the pulse signal φVRS is applied to the gate of the MOS transistor T3 to reset the voltage at the connection node a, and then the output signal is read by applying the pulse signal φV to the gate of the MOS transistor T4. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T2, and is read as the output signal when initialized. When the output signal is read, the above-described imaging operation is performed again.

The signal thus initialized is stored in a memory such as a line memory as correction data, and the output signal at the time of actual image pickup is corrected for each pixel by using this correction data. A component due to pixel variation can be removed from the output signal. When switching the output conversion operation of the pixel to the logarithmic conversion operation or the linear conversion operation, first, the voltage value of the signal φVSS is switched to the third voltage and the fourth voltage, respectively, and the respective conversion operations are performed. By performing the above-described variation detection operation, each pixel is reset, and then the above-described imaging operation is performed.

The switch S used in the pixel of the present embodiment is
FIG. 6 shows a configuration using a MOS transistor for W.
That is, a sixth MOS transistor T6 serving as a substitute for the switch SW is provided. The drain of the MOS transistor T6 is connected to the connection node b, the source is connected to the constant current source 9, and the signal φS is connected to the gate of the MOS transistor T6. Is entered. When performing the imaging operation, the MOS
A low-level signal φS is applied to the gate so as to turn off the transistor T6, and a high-level signal is applied to the gate so as to turn on the MOS transistor T6 when performing a variation detection operation or a reset operation. φS
Is given.

<Second Embodiment> A second embodiment will be described with reference to the drawings. FIG. 7 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 7, in this embodiment, the MO
By applying the signal φVPD to the drain of the S transistor T2, the potentials of the capacitor C and the connection node a are initialized, whereby the MOS transistor T3
Has been removed. Other configurations are the same as those of the first embodiment (FIG. 6). During the high level period of the signal φVPD, integration is performed by the capacitor C. During the low level period, the charge of the capacitor C is discharged through the MOS transistor T2, and the voltage of the capacitor C and the MO
The gate of the S transistor T5 substantially becomes a low level voltage of the signal φVPD (reset). In the present embodiment, the configuration is simplified because the MOS transistor T3 can be omitted.

At this time, as in the first embodiment, the MO
The voltage of the signal φVPG for operating the S transistor T1 in the subthreshold region is a first voltage, and the voltage of the signal φVPG for turning off the MOS transistor T1 is a second voltage. As for the signal φVSS applied to the constant current source 9, the voltage of the signal φVSS for flowing a current to the MOS transistor T1 when detecting pixel variation is the third voltage, and the gate voltage of the MOS transistor T2 when resetting is performed. The voltage of the signal φVSS for raising is set as a fourth voltage.

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, the voltage of the signal φVSS is set to the third voltage. (1-a) Imaging Operation Using the signal φVPG as the first voltage, the MOS transistor T1
Is operated in the sub-threshold region and MO
The signal φS applied to the gate of the S transistor T6 is set to low level, and the MOS transistor T6 is turned off. At this time, when light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T1 and the gate of the MOS transistor T2. appear. At this time, since the negative photocharge generated in the photodiode PD flows into the source of the MOS transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which changes in a natural logarithm with respect to the photocurrent appears at the gate of the MOS transistor T2, the signal φVPD is first set to a low level (a voltage lower than the signal φVPS), and the voltage of the capacitor C is reduced. The charge is discharged to the signal line of the signal φVPD through the MOS transistor T2, thereby resetting the voltage of the capacitor C and the connection node a. At this time, the voltage of the connection node a is set to M
Reset is performed so that the voltage becomes lower than the surface potential determined by the gate voltage of the MOS transistor T2 so that the OS transistor T2 can operate. Next, after the signal φVPD is set to the high level (for example, a voltage substantially equal to the DC voltage VPD), the signal φV is set to the high level to set the MOS φ
The transistor T4 is turned on.

At this time, the voltage of the connection node a becomes the signal φV
The reset by the PD causes the MOS transistor T2 to operate, and a voltage obtained by sampling the surface potential determined by the gate voltage of the MOS transistor T2 is applied to the gate of the MOS transistor T5.
Therefore, since the gate voltage of the MOS transistor T5 becomes a value proportional to the value obtained by logarithmically converting the amount of incident light, when the MOS transistor T4 is turned on, the current that becomes a value obtained by natural logarithmically converting the photocurrent is a MOS current. Transistor T
4, and are led out to the output signal line 6 via T5. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(1-b) Sensitivity Variation Detection FIG. 8 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. As described above, after the pulse signal φVPD is supplied to the drain of the MOS transistor T2 and the voltage at the connection node a is reset, the pulse signal φV is supplied to the gate of the MOS transistor T4, and the output signal is read. First, the signal φS is set to high level to turn on the MOS transistor T6, thereby connecting the constant current source 9 to the connection node b.
Note that, as described above, the signal φVSS is set to the third voltage so that a large current flows from the MOS transistor T1 to the constant current source 9.

At this time, similarly to the first embodiment, a current substantially equal to the current flowing through the constant current source 9 flows through the MOS transistor T1. Therefore, the voltage appearing at the connection node b at this time is determined by the current flowing through the constant current source 9 and becomes a voltage corresponding to the variation in the threshold value of the MOS transistor T1 of each pixel. Then, a pulse signal φVPD is applied to the drain of the MOS transistor T2 to reset the voltage of the connection node a. Thereafter, a pulse signal φV is supplied to the gate of the MOS transistor T4, and the output signal amplified by the MOS transistor T5 is read.

At this time, the read output signal is
Since the value depends on the threshold voltage of the S transistor T1,
As a result, it is possible to detect variations in the sensitivity of each pixel. Finally, the signal φS is set to the low level so that the next imaging operation can be performed.
Turn 6 OFF. A signal obtained by detecting the variation in sensitivity thus detected is stored as correction data in a memory such as a line memory, and an output signal at the time of actual imaging is corrected for each pixel using the correction data. Accordingly, it is possible to remove components due to pixel variations from the output signal.

(2) A case where a photocurrent is linearly converted and output. At this time, similarly to the first embodiment, the signal φVPG is always set to the second voltage, and the MOS transistor T1 is always turned off.
In this state, the MOS transistor T2 functions as a signal amplification transistor. The voltage of the signal φVSS is set to the fourth voltage.

(2-a) Imaging Operation First, as in the first embodiment, by setting the signal φS to low level and turning off the MOS transistor T6, the constant current source 9 turns on the MOS transistor T2. The state is not connected to the connection node b between the gate and the cathode of the photodiode PD. At this time, when a photocurrent flows through the photodiode PD, the gate voltage of the MOS transistor T2 changes. That is, the photoelectric charge more negative than the photodiode PD causes the MOS transistor T
2 and the gate voltage of the MOS transistor T2 becomes a value linearly changed with respect to the photocurrent.
At this time, since the negative photocharge generated in the photodiode PD flows into the gate of the MOS transistor T2, the gate voltage of the MOS transistor T2 decreases as more intense light enters.

When a voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T2, first, a low-level signal φVPD is applied to the drain of the MOS transistor T2, and the signal φVPD is supplied through the MOS transistor T2. To discharge the signal φVPD to reset the voltage of the capacitor C and the connection node a. Next, after the signal φVPD is set to the high level, the signal φV is set to the high level to turn on the MOS transistor T4.

Then, the connection node a is reset and M
Since the voltage is lower than the surface potential determined by the gate voltage of the OS transistor T2, the MOS
The transistor T2 operates, and the MOS transistor T
A voltage obtained by sampling the surface potential determined by the gate voltage of No. 2 is applied to the gate of the MOS transistor T5. Therefore, the gate voltage of the MOS transistor T5 becomes a value proportional to the value obtained by integrating the amount of incident light.
When the MOS transistor T4 is turned on, a current having a value obtained by linearly converting the photocurrent is led out to the output signal line 6 via the MOS transistors T4 and T5. When a signal proportional to the value of the incident light amount is read out in this manner,
Turn off the MOS transistor T4.

(2-b) Reset Operation FIG. 9 shows a timing chart of each signal when the reset operation of each pixel is performed. As described above, the pulse signal φ
After VPD is applied to the drain of MOS transistor T2 to reset the voltage at connection node a, pulse signal φ
When V is applied to the gate of the MOS transistor T4 and the output signal is read, first, the signal φS is set to the high level to turn on the MOS transistor T6. As described above, when the MOS transistor T6 is turned on, the fourth voltage is applied to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T2 is reset, as in the first embodiment. When the gate voltage of MOS transistor T2 is reset in this manner, signal φS
To low level, turning off MOS transistor T6
To

Next, after a pulse signal φVPD is applied to the drain of the MOS transistor T2 to reset the voltage of the connection node a, a pulse signal φV is applied to the gate of the MOS transistor T4 to read an output signal. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T2, and is read as the output signal when initialized. When the output signal is read, the above-described imaging operation is performed again.

The signal thus initialized is stored as correction data in a memory such as a line memory, and the output signal at the time of actual imaging is corrected for each pixel using this correction data. A component due to pixel variation can be removed from the output signal.

<Third Embodiment> A third embodiment will be described with reference to the drawings. FIG. 10 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 10, in this embodiment, the MOS transistors T2 and T3 in the pixel of the first embodiment (FIG. 6) are P-channel MOS transistors,
The DC voltage VPS is applied to the drain of the MOS transistor T2, and the DC voltage VPS is applied to the other end of the capacitor C having one end connected to the source of the MOS transistor T2.
PD is applied. A DC voltage V RB is applied to the drain of the MOS transistor T3, and the gate of the MOS transistor T5 is connected to its source. The other configuration is the same as the configuration of the pixel in FIG. Note that the DC voltage V RB applied to the source of the MOS transistor T3 is
The voltage is higher than VPS.

At this time, as in the first embodiment, the MO
The voltage of the signal φVPG for operating the S transistor T1 in the subthreshold region is a first voltage, and the voltage of the signal φVPG for turning off the MOS transistor T1 is a second voltage. As for the signal φVSS applied to the constant current source 9, the voltage of the signal φVSS for flowing a current to the MOS transistor T1 when detecting pixel variation is the third voltage, and the gate voltage of the MOS transistor T2 when resetting is performed. The voltage of the signal φVSS for raising is set as a fourth voltage.

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, the voltage of the signal φVSS is set to the third voltage. Then, using the signal φVPG as the first voltage, the MOS transistor T1 is operated in the sub-threshold region, and the signal φS given to the gate of the MOS transistor T6 is set to low level, so that the MOS transistor T6
Is turned off.

(1-a) Sensitivity Variation Detection FIG. 11 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. When the pulse signal φV is M
When the output signal is given to the gate of the OS transistor T4 and read out, as in the first embodiment (FIG. 6),
First, the signal φS is set to high level to turn on the MOS transistor T6, thereby connecting the constant current source 9 to the connection node b. As described above, a large current flows from the MOS transistor T1 to the constant current source 9,
Signal φVSS is set to the third voltage.

At this time, as in the first embodiment, a current substantially equal to the current flowing through the constant current source 9 flows through the MOS transistor T1. Therefore, the voltage appearing at the connection node b at this time is determined by the current flowing through the constant current source 9 and becomes a voltage corresponding to the variation in the threshold value of the MOS transistor T1 of each pixel. Then, a pulse signal φVRS is supplied to the gate of the MOS transistor T3 to reset the voltage of the connection node a. Thereafter, a pulse signal φV is supplied to the gate of the MOS transistor T4, and the output signal amplified by the MOS transistor T5 is read. Note that M
A pulse signal φV applied to the gate of the OS transistor T3
RS is a low-level pulse signal.

At this time, the read output signal is
Since the value depends on the threshold voltage of the S transistor T1,
As a result, it is possible to detect variations in the sensitivity of each pixel. Finally, the signal φS is set to the low level so that the next imaging operation can be performed.
After turning off the transistor 6, the pulse signal φVRS is supplied to the gate of the MOS transistor T3 to reset the voltage of the connection node a. A signal obtained by detecting the variation in sensitivity thus detected is stored as correction data in a memory such as a line memory, and an output signal at the time of actual imaging is corrected for each pixel using the correction data. Accordingly, it is possible to remove components due to pixel variations from the output signal.

(1-b) Imaging Operation As described in the reset operation, the MOS transistor T
The image pickup operation is started when the pulse signal φVRS is applied to the gate of No. 3 and the voltage of the connection node a and the capacitor C are reset. At this time, when light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T1 and the gate of the MOS transistor T2. appear. At this time, the negative photocharge generated in the photodiode PD is M
Since the current flows into the source of the OS transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which changes in a natural logarithmic manner with respect to the photocurrent appears at the gate of the MOS transistor T2, the connection node a is reset and is higher than the surface potential determined by the gate voltage of the MOS transistor T2. Since the voltage is a voltage, a positive charge flows from the capacitor C via the MOS transistor T2. At this time, by the gate voltage of the MOS transistor T2,
The amount of positive charge flowing from the capacitor C is determined. That is, the amount of positive charge flowing from the capacitor C increases as the source voltage of the MOS transistor T1 decreases as the strong light enters.

As described above, the positive charge flows from the capacitor C, and the voltage at the connection node a becomes a value proportional to the value obtained by logarithmically converting the integrated value of the incident light amount. And the pulse signal φ
When V is applied to turn on the MOS transistor T4,
A current having a value obtained by converting the integral value of the photocurrent into a natural logarithm is led out to the output signal line 6 via the MOS transistors T4 and T5. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(2) A case where a photocurrent is linearly converted and output. At this time, similarly to the first embodiment, the signal φVPG is always set to the second voltage, and the MOS transistor T1 is always turned off.
In this state, the MOS transistor T2 functions as a signal amplification transistor. The voltage of the signal φVSS is set to the fourth voltage. First, as in the first embodiment, the signal φS is set to the low level, and the MOS transistor T6 is turned off.
Is not connected to the connection node b between the gate of the photodiode PD and the cathode of the photodiode PD.

(2-a) Reset Operation FIG. 12 shows a timing chart of each signal when each pixel is reset. When the pulse signal φV is applied to the gate of the MOS transistor T4 and the output signal is read, first, the signal φS is set to the high level to turn on the MOS transistor T6. When the MOS transistor T6 is turned on in this manner, as in the first embodiment,
The fourth voltage is applied to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T2 is reset. Then, when the gate voltage of the MOS transistor T2 is reset as described above, the signal φS is set to low level, and the MOS transistor T6 is turned off.

Next, after a pulse signal φVRS is applied to the gate of the MOS transistor T3 to reset the voltage of the connection node a, a pulse signal φV is applied to the gate of the MOS transistor T4 to read an output signal. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T2, and is read as the output signal when initialized. When the output signal is read, M
After the pulse signal φVRS is supplied to the gate of the OS transistor T3 to reset the voltage of the connection node a, the imaging operation is performed. The pulse signal φVRS is a low-level pulse signal.

The signal thus initialized is stored in a memory such as a line memory as correction data, and an output signal at the time of actual image pickup is corrected for each pixel by using this correction data. A component due to pixel variation can be removed from the output signal.

(2-b) Imaging Operation As described in the reset operation, the MOS transistor T
The image pickup operation is started when the pulse signal φVRS is applied to the gate of No. 3 and the voltage of the connection node a and the capacitor C are reset. At this time, when a photocurrent flows through the photodiode PD, the gate voltage of the MOS transistor T2 changes. That is, a negative photocharge is given from the photodiode PD to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T2 becomes a value that changes linearly with respect to the photocurrent. At this time, since the negative photocharge generated in the photodiode PD flows into the gate of the MOS transistor T2, the gate voltage of the MOS transistor T2 decreases as more intense light enters.

When a voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T2, the connection node a is reset and a voltage higher than the surface potential determined by the gate voltage of the MOS transistor T2 is obtained. , A positive charge flows from the capacitor C via the MOS transistor T2. At this time, the amount of positive charge flowing from the capacitor C is determined by the gate voltage of the MOS transistor T2. That is,
The more positive light is incident and the lower the gate voltage of the MOS transistor T2, the greater the amount of positive charges flowing from the capacitor C.

As described above, the positive charge flows from the capacitor C, and the voltage at the connection node a becomes a value proportional to the integral value of the incident light amount. When the MOS transistor T4 is turned on by applying the pulse signal φV, a current which is a value obtained by linearly converting the integrated value of the photocurrent is led out to the output signal line 6 via the MOS transistors T4 and T5. You. When the signal (output current) proportional to the integral value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

Note that, as in the second embodiment (FIG. 7), M
The structure is such that a pulse signal (for example, φVPS) is applied to the drain of the OS transistor T2.
The connection node a from the MOS transistor T2 by PS
May be configured so that the MOS transistor T3 is omitted from the pixel having the configuration shown in FIG. In this case, the pulse signal φVPS applied to the drain of the MOS transistor T2 is supplied from a power supply line different from the DC voltage VPS applied to the anode of the photodiode PD.

<Fourth Embodiment> A fourth embodiment will be described with reference to the drawings. FIG. 13 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 13, in this embodiment, M
The DC voltage VPD is applied to the drain of the OS transistor T2, and the capacitor C and the MOS transistors T3 and T5 are omitted. Other configurations are the same as those of the first embodiment (FIG. 6).

At this time, as in the first embodiment, the MO
The voltage of the signal φVPG for operating the S transistor T1 in the subthreshold region is a first voltage, and the voltage of the signal φVPG for turning off the MOS transistor T1 is a second voltage. As for the signal φVSS applied to the constant current source 9, the voltage of the signal φVSS for flowing a current to the MOS transistor T1 when detecting pixel variation is the third voltage, and the gate voltage of the MOS transistor T2 when resetting is performed. The voltage of the signal φVSS for raising is set as a fourth voltage.

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, the voltage of the signal φVSS is set to the third voltage. (1-a) Imaging Operation Using the signal φVPD as the first voltage, the MOS transistor T1
Is operated in the sub-threshold region and MO
The signal φS applied to the gate of the S transistor T6 is set to low level, and the MOS transistor T6 is turned off. At this time, when light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T1 and the gate of the MOS transistor T2. appear. At this time, since the negative photocharge generated in the photodiode PD flows into the source of the MOS transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which has changed in a natural logarithmic manner with respect to the photocurrent appears at the gate of the MOS transistor T2, a pulse signal φV is supplied to turn on the MOS transistor T4, and the photocurrent is naturally logarithmically changed. Is output to the output signal line 6 via the MOS transistors T2 and T4. When a signal (output current) proportional to the logarithmic value of the incident light amount is read out in this manner,
Turn off the MOS transistor T4.

(1-b) Sensitivity Variation Detection FIG. 14 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. As described above, when the pulse signal φV is applied to the gate of the MOS transistor T4 and the output signal is read, first, as in the first embodiment (FIG. 6), the signal φS is set to the high level, and M
By turning on the OS transistor T6, the constant current source 9 is connected to the connection node b. Note that, as described above, the signal φVSS is set to the third voltage so that a large current flows from the MOS transistor T1 to the constant current source 9.

At this time, as in the first embodiment, a current substantially equal to the current flowing through the constant current source 9 flows through the MOS transistor T1. Therefore, the voltage appearing at the connection node b at this time is determined by the current flowing through the constant current source 9 and becomes a voltage corresponding to the variation in the threshold value of the MOS transistor T1 of each pixel. Thus, when a current flows through the MOS transistor T1, the MOS transistor T1
The pulse signal φV is applied to the gate of No. 4 to read the output signal.

At this time, the read output signal is
Since the value depends on the threshold voltage of the S transistor T1,
As a result, it is possible to detect variations in the sensitivity of each pixel. Finally, the signal φS is set to the low level so that the next imaging operation can be performed.
Turn 6 OFF. A signal obtained by detecting the variation in sensitivity thus detected is stored as correction data in a memory such as a line memory, and an output signal at the time of actual imaging is corrected for each pixel using the correction data. Accordingly, it is possible to remove components due to pixel variations from the output signal.

(2) A case where a photocurrent is linearly converted and output. At this time, similarly to the first embodiment, the signal φVPG is always set to the second voltage, and the MOS transistor T1 is always turned off.
In this state, the MOS transistor T2 functions as the signal amplification transistor T1.
The voltage of the signal φVSS is set to the fourth voltage.

(2-a) Imaging Operation First, as in the first embodiment, by setting the signal φS to low level and turning off the MOS transistor T6, the constant current source 9 turns on the MOS transistor T2. The state is not connected to the connection node b between the gate and the cathode of the photodiode PD. At this time, when a photocurrent flows through the photodiode PD, the gate voltage of the MOS transistor T2 changes. That is, the photoelectric charge more negative than the photodiode PD causes the MOS transistor T
2 and the gate voltage of the MOS transistor T2 becomes a value linearly changed with respect to the photocurrent.
At this time, since the negative photocharge generated in the photodiode PD flows into the gate of the MOS transistor T2, the gate voltage of the MOS transistor T2 decreases as more intense light enters.

When a voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T2, a pulse signal φV is supplied to the MOS transistor T2.
Turn 4 ON. At this time, a current that is a value obtained by linearly converting the integrated value of the photocurrent is a MOS transistor T
2, and output to the output signal line 6 via T4. When the signal (output current) proportional to the integral value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(2-b) Reset Operation FIG. 15 shows a timing chart of each signal when each pixel is reset. As described above, the pulse signal φV
Is supplied to the gate of the MOS transistor T4 to read out the output signal. First, the signal φS is set to the high level to turn on the MOS transistor T6. As described above, when the MOS transistor T6 is turned on, the fourth gate is connected to the gate of the MOS transistor T2 as in the first embodiment.
The voltage is applied, and the gate voltage of the MOS transistor T2 is reset. Then, the signal φS is set to the low level again to turn off the MOS transistor T6.

Next, a pulse signal φV is applied to the gate of the MOS transistor T4 to read an output signal. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T2, and is read as the output signal when initialized. When the output signal is read, the above-described imaging operation is performed again. The signal initialized at this time is stored as correction data in a memory such as a line memory, and for each pixel, the output signal at the time of actual imaging is corrected using this correction data, so that the output signal is Components due to pixel variations can be removed.

In this embodiment, as in the first to third embodiments, the optical signal is not once integrated by the capacitor C, so that the integration time becomes unnecessary.
Further, since it is not necessary to reset the capacitor C, the signal processing can be speeded up accordingly. In the present embodiment, the first
As compared with the third embodiment, since the capacitor C and the MOS transistor T5 can be omitted, the configuration is further simplified and the pixel size can be reduced.

In the first to fourth embodiments described above, signal reading from each pixel is performed by using a charge-coupled device (CC).
D) may be used. in this case,
By providing a potential barrier with a variable potential level corresponding to the MOS transistor T4,
What is necessary is just to read the electric charge to CCD.

In the first to fourth embodiments, when performing the linear conversion operation, the connection node b is reset by turning on the switch SW or the sixth MOS transistor T6 and applying the fourth voltage of the signal φVSS. I have done,
The connection node b may be reset by turning on the first MOS transistor T1. At this time, a signal φD whose voltage becomes the first voltage during the logarithmic conversion operation and becomes the fourth voltage during the linear conversion operation is applied to the drain of the first MOS transistor T1. At this time, the design of the subsequent stage is optimized so that the signal reading in the subsequent stage is not hindered, so that the potential of the connection node a falls within a predetermined voltage range between the reset period and the logarithmic output operation period. The signal φD
May be a fixed value.

In the first, second and fourth embodiments described above, all the MOS transistors T1 to T6, which are active elements in the pixel, are constituted by N-channel MOS transistors. Transistors T1 to T6
May be constituted by P-channel MOS transistors. In the third embodiment, the N-channel MOS transistor in the pixel may be replaced with a P-channel MOS transistor, and the P-channel MOS transistor may be replaced with an N-channel MOS transistor.

FIGS. 18 to 21 show fifth to eighth embodiments in which the MOS transistors of the pixels of the first to fourth embodiments are constituted by MOS transistors of opposite polarities. Therefore, the polarity of the connection and the polarity of the applied voltage are reversed in FIGS. For example, in FIG. 18 (fifth embodiment), the photodiode PD has a cathode connected to the DC voltage VPS and an anode connected to the first MOS transistor.
The source of the transistor T1 is connected to the gate of the second MOS transistor. First MOS transistor T1
The DC voltage VPD is input to the drain of.

When a pixel as shown in FIG. 18 performs logarithmic conversion, the voltage of the DC voltage VPS and the DC voltage VPD are
PS> VPD, which is the reverse of FIG. 6 (first embodiment). The output voltage of the capacitor C is a voltage having a high initial value and drops by integration. Further, a third MOS transistor T3, a fourth MOS transistor T4, and a sixth
When turning on the OS transistor T6, a low voltage is applied to the gate. Further, in the embodiment of FIG. 20 (seventh embodiment), the third MOS transistor T3 is
When N is applied, a high voltage is applied to the gate. As described above, when the MOS transistors having the opposite polarities are used, although the voltage relationship and the connection relationship are partially different, the configuration is substantially the same, and the basic operation is the same.
FIG. 21 is shown only in the drawing, and the description of its configuration and operation is omitted.

FIG. 16 is a block circuit configuration diagram for explaining the overall configuration of a solid-state imaging device including pixels according to the fifth to eighth embodiments. In FIG. 16, the same portions (same role portions) as those in FIG. Hereinafter, the configuration of FIG. 16 will be briefly described.
The output signal lines 6-1, 6-2,... Arranged in the column direction
., P-channel MOS transistor Q for 6-m
1 and a P-channel MOS transistor Q2 are connected. The gate of the MOS transistor Q1 is a DC voltage line 1
1, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, and the source is the final signal line 10.
, And the gate is connected to the horizontal scanning circuit 3. Here, the MOS transistor Q1 forms an amplification circuit as shown in FIG. 17A together with the P-channel MOS transistor Ta in the pixel. The MOS transistor Ta corresponds to the fifth MOS transistor T5 in the fifth to seventh embodiments, and corresponds to the second MOS transistor T5 in the eighth embodiment.
This corresponds to the OS transistor T2.

In this case, MOS transistor Q1 is connected to MO
It serves as a load resistance or a constant current source for the S transistor Ta. Therefore, the relationship between DC voltage VPS 'connected to the source of transistor Q1 and DC voltage VPD' connected to the drain of MOS transistor Ta is VPD '<V
PS ′, and the DC voltage VPD ′ is, for example, a ground voltage (ground). The drain of the transistor Q1 is connected to the transistor Ta, and a DC voltage is applied to the gate. The P-channel MOS transistor Q2 is controlled by the horizontal scanning circuit 3, and leads the output of the amplifier circuit to the final signal line 10. Considering the fourth MOS transistor T4 provided in the pixel as in the fifth to eighth embodiments, the circuit in FIG. 17A is represented as in FIG. 17B.

[0112]

As described above, according to the solid-state imaging device of the present invention, whether an electric signal generated by a photosensitive element such as a photodiode is logarithmically converted or output or linearly converted and output. Can be freely selected. So, for example,
Switching to logarithmic conversion is used for imaging a subject with a wide luminance range, and switching to linear conversion is used for imaging a low-luminance subject or a subject with a narrow luminance range. Thus, a wide range of subjects from low luminance to high luminance can be imaged with high accuracy.

Further, according to the solid-state imaging device of the present invention, when any output state is selected, the variation in sensitivity of each pixel can be detected, and high-quality imaging can be performed. By configuring the active element with a MOS transistor, high integration is facilitated, and the active element can be formed on a single chip together with peripheral processing circuits (A / D converter, digital system processor, memory) and the like.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram of a part of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 4 is a timing chart of a signal applied to each element of a pixel used in the first embodiment.

FIG. 5 is a timing chart of a signal applied to each element of a pixel used in the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 8 is a timing chart of signals applied to each element of a pixel used in the second embodiment.

FIG. 9 is a timing chart of a signal applied to each element of a pixel used in the second embodiment.

FIG. 10 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 11 is a timing chart of a signal applied to each element of a pixel used in the third embodiment.

FIG. 12 is a timing chart of a signal applied to each element of a pixel used in the third embodiment.

FIG. 13 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 14 is a timing chart of a signal applied to each element of a pixel used in the fourth embodiment.

FIG. 15 is a timing chart of a signal applied to each element of a pixel used in the fourth embodiment.

FIG. 16 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case where an active element in a pixel is configured by a P-channel MOS transistor.

FIG. 17 is a circuit diagram of a part of FIG. 16;

FIG. 18 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 21 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a configuration of one pixel of a conventional example.

[Explanation of symbols]

 G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line 7-1 to 7-n line 8-1 to 8-m current supply line 9-1 to 9-m constant current source 10 signal line 11 DC voltage line 12 line PD photodiode T1 to T6 first to sixth MOS transistors C capacitor SW switch

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AA06 AB01 BA14 CA03 DD09 DD11 DD12 FA06 FA50 5C024 AX01 CX27 CX43 CY16 EX03 GX03 GY38 GY39 GZ02 HX17 HX35 HX40 HX41 HX50

Claims (12)

[Claims] A plurality of pixels each including a photoelectric conversion unit having a photoelectric conversion element for generating an electric signal corresponding to the amount of incident light, and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line; The operation state of the photoelectric conversion means can be switched between a first state in which the electric signal is converted linearly and a second state in which the electric signal is converted logarithmically, and a detection for detecting a variation in sensitivity of each pixel. A solid-state imaging device comprising means. 2. The solid-state imaging device according to claim 1, wherein the detection unit includes a current source, and a switch that electrically connects and disconnects the current source and the photoelectric conversion unit. 3. A matrix comprising: a pixel having photoelectric conversion means having a photoelectric conversion element for generating an electric signal corresponding to the amount of incident light, and a lead-out path for leading an output signal of the photoelectric conversion means to an output signal line. In a two-dimensional solid-state imaging device, the photoelectric conversion unit includes: a photoelectric conversion element in which a DC voltage is applied to a second electrode; a first electrode, a second electrode, and a control electrode; Comprises a first transistor connected to a first electrode of the photoelectric conversion element, a first electrode, a second electrode, and a control electrode. A DC voltage is applied to the first electrode, and the control electrode is connected to the first electrode. A second transistor that is connected to a second electrode of the transistor and outputs an electric signal from the second electrode; a current source having one end to which a DC voltage is applied; one end connected to the other end of the current source; The other end is first
And a switch connected to a connection node between the second electrode of the transistor and the control electrode of the second transistor. The operation of the photoelectric conversion unit is performed by changing a voltage applied to the control electrode of the first transistor. The state can be switched between a first state in which the electric signal is converted linearly and a second state in which the electric signal is converted logarithmically. When an imaging operation is performed, the switch is turned off. Wherein the switch is turned on when detecting a variation in the sensitivity of the solid-state imaging device. 4. The method according to claim 1, wherein the switch is turned on to connect the current source to a second electrode of the first transistor, and a signal output at this time is a signal representing a variation in sensitivity of each pixel. The solid-state imaging device according to claim 3, wherein: 5. When the photoelectric conversion means operates in the first state, the switch is turned on when detecting a variation in sensitivity of a pixel, and a control electrode of the second transistor is kept constant for all pixels. When the photoelectric conversion means operates in the second state, the switch is turned on when detecting the variation in the sensitivity of the pixel, and the first transistor is turned on. A constant current is supplied to a current source so that a flowing current becomes a constant current value for all pixels, and the current source is supplied when the photoelectric conversion unit is operated in a first state and when the photoelectric conversion unit is operated in a second state. The solid-state imaging device according to claim 3, wherein a voltage applied to the solid-state imaging device is changed. 6. The solid-state imaging device according to claim 3, wherein said switch is a transistor. 7. Each of the pixels has an amplifying transistor for amplifying an output signal of the photoelectric conversion means, and outputs an output signal of the amplifying transistor to the output signal line via the output path. The solid-state imaging device according to claim 3, wherein: 8. The solid state according to claim 7, further comprising a load resistor or a constant current source connected to the output signal line, wherein the total number of the load resistors or the constant current source is smaller than the total number of pixels. Imaging device. 9. The load resistor or the constant current source has a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control electrode connected to a DC voltage. The solid-state imaging device according to claim 8, wherein the solid-state imaging device is a transistor for use. 10. The amplifying transistor is an N-channel MOS transistor, and a DC voltage applied to a first electrode of the amplifying transistor is lower than a DC voltage connected to a second electrode of the resistor transistor. The solid-state imaging device according to claim 9, wherein the solid-state imaging device has a high potential. 11. The amplifying transistor is a P-channel MOS transistor, and a DC voltage applied to a first electrode of the amplifying transistor is lower than a DC voltage connected to a second electrode of the resistor transistor. The solid-state imaging device according to claim 9, wherein the solid-state imaging device has a low potential. 12. The method according to claim 3, wherein the derivation path includes a switch for sequentially selecting a predetermined one from all the pixels and deriving a signal amplified from the selected pixel to an output signal line. The solid-state imaging device according to claim 11.