JP2003258149A - Wiring structure of area layout type semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a wiring structure of an area arrangement type semiconductor device which can easily draw out wiring from each land of a printed board on which an area arrangement type semiconductor element is mounted. A plurality of bumps arranged in a grid pattern are formed on a mounting portion of a CSP, and a plurality of lands are formed on a printed board corresponding to the bumps. When a plurality of lands 4 are connected to increase the current capacity of the lands 4 arranged in a lattice, the lands 4a existing in the outer row and the lands 4a existing in the inner row are connected to each other. 9
b, and are drawn out to the periphery of the CSP 1 by one wiring 9a. Thus, the possibility that the connection wiring 9b intersects with the wiring 9 drawn from another land 4 can be reduced, and the wiring 9 can be drawn from each land 4 easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure in an area-arranged semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a plurality of bumps are arranged in a grid pattern on a mounting surface of an area-arranged semiconductor element, and the plurality of bumps are bonded to a plurality of lands formed on a printed circuit board, respectively. The area-arranged semiconductor device is mounted on a printed circuit board. At this time, the plurality of bumps and the plurality of lands have a one-to-one correspondence, and each one of the bumps and the lands connects the semiconductor element and the wiring of the printed circuit board to the power supply terminal, the GND terminal, and the input.・ Functions as terminals such as output terminals.

The wiring connected to the land of the printed circuit board is drawn around the area-arranged semiconductor element. In this case, the printed board is configured as a multi-layered board in order to easily draw out from the lands belonging to the inner peripheral row of the plurality of lands arranged in a grid pattern, and the lands belonging to the inner peripheral row are once dropped to the lower layer. And is configured to pull out the wiring. However, if the number of layers is equal to the number of rows of lands arranged in a grid pattern, the number of layers of the multilayer substrate increases,
Lead wires from lands belonging to a plurality of columns are formed per layer.

[0004]

As described above, one land is assigned to each bump of the conventional area-arranged semiconductor device. However, depending on the circuit scale of the semiconductor element and the type of signal to be transmitted, it may be necessary to increase the current capacity of terminals such as the power supply terminal, the GND terminal, and the output terminal.

In order to increase the current capacity of the terminal, it is possible to construct one terminal from a plurality of bumps and a plurality of lands. However, FIG. 9 (a), (b),
As shown in (c), a plurality of bumps 3 forming one terminal
a and a plurality of lands 4a are assigned to the outermost row,
The wiring 9 cannot be pulled out from the land 4 belonging to the column on the inner peripheral side. In this case, it is necessary to increase the number of layers of the printed board in order to draw out the wiring 9 from the land 4 belonging to the row on the inner peripheral side, which causes an increase in the manufacturing cost of the printed board. 9A is a plan view showing the arrangement of bumps on the mounting surface of the area-arranged semiconductor element.
FIG. 9B is an array diagram showing an array of lands on the first layer of the printed circuit board, and FIG. 9C is an array diagram showing an array of lands on the second layer of the printed circuit board.

The present invention has been made in view of the above points,
Even if a plurality of lands are connected to one wiring, the wiring structure of the area-arranged semiconductor device in which the wiring can be easily pulled out from the lands belonging to the column on the inner peripheral side without increasing the number of layers of the printed circuit board is provided. The purpose is to provide.

[0007]

In order to achieve the above object, the wiring structure of an area-arranged semiconductor device according to claim 1 has an area arrangement in which a plurality of bumps are arranged in a grid on a mounting surface of a package. Type semiconductor element and an area arrangement including a printed board having a plurality of lands as connection terminals electrically connected to the bumps and wirings respectively connected to the plurality of lands, which are formed in the same grid shape as the bumps When at least two lands are connected to one wiring in the semiconductor device of the type, at least two lands are connected to a land belonging to a row on the outer peripheral side of a plurality of lands arranged in a grid pattern. It is characterized in that it consists of lands belonging to the row on the circumferential side.

When at least two lands are connected to one wiring in this manner, the lands are not allocated only to the outer peripheral row, but at least one land is allocated to the inner peripheral row. Select from the land to which you belong. In this case, the two lands are connected by wiring, but since the connection wiring is not for lands belonging to the same column but for lands belonging to different columns, the connection wiring is pulled out from each land. It is possible to reduce the possibility that the wiring will intersect with the wiring. This makes it possible to easily draw out the wiring from each land.

As described in claim 2, the row on the outer peripheral side and the row on the inner peripheral side each having at least two lands connected to one wiring are adjacent to each other. Is preferred. In this way, when the lands on the outer peripheral side and the lands on the inner peripheral side are connected by wiring, since the rows are adjacent to each other, the connecting wiring between the lands can be short. Therefore,
Since it is possible to suppress the reduction of the space of the lead wiring that passes between the lands as much as possible, it is possible to connect the wiring to the lands belonging to the inner peripheral row. Further, the wiring distance itself can be short, which is advantageous in terms of cost and quality.

As described in claim 3, an area-arranged semiconductor element in which a plurality of bumps are arranged in a grid on the mounting surface of the package and a grid similar to the bumps are formed and electrically connected to the bumps. In an area-arranged semiconductor device including a plurality of lands as connection terminals and a printed circuit board having wirings respectively connected to the plurality of lands, at least two lands are connected to one wiring. In this case, the at least two lands are characterized by being composed only of lands belonging to an inner peripheral side row surrounded by an outermost peripheral row of a plurality of lands arranged in a grid pattern.
When the lands belonging to the outermost row are connected to each other, the connection wiring affects the extraction of the wiring from all the lands located on the inner circumference side. On the other hand, when the lands belonging to the row on the inner peripheral side are connected to each other, there are no lands on the inner peripheral side of the connected lands, or the lands are small in number even if they exist. Therefore, if at least two lands belonging to the column on the inner peripheral side are connected to one wiring, the wiring can be easily pulled out from other lands.

As described in claim 4, at least 2
It is preferable that each land belongs to a row on the inner peripheral side surrounded by the outermost row of a plurality of lands arranged in a grid pattern, and is composed of adjacent lands in the same row. As a result, the connection wiring between at least two lands can be short, and the influence exerted on the drawing of the wiring from other lands can be further reduced.

As described in claim 5, the row on the inner peripheral side is
It is preferable to have a plurality of rows, and the at least two lands thereof be lands belonging to at least two adjacent rows in the plurality of rows on the inner peripheral side. Also for this, the connection wiring between at least two adjacent lands can be short,
Moreover, since the direction of the connection wiring is not perpendicular to the direction of the wiring drawn from the other land, the possibility that the connection wiring intersects the drawn wiring from the other land can be further reduced.

According to claim 6, at least 2
It is preferable that the individual lands include lands that belong to different rows and that are arranged vertically to the rows. In this way, at least two lands include lands arranged in the vertical direction with respect to the rows arranged in a grid pattern,
When the lands are connected by wiring, the direction of the connecting wiring is the same as the direction of the lead-out wiring from other lands. As a result, it is possible to further reduce the possibility that the connection wiring intersects with the wiring extending from another land.

According to a seventh aspect of the present invention, an area-arranged semiconductor element in which a plurality of bumps are arranged in a grid pattern on the mounting surface of the package and a grid pattern similar to the bumps are formed and electrically connected to the bumps. When connecting at least two lands to one wiring in an area-arranged semiconductor device including a plurality of lands as connection terminals and a printed circuit board having wirings respectively connected to the plurality of lands In addition, the at least two lands are composed of a land located at a corner of an outermost row of a plurality of lands arranged in a grid and a land adjacent to the land located at the corner.

Thus, at least two lands are
If the land is located at the corner of the outermost row of lands arranged in a grid pattern and the land adjacent to it, the connection wiring between the lands is short, and the land on the inner circumference side surrounded by the outermost row is surrounded. The corner lands existing in the row have four wiring lead-out points between the lands of the outermost row, and the wiring can be selected from these locations. Therefore, the wiring can be drawn from the land belonging to the inner row. It can be done easily.

According to claim 8, at least 2
The wiring connecting the individual lands has a line width larger than that of the wiring connected to the other lands.

As described above, when the wiring having the thick line width is formed between the lands and the individual lands, the respective wiring pitches are shortened, the insulation resistance is affected, and the lands from the lands belonging to the column on the inner peripheral side are affected. There is no space for wiring. Further, when the thin line width is joined to a plurality of lands, the line width is thin even if an attempt is made to pass a large current, the resistance value increases, and the current does not flow sufficiently. However, by adopting the wiring structure as described above, it is possible to connect a plurality of lands with a thick wiring, and there is no influence on the drawing of the wiring from other lands belonging to the inner peripheral side column.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A wiring structure of an area-arranged semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an area-arranged semiconductor device according to this embodiment. The area-arranged semiconductor device is a CSP (Chip Size Packa).
ge) 1 and the like, and the printed circuit board 2 made of glass epoxy resin or the like. CSP
1 has a plurality of bumps 3 arranged in a grid on its mounting surface as connection terminals, and the printed circuit board 2 has lands 4 at the ends of a conductor pattern made of Cu as connection terminals. As the printed board 2, a build-up printed wiring board is used in which the core layer is the center and the insulating layers and the conductor wiring layers are repeatedly formed so as to be alternately stacked to form a multilayer. Since wiring is performed with the plurality of lands 4 formed on the surface of the printed board 2, via holes 5, through holes 6, core vias 7 and the like are formed between the layers of the printed board 2.

Here, for mounting the CSP 1 on the printed board 2, the CSP 1 is mounted on the printed board 2 so that the lands 4 of the printed board 2 and the bumps 3 of the CSP 1 overlap each other.
In that state, reflow soldering is performed. The bumps 3 are solder balls, and lead-tin eutectic solder is used as the material thereof. Its melting point is 183 ° C. Further, in this example, the arrangement of the bumps 3 is 4
A total of 144 solder balls in rows are mounted on the mounting surface. Although the reflow condition at this time varies depending on the bump pitch and the bump diameter, the peak temperature is about 230 ° C. on the surface of the package because the solder bump 3 is melted.

On the other hand, the lands 4 on the printed circuit board 2 are connected to wirings, and the respective wirings are connected to external terminals such as a power source and a ground or to other elements on the printed circuit board 2. The space between the CSP 1 and the printed circuit board 2 is sealed with a filling resin 8, and epoxy resin or the like is used as the material. Here, as an example of the area-arranged semiconductor device, CS
P1 was mentioned, but other than that, BGA (Ball Gr
id Array), FC (Flip Chip), etc. can be applied.

FIG. 2A shows the bumps 3 on the mounting surface of the CSP 1.
2 (b) is a plan view showing the arrangement, FIG. 2 (b) is a diagram showing the wiring structure of the lands 4 on the first layer of the printed circuit board 2 and the wiring 9 connected to each land 4, and FIG. It is a figure which shows the arrangement | positioning of the land 4 in the 2nd layer of the board | substrate 2. FIG. 2B and 2C, focusing on one side of the lattice of the mounting surface of the CSP 1 in FIG. 2A,
The lands 4 and the wirings 9 of the first and second layers of the printed circuit board 2 corresponding to the bumps 3 existing in the region surrounded by the four-row 36-dotted line are shown. Also surrounded by a solid line 3
The individual bumps 3a correspond to the three lands 4a connected to the single wiring 9a shown in FIG. 2B. In this example, the bumps 3 of the CSP 1 and the printed circuit board 2 are all used.
The land 4 of 1 corresponds to 1: 1.

The land 4b which cannot be connected to the wiring 9 on the first layer of the printed circuit board 2 is transferred to the second layer by land on via, and the connection to the wiring 9 is made on the second layer. Done. At this time, as a method of forming a via hole used for transfer from the first layer to the second layer, CO ₂ or UV is used.
-Laser processing such as YAG is used.

Here, when a plurality of (three in this example) lands 4 of the printed circuit board 2 are connected to one wiring, as shown in FIG. It is preferable to use not only four lands 4 but also three lands 4a including lands 4 belonging to the inner circumferential side row. One such land 3a
When connected to the book wiring 9a, the direction of the connection wiring 9b between the outermost row land 4a and the land 4a on the inner circumferential side is vertical or oblique to each row of the lands 4. Therefore,
Since it is possible to prevent the wiring 9 drawn from each land 4 and the connection wiring 9b from intersecting each other, it is possible to easily draw the wiring from another land 4. The lands 4b that could not be wired in the first layer are transferred to the second layer of the printed circuit board 2 through the via holes 7 as shown in FIGS. 2B and 2C. Then, in the second layer, the land 4 and the wiring 9 are connected.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (c).

Since the method of joining the CSP 1 and the printed circuit board 2 in the second embodiment is common to that in the first embodiment, the detailed description of the common parts will be omitted and the different parts will be focused. Explained.

The second embodiment differs from the first embodiment in that at least two lands 4a (three in this example) connected to one wiring 9a are adjacent to each other. Is to exist. Here, FIG. 3A shows C
It is a plan view showing an array of bumps 3 on the mounting surface of SP1,
FIG. 3B is a diagram showing a wiring structure of the lands 4 on the first layer of the printed circuit board 2 and the wiring 9 connected to each land 4, and FIG. 3C is a land on the second layer of the printed circuit board 2. It is a figure which shows the arrangement | sequence of 4.

As shown in FIGS. 3 (a) to 3 (c), 1
The land 4a connected to the book wiring 9a is composed of a land 4a belonging to the outermost row and a land 4a belonging to the inner row, and each land 4a is present in an adjacent row. In this case, as in the case of FIGS. 2A to 2C, the direction of the connection wiring 9b between the lands of the lands 4a connected to one wiring 9a is the same as the direction of each column of the lands 4. Instead, it is either vertical or diagonal to each row. Therefore, the wiring 9 can be easily pulled out from the other land 4. Furthermore,
According to the present embodiment, since the wiring distance between each land 4a connected to one wiring 9a is short, the wiring 9 can be more easily drawn from the other land 4, which is also advantageous in terms of cost.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. 4 (a) to 4 (c).

Since the method of joining the CSP 1 and the printed circuit board 2 in the third embodiment is common to that in the first embodiment, the detailed description of the common parts will be omitted below, and the different parts will be emphasized. Explained.

The third embodiment differs from the first embodiment in that at least two lands 4a (three in this example) connected to one wiring 9a are each land 4. It is composed of lands 4a positioned in the vertical direction with respect to the rows. 4A is a plan view showing the arrangement of the bumps 3 on the mounting surface of the CSP 1, and FIG. 4B is a land 4 on the first layer of the printed board 2 and wirings connected to each land 4. 9 is a view showing the wiring structure of FIG. 9, and FIG. 4C is a view showing the arrangement of the lands 4 in the second layer of the printed board 2.

As shown in FIGS. 4 (a) to 4 (c),
Since the three lands 4a, which are the lands 4 belonging to the outermost row and the lands 4 belonging to the two rows on the inner circumference side, are located in the vertical direction with respect to each row of the lands 4, these lands 4a are connected to each other. The connecting wirings 9b to be connected are also vertical to each column of the lands 4. Therefore, since the connection wiring 9b coincides with the drawing direction of the wiring 9 from the other land 4, the connection wiring 9b and the drawing wiring 9 from the other land 4 do not intersect at all, and the connection wiring 9b from the other land 4 does not intersect. The wiring 9 can be pulled out more easily. Further, since the wiring distance between each land 4a connected to one wiring 9a is short, it is advantageous in terms of cost.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 5 (a) to 5 (c).

Since the method for joining the CSP 1 and the printed circuit board 2 in the fourth embodiment is common to that in the first embodiment, the detailed description of the common parts will be omitted below, and the different parts will be focused. Explained.

The fourth embodiment differs from the first embodiment in that at least two lands 4a (three in this example) connected to one wiring 9a are the outermost rows. It does not include the lands 4 belonging to, but is composed only of the lands 4a belonging to the inner circumferential row. Note that FIG. 5A shows CSP1.
5 is a plan view showing the arrangement of the bumps 3 on the mounting surface of FIG.
FIG. 5B is a diagram showing the wiring structure of the lands 4 on the first layer of the printed board 2 and the wiring 9 connected to each land 4, and FIG. 5C is the land 4 on the second layer of the printed board 2.
It is a figure which shows the arrangement | sequence of.

As shown in FIGS. 5 (a) -5 (c),
Since the three lands 4a connected to one wiring 9a are composed only of the lands 4a belonging to the innermost row, the land 4a between all the lands 4 of the lands 4 belonging to the outermost row It is possible to draw out the wiring 9 of the other land 4 belonging to the column. In this way, even if the lands 4a belonging to the column on the inner peripheral side are connected, the influence on the lead-out of the wiring 9 from the other lands 4 is small. Further, regarding the lands 4a connected by the connection wirings 9b, the number of the wirings 9a drawn out between the lands 4 belonging to the row on the outer peripheral side is only one, so that wirings 9 from more lands 4 in the same layer can be connected. You can withdraw.

(Fifth Embodiment) Next, the fifth embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 6A to 6C.

Since the method of joining the CSP 1 and the printed circuit board 2 in the fifth embodiment is common to that in the first embodiment, the detailed description of the common parts will be omitted and the different parts will be focused. Explained.

The fifth embodiment differs from the first embodiment in that at least two (3 in this example) lands 4a connected to one wiring 9a are the outermost row. The land 4 belonging to the inner peripheral side is not included, and each land 4a is formed of the adjacent lands 4a in the same row. In addition, FIG. 6A shows a CSP.
7 is a plan view showing the arrangement of the bumps 3 on the mounting surface of FIG.
FIG. 6B is a diagram showing the wiring structure of the lands 4 on the first layer of the printed board 2 and the wiring 9 connected to each land 4, and FIG. 6C is the land 4 on the second layer of the printed board 2.
It is a figure which shows the arrangement | sequence of.

As shown in FIGS. 6 (a) to 6 (c),
The land 4 belonging to the outermost row is not included, but the three adjacent lands 4a belonging to the same row on the inner circumference side are connected to one wiring 9.
When connected to a, the direction of the connection wiring 9b between each land 4a is the same as the arrangement direction of the lands 4. For that reason,
When the number of lands 4a connected to one wiring 9a is 3 or more, a portion intersecting with the drawing direction of the wiring 9 from the lands 4 belonging to the column on the inner peripheral side is further formed. However, since the land 4 existing on the inner peripheral side of the land 4a connected by the connection wiring 9b can be dropped to the second layer to draw out the wiring, even if the land 4a on the inner peripheral side is connected, The influence on the drawing of the wiring 9 of the land 4 is small. Further, since the wiring distance between each land 4a connected to one wiring 9a can be shortened, the wiring 9 can be easily pulled out from the other land 4, which is advantageous in terms of cost.

(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 7 (a) to 7 (c).

Since the method of joining the CSP 1 and the printed circuit board 2 in the sixth embodiment is common to that in the first embodiment, the detailed description of the common parts will be omitted below, and the different parts will be emphasized. Explained.

The sixth embodiment differs from the first embodiment in that at least two (three in this example) lands 4a connected to one wiring 9a are the outermost rows. This is a point which does not include the lands 4 belonging to the above, but is composed of the lands 4a belonging to the inner circumferential row and belonging to the adjacent row. 7A is a plan view showing an arrangement of the bumps 3 on the mounting surface of the CSP 1, and FIG. 7B is a land 4 on the first layer of the printed circuit board 2 and wirings connected to each land 4. 9 is a view showing the wiring structure of FIG. 9, and FIG. 7C is a view showing the arrangement of the lands 4 in the second layer of the printed board 2.

Here, as shown in FIGS. 7A to 7C, the lands 4a belonging to the column on the inner peripheral side and adjacent to two columns are connected to each other by the connection wiring 9b between the lands 4a. The direction is vertical or oblique with respect to the column direction, and thus does not intersect with the lead-out of the wiring 9 from another land 4. Furthermore, since only the lands 4a belonging to the column on the inner peripheral side are connected by the connection wirings 9b, the influence on the wirings 9 drawn from the other lands 4 is small.

(Seventh Embodiment) Next, the seventh embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 8 (a) to 8 (c).

Since the method of joining the CSP 1 and the printed circuit board 2 in the seventh embodiment is common to that in the first embodiment, the detailed description of the common parts will be omitted and the different parts will be focused. Explained.

The seventh embodiment differs from the first embodiment in that at least two lands 4a (three in this example) connected to one wiring 9a are the outermost rows. Is to include the land 4 of the corner belonging to. 8A is a plan view showing the arrangement of the bumps 3 on the mounting surface of the CSP 1, and FIG. 8B is a first view of the printed circuit board 2 in the area surrounded by the one-dot chain line in FIG. 8A. The figure which shows the wiring structure of the land 4 and the wiring 9 connected to each land 4 in a layer, FIG.8 (c) is the 2nd layer of the printed circuit board 2 in the area | region enclosed by the dashed-dotted line of FIG.8 (a). Land 4 at
It is a figure which shows the arrangement | sequence of.

As shown in FIGS. 8 (a) to 8 (c), even if the land 4a at the corner existing in the outermost row and the adjacent lands 4a on both sides thereof are connected by the connection wiring 9b,
The corner lands 4 belonging to the column on the inner peripheral side are connected to the lands 4a at the corners belonging to the outermost column because there are usually four locations where the wiring 9 is pulled out from the land 4. It is not easily affected by the wiring 9b.
Therefore, even if the land 4a belonging to the outermost row is included,
The wiring 9 can be easily pulled out from the land 4 belonging to the column on the inner peripheral side.

In any of the first to seventh embodiments described above, the connection wiring 9b between at least two lands 4a has a line width thicker than the wiring 9 drawn from the other lands 4. be able to. In this way, when the wiring 9 having a thick line width is formed between the individual lands 4, the wiring pitches are shortened, the insulation resistance is affected, and the lands 4 belonging to the inner circumferential side are arranged. There is no space to draw out the wiring 9. Further, when the thin line width is bonded to the plurality of lands 4, the line width is small even if an attempt is made to pass a large current, the resistance value increases, and the current does not sufficiently flow. However, by adopting the wiring structure as described above, the plurality of lands 4a are connected by the thick connection wiring 9b to increase the current capacity and influence the extraction of the wiring 9 from the land 4 belonging to the inner peripheral side. There is no.

[Brief description of drawings]

FIG. 1 is a sectional view of an area-arranged semiconductor device according to a first embodiment.

FIG. 2 shows a wiring structure according to the first embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 3 shows a wiring structure according to a second embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 4 shows a wiring structure according to a third embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 5 shows a wiring structure according to a fourth embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 6 shows a wiring structure according to a fifth embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 7 shows a wiring structure according to a sixth embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 8 shows a wiring structure according to a seventh embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

FIG. 9 shows a wiring structure according to an eighth embodiment,
(A) is a plan view showing an arrangement of bumps on a mounting surface of a CSP,
(B) is an array diagram showing an array of lands on the first layer of the printed board, and (c) is an array diagram showing an array of lands on the second layer of the printed board.

[Explanation of symbols]

1 ... CSP, 2 ... Printed circuit board, 3 ... Bump, 4 ... Land, 4a ... Three lands connected to one terminal, 4
b ... Land transferred to lower layer, 5 ... Via hole, 9 ... Wiring, 9a ... Wiring drawn from three lands, 9b ... Connection for connecting between three lands wiring

Claims (8)

[Claims] 1. An area-arranged semiconductor element in which a plurality of bumps are arranged in a grid on a mounting surface of a package, and a connection terminal which is formed in the same grid as the bumps and is electrically connected to the bumps. In an area-arranged semiconductor device including a plurality of lands and a printed circuit board having wirings respectively connected to the plurality of lands, when at least two lands are connected to one wiring, 2. The wiring structure of an area-arranged semiconductor device, wherein the two lands are composed of lands belonging to a row on the outer peripheral side and lands belonging to a row on the inner peripheral side of the plurality of lands arranged in a grid pattern. 2. The row on the outer peripheral side and the row on the inner peripheral side having at least two lands each connected to one wiring are adjacent to each other. The wiring structure of the described area-arranged semiconductor device. 3. An area-arranged semiconductor element in which a plurality of bumps are arranged in a grid pattern on a mounting surface of a package, and a connection terminal which is formed in a grid pattern similar to the bumps and is electrically connected to the bumps. In an area-arranged semiconductor device including a plurality of lands and a printed circuit board having wirings respectively connected to the plurality of lands, when at least two lands are connected to one wiring, The wiring structure for an area-arranged semiconductor device, wherein at least two lands are composed only of lands belonging to a column on the inner peripheral side surrounded by the outermost column of the plurality of lands arranged in a grid pattern. 4. The at least two lands belong to a row on the inner peripheral side surrounded by the outermost row of the plurality of lands arranged in a lattice, and are composed of adjacent lands in the same row. The wiring structure of the area-arranged semiconductor device according to claim 3. 5. The inner peripheral row has a plurality of rows, and the at least two lands are lands belonging to at least two adjacent rows in the plurality of inner peripheral rows. The wiring structure of the area-arranged semiconductor device according to claim 3. 6. The land according to claim 1, wherein the at least two lands include lands that belong to different rows and are arranged in a vertical direction with respect to the rows.
3. The wiring structure of the area-arranged semiconductor device according to any one of items 1 to 3. 7. An area-arranged semiconductor device in which a plurality of bumps are arranged in a grid on a mounting surface of a package, and a connection terminal which is formed in a grid similar to the bumps and is electrically connected to the bumps. In an area-arranged semiconductor device including a plurality of lands and a printed circuit board having wirings respectively connected to the plurality of lands, when at least two lands are connected to one wiring, The two lands include a land located at a corner of the outermost row of the plurality of lands arranged in a lattice and a land adjacent to the land located at the corner, and the area-arranged semiconductor device. Wiring structure. 8. The area arrangement according to claim 1, wherein the wiring connecting the at least two lands has a line width larger than that of a wiring connected to another land. Type semiconductor device wiring structure.