JP2002009227A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: In a semiconductor laminated module having a memory function, an object is to provide a semiconductor memory module which is stacked in a plurality of stages without changing wiring of each semiconductor memory element. A flash memory is mounted on an interposer substrate, and the interposer substrates are arranged so as to overlap with each other via a spacer substrate.
4, the terminals 25, and the connection patterns 26 separately connect the electrodes of the flash memory 10 as necessary.
Or connect them in common.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a plurality of semiconductor elements arranged in a thickness direction thereof and a method of manufacturing the same.

[0002]

2. Description of the Related Art A memory module using a plurality of semiconductor memory chips and mounting these memory chips on a base substrate is used as storage means of electronic equipment. Here, if a structure in which memory chips are arranged on the base substrate is adopted, a large area is required in the surface direction of the base substrate. Therefore, the overall shape is suitable for a semiconductor memory having a card shape.

On the other hand, in the case of a stick-shaped semiconductor memory module whose dimensions in the plane direction are limited, when semiconductor memories are arranged in a plane on a base substrate, they are arranged because the area cannot be large. This places a limit on the number of semiconductor memories. The capacity of the memory module is proportional to the number of semiconductor memory chips. Therefore, in order to obtain a large capacity, it is necessary to laminate in three-dimensional directions.

In order to attain such an object, for example, as shown in FIG. 18, the semiconductor elements 1 are mounted on a base substrate 3 in a state of being arranged in the thickness direction. Here, the semiconductor element 1 is a TCP (Tape Carr).
In this case, a very thin lead is thermocompressed and laminated on the base substrate 3 as typified by an inner package.

Japanese Patent Application Laid-Open No. 2-198148 discloses that
A lamination method using a solder ball is disclosed. Here, as shown in FIG. 16, a plurality of semiconductor elements 1 are mounted on the auxiliary substrate 6, respectively, and these auxiliary substrates 6 are stacked in multiple stages via solder balls 7 and mounted on the base substrate 3. I have.

[0006]

The method of laminating the semiconductor element 1 shown in FIG. 18 has a drawback that requires a special technique.
Further, the semiconductor memory 1 needs to connect its write control terminal and read control terminal to terminals on the base substrate 3 which are different for each semiconductor memory chip. Therefore, in the case of adopting a structure in which the leads 2 of the same form are stacked as shown in FIG. 18, the write control terminal and the read control terminal of each semiconductor memory 1 must be changed for each semiconductor memory. This causes a problem that the types of semiconductor memories increase.

In the case of another laminated structure of the semiconductor elements 1 shown in FIG. 6, the structure in which the semiconductor balls 1 are laminated by the solder ball 7 at the same position is adopted. In order to form a wiring structure in which the read control terminals are not short-circuited, the semiconductor elements 10 in which the write control terminals and the read control terminals of the plurality of semiconductor elements 10 stacked on each other are provided at different positions must be combined. There is a problem to be solved.

[0008] For these reasons, the number of stacked semiconductor elements 1 is limited, and as the types of semiconductor elements increase, management during production becomes complicated. Also, TCP (Tape)
In both the method using Carrier Package) and the method using solder balls 7, there is a problem that the layers cannot be stacked unless a special method is used, so that it is impossible to cope realistically.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and is intended for a case where a plurality of semiconductor elements having terminals which cannot be connected to be short-circuited are arranged in the direction of their thickness. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which enable a plurality of layers to be easily stacked without changing the wiring of each semiconductor element. It is another object of the present invention to provide a semiconductor memory module structure and a method of manufacturing the same in which a plurality of layers can be stacked without changing the wiring of semiconductor elements constituting each semiconductor memory in a semiconductor laminated module having a memory function.

[0010]

According to one aspect of the present invention, there is provided a semiconductor device having a plurality of semiconductor elements arranged in a thickness direction thereof, wherein an interposer substrate on which the respective semiconductor elements are mounted is disposed between the interposer substrate and the interposer substrate. And a base substrate on which the plurality of semiconductor elements are mounted via the interposer substrate and the spacer substrate. It is.

Here, the semiconductor element may be a semiconductor memory chip. Further, the interposer substrate may be a hard substrate or a flexible substrate made of an organic material. The spacer substrate may have a dimension in the height direction larger than the thickness of the semiconductor element, and a conduction means may be constituted by a through hole or a conductive layer on the outer surface. The spacer substrate may be interposed between the interposer substrates and between the interposer substrate and the base substrate in a region where the semiconductor element is not mounted. Further, semiconductor elements may be mounted on both surfaces of the interposer substrate. No.

Another main invention of the present application is a semiconductor device having a plurality of semiconductor elements arranged in a thickness direction thereof.
The present invention relates to a semiconductor device comprising: a spacer substrate on which the semiconductor elements are arranged at predetermined intervals in a thickness direction thereof; and conductive means provided on the spacer substrate for connecting the semiconductor elements.

Here, each of the plurality of semiconductor elements may be constituted by a semiconductor memory, and a semiconductor memory module may be constituted by the plurality of semiconductor memories. Further, the plurality of semiconductor elements may each be configured by a semiconductor flash memory, and a semiconductor memory module may be configured by the plurality of semiconductor flash memories. The conductive means provided on the spacer substrate has a through hole formed to penetrate in the thickness direction of the semiconductor element, and a terminal connected to an electrode of the semiconductor element,
The input and output of signals to and from the semiconductor element may be controlled by the connection between the through hole and the terminal. Further, each of the plurality of semiconductor elements may be composed of a semiconductor memory, and the write control electrode and the read control electrode of each semiconductor memory may be connected to separate through holes via terminals of the spacer substrate.
The conductive means provided on the spacer substrate is a through hole formed to penetrate in the thickness direction of the semiconductor element, and the interposer substrate has a through hole connected to the through hole of the spacer substrate. A terminal connected to an electrode of the semiconductor element may be formed, and input / output of a signal to / from the semiconductor element may be controlled by a pattern of the terminal on the interposer substrate.

According to still another aspect of the present invention, there is provided a semiconductor device having a plurality of semiconductor elements arranged in a thickness direction thereof.
The present invention relates to a semiconductor device comprising: a lead provided on each semiconductor element and projecting laterally; and a spacer substrate arranged between leads of the semiconductor element and arranging the semiconductor elements at a predetermined interval. . Here, the lead may be a lead that does not lead bend the lead frame.

[0015] Further, the invention relating to a manufacturing method includes a step of applying a flux to at least a region on one surface of a semiconductor package having a semiconductor element where terminals are provided;
A step of mounting the spacer substrate having terminals coated with solder on the semiconductor package and performing reflow to connect the semiconductor package and the spacer substrate,
Applying a flux to at least a region of the other surface of the semiconductor package where terminals are provided, and performing reflow by overlapping the semiconductor package to which the spacer substrate is connected and the other surface is coated with the flux. And a step of laminating the semiconductor device. Here, the spacer substrate may be singulated by dicing after applying a solder coat to the terminals.

According to a preferred aspect of the present invention, when semiconductor memories are stacked in multiple stages, a connection spacer substrate is used to control the identification signals of the semiconductor memories and to share the wiring of the semiconductor packages to be stacked. Accordingly, it is possible to easily manufacture a multi-stage stacked semiconductor memory module. In particular, it is an object of the present invention to provide a semiconductor memory module comprising a plurality of semiconductor memories, wherein a plurality of semiconductor memories can be easily stacked without changing the wiring of each semiconductor memory.

Such a laminated structure is shown in FIGS.
As shown in the figure, after a semiconductor element 10 is stacked on one surface of a hard substrate 11 or a flexible substrate 11 made of an organic material and packaged, characteristics are determined and electrical measurements are performed, and then wiring and through holes are formed. The present invention relates to a multi-layered structure of a semiconductor memory which is connected to the connecting spacer substrate 12 by soldering or the like, and is laminated and modularized while maintaining electrical and mechanical bonding. Such an embodiment is very effective when stacking semiconductor elements in multiple stages, and is particularly preferably applied to the stacking of semiconductor memories.

Here, as shown in FIGS. 5 to 8, the spacer substrate 12 for connecting the semiconductor memories in the arrangement direction employs a different wiring pattern for each stage. That is, depending on the lamination layer in which the spacer substrate 12 is used, especially the connection pattern 26 connecting the through hole 24 and the electrode 25
There is a great feature in differentiating.

When the semiconductor memories constituted by the semiconductor elements 10 are stacked in multiple stages in parallel, the circuit blocks shown in FIG. In order to control data input / output, write control terminals CE0 to CE3 and read control terminals RE0 to RE3 must be separately supplied to ROM0 to ROM3. On the other hand, I / O1 to 8 terminals, WE terminal (write enable terminal), CLE terminal (command latch enable terminal), ALE terminal (address latch enable terminal), WP terminal (write protect terminal), R / B terminal ( Ready and busy output terminals), GND terminal (ground input terminal), Vcc terminal (power supply terminal), and Vss terminal (ground terminal) may be shared and function.

That is, when four semiconductor memory elements 10 of ROM0 to ROM3 are stacked in multiple stages in parallel, as is apparent from the circuit block shown in FIG. 9, the write control CE terminal and the read control The RE terminals must be independent of each other. On the other hand, the other terminals can be shared by the four semiconductor memories ROM0 to ROM3.

Therefore, in this embodiment, the connection between the through hole 24 of the spacer substrate 12 and the terminal 25 is devised so that only the identification terminal of the semiconductor memory 10 for performing the recording operation is not short-circuited between the semiconductor memories ROM0 to ROM3. are doing. In other words, the arrangement of the connection patterns 26 is changed for each spacer substrate 12, thereby changing the connection between the through hole 24 and the terminal 25 to make them different.

The electrical connection between the upper surface and the lower surface of the spacer substrate 12, that is, in the laminating direction thereof, is made through holes 24. Here, the spacer substrate 12
May be an organic composite material, or a ceramic substrate may be used. Further, instead of the through hole 24 as a conducting means in the laminating direction, a wiring pattern may be formed on the end face of the spacer substrate 24 by a method such as plating and connected.

Although the semiconductor element 10 can be directly connected to the spacer substrate 12, here, FIGS.
The interposer substrate 11 is mounted on an interposer substrate 11 as shown in FIG. The interposer substrate 11 may be a hard substrate or a flexible substrate made of an organic material. The semiconductor element 10 is mounted on the interposer substrate 11 by flip-chip mounting and packaged.

As shown in FIG. 3, terminals 18 for connection to terminals 25 on the surface of the spacer substrate 12 are formed near the periphery of both sides of the interposer substrate 11. The terminals 18 extend toward the center of the interposer substrate 11 in the width direction, as shown in FIG. 4, so that they are located on the lower surface of the electrodes 19 of the semiconductor element 10. The electrodes 19 of the semiconductor element 10 and the terminals of the interposer substrate 11 are connected by, for example, solder bumps 20. The connection between the interposer substrate 11 and the spacer substrate 12 is made by soldering. A similar effect can be expected even if a conductive adhesive is used instead of the solder.

The semiconductor memory 10 includes an interposer substrate 11
May be mounted on only one side (see FIG. 1), or may be mounted on both sides of the interposer substrate 11 (see FIG. 13). Particularly in the latter case, a semiconductor memory in which one semiconductor integrated circuit pattern is inverted can be used. In this case, the wiring patterns in the semiconductor package and on the printed circuit board for connection can be simplified.

Naturally, the semiconductor memory can be mounted by using a wire bonding method. A semiconductor element is mounted on one surface of the interposer substrate 11 by flip chip bonding, and a wire bonding method is mounted on the opposite surface. May be used to mount the semiconductor element.

As shown in FIG. 17, a package which has been subjected to insulation sealing can be used as a semiconductor memory package. In this case, after performing the same processing as the conventional TSOP package using a metal lead frame,
The same effect can be obtained by connecting to the connection terminal of the spacer substrate without performing lead bending.

According to the semiconductor memory module of such an embodiment, even when the number of semiconductor elements to be combined is increased to increase the capacity of the semiconductor memory module, the wiring pattern of each semiconductor memory remains unchanged. Can be used in state. That is, by preparing in advance the spacer substrate 12 having a different wiring pattern for each lamination stage, it is possible to easily laminate a plurality of stages. As a result, the capacity of the semiconductor memory module can be increased, and a high-capacity semiconductor memory device having a small space in the plane direction can be provided.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. First, a first embodiment will be described with reference to FIGS.
It will be explained by. In the first embodiment, as shown in FIGS. 1 and 2, a semiconductor element 10 made of a NAND flash memory having a capacity of 32 M is
It relates to memory modules arranged in rows. Such a NAND flash memory 10 is mounted on an interposer substrate 11 as shown in FIGS. As shown in FIG. 3, the surface of the interposer substrate 11 has a through hole 17 and a terminal 18 formed in advance.
This is a glass epoxy substrate having a thickness of 1 mm.

An aluminum electrode 19 is formed on the lower surface of the flash memory 10, as shown in FIG.
A solder bump 20 having a Pb content of 96% by weight and a Sn content of 4% by weight and a height of about 100 μm is formed thereon by a wafer plating method. Then, eutectic solder is supplied to the interposer substrate 11 to the solder connection portions of the terminals 18 by a printing method, the semiconductor memory 10 having the solder bumps 20 is mounted, and these are connected by a reflow process. After washing the excess flux component with an organic solvent, an epoxy resin 21 is filled between the semiconductor memory 10 and the interposer substrate 11 and cured, thereby forming a semiconductor memory package.

The packaged semiconductor elements 10 are stacked on each other via the spacer substrate 12. Here, as shown in FIGS. 5 to 8, a pair of spacer substrates 12 is used so as to be arranged on both sides for each layer. Each spacer substrate 12 has a through hole 24 and a terminal 25, and both are connected by a wiring pattern 26.

Here, the terminals CE0 to CE3 and the terminals RE0 to RE3 are connected independently of each other in the flash memory 10 so that the circuit shown in FIG. 9 is obtained. Wiring is performed by a connection pattern 26 so as to be commonly connected to the memory 10.

Then, flux is printed on a portion of the terminal 18 formed on the lower surface of the interposer substrate 11 by a mesh screen, and the through hole 24 and the terminal 2 are printed.
The spacer substrate 12 in which solder is pre-coated on the portion 5 is mounted on both ends of the interposer substrate 11 and reflow processing is performed. Thereby, the connection between the spacer substrate 12 and the interposer substrate 11 is performed. Thereafter, the modularized semiconductor device is mounted on the base substrate 13.

As described above, in the present embodiment, the semiconductor memory 10 in which the spacer substrate 12 for lamination is connected in advance.
Are prepared, and flux is supplied to the surface of the package of the semiconductor memory 10 opposite to the connection surface of the stacking spacer substrate 12, reflow heating is performed, and the layers are sequentially stacked to finally obtain 32M × 4 = 128M A semiconductor memory module having a storage capacity of?

FIG. 10 shows a process of manufacturing a semiconductor device comprising such a semiconductor memory package. The flash memory 10 constituting the semiconductor package is mounted on the interposer substrate 11 in advance, and a semiconductor memory package as shown in FIG. 4 is manufactured. Then, various electrical characteristics of such a memory package are measured, and a good product is determined. Then, a flux is applied by printing to the surface of the terminal 18 and the through hole 17 on the surface opposite to the surface on which the semiconductor chip 10 is mounted, in particular, of the interposer substrate 11 of the selected semiconductor memory package made of non-defective products.

On the other hand, the spacer substrate 12 is formed by integrally forming a plurality of spacer substrates 12 and forming a pattern as shown in FIGS. Then, a eutectic solder paste is applied to the surfaces of the terminals 25 and the through holes 24 connected to the semiconductor package to a thickness of about 150 μm by a printing method.
Then, the printed solder is melted by performing a reflow process, and a solder coating is performed. Thereafter, individual dicing is performed by dicing. As a result, an elongated quadrangular prism-shaped spacer substrate 12 is obtained.

The spacer substrate 12 is mounted on the surface opposite to the mounting surface of the semiconductor element 10 of the semiconductor package on which the flux is printed on the terminals as described above, and reflow processing is performed. Through such processing, connection between the semiconductor memory 10 and the spacer substrate 12 is achieved.

As described above, four semiconductor memory packages to which the spacer substrates 12 for lamination are connected are prepared. Then, the spacer substrate 1 of each semiconductor memory package
Flux is printed on the surface opposite to the connection surface of No. 2 and reflow heating is performed. Thus, the semiconductor memory packages are stacked in a plurality of stages. By such a process,
A semiconductor memory module having a four-layer structure as shown in FIGS. 1 and 2 is manufactured.

Next, another embodiment will be described with reference to FIGS.
It will be explained by. As described above, as shown in FIG. 9, the write control terminals CE0 to CE3 and the read control terminal R
Regarding E0-RE3, each semiconductor memory 10
Need to be connected separately. Therefore, in this embodiment, through holes 17 are formed on both sides of the interposer substrate 10, and the connection of the terminals 18 formed of the conductor patterns connected to these through holes 17 is different between the interposer substrates 11 of each layer. I try to tighten.

The interposer substrate 11 shown in FIG. 11 is a substrate used for the memory package of the uppermost layer.
By changing the wiring pattern 18 of the interposer substrate 11 in this manner, it becomes possible to share the pattern of the spacer substrate 12 of each layer. That is, here, it is possible to adopt a structure in which the through holes 24 are simply formed on both sides of the spacer substrates 12 of all the layers as shown in FIG. Note that the relay terminal 25 may be provided on the spacer substrate 12 also here.

According to such a configuration, the semiconductor device 10
By simply changing the wiring of the wiring pattern 18 of the interposer substrate 11 for each layer without changing the wiring of the interposer substrate 11, some of the electrodes are connected in common, and if necessary, other electrodes are separately connected to the respective semiconductor elements. It is possible to connect to Therefore, according to such a configuration, all the spacer substrates 12 can be formed in the same pattern, and the management thereof is facilitated.

Next, still another embodiment will be described with reference to FIGS.
6 will be described. In this embodiment, two NAND flash memories 10 each having a capacity of 32 M and two NAND flash memories 10 each having a pattern of 32 M and having the same pattern as the wiring pattern of such a flash memory are provided. In combination, a memory package is assembled by these four flash memories 10 in total. Here, as shown in FIG. 14, the semiconductor memory 10 is formed on both sides of a glass epoxy substrate 11 having a thickness of 0.1 mm in which through-holes 17 and terminals 18 are formed by a pattern in the same manner as in the first embodiment. Were mounted one by one as shown in FIG.

Then, such a semiconductor memory package was stacked via a stacking spacer substrate 12 as shown in FIGS. Here, connection pattern 2 for connecting through-hole 24 of spacer substrate 12 and terminal 25 is provided.
6, the CE terminal and the RE terminal of the four flash memories 10 which are stacked and arranged are the same as in the first embodiment.
Each semiconductor memory 10 is configured to be connected separately to each other for identification, and the other terminals are patterned so as to be commonly connected. Then, the spacer substrate 12 shown in FIG. 15 is disposed between the upper interposer substrate 11 and the intermediate interposer substrate 11, while the lower interposer substrate 11 and the base substrate 13
And the spacer substrate 12 is disposed between them.

As described above, 32M × 4 = 128M is formed by the four interposer substrates 11 and the spacer substrates 12 combined in two stages, which are composed of four flash memories 10.
Was obtained.

FIG. 17 shows still another embodiment. This embodiment shows a structure in which the interposer substrate 11 is omitted, and instead of the interposer substrate 11, the leads 32 of the lead frame of the flash memory 10 having the insulating package 30 are connected to the terminals 25 of the spacer substrate 12. I have. In this embodiment, the pattern arrangement of each step of the spacer substrate 12 is the first pattern shown in FIGS.
In this embodiment, the leads 32 of each level of the flash memory 10 are directly soldered and connected to the terminals 25 of the spacer substrate 12 as described above. Here, the lead 32 is a wire 31
Are connected to the electrodes of the flash memory 10 via the. Here, the lead 32 is formed by not performing lead bending of the lead frame.

According to the semiconductor memory module of this embodiment, it is possible to omit the interposer substrate 11 and to manufacture a memory module comprising a semiconductor element whose semiconductor chip is insulated by the insulating package 30. Become.

[0047]

As described above, according to one aspect of the present invention, in a semiconductor device having a plurality of semiconductor elements arranged in the thickness direction, an interposer substrate mounting each semiconductor element and an interposer substrate are provided. And a base substrate on which a plurality of semiconductor elements are mounted via the interposer substrate and the spacer substrate, the spacer substrate having conductive means for making connection between the interposer substrates.

Therefore, according to such a configuration, it is possible to obtain a semiconductor device in which a plurality of semiconductor elements are arranged in the thickness direction. Here, the connection between the electrodes of each semiconductor element can be arbitrarily changed by the conductive means of the spacer substrate, and the electrodes of each semiconductor element can be separated from each other as necessary, or can be commonly used as necessary. It will be possible to connect.

Another main invention of the present application is a semiconductor device having a plurality of semiconductor elements arranged in the thickness direction thereof, wherein a spacer substrate in which the semiconductor elements are arranged at predetermined intervals in the thickness direction is provided. A conductive means provided on the spacer substrate for making connection between the semiconductor elements.

Therefore, according to such a configuration, it is possible to obtain a semiconductor device in which a plurality of semiconductor elements are arranged in the thickness direction. Here, it is provided on the spacer substrate,
According to the connection of the conducting means for making the connection between the semiconductor elements,
It becomes possible to connect the electrodes of each semiconductor element separately from each other or to connect the corresponding electrodes in common.

The main invention relating to the manufacturing method includes a step of applying a flux to at least a region where a terminal is provided on one surface of a semiconductor package having a semiconductor element, and a method of forming a spacer substrate having a terminal coated with solder. A step of connecting the semiconductor package and the spacer substrate by mounting on the semiconductor package and performing reflow, a step of applying a flux to at least a region on the other surface of the semiconductor package where terminals are provided, and a step of connecting the spacer substrate. And reflowing and stacking semiconductor packages having the other surface coated with flux.

Therefore, according to such a method of manufacturing a semiconductor device, it is possible to efficiently manufacture a semiconductor device in which a plurality of semiconductor elements are arranged in the thickness direction, and in particular, a memory having a plurality of semiconductor elements. Efficient production of modules becomes possible.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view illustrating a configuration of a semiconductor device according to a first embodiment.

FIG. 2 is an exploded perspective view of the semiconductor device.

FIG. 3 is a plan view of an interposer substrate.

FIG. 4 is a longitudinal sectional view of a memory package having a semiconductor element mounted on an interposer substrate.

FIG. 5 is a plan view of an uppermost spacer substrate.

FIG. 6 is a plan view of a second-level spacer substrate.

FIG. 7 is a plan view of a third-level spacer substrate.

FIG. 8 is a plan view of a fourth-level spacer substrate.

FIG. 9 is a block diagram showing connections between respective semiconductor elements of the semiconductor memory module.

FIG. 10 is a flowchart showing a manufacturing method.

FIG. 11 is a plan view of an interposer substrate according to another embodiment.

FIG. 12 is a plan view of the spacer substrate.

FIG. 13 is a longitudinal sectional view of a semiconductor memory module according to still another embodiment.

FIG. 14 is a plan view of an interposer substrate.

FIG. 15 is a plan view of an upper-level spacer substrate.

FIG. 16 is a plan view of a lower-level spacer substrate.

FIG. 17 is a longitudinal sectional view of a memory module according to still another embodiment.

FIG. 18 is a longitudinal sectional view of a conventional semiconductor memory module.

FIG. 19 is a longitudinal sectional view of another conventional memory module.

[Explanation of symbols]

1 semiconductor device, 2 lead, 3 base board,
6 auxiliary board, 7 solder ball, 10 semiconductor element (flash memory), 11 interposer board,
12 ‥‥ spacer substrate, 13 ‥‥ base substrate, 17 ‥‥
Through hole, 18mm terminal (conductor pattern), 19mm
‥ Aluminum electrode, 20 ‥‥ solder bump, 21 ‥‥ epoxy resin, 24 ‥‥ through hole, 25 ‥‥ terminal, 26 ‥
‥ Connection pattern, 30 ‥‥ Insulation package, 31 ‥‥ Wire, 32 ‥‥ Lead

Claims (16)

[Claims] 1. A semiconductor device comprising a plurality of semiconductor elements arranged in a thickness direction thereof, wherein said semiconductor element is mounted on an interposer substrate, said interposer substrate being disposed between said interposer substrates, and a connection between said interposer substrates. And a base substrate on which the plurality of semiconductor elements are mounted via the interposer substrate and the spacer substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a semiconductor memory chip. 3. The semiconductor device according to claim 1, wherein said interposer substrate is a hard substrate or a flexible substrate made of an organic material. 4. The spacer substrate according to claim 1, wherein a dimension in a height direction of the spacer substrate is larger than a thickness of the semiconductor element, and a conduction means is constituted by a through hole or a conductive layer on an outer surface. Semiconductor device. 5. The semiconductor according to claim 1, wherein the spacer substrate is interposed between the interposer substrates and between the interposer substrate and a base substrate in a region where the semiconductor element is not mounted. apparatus. 6. The semiconductor device according to claim 1, wherein semiconductor elements are mounted on both surfaces of said interposer substrate. 7. A semiconductor device comprising a plurality of semiconductor elements arranged in a thickness direction thereof, wherein the semiconductor element is arranged on the spacer substrate at a predetermined interval in the thickness direction; And a conducting means for connecting the semiconductor elements. 8. The semiconductor device according to claim 7, wherein each of said plurality of semiconductor elements comprises a semiconductor memory, and said plurality of semiconductor memories constitute a semiconductor memory module. 9. The semiconductor device according to claim 7, wherein each of said plurality of semiconductor elements comprises a semiconductor flash memory, and said plurality of semiconductor flash memories constitute a semiconductor memory module. 10. A conductive means provided on the spacer substrate has a through hole formed through the semiconductor element in a thickness direction thereof, and a terminal connected to an electrode of the semiconductor element. The semiconductor device according to claim 7, wherein input / output of a signal to / from the semiconductor element is controlled by connecting the through hole and the terminal. 11. A semiconductor device comprising: a plurality of semiconductor elements each comprising a semiconductor memory; and a write control electrode and a read control electrode of each semiconductor memory connected to separate through holes via terminals of the spacer substrate. The semiconductor device according to claim 10, wherein: 12. A through-hole formed in the spacer substrate so as to penetrate in a thickness direction of the semiconductor element, and is connected to the interposer substrate with a through-hole of the spacer substrate. A through hole and a terminal connected to the electrode of the semiconductor element are formed,
The semiconductor device according to claim 7, wherein input / output of a signal to / from the semiconductor element is controlled by a pattern of the terminal of the interposer substrate. 13. A semiconductor device in which a plurality of semiconductor elements are arranged in the thickness direction thereof, wherein a lead provided on each semiconductor element and protruding laterally is provided between the leads of the semiconductor element. A spacer substrate on which the semiconductor elements are arranged at predetermined intervals. 14. The semiconductor device according to claim 13, wherein said lead is a lead which does not perform lead bending of a lead frame. 15. A step of applying a flux to at least a region on one surface of a semiconductor package having a semiconductor element where terminals are provided, and mounting a spacer substrate having terminals coated with solder on the semiconductor package. Connecting the semiconductor package and the spacer substrate by performing a reflow process, applying a flux to at least a region of the other surface of the semiconductor package where terminals are provided, and A method of stacking semiconductor packages having a flux applied to the other surface by overlapping and reflowing the semiconductor packages. 16. The method of manufacturing a semiconductor device according to claim 15, wherein said spacer substrate is divided into individual pieces by dicing after applying a solder coat to terminals.