JP2003249661A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve characteristic by selecting insulating films to be formed above and below a crystalline semiconductor film while considering stress balance. <P>SOLUTION: An oxidized silicon nitride film having tensile stress is formed on a substrate, the crystalline semiconductor film having tensile stress is formed on the oxidized silicon nitride film, and an oxidized silicon nitride film having compression stress is formed on the crystalline semiconductor film. Another oxidized silicon nitride film is formed between the oxidized silicon nitride film having the tensile stress and the crystalline semiconductor film. The oxidized silicon nitride film having the tensile stress is formed by a plasma CVD method using mixture gas composed of SiH<SB>4</SB>, N<SB>2</SB>O and NH<SB>3</SB>. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an integrated circuit using a thin film transistor on a substrate and a manufacturing method thereof. For example, the present invention relates to a configuration of an electro-optical device represented by a liquid crystal display device and an electronic apparatus including the electro-optical device.

[0002]

2. Description of the Related Art A semiconductor device represented by an active matrix type liquid crystal display device has been developed by arranging a large number of TFTs (thin film transistors) on a substrate. The TFT has an active layer formed of at least an island-shaped semiconductor film, a first insulating layer provided on the substrate side of the active layer, and a second insulating layer provided on the opposite side of the active layer from the substrate side. Had a laminated structure. Alternatively, it has a structure in which the first insulating layer is omitted and an active layer and a second insulating layer provided in close contact with the surface of the active layer opposite to the substrate side are stacked. It was

A structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer via the first insulating layer is called an inverted stagger type or a bottom gate type. On the other hand, a structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer via the second insulating layer is called a forward stagger type or a top gate type.

As a semiconductor film used for a TFT, it is considered that an amorphous semiconductor and a crystalline semiconductor capable of obtaining high mobility are suitable. Here, the crystalline semiconductor is
It includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The insulating layer is typically formed of a material such as silicon oxide, silicon nitride, or silicon oxynitride.

Further, as an example of the semiconductor layer, JP-A-7-130652, JP-A-8-78329, JP-A-10-135468, or JP-A-1-135468.
The semiconductor disclosed in 0-135469 is known.

By the way, CVD (chemical vapor deposition),
It has been known that a thin film of the above material produced by a known film forming technique such as a sputtering method or a vacuum evaporation method has an internal stress. The internal stress was further considered to be separated into the intrinsic stress inherent in the thin film and the thermal stress caused by the difference in thermal expansion coefficient between the thin film and the substrate. The effect of thermal stress could be neglected by controlling the thermal expansion coefficient of the substrate and the process temperature of the TFT manufacturing process, but the mechanism of intrinsic stress generation is not always clear, and the growth of thin film It was thought that phase changes and composition changes due to the process and subsequent heat treatment were complicatedly entangled.

Generally, the internal stress is as shown in FIG.
When the thin film contracts with respect to the substrate, the substrate is affected by the deformation and deforms with the thin film inside, and this is called tensile stress. On the other hand, when the thin film tries to stretch, the substrate is compressed and deformed with the thin film facing outward, and this is called compressive stress. Thus, for the sake of convenience, the definition of internal stress has been considered centering on the substrate. In this specification, the internal stress is described according to this definition.

It has been known that a crystalline semiconductor film produced from an amorphous semiconductor film by a method such as a thermal annealing method or a laser annealing method undergoes volume shrinkage during the crystallization process. The ratio depends on the state of the amorphous semiconductor film, but is 0.
It was said to be about 1 to 10%. As a result, tensile stress is generated in the crystalline semiconductor film, and its magnitude is about 1 ×.
It could reach 10 ⁹ Pa. Also, a silicon oxide film,
It has been known that the internal stress of an insulating film such as a silicon nitride film or a silicon oxynitride film changes variously from a compressive stress to a tensile stress depending on the film manufacturing conditions and the subsequent heat treatment conditions.

[0009]

In the technical field of VLSI, the problem of stress has been pointed out as one of the causes of the failure of the device. As the degree of integration increased, the influence of local stress was inevitable. For example,
It has been considered that heavy metal impurities are trapped in a region where stress is concentrated to cause various failure modes, and dislocations generated to relax the stress are also factors that deteriorate device characteristics.

However, regarding a TFT formed by laminating a plurality of thin films such as a semiconductor film and an insulating film, the effect that the internal stress of each thin film interacts with each other has not been sufficiently clarified. It was

Although there are several characteristic parameters that represent the TFT characteristics, the field effect mobility is one of the criteria for its good performance. Then, the structure of the TFT and its manufacturing process have been carefully studied from theoretical analysis and empirical aspects in order to achieve high field effect mobility. It was thought that particularly important factors were to reduce the bulk defect density in the semiconductor layer and the interface state density at the interface between the semiconductor layer and the insulating layer as much as possible.

The present inventor has found that in order to reduce the bulk defect density and interface defect density formed in the crystalline semiconductor layer, T
It was considered that not only optimizing the FT fabrication conditions, but also considering the internal stress of each thin film and reducing the defect density while balancing the stress. An object of the present invention is to solve the above problems and to realize a TFT in which the bulk defect density and the interface defect density are reduced without generating strain in the crystalline semiconductor layer.

[0013]

As described above, tensile stress is inherent in a crystalline semiconductor film manufactured from an amorphous semiconductor film. In a TFT having such a crystalline semiconductor film as an active layer, in order to stack a gate insulating film, another insulating film and a conductive film without causing strain on the crystalline semiconductor film, stress balance should be considered. It was necessary to do.

The stress balance to be considered here is
It is not to cancel the internal stress of each laminated thin film to make the synthetic stress zero, but to concentrate on the crystalline semiconductor film having tensile stress, and to prevent distortion in the crystalline semiconductor film. The thin films having the internal stress are laminated.

FIG. 4 illustrates the concept of the present invention. It was considered that it is desirable that the thin film provided on the substrate side of the crystalline semiconductor film has tensile stress with respect to the crystalline semiconductor film having tensile stress (FIG. 4B). On the other hand, it was considered that the thin film provided on the surface of the crystalline semiconductor film opposite to the substrate side should have compressive stress (FIG. 4).
(A)). In any case, when the crystalline semiconductor film is about to shrink, if stress acts in the direction of stretching the crystalline semiconductor film, it is expected that strain will occur in the crystal grain boundaries and microcracks will be formed. In such a case, dislocations and crystal defects are generated in that region, and many dangling bonds are formed. Therefore, by applying a tensile stress to the thin film provided on the substrate side with respect to the crystalline semiconductor film, the stress could be applied in the same direction as when the crystalline semiconductor layer tried to contract. On the contrary, by giving a compressive stress to the thin film provided on the side opposite to the substrate side with respect to the crystalline semiconductor film, the stress is applied in the same direction as the crystalline semiconductor layer tries to contract. I was able to. That is, the defect density could be effectively reduced only when the stress was applied from another thin film in the direction of contracting the crystalline semiconductor film.

In order to control the internal stress of the thin film, it suffices to consider the manufacturing conditions and the subsequent heat treatment conditions. For example, a silicon oxynitride film formed by a plasma CVD method can be changed from compressive stress to tensile stress by changing the composition ratio of nitrogen and oxygen and the amount of contained hydrogen. Further, the magnitude of internal stress could be changed by changing the film formation rate of the silicon nitride film formed by the plasma CVD method.

Further, what is important in considering the stress balance is the temperature control throughout the manufacturing process of the TFT. Even if the thin film formed by the plasma CVD method or the sputtering method has a predetermined internal stress in the initial state, the internal stress may change in the opposite direction due to the substrate heating temperature in the subsequent steps. . On the contrary, it was also possible to change the internal stress by utilizing this property. For example, when a silicon nitride film having a compressive stress is heat-treated at a temperature of 300 ° C. or higher, the tensile stress can be changed.

A gate electrode is provided so as to apply a predetermined voltage to the active layer via the first insulating layer provided on the substrate side of the active layer made of the island-shaped semiconductor film formed on the substrate. For example, an inverted stagger type or bottom gate type TFT could be formed. Further, if a gate electrode is provided so as to apply a predetermined voltage to the active layer through the second insulating layer provided on the side opposite to the substrate side of the active layer, a forward stagger type or top gate type TFT can be obtained. Could be formed.

The material of the insulating film used for the first insulating layer or the second insulating layer is not particularly limited, but it was necessary to be able to control the internal stress in some way. For that purpose, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a tantalum oxide film, etc. were suitable. The method for producing the silicon nitride film is not limited, but when it is produced by the plasma CVD method, for example, SiH ₄ , N
A mixed gas of H ₃ , N ₂ and H ₂ can be prepared. Then, by changing the gas mixture ratio and the discharge power density, the silicon nitride film could be produced under the conditions of different film formation rates. The internal stress measuring device is an Ionic System M
odel-30114 was used. The measurement used the sample produced on the silicon wafer.

Regarding the value of internal stress, tensile stress is indicated by a positive value and compressive stress is indicated by a negative value to distinguish them. The data in FIG. 17 shows that the silicon nitride films formed at different film formation rates with the substrate temperature at the time of film formation being 400 ° C. all had compressive stress, but were subjected to heat treatment at 500 ° C. for 1 hour. When,
The tensile stress could be changed. Such a change was realized when heat treatment was performed at a temperature higher than the substrate temperature at the time of film formation, and it was considered that the change was due to the densification of the silicon nitride film. Therefore, as the silicon nitride film, it was possible to produce both a film having a compressive stress and a film having a tensile stress.

The silicon oxynitride film is a plasma C
It was produced from a mixed gas of SiH ₄ and N ₂ O using the VD method. Also here, the silicon oxynitride film could be formed by changing the film formation rate by changing the gas mixture ratio and the discharge power density. FIG. 18 shows values of internal stress of a silicon oxynitride film manufactured at a substrate temperature of 400 ° C. Each sample having a different film formation rate had a compressive stress. Further, even if the heat treatment was performed at 450 ° C. for 4 hours, the absolute value of the compressive stress was reduced, but the state was still maintained.

Similarly, the characteristics of FIG. 19 are data of internal stress of the silicon oxynitride film, but SiH ₄ and N ₂ O
In addition, data of a silicon oxynitride film produced by further mixing NH ₃ is shown. When NH ₃ gas was added during film formation, the characteristics changed from compressive stress to tensile stress. Furthermore, the tensile stress could be increased when the sample was heat-treated at 550 ° C. for 4 hours. Such changes in stress corresponded to changes in the composition ratio of nitrogen concentration and oxygen concentration in the silicon oxynitride film. Table 1 shows the results of measuring the concentration of each element in the silicon oxynitride film by the Rutherford backscattering method (RBS).

[0023]

[Table 1]

While the nitrogen and oxygen contents of the silicon oxynitride film are 7 atomic% and 59.5 atomic%, respectively, by adding ₃₀ SCCM of NH ₃ gas at the time of film formation, the nitrogen content and the oxygen content are respectively changed. 24.0 atomic
% And 26.5 atomic%. Also, NH
_By adding 100 SCCM of ₃ gases, nitrogen content and oxygen content were 44.1 atomic% and 6.0 atomic, respectively.
Could be%. That is, it was possible to increase the nitrogen concentration and reduce the oxygen concentration in the silicon oxynitride film by adding NH ₃ gas. At this time, it was possible to change from compressive stress to tensile stress. The composition of various silicon oxynitride films obtained by adding NH ₃ gas was examined, and it was found that the content of silicon was about 34%.
atomic%, hydrogen was about 16 atomic%, and the total of nitrogen and oxygen was about 50 atomic%. And, those having a nitrogen concentration of 25 atomic% or more and less than 50 atomic% clearly have tensile stress, and 5 atomic% or more and 25 atomic% or more.
Less than one indicated compressive stress. The change in internal stress due to heat treatment could be considered in association with the change in the amount of hydrogen contained in the film as shown in FIG. The data in FIG. 20 shows the results of measuring the contained hydrogen concentration of the silicon oxynitride film produced by adding the NH ₃ gas by FT-IR. In the heat treatment at 500 ° C. for 1 hour, hydrogen bonded to silicon is preferentially released. This tendency is due to the temperature of the substrate during film formation (Tsu shown in the upper right of each graph in FIG. 20).
The lower the value (see b), the more prominent it appears. It is expected that the release of hydrogen bonded to silicon creates an unpaired bond, and the tensile stress is strengthened by the interaction (attractive force) of the unbonded bond. Thus, it was possible to change the internal stress also by reducing the hydrogen concentration in the film.

As described above, the internal stress is controlled by controlling the film forming rate, applying a heat treatment at a temperature higher than the substrate temperature at the time of film forming, or controlling the film forming condition to change the composition of the film. We were able to. As is well known, a TFT is completed by repeatedly forming a thin film and etching, but what is important here is control of the process temperature throughout the manufacturing process. Then, the maximum temperature of the process should be determined in consideration of the internal stress of the laminated thin films.

As described above, according to the present invention, the island-shaped semiconductor film formed on the substrate is used as an active layer, and the island-shaped semiconductor film is provided between the active layer and the substrate, and the concentration of nitrogen contained therein is higher than the concentration of oxygen contained therein. A first insulating layer having a silicon oxynitride film and a second silicon oxynitride film having a contained nitrogen concentration lower than the contained oxygen concentration and a surface of the active layer opposite to the substrate. And a second insulating layer having a third silicon oxynitride film having a contained nitrogen concentration lower than the contained oxygen concentration.

The active layer has a tensile stress, and the first layer
The first silicon oxynitride film having a nitrogen content in the insulating layer higher than the oxygen content has a tensile stress, and the nitrogen concentration in the second insulating layer is lower than the oxygen content in the third insulating layer. The silicon oxynitride film is characterized by having a compressive stress. The difference in absolute value of tensile stress between the first insulating layer and the semiconductor layer, or the difference between absolute value of compressive stress in the second insulating layer and tensile stress in the semiconductor layer is 5 × 10 5. It is desirable to be within ⁸ Pa.

Further, the first silicon oxynitride film having a content nitrogen concentration higher than the content oxygen concentration has a content nitrogen concentration of 25 atomic% or more and less than 50 atomic%, and the content nitrogen concentration is lower than the content oxygen concentration. The nitrogen concentration of the silicon oxynitride film is characterized by being 5 atomic% or more and less than 25 atomic%.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION [Embodiment 1] An embodiment of the present invention will be described with reference to FIG. 1A to 1C, a first insulating layer 10 is formed on a substrate 101 having an insulating surface.
2 is formed. The first insulating layer 102 is formed from the substrate side by a nitrogen-rich silicon oxynitride film 102a having a nitrogen content of 25 atomic% or more and less than 50 atomic% and a silicon oxynitride film 102b having a nitrogen content of 5 atomic% or more and less than 25 atomic%. ing. The nitrogen-rich silicon oxynitride film 102a is 5 × 10 ⁸ Pa or more and 2 × 10 ⁹ Pa or more.
It has a tensile stress of. Further, the silicon oxynitride film 102b is a film having a compressive stress of −5 × 10 ⁸ Pa or less, and by providing it between the nitrogen-rich silicon oxynitride film 102a and the active layer 103, the action of the stress is somewhat relaxed. It is provided to do so.

The active layer 103 is a crystalline semiconductor film produced by subjecting an amorphous semiconductor film to a laser annealing method or a thermal annealing method. Have stress. Then, if necessary, the channel formation region 103a and the LDD region 10 are formed.
3b, a source region 103c, and a drain region 103d are provided. Source electrode 106 and drain electrode 107
Is provided by forming a contact hole in a part of the second insulating layer 104.

The second insulating layer 104 is laminated on the active layer 103, and is a top gate type TFT as shown in FIG.
In this case, the gate insulating film 104a is provided first and is formed of a silicon oxynitride film having a nitrogen concentration of 5 atomic% or more and less than 25 atomic%. A gate electrode is provided at a predetermined position on this.

In FIG. 1A, a silicon nitride film 1 is formed on top of this.
04b and a silicon oxide film 104c are formed. The silicon nitride film 104b was formed by controlling the film formation rate so as to give a compressive stress. The compressive stress of this film is -2
It was in the range of × 10 ⁸ to 1 × 10 ⁹ Pa.

FIG. 1B shows a structure in which a silicon oxide film 104d and a silicon nitride film 104e are formed on the gate insulating film 104a. The silicon oxide film 104d is 5 × 10
The stress is ⁹ Pa or less, and the compressive stress may be applied by the silicon nitride film 104e formed thereon.

In FIG. 1C, a silicon nitride film 104f, a silicon oxide film 104g, and a silicon oxide film 104g are formed on the gate insulating film 104a.
Silicon nitride film 104h, silicon oxynitride film 104i
The structure which formed is shown. The compressive stress is the silicon nitride film 10
4f, 104h, and contained nitrogen concentration is 5 atomic% or more 25
It has less than atomic% of the silicon oxynitride film 104i. By providing a film having a compressive stress on the source electrode 106 and the drain electrode 107, the active layer 103 could be more effectively stressed.

[Embodiment 2] An embodiment of the present invention will be described with reference to FIG. In FIGS. 2A to 2D, a first insulating layer 202 is formed over a substrate 201 having an insulating surface. As in the first embodiment, a nitrogen-rich silicon oxynitride film 202a having a nitrogen content of 25 atomic% or more and less than 50 atomic% and a nitrogen content of 5 atomic% are contained.
The silicon oxynitride film 202b of 25 atomic% or more is provided. Nitrogen-rich silicon oxynitride film 20
2a has a tensile stress. The active layer 203 is a crystalline semiconductor film made of an amorphous semiconductor film by a method such as a laser annealing method or a thermal annealing method, and if necessary, a channel forming region 203a, an LDD region 203b, a source region 203c, and a drain region. 203d is provided. The source electrode 206 and the drain electrode 207 are provided by forming a contact hole in part of the second insulating layer 204. The second insulating layer 204 is laminated on the active layer 203, and is a top gate type TFT as shown in FIG.
In this case, the gate insulating film 204a is provided first and is formed of a silicon oxynitride film having a nitrogen concentration of 5 atomic% or more and less than 25 atomic%. A gate electrode is provided at a predetermined position on this.

In FIG. 2A, a silicon oxide film 204b and a silicon oxynitride film 204c are formed on the gate insulating film 204a.
Is formed. The silicon oxynitride film 204c was made to have a compressive stress with a nitrogen concentration of 5 atomic% or more and less than 25 atomic%. Therefore, the stress is applied to the active layer 203 from the nitrogen-rich silicon oxynitride film 202a and the silicon oxynitride film 204c.
Here, by providing a film having a compressive stress over the source electrode 206 and the drain electrode 207, the active layer 203
It was possible to effectively apply the stress.

FIG. 2B shows a silicon oxynitride film 204d and a silicon oxide film 204 on the gate insulating film 204a.
e, a silicon oxynitride film 204f is provided. Then, the nitrogen-rich silicon oxynitride film 202
A stress is applied to the active layer 203 from a and the silicon oxynitride films 204d and 204f.

FIG. 2C shows a structure in which a silicon oxide film 204g, a silicon oxynitride film 204h having compressive stress, and a silicon oxynitride film 204i are provided over the gate insulating film 204a. Further, FIG. 2D shows a silicon oxide film 2
04j, a silicon oxynitride film 204k, and a silicon oxynitride film 204l.

As described above, in order to change the internal stress from tensile stress to compressive stress by controlling the composition ratio of the nitrogen content and oxygen content of the silicon oxynitride film, SiH ₄ , N used for film formation is used. It was easy to change the mixing ratio of the ₂ O and NH ₃ gases, and this was easy. When a silicon oxynitride film having an absolute value of internal stress of 5 × 10 ⁸ Pa or more is provided, it is not formed in close contact with the active layer 203, but a film having a small stress such as a silicon oxide film is interposed. It was good to set up.

[0040]

[Embodiment] [Embodiment 1] This embodiment will be described with reference to FIGS. First, as the substrate 601, a glass substrate, for example, # 1737 substrate manufactured by Corning Incorporated was prepared. Then, the gate electrode 602 was formed over the substrate 601. Here, a tantalum (Ta) film was formed to a thickness of 200 nm by using a sputtering method. The gate electrode 602 is formed of a tantalum nitride film (film thickness 50 nm) and a Ta film (film thickness 250 nm).
It may be a two-layer structure. The Ta film is formed by sputtering using Ar gas with Ta as the target. However, when sputtering is performed with a mixed gas of Ar gas and Xe gas, the absolute value of the internal stress can be 2 × 10 ⁸ Pa or less. It was (Figure 5 (A))

Then, the first insulating layer 603 and the amorphous semiconductor layer 604 were successively formed without sequentially exposing to the atmosphere. First
The insulating layer 603 is a nitrogen-rich silicon oxynitride film 60.
3a (film thickness 50 nm) and silicon oxynitride film (film thickness 12
5 nm). The nitrogen-rich silicon oxynitride film 603a was formed by a plasma CVD method from a mixed gas of SiH ₄ , N ₂ O, and NH ₃ . In addition, the amorphous semiconductor layer 60
4 was also formed by the plasma CVD method to a thickness of 20 to 100 nm, preferably 40 to 75 nm. (Fig. 5
(B))

Then, heat treatment was carried out at 450 to 550 ° C. for 1 hour. By this heat treatment, the first insulating layer 603
Hydrogen was released from the amorphous semiconductor layer 604 and a tensile stress could be applied. After that, the amorphous semiconductor layer 604 was subjected to a crystallization step to form a crystalline semiconductor layer 605. A laser annealing method or a thermal annealing method may be used for the crystallization step here. In the laser annealing method, for example, KrF excimer laser light (wavelength 248 nm) is used to form a linear beam, and the oscillation pulse frequency is 30 Hz and the laser energy density is 100 to 5
The amorphous semiconductor layer was crystallized at 00 mJ / cm ² and the overlap ratio of the linear beam was 96%. Here, as the amorphous semiconductor layer was crystallized, volume contraction occurred, and the tensile stress of the formed crystalline semiconductor layer 605 increased. (Fig. 5 (C))

Next, an insulating film 606 was formed in contact with the crystalline semiconductor layer 605 thus formed. Here, the silicon oxynitride film was formed to a thickness of 200 nm. After that, a resist mask 607 in contact with the insulating film 606 was formed by a patterning method using exposure from the back surface.
Here, the gate electrode 602 serves as a mask, and the resist mask 607 can be formed in a self-aligning manner. Then, as shown in the drawing, the size of the resist mask was slightly smaller than the width of the gate electrode due to the light wraparound. (Figure 5 (D))

Then, the insulating film 606 was etched using the resist mask 607 to form a channel protective film 608, and then the resist mask 607 was removed. Through this step, the surface of the crystalline semiconductor layer 605 other than the region in contact with the channel protective film 608 was exposed. The channel protective film 608 has a function of preventing impurities from being added to the channel region in the subsequent step of adding impurities. (Fig. 5 (E))

Next, by patterning using a photomask, a resist mask 609 covering a part of the n-channel type TFT and the region of the p-channel type TFT is formed, and in the region where the surface of the crystalline semiconductor layer 605 is exposed. A step of adding an impurity element imparting n-type was performed. And
First impurity region (n ⁺ type region) 610a is formed. In this embodiment, since phosphorus was used as the impurity element imparting n-type, phosphine (PH ₃ ) was used in the ion doping method, the dose amount was 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 10 kV. In addition, the resist mask 609
The width of the n ⁺ type region was determined by the practitioner as appropriate, and the n ⁻ type region having a desired width and the channel forming region could be easily obtained. (Fig. 6
(A))

After removing the resist mask 609, the second
The insulating film 611 was formed. Here, a silicon oxynitride film (film thickness: 50 nm) having a compressive stress at the contained nitrogen concentration shown in Embodiment 1 of 5 atomic% or more and less than 25 atomic% is used.
Was manufactured by the plasma CVD method. The silicon oxynitride film had compressive stress. (Fig. 6 (B))

Then, a step of adding an impurity element imparting n-type conductivity to the crystalline semiconductor layer provided on the surface of the mask insulating film 611 is performed to form a second impurity region (n ⁻ -type region).
612 was formed. However, in order to add impurities to the crystalline semiconductor layer thereunder through the mask insulating film 611,
It is necessary to set appropriate conditions in consideration of the thickness of the mask insulating film 611. Here, the dose amount is 3 × 10 ¹³
The atoms / cm ² and the acceleration voltage were 60 kV. The second impurity region 612 thus formed functions as an LDD region. (Fig. 6 (C))

Next, a step of forming a resist mask 614 covering the n-channel TFT and adding an impurity element imparting p-type to the region where the p-channel TFT is formed was performed. Here, diborane (B
₂ H ₆ ) and boron (B) was added. Dose amount is 4
It was set to × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 30 kV. (Fig. 6
(D))

Then, after performing the step of activating the impurity element by the laser annealing method or the thermal annealing method, heat treatment (300 to 500 ° C., 1 hour) was performed in a hydrogen atmosphere to hydrogenate the whole. (Figure 7 (A))

Further, hydrogen may be produced by hydrogen produced by making plasma. After that, the channel protective film 608 and the mask insulating film 611 were selectively removed with a hydrofluoric acid-based etching solution, and the crystalline semiconductor layer was etched into a desired shape by a known patterning technique. (Fig. 7
(B))

Through the above steps, the source region 615, the drain region 616, and the LDD region 6 of the n-channel TFT.
17 and 618, the channel forming region 619 is formed, and the source region 621 and the drain region 62 of the p-channel TFT are formed.
2. A channel forming region 620 was formed. Then n
A second insulating layer was formed to cover the channel TFT and the p channel TFT. As the second insulating layer, first, an insulating film 623 made of a silicon oxide film was formed to a thickness of 1000 nm. (Fig. 7 (C))

Then, contact holes are formed, and source electrodes 624 and 626 and drain electrodes 625 and 627 are formed.
Was formed. Further, as the second insulating layer, the source electrodes 624 and 62 are formed on the insulating film 623 made of a silicon oxide film.
6, a silicon oxynitride film 628 was formed to cover the drain electrodes 625 and 627. This silicon oxynitride film was made to have a compressive stress by containing nitrogen in an amount of 5 atomic% or more and less than 25 atomic%. After obtaining the state shown in FIG. 7D, finally, a heat treatment is performed in a hydrogen atmosphere to hydrogenate the whole and n
A channel type TFT and a p channel type TFT are completed. The hydrogenation process could also be realized by exposing it to a plasmaized hydrogen atmosphere.

Example 2 n using the manufacturing process of Example 1
An example of a semiconductor device including a channel TFT and a p-channel TFT will be described with reference to FIG. FIG. 8 shows an inverter circuit which is a basic configuration of a CMOS circuit.
By combining such inverter circuits, NA
Configure basic circuits such as ND circuit, NOR circuit,
Further complicated shift register circuits and buffer circuits can be configured. FIG. 8A is a diagram corresponding to a top view of the CMOS circuit, and a dotted line AA ′ in FIG.
FIG. 8B is a cross-sectional structural view of the.

In FIG. 8B, n-channel type and
Both p-channel TFTs are formed on the same substrate
It The gate electrode 902 is formed in the p-channel TFT.
And has a tensile stress as a first insulating layer thereon.
Nitrogen-rich silicon oxynitride film 903 and oxynitride silicon
A recon film 904 is provided. And the first
An active layer made of a crystalline semiconductor film is formed in contact with the edge layer.
, P⁺Regions 912 (drain region), 915 (source
Region) and a channel formation region 914 are provided.
A second insulating layer is provided in contact with the semiconductor layer, where
Is a silicon oxide film 917 and a silicon oxynitride film 919.
Are formed. And provided on the silicon oxide film
Source electrode 920, drain through contact hole
The electrode 918 is formed. On the other hand, n-channel type TF
The active layer of T has n⁺Mold region 905 (source region), 9
11 (drain region) and channel formation region 909,
Note n ⁺N between the mold region and the channel formation region^-Type area
It has been burned. Similarly, the interlayer insulating film 917 has a capacitor
Tact hole is formed, source electrode 916, drain
An electrode 918 is provided.

Such a CMOS circuit is used in the peripheral drive circuit of an active matrix type liquid crystal display device, EL (Elec
It can be applied to a driving circuit of a troluminescence type display device, a reading circuit of a contact image sensor, and the like.

[Embodiment 3] This embodiment will be described with reference to FIGS. 9 and 10. Here, an embodiment will be described in which an n-channel TFT and a p-channel TFT are manufactured on the same substrate to form an inverter circuit which is a basic configuration of a CMOS circuit. In FIG. 9A, the substrate 7 having an insulating surface
A first insulating layer is formed on 01. This is because a nitrogen-rich silicon oxynitride film 702 having a nitrogen concentration of 25 atomic% or more and less than 50 atomic% is 20 to 100 nm,
Typically, it is formed to a thickness of 50 nm and the concentration of nitrogen contained is 5
A silicon oxynitride film 703 of atomic% or more and less than 25 atomic% is 50 to 500 nm, typically 150 to 200
It was formed to a thickness of nm. The nitrogen-rich silicon oxynitride film 702 has tensile stress. The second island-shaped semiconductor film 704, the first island-shaped semiconductor film 705, and the gate insulating film 706 were formed. The gate insulating film 706 is formed of a silicon oxynitride film. The island-shaped semiconductor film is a crystalline semiconductor film formed by a method such as a laser annealing method or a thermal annealing method, which is an amorphous semiconductor film, and is separated and formed into island shapes by a known technique. (Fig. 9 (A))

The semiconductor materials applicable here include silicon (Si), germanium (Ge), silicon germanium alloy, and silicon carbide, and other compound semiconductor materials such as gallium arsenide can also be used. The semiconductor film is formed to have a thickness of 10 to 100 nm, typically 50 nm. Hydrogen is contained in the amorphous semiconductor film formed by the plasma CVD method at a rate of 10 to 40 atomic%. The amorphous semiconductor film has an arbitrary internal stress from compression stress to tensile stress depending on the manufacturing conditions. However, a heat treatment process of 400 to 500 ° C. is performed before the crystallization process to release hydrogen from the film. By doing so, most of them changed into tensile stress.

Then, resist masks 707 and 708 were formed to cover the channel formation regions of the second island-shaped semiconductor film 704 and the first island-shaped semiconductor film 705. At this time, the resist mask 709 may be formed also in the region where the wiring is formed. Then, a step of adding an impurity element imparting n-type conductivity to form a second impurity region was performed. Here, phosphorus (P) is added by an ion doping method using phosphine (PH ₃ ). In this step, the gate insulating film 7
The acceleration voltage was set as high as 80 keV in order to add phosphorus to the underlying semiconductor film through 06. The concentration of phosphorus added to the island-shaped semiconductor film is 1 × 10 ¹⁶ to 1 × 1.
The preferable range is 0 ¹⁹ atoms / cm ³ , and here it is 1
It was set to × 10 ¹⁸ atoms / cm ³ . Then, phosphorus-doped regions 710 and 711 were formed in the semiconductor film. A part of this region functions as an LDD region. (Fig. 9 (B))

Then, a conductive layer 712 was formed on the surface of the gate insulating film 706. The conductive layer 712 is made of Ta, Ti, M
It is formed using a conductive material whose main component is an element selected from o and W. The conductive layer 712 has a thickness of 100 to
The thickness may be 500 nm, preferably 150 to 400 nm. Ta, Ti, W, Mo produced by sputtering method
The thin films such as had a large compressive stress. However, the stress could be effectively reduced by adding Xe gas in addition to Ar gas during sputtering film formation. (Fig. 9
(C))

Next, resist masks 713 to 716 were formed. The resist mask 713 is a p-channel TFT
And the resist masks 715 and 716 are for forming gate wirings and gate bus lines. Further, the resist mask 714 is formed so as to cover the entire surface of the first island-shaped semiconductor film 705, and is provided to serve as a mask for preventing addition of impurities in the next step. An unnecessary portion of the conductive layer 712 is removed by a dry etching method,
The gate electrode 717, the gate wiring 719, and the gate bus line 720 were formed. Here, if a residue remains after etching, it is preferable to perform an ashing process. Then, leaving the resist masks 713 to 716 as they are, an impurity element imparting p-type conductivity is added to a part of the second island-shaped semiconductor film 704 in which the p-channel TFT is formed to form a third impurity region. Formed. Here, boron was used as the impurity element and was added by an ion doping method using diborane (B ₂ H ₆ ). Again, the acceleration voltage is 80 ke
As V, boron was added at a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 9D, third impurity regions 721 and 722 to which boron is added at a high concentration are formed.

After removing the resist mask provided in FIG. 9D, resist masks 723 to 725 were formed again. This is for forming the gate electrode of the n-channel TFT, and the first gate electrode 726 was formed by the dry etching method. At this time, the first gate electrode 726 was formed so as to overlap with part of the second impurity regions 710 and 711 with the gate insulating film interposed therebetween. (Fig. 9 (E))

Next, resist masks 729 to 731 were formed. The resist mask 730 is the first gate electrode 72.
6 to cover the second impurity regions 710 and 711.
It is formed so as to overlap with a part of. This is L
The offset amount of the DD area is determined. And
A step of forming a first impurity region by adding an impurity element imparting n-type conductivity is performed, and a first impurity region 732 that serves as a source region and a first impurity region 73 that serves as a drain region are formed.
3 was formed. Also in this step, the acceleration voltage was set to a high value of 80 keV in order to add phosphorus to the semiconductor layer thereunder through the second insulating layer 706. The phosphorus concentration in this region is higher than that in the step of adding the first impurity element imparting n-type conductivity, and is 1 × 10 ¹⁹ to 1 × 10 ²¹ atom
s / cm ³ is preferable, here 1 × 10 ²⁰ atoms / c
m ³ (Fig. 10 (A))

Then, the gate insulating film 706, the first and second gate electrodes 726 and 717, the gate wiring 727,
A silicon oxide film 734 is formed on the surface of the gate bus line 728.
Was formed to a thickness of 1000 nm. After that, heat treatment was performed, which was added to each concentration of n-type or p-type.
It was necessary to do so to activate the impurity element that imparts the mold. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-mentioned excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it is difficult to activate even the shaded region under the gate electrode. Here, activation was performed by the thermal annealing method. The heat treatment is 300 to 600 in a nitrogen atmosphere.
C, preferably 350-550 C, here 450 C,
The treatment was carried out for 2 hours. In this heat treatment, 3 to 90% of hydrogen may be added to the nitrogen atmosphere. Further, after the heat treatment, it is further conducted in a hydrogen atmosphere of 3 to 100% at 150 to 500 ° C., preferably 300 to 450 ° C.
It is advisable to perform the hydrotreating step for up to 12 hours. Or
The hydrogenation treatment may be performed with hydrogen produced by plasmaizing at a substrate temperature of 150 to 500 ° C., preferably 200 to 450 ° C. In any case, by compensating for the defects that hydrogen remains in the semiconductor layer and at its interface, T
The characteristics of FT could be improved.

After that, a predetermined resist mask was formed on the silicon oxide film 734, and then a contact hole reaching the source region and the drain region of each TFT was formed by etching. Then, the source electrode 73
6, 737 and the drain electrode 738 were formed. Although not shown, in this embodiment, this electrode is formed of Ti film of 100 n
A 300 nm Al film containing m and Ti and a 150 nm Ti film were used as electrodes having a three-layer structure formed continuously by a sputtering method. Further, a silicon oxynitride film 735 having a nitrogen concentration of 5 atomic% to 25 atomic% was formed on the entire surface.
The film had compressive stress. When the second hydrogenation treatment was performed in this state, the characteristics of the TFT could be further improved. Again, 300 in a 1-5% hydrogen atmosphere
It suffices to perform the heat treatment at ˜450 ° C., preferably 300 to 350 ° C. for about 1 to 6 hours. Alternatively, hydrogenation could be performed by exposing it to hydrogen produced by making it plasma.

Through the above steps, the first insulating layer is a nitrogen-rich silicon oxynitride film 7 having a tensile stress.
02, a gate insulating film 70 formed of a silicon oxynitride film 703 and a second insulating layer of a silicon oxynitride film.
6, silicon oxide film 734, silicon oxynitride film 735
It consisted of And p-channel TF
The T was formed in a self-aligned manner (self-aligned), and the n-channel TFT was formed in a non-self-aligned manner (non-self-aligned).

In the n-channel type TFT of the CMOS circuit, the channel forming region 742 and the first impurity regions 745 and 74 are formed.
6, and second impurity regions 743 and 744 were formed. Here, the second impurity region is a region (GOLD: Gate Overlapped Drain) 743a, 744 overlapping the gate electrode.
a and a region (LDD region) 74 that does not overlap the gate electrode 74
3b and 744b were formed respectively. Then, the first impurity region 745 became a source region and the first impurity region 746 became a drain region. On the other hand, in the p-channel TFT, the channel formation region 739 and the third impurity regions 740 and 741 were formed. Then, the third impurity region 740 is used as a source region and the third impurity region 741 is used.
Became the drain region. (Figure 10 (B))

FIG. 10C is a top view of the inverter circuit, and shows the AA ′ sectional structure of the TFT portion, the BB ′ sectional structure of the gate wiring portion, and the C portion of the gate bus line portion.
The −C ′ cross-sectional structure corresponds to FIG. 10 (B). In the present invention, the gate electrode, the gate wiring, and the gate bus line are formed from the first conductive layer. 9 and 1
In FIG. 0, a CMOS circuit formed by complementarily combining an n-channel TFT and a p-channel TFT is shown as an example, but an NMOS circuit using the n-channel TFT, a pixel portion of a liquid crystal display device, an EL display The present invention can also be applied to a device, a reading circuit of an image sensor, and the like.

[Embodiment 4] In the present embodiment, the configuration of the present invention will be described with reference to FIGS. A method for manufacturing the formed active matrix substrate will be described.

First, a nitrogen-rich first silicon oxynitride film 1102 is formed as a first insulating layer on the substrate 1101.
a was formed to a thickness of 50 to 500 nm, typically 100 nm, and a second silicon oxynitride film 1102b was formed to a thickness of 100 to 500 nm, typically 200 nm. Nitrogen-rich first silicon oxynitride film 110
2a has a nitrogen concentration of 25 atomic% or more and 50 atom
It was set to be less than ic%. The nitrogen-rich first silicon oxynitride film 1102a was made of SiH ₄ , N ₂ O, and NH ₃ and had a tensile stress as shown in FIG. Then, the internal stress was retained even in the heat treatment accompanying the crystallization process and the gettering process. Furthermore, island-shaped crystalline semiconductor films 1103, 1
104 and 1105 and a gate insulating film 1106 were formed. The island-shaped crystalline semiconductor film was obtained by forming a crystalline semiconductor film from an amorphous semiconductor film by a crystallization method using a catalytic element, and separating and processing the crystalline semiconductor film into islands. The gate insulating film 1106 was a silicon oxynitride film made of SiH ₄ and N ₂ O and had a compressive stress. Here, it is formed with a thickness of 10 to 200 nm, preferably 50 to 150 nm. (Figure 11 (A))

Next, resist masks 1107 to 1111 were formed to cover the island-shaped semiconductor film 1103 and the channel formation regions of the island-shaped semiconductor films 1104 and 1105. At this time,
The resist mask 1109 may be formed also in the region where the wiring is formed. Then, an impurity element imparting n-type conductivity was added to form a second impurity region. Phosphorus (P) was added by an ion doping method using phosphine (PH ₃ ). In this step, the accelerating voltage was set to 65 keV in order to add phosphorus to the underlying island-shaped semiconductor film through the gate insulating film 1106. The concentration of phosphorus added to the island-shaped semiconductor is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , and here it is set to 1 × 10 ¹⁸ atoms / cm ³ . Then, the regions 1112 to 1116 to which phosphorus is added
Was formed. A part of this region serves as a second impurity region functioning as an LDD region. (Fig. 11
(B))

After that, the resist mask was removed and a conductive layer 1117 was formed on the entire surface. The conductive layer 1117 is T
A conductive material whose main component is an element selected from a, Ti, Mo, and W is used. The thickness of the conductive layer 1117 is 1
It may be formed to have a thickness of 00 to 1000 nm, preferably 150 to 400 nm. Here, Ta is sputtered and A
It was formed by using a mixed gas of r and Xe. (Figure 11 (C))

Next, the gate electrode of the p-channel TFT, the gate wiring of the CMOS circuit and the pixel portion, and the gate bus line were formed. Since the gate electrode of the n-channel TFT is formed in a later step, the resist mask 11 is formed so that the conductive layer 1117 remains on the entire surface of the island-shaped semiconductor film 1104.
19, 1123 was formed. An unnecessary portion of the conductive layer 1117 was removed by a dry etching method. Etching of Ta was performed with a mixed gas of CF ₄ and O ₂ . And
Gate electrode 1124 and gate wirings 1126 and 1128
Then, the gate bus line 1127 was formed. And
Leave the resist masks 1118 to 1123 as they are,
Island-shaped semiconductor film 1103 on which p-channel TFT is formed
A step of adding a third impurity element imparting p-type was performed to a part of the above. Here, boron was used as the impurity element and was added by an ion doping method using diborane (B ₂ H ₆ ). Here again, the acceleration voltage is set to 80 keV and 2 × 10
Boron was added to a concentration of ²⁰ atoms / cm ³ . And FIG.
As shown in FIG. 2 (A), the third boron added in a high concentration
Impurity regions 1130 and 1131 were formed.

After removing the resist mask provided in FIG. 12A, new resist masks 1124 to 113 are formed.
Formed 0. This is for forming the gate electrode of the n-channel TFT, and the gate electrodes 1131 to 1133 were formed by the dry etching method. At this time, the gate electrodes 1131 to 1133 have the second impurity region 1
It was formed so as to partially overlap with 112 to 1116.
(Fig. 12 (B))

Then, a new resist mask 1135 to
1141 was formed. Resist mask 1136, 113
9, 1140 are gate electrodes 113 of n-channel TFTs
1 to 1133 and a part of the second impurity region is formed. Here, the resist mask 113
6, 1139 and 1140 determine the offset amount of the LDD region. Then, a step of forming the first impurity region by adding an impurity element imparting n-type conductivity was performed. Then, the first impurity region 114 to be the source region
3, 1144 and the first impurity region 1 to be the drain region
142, 1145 and 1146 were formed. Also in this step, phosphorus is added to the underlying island-shaped semiconductor film through the gate insulating film 1106, and the concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type conductivity. It is preferably 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ^3, and here, 1 × 10 ²⁰ atoms / cm ³ . At this time, phosphorus-added regions 1180 and 1181 were formed also in part of the source and drain regions of the p-channel TFT. However, the phosphorus concentration in this region is about 1 of the boron concentration.
/ 2, and the conductivity type remains p-type. (Fig. 12
(C))

After the steps up to FIG. 12C are completed, a silicon oxide film 1147 is formed. TEOS here
Plasma C using (Tetraethyl Orthosilicate) as a raw material
It was formed to a thickness of 1000 nm by the VD method. In this state, heat treatment was performed in a nitrogen atmosphere at 400 to 800 ° C. for 1 to 24 hours, for example, 525 ° C. for 8 hours. By this step, the impurity element imparting n-type and p-type added could be activated. Further, the phosphorus-added regions 1142 to 1146 and 1180 and 1181 became gettering sites, and the catalyst element remaining in the crystallization step could be segregated in this region. As a result, the catalytic element could be removed at least from the channel formation region. After this heat treatment, 150 to 500 ° C., preferably 300 to 450, in a hydrogen atmosphere of 3 to 100%.
It is advisable to perform the step of hydrotreating at 2 ° C. for 2 to 12 hours. Alternatively, 150 to 500 ° C, preferably 200 to 450 ° C
The hydrogenation treatment may be performed with hydrogen produced by plasmaizing the substrate temperature. In any case, the characteristics of the TFT could be improved by compensating for the defect that hydrogen remains in the semiconductor layer or at the interface thereof. (Fig. 13
(A))

Thereafter, the silicon oxide film 1147 was patterned to form contact holes reaching the source region and the drain region of each TFT. Then, the source electrodes 1149, 1150, 1151 and the drain electrodes 1152, 1153 were formed. Although not shown, in this embodiment, this electrode was used as an electrode having a three-layer structure in which a Ti film having a thickness of 100 nm, a Ti-containing Al film having a thickness of 300 nm, and a Ti film having a thickness of 150 nm were successively formed by a sputtering method. When the second hydrogenation treatment was performed in this state, the characteristics of the TFT could be further improved. Again, 300-450 ° C, preferably 300-350 ° C in a 1-5% hydrogen atmosphere.
It suffices to perform the heat treatment for about 1 to 6 hours. Alternatively,
It was possible to hydrogenate by exposing it to hydrogen produced by making it plasma. Then, the silicon oxynitride film 1148 is formed with a thickness of 100 to 500 nm, for example, 300 n.
The film was formed to a thickness of m. The silicon oxynitride film 1148 is formed by the plasma CVD method, and based on the data in FIG.
It is made from a mixed gas of iH ₄ , N ₂ O and NH _3, and is formed so that the concentration of nitrogen contained in the film is less than 25 atomic%.
It has a compressive stress. (Fig. 13 (B))

Through the above steps, the first insulating layer is a nitrogen-rich first silicon oxynitride film 1102a and second silicon oxynitride film 1102b having tensile stress.
The second insulating layer is formed of a gate insulating film 1106 made of a silicon oxynitride film, a silicon oxide film 1147,
It was composed of a silicon oxynitride film 1148. The p-channel TFT was formed in a self-aligned manner (self-aligned), and the n-channel TFT was formed in a non-self-aligned manner (non-self-aligned).

Through the above steps, the channel formation region 1157, the first impurity regions 1160 and 1161, the second impurity region 1158, and the n-channel TFT of the CMOS circuit are formed.
1159 was formed. Here, the second impurity region is
A region (GOLD region) 1158a overlapping the gate electrode,
1159a and regions (LDD regions) 1158b and 1159b that do not overlap with the gate electrode are formed, respectively. Then, the first impurity region 1160 serves as a source region,
The first impurity region 1161 became a drain region. p
The channel type TFT has a channel forming region 1154, a third
Impurity regions 1155 and 1156 were formed. Then, the third impurity region 1155 serves as a source region and the third impurity region 1156 serves as a drain region. Further, the n-channel TFT (pixel TFT) in the pixel portion has a multi-gate structure, and the channel forming regions 1162 and 11
63 and the first impurity regions 1168, 1169, 1145.
And second impurity regions 1164 to 1167 were formed.
Here, the second impurity region is a region 1 overlapping the gate electrode.
Areas 1164b, 1165b, 1166b, 11 that do not overlap with 164a, 1165a, 1166a, 1167a
67b was formed.

Thus, as shown in FIG. 13B, an active matrix substrate having a CMOS circuit and a pixel portion formed on the substrate 1101 was manufactured. Also, the pixel TFT
On the drain side of, the low-concentration impurity region 1170, the gate insulating film 1106, and the storage capacitor electrode 117 to which the impurity element imparting n-type is added at the same concentration as that of the second impurity region.
1 and the storage capacitor provided in the pixel portion were formed at the same time.

[Embodiment 5] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 4 will be described with reference to FIGS. An interlayer insulating film 1401 made of an organic resin was formed to a thickness of about 1000 nm on the active matrix substrate in the state of FIG. 13B. As the organic resin film, polyimide, acryl, polyimide amide or the like can be used. The advantage of using an organic resin film is
The film forming method is simple, the relative dielectric constant is low, so that the parasitic capacitance can be reduced and the flatness is excellent. Note that organic resin films other than those described above can also be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate is used, and is baked at 300 ° C. The internal stress of this organic resin film was about 1 × 10 ⁸ Pa, and it was not so much a problem in consideration of the stress balance in view of its absolute value. Then, a contact hole reaching the drain electrode 1153 was formed in the interlayer insulating film 1401 to form a pixel electrode 1402. As the pixel electrode 1402, a transparent conductive film may be used in the case of a transmissive liquid crystal display device, and a metal film may be used in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed with a thickness of 100 nm by a sputtering method. (Figure 14 (A))

Next, as shown in FIG. 14B, an alignment film 1501 is formed on the surfaces of the interlayer insulating film 1401 and the pixel electrode 1402. Polyimide resin is often used for the alignment film of a liquid crystal display element. Opposing substrate 1502
Then, a transparent conductive film 1503 and an alignment film 1504 were formed. After the alignment film was formed, a rubbing process was performed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle. Through the above steps, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are attached to each other by a known cell assembling step via a sealant, a spacer (both not shown) and the like. afterwards,
A liquid crystal material 1505 was injected between both substrates and completely sealed with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 14B is completed.

Next, the structure of the active matrix type liquid crystal display device of this embodiment will be described with reference to FIGS. FIG. 15 is a perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel portion 1601, a scan (gate) line driver circuit 1602, and a signal (source) line driver circuit 1603 which are formed over a glass substrate 1101. The pixel TFT 1600 in the pixel portion is an n-channel TFT, and the driving circuit provided in the periphery is basically formed of a CMOS circuit. The scan (gate) line driver circuit 1602 and the signal (source) line driver circuit 1603 are connected to the pixel portion 1601 by a gate wiring 1703 and a source wiring 1704, respectively.

FIG. 16A is a top view of the pixel portion 1601 and is a top view of almost one pixel. An n-channel type pixel TFT is provided in the pixel portion. Gate wiring 170
The gate electrode 1702 continuously formed on the semiconductor layer 3 is formed on the semiconductor layer 17 under the gate electrode 1702 via a gate insulating film not shown.
It intersects with 01. Although not shown, a source region, a drain region, and a first impurity region are formed in the semiconductor layer. Further, on the drain side of the pixel TFT, a storage capacitor 1707 is formed from a semiconductor layer, a gate insulating film, and an electrode formed of the same material as the gate electrode. The cross-sectional structure taken along line AA ′ in FIG. 16A corresponds to the cross-sectional view of the pixel portion in FIG. 14B. On the other hand, in the CMOS circuit shown in FIG. 16B, the gate electrodes 1124 and 11 extending from the gate wiring 1126.
31 intersects with the semiconductor layers 1103 and 1104 thereunder via a gate insulating film (not shown), respectively. Although not shown, a source region, a drain region, and an LDD region are similarly formed in the semiconductor layer of the n-channel TFT. Further, a source region and a drain region are formed in the semiconductor layer of the p-channel TFT. And the positional relationship is that the cross-sectional structure along BB 'is
This corresponds to the cross-sectional view of the pixel portion illustrated in FIG.

Although the pixel TFT 1600 has a double gate structure in this embodiment, it may have a single gate structure or a triple gate multi-gate structure. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of the gate electrode, the source region of the semiconductor layer provided via the gate insulating film, the drain region, and the other impurity regions. The practitioner may make the appropriate decision.

[Embodiment 6] In this embodiment, a basic method for manufacturing a semiconductor film to be a first insulating layer and an active layer will be described. In FIG. 21, a glass substrate, a ceramics substrate, a quartz substrate, or the like can be used as the substrate 2101. Alternatively, a silicon substrate having a surface formed with an insulating film such as a silicon oxide film or a silicon nitride film, or a metal substrate typified by stainless steel may be used. When using a glass substrate,
It is desirable to perform heat treatment in advance at a temperature below the strain point. For example, when using Corning # 1737 substrate, 500 to 650 ° C., preferably 595 to 645.
It is advisable to perform a heat treatment at a temperature of 1 to 24 hours.

Then, the first insulating layer 2102 was formed on the main surface of the substrate 2101. Here, the oxynitride 2102a having tensile stress and the silicon oxynitride film 210 are used.
Formed 2b. The first insulating layer may be a film having tensile stress, and may be formed of a single layer or a plurality of layers selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, and a tantalum oxide film. These films may be formed by a known plasma CVD method or sputtering method. When a silicon oxynitride film is used, 2
The thickness may be 0 to 100 nm, typically 50 nm. Further, a silicon oxynitride film is formed on the silicon nitride film in a thickness of 50 to 500 nm, typically 50 to 200 n.
It may be formed to a thickness of m. Then, the amorphous semiconductor layer 2103 was formed over the first insulating layer. This may be an amorphous semiconductor formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method.
i), germanium (Ge), silicon germanium alloy, and silicon carbide, and other compound semiconductor materials such as gallium arsenide can be used. The semiconductor layer is formed to have a thickness of 10 to 100 nm, typically 50 nm. In addition, the first insulating layer and the amorphous semiconductor layer 210
It is also possible to continuously form 3 and 3 by a plasma CVD method or a sputtering method. After each layer is formed, the surface is not exposed to the atmosphere, so that the surface can be prevented from being contaminated. (Figure 21 (A))

Next, a crystallization step was performed. For the step of crystallizing the amorphous semiconductor layer, a known laser annealing method or thermal annealing method may be used. In any case, as the semiconductor layer undergoes a phase change from the amorphous state to the crystalline state, the semiconductor layer becomes denser and contracts in volume, so that tensile stress is generated in the crystalline semiconductor layer 2104. In addition, the amorphous semiconductor layer formed by the plasma CVD method has 10 to 40
Hydrogen is contained in the film at a ratio of atomic%, and a heat treatment step at 400 to 500 ° C. is performed prior to the crystallization step to desorb hydrogen from the film to keep the content of hydrogen at 5 atomic% or less. Was desired. The release of hydrogen resulted in tensile stress. (Figure 21 (B))

Then, a second insulating layer 2105 having a compressive stress was formed in contact with the crystalline semiconductor layer 2104. The second insulating layer 2105 can be formed of a single layer or a plurality of layers selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, and tantalum oxide. Second
The insulating layer 2105 may have a thickness of 10 to 1000 nm, preferably 50 to 400 nm. (Fig. 21
(C))

The first insulating layer 2102 and the second insulating layer 2
105, a silicon nitride film, a silicon oxide film,
The silicon oxynitride film and the tantalum oxide film were able to have stress in both tensile stress and compressive stress depending on the manufacturing conditions. For that purpose, it suffices to appropriately determine the mixing ratio of the gases to be used, the substrate temperature at the time of film formation, the film formation rate, and the like. Such manufacturing conditions differed depending on the individual device used. Further, the film having compressive stress could be converted into a film having tensile stress by adding a heat treatment step. The crystalline semiconductor layer produced from the amorphous semiconductor layer with volume shrinkage is 1
It had a tensile stress of × 10 ⁸ to 1 × 10 ⁹ Pa. For such a crystalline semiconductor layer, a first insulating layer and a second insulating layer are provided.
The difference in absolute value of internal stress of the insulating layer is 5 × 10 ⁹ Pa
It was desirable to do the following: As described above, a structure in which the crystalline semiconductor layer 2104 having tensile stress is provided in close contact with the first insulating layer 2102 having tensile stress and the second insulating layer 2105 having compressive stress is further known. Good characteristics could be obtained by manufacturing a TFT by using the above technique so that the crystalline semiconductor layer 2103 becomes an active layer. At this time, the total internal stress of the laminated crystalline semiconductor layer and insulating layer is 1 × 10 ⁹ Pa in absolute value.
I preferred to have the following: For example, n
The field effect mobility is 100 cm ² / Vsec with the channel type TFT.
The above could have been done. In addition, it was possible to improve the resistance to stress due to heat and voltage application.

FIG. 22 shows another embodiment. A nitrogen-rich silicon oxynitride film 22 having a tensile stress is formed as a first insulating layer 2202 on the main surface of a substrate 2201.
02a and a silicon oxynitride film 2202b are formed. Then, similarly to FIG. 21, an amorphous semiconductor layer 2203 was formed on the surface of the first insulating layer. The thickness of the amorphous semiconductor layer is 10 to 200 nm, preferably 30 to 100 nm
It may be formed in. Further, an aqueous solution containing 10 ppm of the catalytic element in terms of weight was applied by spin coating to form the catalytic element-containing layer 2204 on the entire surface of the amorphous semiconductor layer 2203. The catalytic element that can be used here is nickel (N
In addition to i), germanium (Ge), iron (Fe),
Palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (A
u). The internal stress of the amorphous semiconductor layer was not uniformly determined by the manufacturing conditions.
However, when a hydrogenation process was performed at 400 to 600 ° C. prior to the crystallization process to release hydrogen from the film, tensile stress was generated. At the same time, hydrogen was desorbed from the first insulating layer, so that the tensile stress was also strengthened. (Fig. 22
(A))

Then, a crystalline semiconductor layer 2205 was formed by performing a crystallization step of performing heat treatment at 500 to 600 ° C. for 4 to 12 hours, for example, 550 ° C. for 8 hours. (Fig. 2
2 (B))

Next, a step of removing the catalytic element used in the crystallization step from the crystalline semiconductor film was performed. As the method, here, Japanese Unexamined Patent Publication No. 10-247735 and Japanese Unexamined Patent Publication No.
No. 0-135468, or Japanese Patent Laid-Open No. 10-1354.
The technique described in Japanese Patent No. 69 was used. The technique described in the publication is a technique for removing it by using the gettering action of phosphorus. By this gettering step, the concentration of the catalytic element in the crystalline semiconductor film could be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ . First, a mask insulating film 2206 having a thickness of 150 nm was formed on the surface of the crystalline semiconductor layer 2205, and an opening 2207 was provided by patterning to provide a region where the crystalline semiconductor layer was exposed. Then, a step of adding phosphorus was performed to provide a phosphorus-containing region 2208 in the crystalline semiconductor layer. (Figure 22 (C))

In this state, 550 to 80 in a nitrogen atmosphere.
When heat treatment is performed at 0 ° C. for 5 to 24 hours, for example at 600 ° C. for 12 hours, the phosphorus-containing region 2208 functions as a gettering site, and the catalytic element remaining in the crystalline semiconductor layer 2205 is segregated in the phosphorus-containing region 2208. I was able to do it. (Figure 22 (D))

Then, the mask insulating film 2206 and the phosphorus-containing region 2208 are removed by etching, so that the concentration of the catalyst element used in the crystallization process is 1 × 10.
A crystalline semiconductor layer reduced to ¹⁷ atoms / cm ³ or less could be obtained. Then, a second insulating layer 2210 having a compressive stress was formed in close contact with the crystalline semiconductor layer 2209. The second insulating layer 2210 can be formed using a single layer or a plurality of layers selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, and tantalum oxide. The thickness of the second insulating layer 2210 is 10 to 1000 n.
m, preferably 50 to 400 nm. (Fig. 22 (E))

As described above, the first insulating layer 2202 having a tensile stress and the second insulating layer 22 having a compressive stress.
If a crystalline semiconductor layer 2209 having a tensile stress is provided in close contact with the crystalline semiconductor layer 10 and then a TFT having the crystalline semiconductor layer 2209 as an active layer is manufactured using a known technique, good characteristics are obtained. I was able to. At this time,
It is preferable that the total internal stress of the laminated crystalline semiconductor layer and the insulating layer is 1 × 10 ¹⁰ Pa or less in absolute value. For example, the field effect mobility of the n-channel TFT could be set to 200 cm ² / V · sec or more.

In addition, FIG. 23 shows that the main surface of the substrate 2301 has a first insulating layer 2302 having a tensile stress composed of two layers 2302a and 2302b and an amorphous semiconductor layer 230.
Formed 3. Then, a mask insulating film 2304 was formed on the surface of the amorphous semiconductor layer 2303. At this time, the thickness of the mask insulating film 2304 was set to 150 nm. Further, the mask insulating film 2304 was patterned to selectively form the openings 2305, and then an aqueous solution containing 10 ppm by weight of the catalytic element was applied. As a result, the catalyst element-containing layer 2306 was formed. Catalyst element containing layer 2306
Made contact with the amorphous semiconductor layer 2303 only through the opening 2305. (Figure 23 (A))

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment was performed at 570 ° C. for 14 hours to form the crystalline semiconductor layer 2307. In this crystallization process, the region of the amorphous semiconductor layer in contact with the catalytic element is first crystallized,
Crystallization proceeded laterally from there. The crystalline semiconductor layer 2307 thus formed is composed of rod-shaped or needle-shaped crystals aggregated, and each crystal grows in a certain specific direction when viewed macroscopically, so that the crystallinity is uniform. There was an advantage. (Figure 23 (B))

Next, as in FIG. 22, a step of removing the catalytic element used in the crystallization step from the crystalline semiconductor film was performed. A step of adding phosphorus is performed on the substrate in the same state as in FIG. 23B to form a phosphorus-containing region 2 in the crystalline semiconductor layer.
309 is provided. The phosphorus content in this region is 1 × 10 ¹⁹
It was set to 1 × 10 ²¹ / cm ³ (FIG. 23 (C)). In this state, in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours,
For example, when heat treatment was performed at 600 ° C. for 12 hours, the phosphorus-containing region 2309 worked as a gettering site, and the catalyst element remaining in the crystalline semiconductor layer 2307 could be segregated in the phosphorus-containing region 2309. (Fig. 23
(D))

Then, the mask insulating film and the phosphorus-containing region 2
309 and 309 were removed by etching to form an island-shaped crystalline semiconductor layer 2310. Then, the crystalline semiconductor layer 23
Second insulating layer 2311 having a compressive stress close to
Was formed. The second insulating layer 2311 is formed of one layer or a plurality of layers selected from a silicon oxide film and a silicon oxynitride film. The thickness of the second insulating layer 2311 is 10
˜100 nm, preferably 50 to 80 nm. Then, heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. For example, 950 ℃,
30 minutes. The treatment temperature may be selected in the range of 700 to 1100 ° C., and the treatment time may be selected from 10 minutes to 8 hours. As a result, the crystalline semiconductor layer 23
A thermal oxide film was formed at the interface between 10 and the second insulating layer 2311, the volume of the second insulating layer 2311 was further increased, and the compressive stress on the crystalline semiconductor layer was further increased. (Fig. 23 (E))

As described above, the first insulating layer 2302 having a tensile stress and the second insulating layer 23 having a compressive stress.
11. If a crystalline semiconductor layer 2310 having a tensile stress is provided in close contact with the crystalline semiconductor layer 2310 and then a TFT using the crystalline semiconductor layer 2310 as an active layer is manufactured using a known technique, extremely excellent characteristics are obtained. I was able to get it. For example, an n-channel TFT with a field effect mobility of 200 cm
It could have been set to ² / V · sec or higher.

Further, in FIG. 24, similarly to FIG. 22, after forming the first insulating layer 2402 and the crystalline semiconductor layer 2405, the catalytic element remaining in the crystalline semiconductor layer 2405 is gettered in the liquid phase. You can also For example,
Gettering can be performed by using sulfuric acid as a solution and dipping the substrate in the state of FIG. 24B in a sulfuric acid solution heated to 300 to 500 ° C., and the gettering remains in the crystalline semiconductor layer 2405. The catalytic element could be removed. Besides, nitric acid solution, aqua regia solution, and tin solution may be used. After that, the island-shaped semiconductor layer 2409 and the second insulating layer 2410 were formed.

Example 7 In this example, the TFT of the present invention is used.
A semiconductor device incorporating an active matrix type liquid crystal display device using a circuit will be described with reference to FIGS. 25, 32 and 33.

Such semiconductor devices include personal digital assistants (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV etc. are mentioned. Examples of those are shown in FIGS. 25 and 32.
Shown in.

FIG. 25A shows a mobile phone, which is a main body 90.
01, voice output unit 9002, voice input unit 9003, display device 9004, operation switch 9005, antenna 900
It is composed of 6. The present invention has a voice output unit 900.
2, and can be applied to a display device 9004 including a voice input portion 9003 and an active matrix substrate.

FIG. 25B shows a video camera, which includes a main body 9101, a display device 9102, a voice input section 9103, operation switches 9104, a battery 9105, and an image receiving section 91.
It consists of 06. The present invention has a voice input unit 9103,
And display device 910 including active matrix substrate
2, and can be applied to the image receiving unit 9106.

FIG. 25C shows a mobile computer or a portable information terminal, which includes a main body 9201 and a camera portion 92.
02, an image receiving unit 9203, operation switches 9204, and a display device 9205. The present invention is directed to the image receiving unit 920.
3, and a display device 9 including an active matrix substrate
It can be applied to 205.

FIG. 25D shows a head mount display, which is composed of a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.

FIG. 25E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarization beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The present invention can be applied to the display device 9403.

FIG. 25F shows a portable book, which is a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, the operation switch 9505 and the antenna 9506, and displays the data stored in the mini disk (MD) or DVD or the data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 32A shows a personal computer, which has a main body 9601, an image input section 9602, and a display device 9.
603 and a keyboard 9604.

FIG. 32B shows a player that uses a recording medium (hereinafter, referred to as a recording medium) in which a program is recorded, which includes a main body 9701, a display device 9702, and a speaker section 97.
03, recording medium 9704, and operation switch 9705. This device uses a DVD (Di
It is possible to play music, watch movies, play games, and use the Internet by using a digital versatile disc), a CD, or the like.

FIG. 32C shows a digital camera which is composed of a main body 9801, a display device 9802, an eyepiece section 9803, operation switches 9804, and an image receiving section (not shown).

FIG. 33A shows a front type projector, which comprises a projection device 3601 and a screen 3602. The present invention can be applied to a projection device and other signal control circuits.

FIG. 33B shows another rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 37.
03 and a screen 3704. The present invention can be applied to a projection device and other signal control circuits.

Note that FIG. 33C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 33A and 33B. Projection devices 3601, 37
02 is a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380.
9, a projection optical system 3810. Projection optical system 38
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, etc. in the optical path indicated by an arrow in FIG. Good.

Further, FIG. 33D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 33C. In this embodiment, the light source optical system 3801 includes the reflector 3811, the light source 3812, the lens arrays 3813, and 3.
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 33D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

In addition, the present invention can be applied to an image sensor and an EL type display element. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[Embodiment 8] Various liquid crystals other than nematic liquid crystal can be used for the liquid crystal display device shown in Embodiment 5. For example, 1998, SID, "Characteristics
and Driving Scheme of Polymer-Stabilized Monostabl
e FLCD Exhibiting Fast Response Timeand High Contr
ast Ratio with Gray-Scale Capability "by H. Furue
et al., 1997, SID DIGEST, 841, "A Full-Color Thr
esholdless Antiferroelectric LCD Exhibiting Wide Vi
ewing Angle with Fast Response Time "by T. Yoshida
et al., 1996, J. Mater. Chem. 6 (4), 671-673, "T
hresholdless antiferroelectricity in liquid crysta
ls and its application to displays "by S. Inui et
It is possible to use the liquid crystal disclosed in al. and US Pat. No. 5,594,569.

Ferroelectric liquid crystal (FLC) showing isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 26 shows the electro-optical characteristics of a monostable FLC in which a cholesteric phase-chiral smectic C phase transition is applied while a DC voltage is applied, and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 26 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 26 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For "f-V switching mode", see Terada et al.
Half-V shaped switching mode FLCD ", 46th
Proceedings of the 12th Joint Lecture Meeting on Applied Physics, 1999 1999
Moon, p. 1316, and Yoshihara et al., "Time-division full-color LCD with ferroelectric liquid crystal," Liquid Crystal, Volume 3, No. 19,
Details on page 0.

As shown in FIG. 26, it can be seen that use of such a ferroelectric mixed liquid crystal enables low voltage driving and gradation display. The liquid crystal display device of the present invention can also use a ferroelectric liquid crystal exhibiting such electro-optical characteristics.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optical response characteristics in which the transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (about 1 μm to 2 μm in cell thickness) have been found.

Generally, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and the liquid crystal itself has a high dielectric constant. Therefore, when the thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a pixel requires a relatively large storage capacitance. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low voltage driving is realized, so that low power consumption is realized.

[Embodiment 9] In this embodiment, an example of an active matrix substrate having a structure different from that of Embodiment 4 is shown in FIG.
Will be explained. First, according to the fifth embodiment, FIG.
The steps from (A) to FIG. 12 (C) are performed.

After the steps up to FIG. 12C are completed, a step of forming first interlayer insulating films 3147 and 3148 is performed. First, a silicon nitride film 3147 was formed to a thickness of 50 nm. The silicon nitride film 3147 is formed by plasma CVD
It was possible to apply compressive stress by controlling the film formation rate by changing the high frequency power by the method. Then, the silicon oxynitride film 3148 was formed to a thickness of 950 nm from a mixed gas of SiH ₄ and N ₂ O.

Then, a heat treatment step was performed. The heat treatment step needs to be performed in order to activate the impurity element imparting n-type or p-type added at each concentration. Here, the activation process was performed by the thermal annealing method. The heat treatment was performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C., here 450 ° C. for 2 hours.

After that, contact holes reaching the source region and the drain region of each TFT were formed in the first interlayer insulating films 3147 and 3148 by patterning. Then, the source electrodes 3149, 3150, 3151
And drain electrodes 3152 and 3153 were formed. Although not shown, in this embodiment, this electrode is formed by a Ti film of 100
nm, Al film containing Ti 300 nm, Ti film 150 nm
Was used as an electrode having a three-layer structure continuously formed by a sputtering method.

Through the above steps, the channel formation region 3157, the first impurity regions 3160 and 3161, the second impurity region 3158, and the n-channel TFT of the CMOS circuit are formed.
3159 was formed. Here, the second impurity region is
A region (GOLD region) 3158a overlapping the gate electrode,
3159a and regions (LDD regions) 3158b and 3159b which do not overlap with the gate electrode are formed, respectively. Then, the first impurity region 3160 serves as a source region,
The first impurity region 3161 became a drain region.

In the p-channel TFT, a channel forming region 3154 and third impurity regions 3155 and 3156 are formed. Then, the third impurity region 3155 became a source region and the third impurity region 3156 became a drain region.

The pixel TFT has a multi-gate structure, and channel forming regions 3162 and 3163, first impurity regions 3168, 3169 and 3145, and second impurity regions 3164 to 3167 are formed. Here, the second impurity regions are regions 3164a and 316 overlapping with the gate electrode.
5a, 3166a, 3167a and non-overlapping area 316
4b, 3165b, 3166b and 3167b were formed.

Thus, as shown in FIG. 31, the substrate 310
An active matrix substrate having a CMOS circuit and a pixel portion formed on 1 was manufactured. Further, on the drain side of the pixel TFT, a low concentration impurity region 317 to which an impurity element imparting n-type is added at the same concentration as the second impurity region is added.
0, the gate insulating film 3106, and the storage capacitor electrode 3171 were formed, and the storage capacitor provided in the pixel portion was simultaneously formed.

By providing a layer made of a silicon nitride film as the first interlayer insulating film as in this embodiment, compressive stress can be more effectively given. However, since the silicon nitride film has a reduced transmittance of light having a short wavelength of 500 nm or less, it is not preferable to form the silicon nitride film too thick because the transmittance of the pixel portion is lowered. Therefore, the silicon nitride film of the first interlayer insulating film has a thickness of 20 to 100 nm, preferably 30 to 60 nm.
Formed with a thickness of.

[Embodiment 10] In this embodiment, an EL (electroluminescence) display panel (EL
An example of manufacturing a display device) will be described. FIG. 27A is a top view of an EL display panel using the present invention. In FIG. 27A, 10 is a substrate, 11 is a pixel portion, 12 is a data line side driving circuit, and 13 is a scanning line side driving circuit, and each driving circuit reaches the FPC 17 via wirings 14 to 16 and externally. Connected to equipment.

At this time, the sealing material 19 is provided so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion. Then, the opposing plate 80 is used for sealing. The facing plate 80 may be a glass plate or a plastic plate. Seal 19
An adhesive 81 is further provided on the outer side of the substrate to firmly bond the substrate 10 and the counter plate 80 together, and to prevent the internal elements from being corroded by the intrusion of water or the like from the bonding end surface. Thus, a closed space is formed between the substrate 10 and the counter plate 80. At this time, the EL element is completely enclosed in the closed space and completely shielded from the outside air. Further, a sealing resin 83 is filled between the substrate 10 and the counter plate 80. As the sealing resin 83, an organic resin material selected from silicone-based, epoxy-based, acrylic-based, phenol-based, etc. is used. This improves the effect of preventing the EL element from being deteriorated due to moisture or the like.

FIG. 27B shows a sectional structure of the EL display panel of this embodiment, in which a driving circuit TFT (here, an n-channel type TFT is provided on the substrate 10 and the base film 21.
2 illustrates a CMOS circuit in which a TFT and a p-channel TFT are combined. 22) and a pixel portion TFT 23 (however, only the TFT for controlling the current to the EL element is shown here). As the driving circuit TFT 22, the CMOS shown in FIG.
N-channel TFT or p-channel TFT for circuits
Should be used. In addition, the TFT 23 for the pixel portion is shown in FIG.
The pixel TFT shown in (B) may be used.

The drive circuit TFT 22 and the pixel portion TFT 2
An interlayer insulating film (flattening film) 26 made of a resin material is provided on
A pixel electrode 27 made of a transparent conductive film that is electrically connected to the drain of the pixel portion TFT 23 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used. Then, after forming the pixel electrode 27, an insulating film 28 is formed and an opening is formed on the pixel electrode 27.

Next, the EL layer 29 is formed. EL layer 29
Is a known EL material (hole injection layer, hole transport layer, light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a laminated structure or a single layer structure. A publicly known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight materials (polymer materials).
When a low molecular weight material is used, a vapor deposition method is used, but when a high molecular weight material is used, a simple method such as a spin coating method, a printing method or an inkjet method can be used.

In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display can be performed by forming light emitting layers (red light emitting layer, green light emitting layer, and blue light emitting layer) capable of emitting light with different wavelengths for each pixel using a shadow mask. In addition, a color conversion layer (CC
There is a method in which M) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but any method may be used. Of course, an EL display device that emits monochromatic light can also be used.

After forming the EL layer 29, the cathode 3 is formed thereon.
Form 0. It is desirable to eliminate water and oxygen existing at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, if the EL layer 29 and the cathode 30 are continuously formed in vacuum,
It is necessary to form the EL layer 29 in an inert atmosphere and form the cathode 30 without exposing it to the atmosphere. In this embodiment, multi-chamber method (cluster tool method)
By using the film forming apparatus described above, it is possible to form the film as described above.

In this embodiment, as the cathode 30, Li was used.
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, 1 is formed on the EL layer 29 by vapor deposition.
A LiF (lithium fluoride) film having a thickness of nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in the area indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via the conductive paste material 32.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form a contact hole in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming the pixel electrode contact hole) and at the time of etching the insulating film 28 (at the time of forming the opening before forming the EL layer). Further, when the insulating film 28 is etched, the interlayer insulating film 26 may be collectively etched. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the contact hole can have a good shape.

The wiring 16 is electrically connected to the FPC 17 through a gap (closed with an adhesive 81) between the seal 19 and the substrate 10. Although the wiring 16 has been described here, the other wirings 14 and 15 similarly pass under the sealing material 18 and are electrically connected to the FPC 17.

The present invention can be applied to the EL display panel having the above structure. Here, an example of a more detailed cross-sectional structure of the pixel portion is shown in FIG. 28A, a top surface structure is shown in FIG. 29A, and a circuit diagram is shown in FIG. 29B.
28 (A), 29 (A) and 29 (B), common reference numerals are used, and thus they may be referred to each other. Note that FIG.
29A, 29 </ b> A, and 29 </ b> B are examples of the pixel portion and are not limited to this structure.

In FIG. 28A, the switching TFT 2402 provided on the substrate 2401 is formed using the n-channel TFT of the present invention (for example, shown in FIG. 13). Although a double gate structure is used in this embodiment, there is no significant difference in structure and manufacturing process, and a description thereof will be omitted. However, the double gate structure has an advantage in that two TFTs are substantially connected in series and the off-current value can be reduced. Although a double gate structure is used in this embodiment, a single gate structure may be used, a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, the p-channel TFT of the present invention may be used.

The current controlling TFT 2403 is formed by using the n-channel type TFT of the present invention. At this time, the drain wiring 35 of the switching TFT 2402
Is the gate electrode 37 of the current controlling TFT by the wiring 36.
Electrically connected to. The wiring indicated by 38 is the gate electrode 39 of the switching TFT 2402.
The gate wiring electrically connects a and 39b.

When the characteristics such as the threshold voltage, on-current, and subthreshold constant (S value) of the current control TFT 2403 vary from pixel to pixel, the current control drive E
The light emission intensity of the L element varies, that is, the image display is disturbed. In order to reduce the variation and keep the threshold voltage and the like within a predetermined range, it is necessary to use the TFT structure considering the stress balance as in the present invention. Further, since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and there is a high risk of deterioration due to heat or deterioration due to hot carriers. Therefore, it is necessary to provide a structure in which the LDD region is provided on the drain side of the current control TFT so as to overlap the gate electrode via the gate insulating film.

In this embodiment, the current control TFT 24 is used.
03 is shown as a single gate structure, a plurality of T
A multi-gate structure in which FTs are connected in series may be used.
Furthermore, a structure may be adopted in which a plurality of TFTs are connected in parallel and the channel formation region is substantially divided into a plurality of portions so that heat radiation can be performed with high efficiency. Such a structure is effective as a measure against deterioration due to heat. As described above, the active matrix EL display device can obtain good characteristics by using the TFT described in the third embodiment, the fourth embodiment, or the ninth embodiment. Alternatively, although not shown, the inverted stagger type TFT shown in the first or second embodiment may be applied to the active matrix EL display device of this embodiment.

Further, as shown in FIG. 29A, the wiring to be the gate electrode 37 of the current control TFT 2403 is 24
In the region indicated by 04, it overlaps with the drain wiring 40 of the current control TFT 2403 via the insulating film. At this time, 2
A capacitor is formed in the area indicated by 404. The capacitor 2404 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 2403. The drain wiring 40 is connected to the current supply line (power supply line) 2501 and is constantly applied with a constant voltage.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
1 is provided on the flattening film 42 made of a resin insulating film.
Is formed. It is very important to flatten the step due to the TFT by using the flattening film 42. Since the EL layer formed later is very thin, the presence of the step may cause defective light emission. Therefore, it is desirable to flatten the EL layer before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 is a pixel electrode (cathode of EL element) made of a conductive film having high reflectivity, and is used for the current controlling TFT 2
It is electrically connected to the drain of 403. Pixel electrode 43
It is preferable to use a low resistance conductive film such as an aluminum alloy film, a copper alloy film or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.

Further, the light emitting layer 44 is formed in the groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
A light emitting layer corresponding to each color of B (blue) may be separately formed.
A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV) materials, polyvinylcarbazole (PVK) materials, polyfluorene materials, and the like. There are various types of PPV organic EL materials, for example, "H. Shenk, H. Becker, O. Gelsen, E. Klu.
ge, W.Kreuder, and H.Spreitzer, “Polymers for Light
Emitting Diodes ”, Euro Display, Proceedings, 1999, p.
33-37 "and the materials described in JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for the light emitting layer emitting red light, polyphenylene vinylene is used for the light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for the light emitting layer emitting blue light. Good. Film thickness is 30-150n
It may be set to m (preferably 40 to 100 nm). However, the above example is an organic E that can be used as a light emitting layer.
This is an example of the L material, and the L material is not limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining the light emitting layer, the charge transport layer, or the charge injection layer.

For example, although the polymer material is used for the light emitting layer in this embodiment, a low molecular organic EL material may be used. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
(Polythiophene) or PAni (polyaniline) is used as the EL layer having a laminated structure provided with the hole injection layer 46. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be transparent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible because it is formed after forming a light-emitting layer or a hole injection layer having low heat resistance. Those capable of forming a film at a temperature as low as possible are preferable.

The EL element 2 is formed when the anode 47 is formed.
405 is completed. The EL element 2405 here
Is the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG. 29
As shown in (A), since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the utilization efficiency of light emission is very high, and a bright image can be displayed.

By the way, in this embodiment, the second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. This purpose is to shut off the EL element from the outside, and has both the meaning of preventing deterioration of the organic EL material due to oxidation and the meaning of suppressing degassing from the organic EL material. This improves the reliability of the EL display device.

As described above, the EL display panel of the present invention has the pixel portion composed of the pixels having the structure as shown in FIG. 28, the switching TFT having a sufficiently low off-current value, and the current control resistant to hot carrier injection. And TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained. In the configuration of this embodiment, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the seventh embodiment.

[Embodiment 11] In this embodiment, Embodiment 10 will be described.
A structure in which the structure of the EL element 2405 in the pixel portion shown in FIG. For the explanation, FIG. 28 (B)
To use. Note that the difference from the structure of FIG. 28A is EL
Since only the element portion and the current control TFT are provided, other description will be omitted.

In FIG. 28B, the current control TFT
2601 is formed using the p-channel TFT of the present invention. For the manufacturing process, Embodiments 3, 4, and 9 may be referred to. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the banks 51a and 51b made of an insulating film.
Then, the light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. In this way, the EL element 2602 is formed.

In the case of this embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed, as shown by the arrow. In the case of the structure as in this embodiment, it is preferable that the current controlling TFT 2601 be a p-channel TFT. The configuration of the present embodiment can be implemented by freely combining with the configurations of the first to fourth and ninth embodiments. Further, it is effective to use the EL display panel of the present embodiment as the display section of the electronic device of the seventh embodiment.

[Embodiment 12] In this embodiment, FIG.
FIG. 30 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this example,
2701 is a source wiring of the switching TFT 2702, 2703 is a gate wiring of the switching TFT 2702, 2704 is a current control TFT, 2705 is a capacitor, 2706 and 2708 are current supply lines, 2707 is E.
Let it be an L element.

FIG. 30A shows an example in which the current supply line 2706 is shared between two pixels. That is, the feature is that the two pixels are formed so as to be line-symmetric with respect to the current supply line 2706. In this case, since the number of power supply lines can be reduced, the pixel portion can be made even finer.

Further, FIG. 30B shows the current supply line 270.
8 is an example in which 8 is provided in parallel with the gate wiring 2703. Note that although the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other in FIG. 30B, as long as they are wirings formed in different layers,
Alternatively, the insulating films may be provided so as to overlap with each other. In this case, since the power supply line 2708 and the gate wiring 2703 can share the occupied area, the pixel portion can have higher definition.

30C, the current supply line 2708 is connected to the gate wiring 2703 as in the structure of FIG.
It is characterized in that it is provided in parallel with a and 2703b and that two pixels are formed so as to be line-symmetric with respect to the current supply line 2708. It is also effective to provide the current supply line 2708 so as to overlap with either one of the gate wirings 2703a and 2703b. In this case, since the number of power supply lines can be reduced, the pixel portion can be made even finer. The configuration of this embodiment is the same as that of the tenth embodiment.
Alternatively, the configuration of 11 can be freely combined and implemented. Further, it is effective to use the EL display panel having the pixel structure of this embodiment as the display section of the electronic device of the tenth embodiment.

[Embodiment 13] FIG. 29 shown in Embodiment 10.
29A and 29B, a capacitor 240 for holding the voltage applied to the gate of the current control TFT 2403.
However, the capacitor 2404 can be omitted.

In the case of Example 10, the current controlling TFT 24
Since the n-channel TFT of the present invention as shown in FIG. 28A is used as 03, it has an LDD region provided so as to overlap with the gate electrode (via the gate insulating film. Generally, a parasitic capacitance called a gate capacitance is formed in the region, but this embodiment is characterized in that this parasitic capacitance is positively used as a substitute for the capacitor 2404.

Since the capacitance of this parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region. In addition, FIG. 30 (A), (B),
Similarly, in the structure of (C), the capacitor 2705 can be omitted. The configuration of the present embodiment can be implemented by freely combining with the configurations of the first to fourth and ninth embodiments. Further, it is effective to use the EL display panel having the pixel structure of this embodiment as the display unit of the electronic device of the seventh embodiment.

[0169]

As described above, in a semiconductor device having a semiconductor film formed on a substrate as an active layer, the semiconductor film, the first insulating layer provided on the substrate side with respect to the semiconductor film, and the substrate By considering the stress balance between the insulating layer and the second insulating layer provided on the opposite side, it is possible to reduce strain or generation of defects in the active layer and at the interface with the insulating layer in contact with the active layer. it can. As a result, a high field-effect mobility can be obtained, and a semiconductor device having high reliability can be realized by improving resistance to stress caused by heat or an electric field.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a TFT of this embodiment.

FIG. 2 is a cross-sectional view of the TFT of this embodiment.

FIG. 3 is a diagram illustrating the definition of internal stress of a thin film.

FIG. 4 is a diagram for explaining the concept of stress balance of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a TFT.

6A to 6C are cross-sectional views illustrating a manufacturing process of a TFT.

7A to 7C are cross-sectional views illustrating a manufacturing process of a TFT.

FIG. 8 is a top view, a cross-sectional view, and a circuit diagram of a CMOS circuit.

FIG. 9 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 10 is a cross-sectional view showing a manufacturing process of a TFT, CMOS
Top view of the circuit.

FIG. 11 is a cross-sectional view showing a manufacturing process of an active matrix substrate.

FIG. 12 is a cross-sectional view showing a manufacturing process of an active matrix substrate.

FIG. 13 is a cross-sectional view of an active matrix substrate.

FIG. 14 is a cross-sectional view of an active matrix liquid crystal display device.

FIG. 15 is a perspective view of an active matrix substrate.

16A and 16B are a top view of a pixel portion and a top view of a CMOS circuit.

FIG. 17 is a characteristic diagram of internal stress of a silicon nitride film.

FIG. 18 is a characteristic diagram of internal stress of a silicon oxynitride film.

FIG. 19 is a characteristic diagram of internal stress of a silicon oxynitride film.

FIG. 20 is a characteristic diagram illustrating a change in contained hydrogen concentration of a silicon oxynitride film by heat treatment.

FIG. 21 is a diagram illustrating an example of the invention.

FIG. 22 is a diagram illustrating an example of the invention.

FIG. 23 is a diagram illustrating an example of the invention.

FIG. 24 is a diagram illustrating an example of the present invention.

FIG. 25 illustrates an example of a semiconductor device.

FIG. 26 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

27A and 27B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 28 is a cross-sectional view of a pixel portion of an EL display device.

29A and 29B are a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 30 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG. 31 illustrates an example of a semiconductor device.

FIG. 32 illustrates an example of a semiconductor device.

FIG. 33 illustrates an example of a semiconductor device.

[Explanation of symbols]

601 board 603a, 603b First insulating layer 605 crystalline semiconductor layer 611 Second insulating layer 903, 904 First insulating layer 908 Second insulating layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ritsuko Kawasaki             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Hiroki Adachi, the inventor             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Yasuyuki Arai             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Naoya Sakamoto             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Masahiko Hayakawa             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory F-term (reference) 2H090 HA01 HB03X HB04X HC03                       HD01 JA08 LA04                 2H092 GA59 JA25 JB56 KA04 KB24                       KB25 MA08 MA30 NA25 PA06                 5F110 AA30 BB02 BB04 BB10 CC02                       CC08 DD01 DD02 DD03 DD05                       DD15 DD17 DD25 EE01 EE04                       EE11 EE14 EE28 EE44 FF01                       FF02 FF03 FF04 FF05 FF06                       FF09 FF30 GG01 GG02 GG03                       GG04 GG06 GG13 GG25 GG43                       GG45 HJ01 HJ04 HJ12 HJ23                       HL04 HL06 HL12 HL23 HM15                       NN02 NN03 NN04 NN22 NN23                       NN28 NN35 NN71 NN73 NN78                       PP04 PP05 PP06 PP29 PP34                       PP35 QQ09 QQ11 QQ12 QQ24                       QQ25 QQ28

Claims (3)

[Claims] 1. A first silicon oxynitride film having a tensile stress is formed on a substrate, a second silicon oxynitride film is formed on the first silicon oxynitride film, and a second silicon oxynitride film is formed. A method for manufacturing a semiconductor device, comprising forming a crystalline semiconductor film having a tensile stress on a silicon film, and forming a third silicon oxynitride film having a compressive stress on the crystalline semiconductor film. 2. A first silicon oxynitride film is formed on a substrate by a plasma CVD method using a mixed gas of SiH ₄ , N ₂ O and NH ₃ , and SiH is formed on the first silicon oxynitride film. ₄ and N ₂ O
By the plasma CVD method using a mixed gas consisting of
A silicon oxynitride film is formed, and an amorphous semiconductor film formed by a plasma CVD method is crystallized on the second silicon oxynitride film to form a crystalline semiconductor film, and SiH is formed on the crystalline semiconductor film. _A method for manufacturing a semiconductor device, which comprises forming a third silicon oxynitride film by a plasma CVD method using a mixed gas of ₄ and N ₂ O. 3. The nitrogen concentration on the substrate is 25 atomic.
% Or more and less than 50 atomic% of a first silicon oxynitride film having a thickness of 20 to 100 nm and a nitrogen concentration of 5a on the first silicon oxynitride film.
A second silicon oxynitride film having a thickness of tomic% or more and less than 25 atomic% is formed to have a thickness of 50 to 500 nm, and an amorphous semiconductor film having a thickness of 40 to 75 nm is formed on the second silicon oxynitride film by a plasma CVD method. The crystalline semiconductor film is formed by crystallization, and the concentration of nitrogen contained in the crystalline semiconductor film is 5 atomic.
% Or more and less than 25 atomic% of a silicon oxynitride film is formed.