JP2000243975A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [PROBLEMS] To improve the reliability of a crystalline TFT in a large-area integrated circuit represented by an active matrix liquid crystal display device. SOLUTION: In a TFT having an LDD structure, a structure in which a region where the LDD region overlaps with the gate electrode and a region where the LDD region does not overlap is provided in one TFT. In order to form such a structure, n
The channel type TFT is formed in a non-self-aligned manner, while the p-channel type TFT is formed in a self-aligned manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors on a substrate having an insulating surface, and a method for manufacturing the same. For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with the electro-optical device.

[0002] In this specification, a semiconductor device is
Refers to all devices that function by utilizing semiconductor characteristics.
The above-described electro-optical device and an electronic apparatus equipped with the electro-optical device are included in the category.

[0003]

2. Description of the Related Art Development of a semiconductor device having a large-area integrated circuit composed of a thin film transistor (hereinafter, referred to as TFT) is in progress. Active matrix liquid crystal display devices and contact image sensors are typical examples.

[0004] TFTs can be classified according to their structure and manufacturing method. In particular, a TFT in which a semiconductor film having a crystalline structure is used as an active layer (crystalline TFT) has high field-effect mobility, so that various functional circuits can be formed.

[0005] In the present specification, the semiconductor film having a crystal structure includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor.
0652, JP-A-8-78329, JP-A-10-135468, or JP-A-10-135
No. 469, including the semiconductor disclosed therein.

In an active matrix type liquid crystal display device, a pixel matrix circuit (also referred to as a pixel portion) composed of n-channel TFTs for each functional block, a CMOS
Integrated circuits such as a circuit-based shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit were formed over one substrate.

In the contact type image sensor, integrated circuits such as a sample hold circuit, a shift register circuit, and a multiplexer circuit have been formed using TFTs.

Since the operating conditions of these circuits are not always the same, the characteristics required of the TFT naturally differed to some extent.

For example, the pixel portion has a configuration in which a switch element composed of an n-channel TFT and an auxiliary signal storage capacitor are provided, and the pixel portion is driven by applying a voltage to the liquid crystal. Here, the liquid crystal needs to be driven by alternating current, and a method called frame inversion driving is adopted. Therefore, the required TFT characteristics required that the leakage current be sufficiently reduced.

Further, since a high drive voltage is applied to the buffer circuit, it is necessary to increase the breakdown voltage. Further, in order to enhance the current driving capability, it is necessary to secure a sufficient ON current.

However, there is a problem that the off-current of the crystalline TFT tends to be high. And crystalline TF
It is said that T still falls short of MOS transistors (transistors manufactured on a single crystal semiconductor substrate) used for LSIs and the like in terms of reliability. For example, crystalline TFT
In some cases, a deterioration phenomenon such as a decrease in on-current was observed. The cause is the hot carrier effect, and it has been considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

The structure of the TFT includes a low concentration drain (LD)
D: Lightly Doped Drain) structure is known. In this structure, a low-concentration impurity region is provided between a channel region and a source or drain region to which an impurity is added at a high concentration.
It is called an area.

The LDD structure further has a GOLD that overlaps with the gate electrode depending on the positional relationship with the gate electrode.
(Gate-drain Overlapped LDD) structure and LDD structure that does not overlap with the gate electrode. GOL
In the D structure, the high electric field near the drain was relaxed to prevent the hot carrier effect, and the reliability was improved. For example, "Mutsuko Hatano, Hajime Akimoto and Takesh
i Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997 ”, GOLD with sidewalls made of silicon
Although it has a structure, it has been confirmed that extremely excellent reliability can be obtained as compared with TFTs having other structures.

[0014]

SUMMARY OF THE INVENTION However, GOL
The D structure has a problem that the off-state current becomes larger than that of the normal LDD structure, and it is not always preferable to form all the TFTs with the structure in a large-area integrated circuit. For example, an n-channel type T forming a pixel portion
In the FT, when the off-state current is increased, power consumption is increased or abnormalities are displayed in an image display. Therefore, it is not preferable to use the crystalline TFT having the GOLD structure as it is.

Also, the LDD structure has a problem that the on-current decreases due to an increase in series resistance. The ON current can be freely designed depending on the channel width of the TFT.
It was not always necessary to provide an offset TFT on the FT.

An object of the present invention is to provide a TFT having a structure optimal for each functional circuit in a semiconductor device having a large area integrated circuit represented by an active matrix type liquid crystal display device or an image sensor. Another object is to provide a method for forming such a TFT on the same substrate in the same step.

The present invention is a technique for solving such a problem, and an object of the present invention is to realize a crystalline TFT having a reliability equal to or higher than that of a MOS transistor. It is another object of the present invention to improve the reliability of a semiconductor device having a large-area integrated circuit in which various functional circuits are formed using such a crystalline TFT.

[0018]

According to the present invention, there is provided a TFT having an LDD structure, wherein the LDD region overlaps with a gate electrode.
A non-overlapping region is provided in one TFT.

Further, the present invention relates to a semiconductor device having a large area integrated circuit typified by an active matrix type liquid crystal display device and an image sensor. Makes it possible to make the ratio of a region overlapping with the gate electrode to a region not overlapping different for each TFT.

To achieve such a configuration, the n-channel TFT is non-self-aligned (non-self-aligned), while the p-channel TFT is self-aligned (self-aligned).
In the process.

Therefore, the present invention provides a semiconductor device having a semiconductor layer, a gate insulating film, a gate electrode, and a gate wiring connected to the gate electrode on a substrate having an insulating surface. Comprises a first conductive layer, the semiconductor layer is sandwiched between the channel forming region, one conductivity type first impurity region, the channel forming region and the one conductivity type first impurity region, And a second impurity region of one conductivity type in contact with the channel formation region, and a part of the second impurity region of one conductivity type is connected to the gate electrode via the gate insulating film. It has an overlapping structure.

The first conductive layer applied to the present invention is formed of one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), or A compound containing the above-described element as a main component is used. The second conductive layer is a low-resistance conductive material typified by one or more elements selected from aluminum (Al) and copper (Cu), or a compound containing the element as a main component. .

The present invention can be applied to a semiconductor device having a CMOS circuit formed of a pixel portion formed of an n-channel thin film transistor, an n-channel thin film transistor, and a p-channel thin film transistor.

However, in the above-mentioned CMOS circuit, it is not always necessary to apply the configuration of the present invention to a p-channel TFT.

According to another structure of the present invention, in a semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor in one pixel, a gate electrode of the n-channel thin film transistor and the p-channel thin film transistor; The gate wiring connected to
A semiconductor layer of the n-channel thin film transistor, the first conductive layer being in contact with a gate insulating film, wherein the semiconductor layer of the n-channel thin film transistor includes a channel formation region, a first impurity region of one conductivity type, A second impurity region of one conductivity type sandwiched between the first impurity regions and in contact with the channel formation region; and a part of the second impurity region of one conductivity type is Overlap with the above p
The semiconductor layer of the channel thin film transistor has a channel formation region and a third impurity region having a conductivity type opposite to the one conductivity type, and the third impurity region is provided outside the gate electrode. It is characterized by having.

Alternatively, in a semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor in one pixel, a gate electrode of the n-channel thin film transistor and a p-channel thin film transistor;
The gate wiring connected to the gate electrode includes a first conductive layer in contact with a gate insulating film, and the semiconductor layer of the n-channel thin film transistor includes a channel formation region, a first conductivity type first impurity region, A second impurity region of one conductivity type sandwiched between the channel formation region and the first impurity region of one conductivity type and in contact with the channel formation region. Part of the impurity region of
The semiconductor layer of the p-channel thin film transistor overlaps with the gate electrode and includes a channel formation region and a third impurity region having a conductivity type opposite to one conductivity type. A part is characterized by overlapping with the gate electrode.

Further, according to the structure of the present invention, a step of forming a semiconductor layer on a substrate having an insulating surface and removing at least a part of the semiconductor layer to form at least a first island-like semiconductor layer and a second island Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and forming one impurity element of the first conductivity type into the first island-shaped semiconductor layer. Forming a second impurity region by adding it to a selected region of the island-shaped semiconductor layer; forming a first conductive layer in contact with the gate insulating film; Second
Forming a second gate electrode overlapping the island-shaped semiconductor layer; and adding an impurity element having a conductivity type opposite to the one conductivity type to a selected region of the second island-shaped semiconductor layer. Forming a first gate electrode overlying the first island-shaped semiconductor layer from the first conductive layer; and forming the first conductivity-type impurity element in the first island-shaped Forming a first impurity region by adding to a selected region of the semiconductor layer.

In another aspect of the present invention, a semiconductor layer is formed on a substrate having an insulating surface, and at least a first island-like semiconductor layer is formed by removing a part of the semiconductor layer; Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and removing one conductivity type impurity element from the first island-shaped semiconductor layer. Forming a second impurity region by adding it to a selected region of the island-shaped semiconductor layer; and forming a first impurity region in contact with the gate insulating film.
Forming a conductive layer, and forming a first gate electrode overlapping the first island-shaped semiconductor layer and a second gate electrode overlapping the second island-shaped semiconductor layer from the first conductive layer Forming a first impurity region by adding an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer; and forming an impurity of a conductivity type opposite to the one conductivity type. Forming a third impurity region by adding an element to a selected region of the second island-shaped semiconductor layer.

In another aspect of the present invention, a semiconductor layer is formed on a substrate having an insulating surface, and at least a first island-like semiconductor layer is formed by removing a portion of the semiconductor layer; Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and forming a conductive type opposite to the one conductive type. Forming a third impurity region by adding a second impurity element to a selected region of the second island-shaped semiconductor layer; and selecting an impurity element of one conductivity type in the first island-shaped semiconductor layer. Forming a second impurity region by adding to the region, forming a first conductive layer in contact with the gate insulating film, and forming the first island-like semiconductor layer from the first conductive layer. The first that overlaps
Forming a first gate electrode and a second gate electrode overlapping the second island-shaped semiconductor layer, and adding an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer. Forming a first impurity region.

Another aspect of the present invention is a process for forming a semiconductor layer on a substrate having an insulating surface, removing at least a portion of the semiconductor layer to form at least a first island-like semiconductor layer, Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and forming a conductive type opposite to the one conductive type. Forming a third impurity region by adding a second impurity element to a selected region of the second island-shaped semiconductor layer; and selecting an impurity element of one conductivity type in the first island-shaped semiconductor layer. Forming a first impurity region by adding the impurity region to the selected region, and forming a second impurity region by adding an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer. Forming a first conductive layer in contact with the gate insulating film; It has a step of forming a second gate electrode overlaps the first above the gate electrode of the second island-shaped semiconductor layer overlapping the first semiconductor island from.

In another aspect of the present invention, a semiconductor layer is formed on a substrate having an insulating surface, and at least a first island-like semiconductor layer is formed by removing a part of the semiconductor layer; Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and removing one conductivity type impurity element from the first island-shaped semiconductor layer. Adding a selected region of the first island-shaped semiconductor layer to form a first impurity region, and adding an impurity element of one conductivity type to the selected region of the first island-shaped semiconductor layer A step of forming a second impurity region; a step of forming a first conductive layer in contact with the gate insulating film; and a second gate overlapping the first conductive layer with the second island-shaped semiconductor layer Forming an electrode, and adding an impurity element having a conductivity type opposite to the one conductivity type to the second island shape. Forming a third impurity region by adding to a selected region of the conductor layer; and forming a first gate electrode overlapping the first island-shaped semiconductor layer from the first conductive layer. have.

Another aspect of the present invention is a process for forming a semiconductor layer on a substrate having an insulating surface, removing at least a portion of the semiconductor layer to form at least a first island-like semiconductor layer, Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and removing one conductivity type impurity element from the first island-shaped semiconductor layer. Forming a first impurity region by adding to a selected region of the one island-shaped semiconductor layer; and selecting an impurity element of a conductivity type opposite to the one conductivity type in the second island-shaped semiconductor layer. Forming a third impurity region by adding the impurity region to the selected region, and forming a second impurity region by adding an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer. Forming a first conductive layer in contact with the gate insulating film; It has a first gate electrode overlapping the first semiconductor island, and forming a second gate electrode overlapping the second semiconductor island from.

In the above structure of the present invention, the first conductive layer is formed of one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), or the first conductive layer. It is desirable to be formed of a compound containing an element as a main component.

[0034]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, an n-channel TFT and a p-channel TFT are formed on the same substrate,
An embodiment for forming an inverter circuit which is a basic configuration of a MOS circuit will be described.

As the substrate 101, a glass substrate, a plastic substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate having a surface on which an insulating film such as a silicon oxide film or a silicon nitride film is formed, or a metal substrate represented by stainless steel may be used. Of course, it is also possible to use a quartz substrate.

On the main surface of the substrate 101 where the TFT is formed, a base film 102 made of a silicon nitride film,
A base film 103 made of a silicon oxide film is formed. These base films are formed by a plasma CVD method or a sputtering method, and are provided to prevent impurities harmful to the TFT from the substrate 101 from diffusing into the semiconductor layer. Therefore, the base film 102 made of a silicon nitride film is
To a thickness of 100 nm, typically 50 nm, and a base film 103 made of a silicon oxide film.
The thickness may be 0 nm, typically 150 to 200 nm.

Of course, the base film 102 made of a silicon nitride film or the base film 10 made of a silicon oxide film
3, but it is most desirable to adopt a two-layer structure in consideration of the reliability of the TFT.

The semiconductor layer formed in contact with the base film 103 is formed by solid-phase growth of an amorphous semiconductor formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method by a laser annealing method or a heat treatment. It is desirable to use a crystalline semiconductor crystallized by the method. Further, a microcrystalline semiconductor formed by the above film formation method can be used. The semiconductor material applicable here includes silicon (Si), germanium (Ge), a silicon germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can be used.

Alternatively, the semiconductor layer formed on the substrate 101 is an SOI (Silicon On I
nsulators) It may be a substrate. Several types of SOI substrates are known depending on the structure and manufacturing method, but typically, SIMOX (Separation by Implante).
d Oxygen), ELTRAN (Epitaxial Layer Transfe
r: a registered trademark of Canon Inc.) substrate, Smart-Cut (a registered trademark of SOITEC Inc.) and the like can be used. Of course, other SOI substrates can be used.

The semiconductor layer has a thickness of 10 to 100 nm, typically 50 nm. 10 to 40 at for an amorphous semiconductor film formed by a plasma CVD method.
Although hydrogen is contained in the film at a ratio of om%, a heat treatment process at 400 to 500 ° C. is performed prior to the crystallization process to desorb hydrogen from the film to reduce the hydrogen content to 5 atom% or less. It is desirable to keep. Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Since the base film and the amorphous semiconductor film can be formed by the same film forming method, the base film 102 and the base film 10 can be formed.
3 and a semiconductor layer may be formed continuously. After each film is formed, the surface is prevented from being exposed to the atmosphere, thereby preventing the surface from being contaminated. As a result, it was possible to eliminate one of the factors that cause variations in TFT characteristics.

In the step of crystallizing the amorphous semiconductor film, a known laser annealing technique or thermal annealing technique may be used. Alternatively, a crystalline semiconductor film can be used by a thermal annealing technique using a catalytic element. Furthermore, when a gettering step is added to a crystalline semiconductor film formed by a thermal annealing technique using a catalytic element to remove the catalytic element, excellent TFT characteristics can be obtained.

A resist mask is formed on the thus formed crystalline semiconductor film by a known patterning method using a first photomask, and the second island-like semiconductor layer 104 and the first Island-shaped semiconductor layer 1
05 was formed.

Next, the second island-like semiconductor layer 104 and the first
A gate insulating film 106 containing silicon oxide or silicon nitride as a main component is formed on the surface of the island-shaped semiconductor layer 105. The gate insulating film 106 may be formed by a plasma CVD method or a sputtering method and have a thickness of 10 to 200 nm, preferably 50 to 150 nm. (Figure 1
(A))

Then, the second photomask is used to form the second
Masks 107 and 108 covering the island-shaped semiconductor layer 104 and the channel formation region of the first island-shaped semiconductor layer 105
Was formed. At this time, a resist mask 109 may be formed in a region where a wiring is to be formed.

Then, a step of forming a second impurity region by adding an impurity element imparting n-type was performed. As an impurity element that imparts n-type to the crystalline semiconductor material, phosphorus (P), arsenic (As), antimony (Sb), and the like are known. Here, phosphorus is used, and phosphine (PH ₃₎ is used. ) Was performed by an ion doping method. In this step, the accelerating voltage is set at 8 to add phosphorus to the semiconductor layer thereunder through the gate insulating film 106.
It was set as high as 0 keV. The concentration of phosphorus added to the semiconductor layer is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , and here is set to 1 × 10 ¹⁸ atoms / cm ³ . Then, a region 110 in which phosphorus is added to the semiconductor layer,
111 was formed. Part of the second impurity region formed here functions as an LDD region.
(Fig. 1 (B))

In order to remove the resist mask, a commercially available alkaline stripper may be used, but the use of the ashing method was effective. The ashing method is a method in which a plasma is formed in an oxidizing atmosphere, and a cured resist is exposed to the plasma to remove the resist. However, it was effective to add water vapor in addition to oxygen in the atmosphere.

Then, the first surface of the gate insulating film 106 is
Of the conductive layer 112 was formed. The first conductive layer 112 is made of T
It is formed using a conductive material mainly containing an element selected from a, Ti, Mo, and W. Then, the first conductive layer 10
7 has a thickness of 10 to 100 nm, preferably 150 to 40 nm.
It may be formed at 0 nm. (Fig. 1 (C))

For example, WMo, TaN, MoTa, WS
Compounds such as ix (x = 2.4 <X <2.7) can be used.

Although conductive materials such as Ta, Ti, Mo and W have higher resistivity than Al and Cu, they can be used without any problem up to about 100 cm ² in relation to the area of the circuit to be manufactured. did it.

Next, resist masks 113, 114, 115 and 116 were formed using a third photomask. The resist mask 113 is for forming a gate electrode of a p-channel TFT.
Reference numerals 5 and 116 are for forming a gate wiring and a gate bus line. Also, the resist mask 11
Reference numeral 4 is formed to cover the entire surface of the first island-shaped semiconductor layer, and is provided as a mask for preventing the addition of impurities in the next step.

Unnecessary portions of the first conductive layer were removed by dry etching, and a second gate electrode 117, a gate wiring 119, and a gate bus line 120 were formed. Here, if a residue remains after etching,
Ashing was good.

Then, the resist masks 113, 114,
P-channel TFT, leaving 115, 116
A step of adding a p-type impurity element to a part of the second island-shaped semiconductor layer 104 in which is formed to form a third impurity region was performed. As the impurity element imparting the p-type, boron (B), aluminum (Al), and gallium (Ga) are known. Here, diborane (B ₂ H ₆ ) is used with boron as the impurity element. Was added by an ion doping method. Again, the acceleration voltage was set to 80 keV, and boron was added at a concentration of 2 × 10 ²⁰ atoms / cm ³ .
Then, as shown in FIG. 1D, third impurity regions 121 and 122 to which boron was added at a high concentration were formed.

After removing the resist mask provided in FIG. 1D, resist masks 123, 124, and 125 were formed using a fourth photomask. The fourth photomask is for forming a gate electrode of an n-channel TFT, and the first gate electrode 126 is formed by a dry etching method. At this time, the first gate electrode 1
26 is formed so as to overlap with a part of the second impurity regions 110 and 111 via the gate insulating film. (Figure 1
(E))

Then, the resist masks 123, 124,
After the 125 was completely removed, resist masks 129, 130, and 131 were formed using a fifth photomask. The resist mask 130 was formed so as to cover the first gate electrode 126 and further overlap a part of the second impurity regions 110 and 111. Resist mask 13
0 determines the offset amount of the LDD region.

Here, part of the gate insulating film may be removed using the resist mask 130 to expose the surface of the semiconductor layer where the first impurity region is formed. By doing so, the step of adding an impurity element imparting n-type, which is performed in the next step, can be effectively performed.

Then, a step of forming a first impurity region by adding an impurity element imparting n-type was performed. Then, a first impurity region 132 serving as a source region and a first impurity region 133 serving as a drain region were formed. Here, the ion doping method using phosphine (PH ₃ ) was performed. Also in this step, the acceleration voltage was set as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 106. The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm 2.
Preferably, it is set to ^3. Here, it is set to 1 × 10 ²⁰ atoms / cm ³ . (Fig. 2 (A))

Then, the gate insulating film 106, the first and second gate electrodes 126 and 117, the gate wiring 127,
The first interlayer insulating film 13 is formed on the surface of the gate bus line 128.
4, 135 were formed. The first interlayer insulating film 134 is a silicon nitride film and has a thickness of 50 nm. The first interlayer insulating film 135 is a silicon oxide film,
It was formed to a thickness of 0 nm.

The first interlayer insulating film 134 made of a silicon nitride film formed here was necessary for performing the next heat treatment step. This was effective in preventing the surfaces of the first and second gate electrodes 126 and 117, the gate wiring 127, and the gate bus line 128 from being oxidized.

The heat treatment step has to be performed in order to activate the n-type or p-type impurity element added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it has been difficult to activate a region under the gate electrode. Therefore, the activation step was performed here by the thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably at 350
The treatment was performed at ℃ 550 ° C., here 450 ° C., for 2 hours.

In this heat treatment step, hydrogen of 3 to 90% may be added in a nitrogen atmosphere. After the heat treatment step, the film is further heated at 150 to 500 ° C., preferably 300 to 450 ° C. in a 3 to 100% hydrogen atmosphere.
It is preferable to perform a hydrogenation process for up to 12 hours. Or
Hydrogen plasma treatment may be performed at a substrate temperature of 150 to 500 ° C, preferably 200 to 450 ° C. In any case, the characteristics of the TFT could be improved by compensating for the defects in which hydrogen remains in the semiconductor layer and at the interface thereof.

After the first interlayer insulating films 134 and 135 are formed using a sixth photomask, a predetermined resist mask is formed, and the respective TFTs are etched by an etching process.
A contact hole reaching the source region and the drain region was formed. Then, a second conductive layer is formed, and a seventh conductive layer is formed.
The source electrodes 136 and 137 and the drain electrode 138 were formed by the patterning process using the photomask described above. Although not shown, in the present embodiment, the electrode second conductive layer is formed of a Ti film having a thickness of 100 nm and a Ti-containing Al film 300.
nm and a Ti film of 150 nm were used as an electrode having a three-layer structure formed continuously by a sputtering method.

Through the above steps, the p-channel TFT is formed in a self-aligned manner (self-aligned), and the n-channel TFT is formed.
The FT was formed non-self-aligned (non-self-aligned).

In the n-channel type TFT of the CMOS circuit, the channel forming region 142 and the first impurity regions 145 and 14 are provided.
6. Second impurity regions 143 and 144 are formed. Here, the second impurity region includes regions (GOLD regions) 143a and 144a that overlap with the gate electrode, and regions (LDD regions) 1 that do not overlap with the gate electrode.
43b and 144b were respectively formed. And the first
The first impurity region 146 became a drain region while the first impurity region 145 became a source region.

On the other hand, in the p-channel type TFT, a channel formation region 139 and third impurity regions 140 and 141 were formed. Then, the third impurity region 140 became a source region, and the third impurity region 141 became a drain region. (FIG. 2 (B))

FIG. 2C is a top view of the inverter circuit, and shows the AA 'sectional structure of the TFT part, the BB' sectional structure of the gate wiring part, and the C-B part of the gate bus line part.
The C ′ cross-sectional structure corresponds to FIG. In the present invention, the gate electrode, the gate wiring, and the gate bus line are formed from the first conductive layer.

FIGS. 1 and 2 show an n-channel TFT and a p-channel TFT.
CMOS with complementary combination of channel type TFT
Although the circuit is described as an example, the present invention can be applied to an NMOS circuit using an n-channel TFT or a pixel portion of a liquid crystal display device.

[Embodiment 2] An embodiment of the present invention will be described with reference to FIGS. Here, an embodiment in which an n-channel TFT and a p-channel TFT are manufactured over the same substrate to form an inverter circuit which is a basic configuration of a CMOS circuit will be described.

First, as in the first embodiment, the substrate 30
1, a base film 302 made of a silicon nitride film, a base film 303 made of a silicon oxide film, a first island-shaped semiconductor layer 305, a second island-shaped semiconductor layer 304, and a gate insulating film 3.
06 was formed. (FIG. 3 (A))

Then, the second photomask is used to form the second
Resist masks 307 and 308 covering the island-shaped semiconductor layer 304 and the channel formation region of the first island-shaped semiconductor layer 305
Was formed. At this time, a resist mask 309 may be formed in a region where a wiring is to be formed.

Then, a step of forming a second impurity region by adding an impurity element imparting n-type was performed. Here, ion doping was performed using phosphorus and phosphine (PH ₃ ). First island-shaped semiconductor layer 3
05, the concentration of phosphorus added is 1 × 10 ¹⁶ to 1 × 10
^It is preferable to be in the range of ¹⁹ atoms / cm ³ , here 1 ×
It was 10 ¹⁸ atoms / cm ³ . Then, regions 310 and 311 in which phosphorus was added to the semiconductor layer were formed. Part of the second impurity region formed here functions as an LDD region. (Fig. 3 (B))

The first surface of the gate insulating film 306 is
Of the conductive layer 312 was formed. The first conductive layer 312 is formed of T
It is formed using a conductive material mainly containing an element selected from a, Ti, Mo, and W. Then, the first conductive layer 31
2 has a thickness of 100 to 1000 nm, preferably 150 to
The thickness may be 400 nm. (FIG. 3 (C))

Next, resist masks 313, 314, 315, and 316 were formed using a third photomask. Using this resist mask, a part of the first conductive layer 312 is removed by a dry etching method, so that a first gate electrode 318, a second gate electrode 317, a gate wiring 319, and a gate bus line 320 are formed. Was formed.
(FIG. 3 (D))

Then, the resist masks 313, 314,
After completely removing 315 and 316, resist masks 321, 322 and 323 were formed using a fourth photomask. The resist mask 322 is used for the first gate electrode 318.
And further overlap with a part of the second impurity regions 310 and 311. The resist mask 322 determines the offset amount of the LDD region.

Then, a step of forming a first impurity region by adding an impurity element imparting n-type was performed. Then, a first impurity region 325 serving as a source region and a first impurity region 324 serving as a drain region were formed. Here, the ion doping method using phosphine (PH ₃ ) was performed. Also in this step, the acceleration voltage was set as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 106. The concentration of phosphorus in this region is preferably set to 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ^3, and is set to 1 × 10 ²⁰ atoms / cm ³ here. (FIG. 3
(E))

Next, resist masks 326, 327, and 328 are formed using a fifth photomask, and a p-type is applied to a part of the second island-shaped semiconductor layer 304 where a p-channel TFT is formed. A step of forming a third impurity region by adding an impurity element was performed. Here, boron was added as an impurity element by ion doping using diborane (B ₂ H ₆ ). Again, the acceleration voltage was set to 80 keV, and boron was added at a concentration of 2 × 10 ²⁰ atoms / cm ³ .
Then, as shown in FIG. 4A, third impurity regions 329 and 330 to which boron was added at a high concentration were formed.

Then, the gate insulating film 306, the first and second gate electrodes 318 and 317, the gate wiring 319,
The first interlayer insulating film 32 is formed on the surface of the gate bus line 320.
9, 330 were formed. The first interlayer insulating film 329 is a silicon nitride film and has a thickness of 50 nm. The first interlayer insulating film 330 is a silicon oxide film,
It was formed to a thickness of 0 nm.

Thereafter, the heat treatment process is performed in the same manner as in the first embodiment, and the source electrode 331, 332 and the drain electrode 33 are formed.
3 is formed, and a channel forming region 337, first impurity regions 340, 3
41, and second impurity regions 338 and 339 are formed.
Here, the second impurity region includes regions (GOLD regions) 338a and 339a that overlap the gate electrode,
Region that does not overlap with the gate electrode (LDD region)
338b and 339b were formed respectively. Then, the first impurity region 340 became a source region, and the first impurity region 341 became a drain region.

On the other hand, the p-channel type TFT has a channel forming region 334 and a third impurity region 33 serving as a source region.
5. A third impurity region 336 to be a drain region was formed. (FIG. 4 (B))

FIG. 4C is a top view of the inverter circuit, and shows the AA 'sectional structure of the TFT portion, the BB' sectional structure of the gate wiring portion, and the C-B structure of the gate bus line portion.
The C ′ cross-sectional structure corresponds to FIG. In the present invention, the gate electrode, the gate wiring, and the gate bus line are formed from the first conductive layer.

FIGS. 3 and 4 show an n-channel TFT and a p-type TFT.
CMOS with complementary combination of channel type TFT
Although the circuit is described as an example, the present invention can be applied to an NMOS circuit using an n-channel TFT or a pixel portion of a liquid crystal display device.

[Embodiment 3] FIG. 2 shows the structure of the TFT of the present invention.
6 will be described in more detail. Here, FIG.
Are used in correspondence with the respective symbols in FIG. 1 and FIG. The second impurity region, which is an LDD region,
The second impurity region 144a which overlaps with the first gate electrode 126 can be divided into a second impurity region 144b which does not overlap. That is, an LDD region (Loff) that does not overlap with an LDD region (Lov) that overlaps with the gate electrode is formed.

In the LDD region, the lengths Lov and Loff can be easily implemented by patterning using three photomasks as described in the first embodiment. Embodiment 1
In the step indicated by, a resist mask is formed with a second photomask, and the second step is performed by a doping step of imparting n-type.
Is formed. A part of this region becomes an LDD region. Then, a first gate electrode is formed by the fourth photomask, and at this time, an overlap region (Lov) of the LDD is formed. Further, an LDD region (Loff) is formed by a resist mask formed by the fifth photomask.
Was formed.

However, these three photomasks are used not only to form a resist mask in the doping process but also as a mask for patterning the gate electrode, and also have these functions.

Therefore, the length of Lov and Loff was given a degree of design freedom, and could be set arbitrarily in consideration of the size of the TFT to be manufactured. This is a very useful method for manufacturing a TFT having a different driving voltage for each functional circuit in a large-area integrated circuit. FIG. 26 shows, as an example, TFs used for a logic circuit portion, a buffer circuit portion, an analog switch portion, and a pixel portion of an active matrix liquid crystal display device.
An example of the design value of T is shown. At this time, each TFT
In consideration of the drive voltage, the second impurity region 144a overlapping the gate electrode and the second impurity region 1 not overlapping the gate electrode, in addition to the channel length, are taken into consideration.
The length of 43b could be set appropriately.

For example, the TFT of the shift register circuit of the driver circuit of the liquid crystal display device and the TFT of the buffer circuit are basically focused on the on-characteristics.
The structure alone may be used, and the second impurity region 144b that does not overlap with the gate electrode is not necessarily provided. However, when it is provided, the value of Loff should be set in the range of 0.5 to 3 μm in consideration of the driving voltage. In consideration of the withstand voltage, it is desirable that the value of the second impurity region 143b which does not overlap with the gate electrode be increased as the driving voltage is increased.

In order to prevent an increase in off-state current of the sampling circuit and the TFT provided in the pixel portion, for example, when the channel length is 3 μm, the second impurity region 143a overlapping with the gate electrode is set to 1.5 μm. The second impurity region 143b that does not overlap with the gate electrode should have a thickness of 1.5 μm. Of course, the present invention is not limited to the design values shown here, but may be determined appropriately.

On the other hand, in the p-channel TFT, only the channel forming region, the source region, and the drain region had to be formed. Of course, the structure may be the same as that of the n-channel TFT of the present invention. However, since the p-channel TFT is originally high in reliability, the n-channel TFT is obtained by increasing the on-current.
It is preferable to balance the characteristics with the above. When the present invention is applied to a CMOS circuit as shown in FIG. 1, it is particularly important to balance these characteristics. However, there is no problem even if the structure of the present invention is applied to a p-channel TFT.

[Embodiment 4] An embodiment of the present invention will be described with reference to FIG. Here, an embodiment in which an n-channel TFT and a p-channel TFT are manufactured over the same substrate to form an inverter circuit which is a basic configuration of a CMOS circuit will be described.

First, as in the first embodiment, FIG.
The substrate in the state of FIG. Then, the resist masks 501, 502, and 503 are formed by the second photomask.
Was formed.

Then, a step of forming a third impurity region by adding an impurity element imparting p-type was performed. Here, boron is used as an impurity element and diborane (B ₂ H ₆ )
And added by an ion doping method. Again, the acceleration voltage was set to 80 keV, and boron was added at a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 5A, third impurity regions 504 and 50 to which boron is added at a high concentration are formed.
5 was formed.

Next, using a third photomask, resist masks 506, 507, and 508 are formed, and an n-type impurity element is added to a selected region of the first island-like semiconductor layer. A step of forming a second impurity region was performed. Here, ion doping was performed using phosphorus and phosphine (PH ₃ ). The concentration of the phosphorus added here is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , and here, it is 1 × 10 ¹⁸ atoms / cm ³ . Then, a region 509 in which phosphorus is added to the semiconductor layer,
510 was formed. Part of the second impurity region formed here functions as an LDD region.
(Fig. 5 (B))

Then, the surface of the gate insulating film 106 is
The first conductive layer 511 was formed using a conductive material mainly containing an element selected from a, Ti, Mo, and W. The thickness of the first conductive layer 511 is 100 to 1000 n.
m, preferably 150 to 400 nm.
(FIG. 5 (C))

Next, resist masks 512, 513, 514, and 515 were formed using a fourth photomask. Then, using this resist mask, a part of the first conductive layer 511 is removed by a dry etching method to form a first gate electrode 517, a second gate electrode 516, a gate wiring 518, and a gate bus line 519. Was formed.
(FIG. 5 (D))

Then, resist masks 520, 521, and 522 were formed using a fifth photomask. The resist mask 521 was formed so as to cover the first gate electrode 517 and overlap with a part of the second impurity regions 509 and 510. The resist mask 521 is
The offset amount of the DD area was determined.

Then, a step of forming a first impurity region by adding an impurity element imparting n-type was performed. Then, a first impurity region 524 serving as a source region and a first impurity region 523 serving as a drain region were formed. Here, the ion doping method using phosphine (PH ₃ ) was performed. The concentration of phosphorus in this region is 1 × 10 ¹⁹ to 1 ×
It is preferably 10 ²¹ atoms / cm ³ , where 1 × 1
It was set to 0 ²⁰ atoms / cm ³ . (FIG. 5E)

Thereafter, the heat treatment process is performed in the same manner as in the first embodiment, and the source electrodes 527 and 528 and the drain electrode 52 are formed.
9 are formed, and a channel forming region 533, first impurity regions 536, and 5 are formed in the n-channel TFT of the CMOS circuit.
37, and second impurity regions 534 and 535 were formed.
Here, the second impurity region includes regions (GOLD regions) 534a and 535a overlapping with the gate electrode,
Region that does not overlap with the gate electrode (LDD region)
534b and 535b were formed respectively. Then, the first impurity region 536 became a source region, and the first impurity region 537 became a drain region. On the other hand, the p-channel TFT includes a channel formation region 530, a third impurity region 531 serving as a source region, and a third impurity region 531 serving as a drain region.
Of impurity region 532 was formed. (FIG. 5 (F))

[Embodiment 5] An embodiment of the present invention will be described with reference to FIG. Here, an embodiment in which an n-channel TFT and a p-channel TFT are manufactured over the same substrate to form an inverter circuit which is a basic configuration of a CMOS circuit will be described.

First, as in the first embodiment, FIG.
The substrate in the state of FIG. Then, the resist masks 601, 602, and 603 are formed by the second photomask.
Was formed.

Then, a step of forming a third impurity region by adding an impurity element imparting p-type was performed. Here, boron is used as an impurity element and diborane (B ₂ H ₆ )
And added by an ion doping method. 80k acceleration voltage
As eV, boron was added to a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 6A, third impurity regions 604 and 605 to which boron was added at a high concentration were formed.

Then, resist masks 606, 607, and 608 were formed using a third photomask. And
A step of adding an impurity element imparting n-type to the first island-shaped semiconductor layer 105 to form a first impurity region was performed.
A first impurity region 610 serving as a source region and a first impurity region 609 serving as a drain region were formed. Here, the ion doping method using phosphine (PH ₃ ) was performed. The concentration of phosphorus in this region is 1 × 10 ¹⁹ to 1 × 10
^It is preferably ²¹ atoms / cm ³ , here 1 × 10 ²⁰ a
toms / cm ³ . (FIG. 6 (B))

Next, using a fourth photomask, resist masks 611, 612, and 613 are formed, and an n-type impurity element is added to a selected region of the first island-shaped semiconductor layer 105 by adding it. And a step of forming a second impurity region. Here, phosphine (P
H ₃ ) was used. The concentration of phosphorus added here is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3.
It is preferable to set the range to 1 × 10 ¹⁸ atoms /
cm ³ . Then, regions 614 and 615 to which phosphorus was added to the semiconductor layer were formed. Part of the second impurity region formed here functions as an LDD region. (Fig. 6 (C))

Then, the surface of the gate insulating film 106 is
The first conductive layer 616 was formed using a conductive material mainly containing an element selected from a, Ti, Mo, and W. The thickness of the first conductive layer 616 is 100 to 1000 n.
m, preferably 150 to 400 nm.
(FIG. 6 (D))

Next, resist masks 617, 618, 619, and 620 were formed using a fifth photomask. Then, part of the first conductive layer 616 was removed by a dry etching method, so that a first gate electrode 622, a second gate electrode 621, a gate wiring 623, and a gate bus line 624 were formed. (FIG. 6E)

Thereafter, the heat treatment process is performed in the same manner as in the first embodiment, and the source electrodes 627 and 628 and the drain electrode 62 are formed.
9, the channel forming region 633 and the first impurity regions 636 and 6 are formed in the n-channel TFT of the CMOS circuit.
37, and second impurity regions 634 and 635 were formed.
Here, the second impurity region includes regions (GOLD regions) 634a and 635a that overlap the gate electrode,
Region that does not overlap with the gate electrode (LDD region)
634b and 635b were formed respectively. Then, the first impurity region 636 became a source region, and the first impurity region 637 became a drain region. On the other hand, the p-channel TFT includes a channel formation region 630, a third impurity region 631 serving as a source region, and a third impurity region 631 serving as a drain region.
Is formed. (FIG. 6 (F))

[Embodiment 6] An embodiment of the present invention will be described with reference to FIG. Here, an embodiment in which an n-channel TFT and a p-channel TFT are manufactured over the same substrate to form an inverter circuit which is a basic configuration of a CMOS circuit will be described.

First, as in the first embodiment, FIG.
The substrate in the state of FIG. Then, the resist masks 701, 702, and 703 are formed by the second photomask.
Was formed.

First, an impurity element imparting n-type conductivity is selectively added to the first island-shaped semiconductor layer 105 to form a first
Was formed. Here, phosphine (P
H ₃ ) was used. The concentration of phosphorus in this region is preferably 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ^3, and in this case, 1 × 10 ²⁰ atoms / cm ³ . Then, regions 704 and 705 in which phosphorus was added to the semiconductor layer were formed. (FIG. 7 (A))

Next, resist masks 706, 707, and 708 are formed using a third photomask, and an n-type impurity element is added to a selected region of the first island-shaped semiconductor layer. A step of forming a second impurity region was performed. The concentration of phosphorus added here is 1 × 10 ¹⁶ to 1 ×
It is preferable to be in the range of 10 ¹⁹ atoms / cm ³ , typically 1 × 10 ¹⁸ atoms / cm ³ . Then, regions 709 and 710 in which phosphorus was added to the semiconductor layer were formed. Part of the second impurity region formed here is LD
It functions as a D area. (FIG. 7 (B))

Then, the surface of the gate insulating film 106 is
The first conductive layer 711 was formed using a conductive material mainly containing an element selected from a, Ti, Mo, and W. The thickness of the first conductive layer 711 is 100 to 1000 n.
m, preferably 150 to 400 nm.
(FIG. 7 (C))

Next, resist masks 712, 713, and 714 were formed using a fourth photomask. The resist mask 712 is for forming the second gate electrode, and the resist mask 713 is formed to cover the entire surface of the first island-shaped semiconductor layer. It was provided as a blocking mask.

Unnecessary portions of the first conductive layer were removed by dry etching, and a second gate electrode 715 was formed. Then, a second p-channel TFT is formed.
A step of adding a p-type impurity element to a part of the island-shaped semiconductor layer 104 to form a third impurity region was performed. The added impurity element imparting p-type is boron, which is added at a concentration of 2 × 10 ²⁰ atoms / cm ³ . And
As shown in FIG. 7D, third impurity regions 718 and 719 to which boron was added at a high concentration were formed.

Next, resist masks 718, 719, 720, 721 were formed using a fifth photomask. Then, using this resist mask, part of the first conductive layers 716 and 717 is removed by a dry etching method, so that the first gate electrode 722, the gate wiring 723,
A gate bus line 721 was formed. (FIG. 7
(E))

Thereafter, the heat treatment process is performed in the same manner as in the first embodiment, and the source electrodes 727 and 728 and the drain electrode 72 are formed.
9, the channel forming region 733 and the first impurity regions 736 and 7 are formed in the n-channel TFT of the CMOS circuit.
37, and second impurity regions 734 and 735 were formed.
Here, the second impurity region includes regions (GOLD regions) 734a and 735a that overlap with the gate electrode,
Region that does not overlap with the gate electrode (LDD region)
734b and 735b were formed, respectively. Then, the first impurity region 736 became a source region, and the first impurity region 737 became a drain region. On the other hand, the p-channel TFT includes a channel formation region 730, a third impurity region 731 serving as a source region, and a third impurity region 731 serving as a drain region.
Impurity region 732 was formed. (FIG. 7 (F))

[Embodiment 7] First, in the same manner as in Embodiment 1, a substrate in the state of FIG. 1A is formed. And the second
Resist masks 801 and 80
2,803 were formed.

First, an impurity element imparting n-type conductivity is selectively added to the first island-shaped semiconductor layer 105 to form a first
Was formed. Here, phosphine (P
H ₃ ) was used. The concentration of phosphorus in this region is preferably set to 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ^3, and is set to 1 × 10 ²⁰ atoms / cm ³ here. Then, regions 804 and 805 to which phosphorus was added to the semiconductor layer were formed. (FIG. 8 (A))

Next, a resist is formed using a third photomask.
Masks 806, 807, 808 and p-type
To form a third impurity region by adding an impurity element
The process was performed. Here, boron is the impurity element
And diborane (B_TwoH₆) And added by ion doping method
did. Here, the acceleration voltage is set to 80 keV and 2 × 10
²⁰atoms / cm^ThreeBoron was added to a concentration of. And FIG.
(B) As shown in FIG.
Impurity regions 809 and 810 were formed.

Next, using a third photomask, resist masks 811, 812, and 813 are formed, and an n-type impurity element is added to a selected region of the first island-like semiconductor layer. A step of forming a second impurity region was performed. Here, ion doping was performed using phosphorus and phosphine (PH ₃ ). The concentration of the phosphorus added here is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , and here, it is 1 × 10 ¹⁸ atoms / cm ³ . Then, a region 814 in which phosphorus is added to the semiconductor layer,
815 was formed. Part of the second impurity region formed here functions as an LDD region.
(FIG. 8 (C))

Then, the surface of the gate insulating film 106 is
The first conductive layer 816 was formed using a conductive material mainly containing an element selected from a, Ti, Mo, and W. The thickness of the first conductive layer 816 is 100 to 1000 n.
m, preferably 150 to 400 nm.
(FIG. 8 (C))

Next, resist masks 817, 818, 819, and 820 were formed using a fourth photomask. Then, using this resist mask, part of the first conductive layer 816 is removed by a dry etching method, so that a first gate electrode 822, a second gate electrode 821, a gate wiring 823, and a gate bus line 824 are formed. Was formed.
(FIG. 8 (E))

Thereafter, the heat treatment process is performed in the same manner as in the first embodiment, and the source electrodes 827 and 828 and the drain electrode 82 are formed.
9, a channel formation region 833 and first impurity regions 836 and 836 are formed in the n-channel TFT of the CMOS circuit.
37, and second impurity regions 834 and 835 were formed.
Here, the second impurity region includes regions (GOLD regions) 834a and 835a that overlap with the gate electrode,
Region that does not overlap with the gate electrode (LDD region)
834b and 835b were formed respectively. Then, the first impurity region 836 became a source region, and the first impurity region 837 became a drain region. On the other hand, the p-channel TFT includes a channel formation region 830, a third impurity region 831 serving as a source region, and a third impurity region 831 serving as a drain region.
Impurity region 832 was formed. (FIG. 8 (F))

[Embodiment 8] First, the state shown in FIG. And FIG. 9 (A)
As shown in the figure, resist masks 901, 902, 903
Was formed. The resist mask 902 is an n-channel type TF
It is formed so as to cover the first gate electrode 126 of T and a part of the second impurity region, and is for forming an LDD. Here, only the drain side of the n-channel TFT is formed. I made it. The LDD prevents an increase in leakage current, but a sufficient effect can be obtained only by providing it on the drain side. (FIG. 9A)

The subsequent steps were performed in the same manner as in Embodiment 1, whereby the CMOS circuit shown in FIG. 9B was formed.
The channel forming region 91 is formed in the n-channel TFT.
4. First impurity regions 917 and 918 and second impurity regions 915 and 916 were formed. Here, as the second impurity region 916, a region (GOLD region) 916a overlapping with the first gate electrode and a region (LDD region) 916b not overlapping with the first gate electrode were formed. And
The first impurity region 917 became a source region, and the first impurity region 918 became a drain region.

[Embodiment 9] This embodiment will be described with reference to FIG. First, following the same steps as in Embodiment 1, FIG.
The state shown in (C) was obtained.

Then, resist masks 1012, 1013, 1014, and 1015 were formed using a photomask, and part of the first conductive layer 511 was removed by dry etching. After that, using the resist mask as it is, a second doping step for imparting n-type is performed,
Region 101 in which phosphorus is added to semiconductor layers 104 and 105
0, 1011, 1020, and 1021 were formed. (FIG. 10A)

Here, the resist mask was completely removed using ashing and an alkaline stripper. Then, a photoresist film was formed again, and a patterning step by exposure from the back surface was performed. At this time, the gate electrode,
The gate wiring and the pattern of the gate bus line play the same role as the photomask, and the resist mask 1022,
1023, 1024, and 1025 were formed on each pattern. Exposure from the back side is performed using direct light and scattered light, and a resist mask is formed on the inside of the gate electrode as shown in FIG. 10B by adjusting exposure conditions such as light intensity and exposure time. We were able to.

Then, the gate electrode, the gate wiring, and a part of the gate bus line are removed by dry etching, so that the first gate electrode 1002, the second gate electrode 1001, the gate wiring 1003, the gate bus line 1004 are removed. Was formed.

The subsequent steps were performed in the same manner as in Embodiment 5, whereby the CMOS circuit shown in FIG. 10C was formed. The channel formation region 1034, the first impurity regions 1037 and 1038, the second
Of impurity regions 1035 and 1036 are formed. Here, the second impurity region is a region (GOLD region) 1035a, 1036 overlapping with the first gate electrode.
a and a non-overlapping region (LDD region) 103
5b and 1036b were formed. Then, the first impurity region 1037 became a source region, and the first impurity region 1038 became a drain region.

[0129]

[Embodiment 1] In this embodiment, a method of simultaneously manufacturing a CMOS circuit which is a basic form of a pixel portion and a driving circuit provided around the pixel portion with reference to FIGS. explain.

In FIG. 11, an alkali-free glass substrate typified by, for example, a 1737 glass substrate manufactured by Corning Incorporated was used as the substrate 1101. Then, the T of the substrate 1101
A base film 1102 is formed on the surface on which the
It was formed by a VD method or a sputtering method. Although the base film 1102 is not shown, the silicon nitride film is formed to a thickness of 25 to 100 nm, here 50 nm, and the silicon oxide film is formed to a thickness of 50 to 30 nm.
It was formed to a thickness of 0 nm, here 150 nm. Also,
As the base film 1102, only a silicon nitride film or a silicon nitride oxide film may be used.

As the base film 1102, in addition to the above materials, a first silicon oxynitride film made of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD to a thickness of 10 to 100 nm is formed. May have a two-layer structure in which a second silicon oxynitride film made of SiH ₄ and N ₂ O is stacked to a thickness of 100 to 200 nm.

[0132] The first silicon oxynitride film is formed by a parallel plate type plasma CVD method. The first silicon oxynitride film is made of 10 SCCM of SiH ₄ , 100 SCCM of NH ₃ ,
N ₂ O was introduced into the reaction chamber at 20 SCCM, and the substrate temperature was changed to 32 SCCM.
5 ° C., reaction pressure 40 Pa, discharge power density 0.41 W / cm ² ,
The discharge frequency was set to 60 MHz. On the other hand, the second silicon oxynitride film was introduced into the reaction chamber with SiH ₄ at ₄ SCCM and N ₂ O at 400 SCCM, and the substrate temperature was 400 ° C. and the reaction pressure was
a, the discharge power density was 0.41 W / cm ² , and the discharge frequency was 60 MHz. These films can be continuously formed only by changing the substrate temperature and switching the reaction gas. Also,
The first silicon oxynitride film is formed so that its internal stress becomes a tensile stress, considering the substrate as a center. The second silicon oxynitride film also has an internal stress in the same direction, but preferably has a smaller stress than the first silicon oxynitride film in absolute value.

Next, a 50 nm film is formed on the underlayer 1102.
An amorphous silicon film having a thickness of 2 was formed by a plasma CVD method. Although it depends on the content of hydrogen, the amorphous silicon film is preferably subjected to dehydrogenation treatment by heating at 400 to 550 ° C. for several hours to reduce the content of hydrogen to 5 atom% or less and to perform the crystallization step. . Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Here, both the base film and the amorphous silicon film are produced by the plasma CVD method. At this time, even if the base film and the amorphous silicon film are formed continuously in vacuum. good. After the formation of the base film, the step of once exposing the film to the air atmosphere made it possible to prevent the surface from being contaminated and to reduce the variation in the characteristics of the TFT to be manufactured.

In the step of crystallizing the amorphous silicon film, a known laser annealing technique or thermal annealing technique may be used. In this embodiment, a crystalline silicon film is formed by condensing a pulse oscillation type KrF excimer laser beam linearly and irradiating the amorphous silicon film.

In this embodiment, a crystalline silicon film is formed from an amorphous silicon film as a semiconductor layer. However, a microcrystalline silicon film may be used, or a crystalline silicon film may be formed directly. .

The crystalline silicon film thus formed was patterned using a first photomask to form island-like semiconductor layers 1103, 1104, and 1105.

Next, the island-like semiconductor layers 1103, 110
4 and 1105, a gate insulating film 1106 containing silicon oxide or silicon nitride as a main component was formed. The gate insulating film 1106 is formed of N ₂ O and S by a plasma CVD method.
iH ₄ 10 to 200 of the silicon nitride oxide film as a raw material
nm, preferably 50 to 150 nm. Here, it was formed to a thickness of 100 nm. (FIG. 11
(A))

Then, using the second photomask, the resist masks 1107 and 1108 covering the semiconductor layer 1103 and the channel formation regions of the semiconductor layers 1104 and 1105 are formed.
1109, 1110, and 1111 were formed. At this time,
A resist mask 1109 may be formed in a region where a wiring is to be formed.

Then, a step of forming a second impurity region by adding an impurity element imparting n-type was performed. Here, ion doping was performed using phosphorus and phosphine (PH ₃ ). In this step, the gate insulating film 11
The accelerating voltage was set to 65 keV in order to add phosphorus to the semiconductor layer below through 06. The concentration of phosphorus added to the semiconductor layer is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm
^It is preferable to set the range to ³ ; here, 1 × 10 ¹⁸ atoms
/ cm ³ . Then, regions 1112, 1113, 1114, 1115, and 1116 in which phosphorus was added to the semiconductor layer were formed. A part of the region to which phosphorus is formed is a second impurity region which functions as an LDD region. (FIG. 11 (B))

Thereafter, the resist mask is removed, and the first mask is removed.
Was formed on the entire surface. First conductive layer 11
17 uses a conductive material mainly containing an element selected from Ta, Ti, Mo, and W. And the first conductive layer 1
The thickness of 117 is 100-1000 nm, preferably 15
What is necessary is just to form in 0-400 nm. Here, Ta was formed by a sputtering method. (FIG. 11 (C))

When a Ta film is used for the first conductive layer, it can be formed by a sputtering method. The Ta film uses Ar as a sputtering gas. When an appropriate amount of Xe or Kr is added to these sputter gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, while the resistivity of the β-phase Ta film is 18 μΩcm.
It is about 0 μΩcm, which is not suitable for a gate electrode. However, since the TaN film has a crystal structure close to the α phase, if a Ta film is formed thereon, an α phase Ta film can be easily obtained. Therefore, although not shown, 1 under the first conductive film.
The TaN film may be formed with a thickness of 0 to 50 nm. Similarly, although not shown, 2 to 20 are formed below the first conductive film.
It is effective to form a silicon film doped with phosphorus (P) with a thickness of about nm. Thus, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, the alkali metal element contained in the first conductive film or the second conductive film in a small amount is diffused into the gate insulating film 1106. Can be prevented. In any case, the first conductive film preferably has a resistivity in the range of 10 to 50 μΩcm.

In addition, a W film can be used. In this case, a W film is formed to a thickness of 200 nm by introducing argon (Ar) gas and nitrogen (N ₂ ) gas by sputtering using W as a target. Formed. Further, the W film can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to make it 0 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains.
When there are many impurity elements such as oxygen in the film, crystallization is inhibited and the resistance is increased. Accordingly, in the case of the sputtering method, a W target having a purity of 99.9999% is used, and the W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation. 9-20
μΩcm can be realized.

Next, resist masks 1118, 1119, 1120, 1121, and 11 are formed using a third photomask.
22, 1123 were formed. The fourth photomask is p
This is for forming a gate electrode of a channel type TFT, a gate wiring of a CMOS circuit and a pixel portion, and a gate bus line. Since the gate electrode of the n-channel TFT is formed in a later step, the resist mask 111 is formed so that the first conductive layer 1117 remains over the entire surface of the semiconductor layer 1104.
9, 1123 were formed.

Unnecessary portions of the first conductive layer were removed by a dry etching method. Ta etching is CF ₄ and O ₂
Was carried out using a mixed gas of Then, the gate electrode 112
4, gate wirings 1126 and 1128 and a gate bus line 1127 were formed.

Then, the resist masks 1118, 111
9, 1120, 1211, 1122, and 1123, and the semiconductor layer 1 on which the p-channel TFT is formed is left.
A step of adding an impurity element imparting p-type to a part of 103 was performed. Here, boron was added as an impurity element by ion doping using diborane (B ₂ H ₆ ). Here, the acceleration voltage is set to 80 keV and 2 × 10
Boron was added to a concentration of ²⁰ atoms / cm ³ . And FIG.
As shown in FIG. 2 (A), the third in which boron is added at a high concentration
Impurity regions 1130 and 1311 were formed.

After removing the resist mask provided in FIG. 12A, a resist mask 1124, 1125, 1126, 1127, 1 is newly formed using a fourth photomask.
128, 1129 and 1130 were formed. The fourth photomask is for forming a gate electrode of an n-channel TFT, and gate electrodes 1131, 1132, and 1133 are formed by a dry etching method. At this time, the gate electrodes 1131, 1132, 1133 are connected to the second impurity regions 1112, 1113, 1114, 1115, 11
16 was formed so as to overlap with a part of the same. (FIG. 12
(B))

After completely removing the resist mask, new resist masks 1135, 1136, 113
7, 1138, 1139, 1140, 1141 were formed. The resist masks 1136, 1139, 1140 are n
Gate electrodes 1131, 1132, 1 of channel type TFT
133 and a part of the second impurity region. Here, the resist masks 1136, 1
Reference numerals 139 and 1140 determine the offset amount of the LDD region.

Then, a step of forming a first impurity region by adding an impurity element imparting n-type was performed. Then, the first impurity regions 1143 and 11 serving as source regions
44, a first impurity region 1142 serving as a drain region,
1145 and 1146 were formed. Here, the ion doping method using phosphine (PH ₃ ) was performed. Also in this step, the acceleration voltage was set to 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 1106. The concentration of phosphorus in this region is the first to give n-type.
Higher concentration than the process of adding the impurity element of
It is preferably 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ^3, and here it is 1 × 10 ²⁰ atoms / cm ³ . (FIG. 12
(C))

When the steps up to FIG. 12C are completed, a step of forming first interlayer insulating films 1147 and 1148 was performed. First, a silicon nitride film 1147 was formed to a thickness of 50 nm. Silicon nitride film 1147 is plasma CVD
₅ SCCM for SiH ₄ and 40 SC for NH ₃
CM, and the N ₂ was introduced 100SCCM 0.7Torr,
300 W high frequency power was applied. And then the first
Silicon oxide film as TEOS as interlayer insulating film 1148
The 500SCCM, the O ₂ was introduced 50SCCM 1Tor
A high-frequency power of 200 W was applied to form a film having a thickness of 950 nm. (FIG. 13)

Then, a heat treatment step was performed. The heat treatment step had to be performed in order to activate the n-type or p-type impurity element added at each concentration. This step includes a thermal annealing method using an electric heating furnace,
The laser annealing method using the above-described excimer laser or the rapid thermal annealing method (RTA method) using a halogen lamp may be used. Here, the activation step was performed by a thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C.
Here, the treatment was performed at 450 ° C. for 2 hours.

After that, the first interlayer insulating films 1147 and 1148 were patterned to form contact holes reaching the source region and the drain region of each TFT. Then, the source electrodes 1149, 1150, 1151
And drain electrodes 1152 and 1153 were formed. Although not shown, in this embodiment, this electrode is
nm, Al film containing Ti 300 nm, Ti film 150 nm
Was used as an electrode having a three-layer structure continuously formed by a sputtering method.

Through the above steps, the channel formation region 1157, the first impurity regions 1160 and 1161, the second impurity region 1158,
1159 was formed. Here, the second impurity region is
Region overlapping with gate electrode (GOLD region)
1158a and 1159a, and regions (LDD regions) 1158b and 1159b that do not overlap with the gate electrode were formed, respectively. Then, the first impurity region 1160
Is a source region, and the first impurity region 1161 is a drain region.

In the p-channel TFT, a channel formation region 1154 and third impurity regions 1155 and 1156 were formed. Then, the third impurity region 1155 became a source region, and the third impurity region 1156 became a drain region.

The n-channel TFT in the pixel portion has a multi-gate structure, and has channel forming regions 1162 and 1116.
63 and first impurity regions 1168, 1169, 1145
And second impurity regions 1164, 1165, 1166, 1
167 were formed. Here, the second impurity regions are regions 1164a, 1165a, and 1166 overlapping with the gate electrode.
a, regions 1164b, 1165 that do not overlap with 1167a
b, 1166b and 1167b were formed.

In this way, as shown in FIG.
An active matrix substrate on which a CMOS circuit and a pixel portion were formed was manufactured. On the drain side of the n-channel TFT in the pixel portion, a low-concentration impurity region 1170, a gate insulating film 1106, and a storage capacitor electrode to which an impurity element imparting n-type is added at the same concentration as the second impurity region. 1171 was formed, and the storage capacitor provided in the pixel portion was formed at the same time.

[Embodiment 2] This embodiment shows an example in which a crystalline semiconductor film used as a semiconductor layer in Embodiment 1 is formed by a thermal annealing method using a catalytic element. When a catalyst element is used, it is desirable to use the technology disclosed in JP-A-7-130652 and JP-A-8-78329.

FIG. 18 shows an example in which the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 is applied to the present invention. First, a silicon oxide film 180 is formed on a substrate 1801.
2 and an amorphous silicon film 1803 was formed thereon. Further, a nickel acetate salt solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 1804. (FIG. 18A)

Next, after the dehydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500 to 650 ° C. for 4 to 12 hours, for example, 550 ° C.
Heat treatment at 8 ° C. for 8 hours to obtain a crystalline silicon film 1805.
Was formed. The crystalline silicon film 180 thus obtained
5 had very good crystallinity. (FIG. 18 (B))

The technique disclosed in Japanese Patent Application Laid-Open No. 8-78329 allows selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. A case where the same technology is applied to the present invention will be described with reference to FIG.

First, a silicon oxide film 1902 is provided on a glass substrate 1901, and an amorphous silicon film 190 is formed thereon.
3. A silicon oxide film 1904 was formed continuously. At this time, the thickness of the silicon oxide film 1904 was set to 150 nm.

Next, the silicon oxide film 1904 was patterned to selectively form openings 1905, and then a nickel acetate solution containing 10 ppm by weight of nickel was applied. Thus, a nickel-containing layer 1906 was formed, and the nickel-containing layer 1906 was in contact with the amorphous silicon film 1902 only at the bottom of the opening 1905. (FIG. 19A)

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment was performed at 570 ° C. for 14 hours to form a crystalline silicon film 1907. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally from there. The crystalline silicon film 1907 thus formed is composed of a collection of rod-shaped or needle-shaped crystals, each of which grows in a specific direction when viewed macroscopically, and thus has uniform crystallinity. There is an advantage. (FIG. 19B)

The catalyst elements usable in the above two technologies are not only nickel (Ni) but also germanium (Ge), iron (Fe), palladium (Pd), tin (S
n), lead (Pb), cobalt (Co), platinum (Pt),
Elements such as copper (Cu) and gold (Au) may be used.

By forming a crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) using the above-described techniques and performing patterning, a crystalline T
An FT semiconductor layer can be formed. The TFT manufactured from the crystalline semiconductor film using the technique of the present embodiment is:
Although excellent characteristics can be obtained, high reliability has been required. However, by adopting the TFT structure of the present invention, the TFT utilizing the technology of this embodiment to the maximum
Can be manufactured.

[Embodiment 3] In this embodiment, as a method of forming a semiconductor layer used in Embodiment 1, after forming an amorphous semiconductor film as an initial film and using the catalyst element to form a crystalline semiconductor film, Then, an example in which a step of removing the catalytic element from the crystalline semiconductor film is performed will be described. In this embodiment, the method is described in JP-A-10-247735 and JP-A-10-1.
The technology described in JP-A-35468 or JP-A-10-135469 was used.

The technique described in this publication is a technique for removing the catalytic element used for crystallization of the amorphous semiconductor film after crystallization by using the gettering action of phosphorus. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1
It can be reduced to 0 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ .

The configuration of this embodiment will be described with reference to FIG. Here, an alkali-free glass substrate typified by a Corning 1737 substrate was used. In FIG. 20A, the underlayer 20 is formed using the crystallization technique described in the third embodiment.
02 shows a state where the crystalline silicon film 2003 is formed. Then, a silicon oxide film 2004 for a mask is formed with a thickness of 150 nm on the surface of the crystalline silicon film 2003, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus was performed to provide a region 2005 in which phosphorus was added to the crystalline silicon film.

In this state, 550 to 80
When heat treatment is performed at 0 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, the region 2005 in which phosphorus is added to the crystalline silicon film functions as a gettering site, and the catalyst remaining in the crystalline silicon film 2003 The element was able to segregate in the region 2005 to which phosphorus was added.

Then, the silicon oxide film 200 for the mask is formed.
4 and the phosphorus-added region 2005 are removed by etching, so that the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. Could be obtained. This crystalline silicon film could be used as it is as the semiconductor layer of the TFT of the present invention shown in the first embodiment.

[Embodiment 4] In this embodiment, another embodiment in which a semiconductor layer and a gate insulating film are formed in the step of manufacturing the TFT of the present invention shown in Embodiment 1 will be described. The configuration of this embodiment will be described with reference to FIG.

Here, at least 700 to 1100 ° C.
A substrate having a high degree of heat resistance is required.
01 was used. A crystalline semiconductor is formed using the techniques described in the second and third embodiments, and the
The semiconductor layers 2102 and 2103 were formed by patterning in the shape of an island in order to obtain the semiconductor layer. Then, the gate insulating film 2104 was formed to cover the semiconductor layers 2102 and 2103 with a film containing silicon oxide as a main component. In this embodiment, a silicon nitride oxide film is formed to a thickness of 70 nm by a plasma CVD method.
The thickness was formed. (FIG. 21A)

Then, heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. In this embodiment, 9
50 ° C., 30 minutes. The processing temperature is 700 to 110.
The temperature may be selected within the range of 0 ° C.
I wish I had to choose between the hours. (FIG. 21 (B))

As a result, under the conditions of this embodiment, a thermal oxide film was formed at the interface between the semiconductor layers 2102 and 2103 and the gate insulating film 2104, and a gate insulating film 2107 was formed. Further, in the course of oxidation in a halogen atmosphere, impurities contained in the gate insulating film 2104 and the semiconductor layers 2102 and 2103, particularly metal impurity elements, formed a compound with halogen and could be removed in the gas phase.

Gate insulating film 21 manufactured by the above steps
In No. 07, the withstand voltage was high and the interface between the semiconductor layers 2105 and 2106 and the gate insulating film 2107 was very good. In order to obtain the structure of the TFT of the present invention, the subsequent steps should have been performed according to the first embodiment.

[Embodiment 5] In this embodiment, a crystalline semiconductor film is formed by the method shown in Embodiment 2 and used in the crystallization step in the method of manufacturing an active matrix substrate in the process shown in Embodiment 1. An example in which the removed catalyst element is removed by gettering will be described. First, in Example 1, FIG.
Semiconductor layers 1103, 1104, 110 shown in FIG.
5 was a crystalline silicon film produced using a catalytic element. At this time, since the catalyst element used in the crystallization step remains in the semiconductor layer, it was desirable to perform the gettering step.

In this case, the steps up to the step shown in FIG. Then, as shown in FIG. 22, new resist masks 2201, 1136, 1137, 113
8, 1139 and 1140 were formed. Then, a step of forming a first impurity region by adding an impurity imparting n-type was performed. Then, regions 2202, 2203, 1142, 1143, 1144 in which phosphorus is added to the semiconductor layer,
1145 and 1146 were formed. (FIG. 22A)

Here, the region 2202 to which phosphorus is added,
Boron, which is an impurity element imparting p-type, has already been added to 2203, and at this time, the phosphorus concentration is 1 × 10
¹⁹ to 1 × 10 ²¹ atoms / cm ^3, which is 1 /
Since it was added at a concentration of about 2, it did not affect the characteristics of the p-channel TFT at all.

In this state, 400 to 80 in a nitrogen atmosphere.
A heat treatment process was performed at 0 ° C. for 1 to 24 hours, for example, 500 ° C. for 12 hours. By this step, the added impurity element imparting n-type and p-type could be activated. Further, the region where the phosphorus was added became a gettering site, and the catalyst element remaining after the crystallization step could be segregated. As a result, the catalytic element could be removed from the channel formation region. (FIG. 22
(B))

After the step of FIG. 22B was completed, an active matrix substrate could be manufactured following the steps of Example 1.

[Embodiment 6] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described with reference to FIGS.

A passivation film 1401 was formed on the active matrix substrate in the state shown in FIG. The passivation film 1401 is a silicon nitride film of 50n.
m. Further, a second interlayer insulating film 1402 made of an organic resin was formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

Further, a third interlayer insulating film was formed. Third
The interlayer insulating film 1404 was formed of an organic resin film such as polyimide. Then, the third interlayer insulating film 1404 and the second
A contact hole reaching the drain electrode 1153 was formed in the interlayer insulating film 1402 and the passivation film 1401 to form a pixel electrode 1405. Pixel electrode 1405
For a transmissive liquid crystal display device, a transparent conductive film may be used, and for a reflective liquid crystal display device, a metal film may be used. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 1405 was formed.

Next, as shown in FIG.
1 is formed on the surface of the third interlayer insulating film 1404 and the pixel electrode 1405. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. Opposite substrate 1502
, A transparent conductive film 1503 and an alignment film 1504 were formed. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were parallel-aligned with a certain pretilt angle.

Through the above steps, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the opposing substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. . afterwards,
A liquid crystal material 1508 was injected between both substrates, and completely sealed with a sealant (not shown). Thus, the active matrix type liquid crystal display device shown in FIG. 15 was completed.

Next, the configuration of the active matrix type liquid crystal display device of this embodiment will be described with reference to FIGS. FIG. 16 is a perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel portion 1601, a scanning (gate) line driving circuit 1603, and a signal (source) line driving circuit 1604 formed over a glass substrate 1101. The pixel TFT 1600 in the pixel portion is an n-channel type TFT, and a driving circuit provided around the pixel TFT 1600 is based on a CMOS circuit. A scan (gate) line driver circuit 1603 and a signal (source) line driver circuit 1604 are connected to the pixel portion 1601 through a gate wiring 1703 and a source wiring 1704, respectively.

FIG. 17 is a top view of the pixel portion 1601.
FIG. 3 is a top view of substantially one pixel. N-channel T
An FT is provided. A gate electrode 1702 formed continuously with the gate wiring 1702 intersects with the underlying semiconductor layer 1701 via a gate insulating film (not shown). Although not shown, a source region, a drain region, and a first impurity region are formed in the semiconductor layer. A semiconductor layer is provided on the drain side of the pixel TFT,
A storage capacitor 1707 is formed from the gate insulating film and an electrode formed using the same material as the gate electrode. Also,
The cross-sectional structure along AA ′ and BB ′ shown in FIG. 17 corresponds to the cross-sectional view of the pixel portion shown in FIG.

In this embodiment, the pixel TFT 1600 has a double gate structure. However, it may have a single gate structure or a multi-gate structure having a triple gate. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of a gate electrode, the structure of a source region, a drain region, and other impurity regions of a semiconductor layer provided with a gate insulating film interposed therebetween. The practitioner may decide appropriately.

[Embodiment 7] FIG. 23 shows an example of a circuit configuration of the active matrix type liquid crystal display device shown in Embodiment 6. The active matrix type liquid crystal display device of this embodiment includes a source signal line side driving circuit 2301, a gate signal line side driving circuit (A) 2307, a gate signal line side driving circuit (B) 2311, a precharge circuit 2312, and a pixel portion 2.
306.

The source signal line side driving circuit 2301 includes a shift register circuit 2302, a level shifter circuit 2303,
A buffer circuit 2304 and a sampling circuit 2305 are provided.

The gate signal line side drive circuit (A) 23
07 includes a shift register circuit 2308, a level shifter circuit 2309, and a buffer circuit 2310. The gate signal line side driver circuit (B) 2311 has the same configuration.

Here, an example of the driving voltage of each circuit is shown.
0 to 16 V, and the level shifter circuits 2303 and 230
9, the buffer circuits 2304, 2310, and the sampling circuit 2305, the pixel section 2306 had a voltage of 14 to 16V. The sampling circuit 2305 has an amplitude of a voltage applied to the pixel portion 2306, and a voltage whose polarity is usually inverted is applied alternately.

According to the present invention, the length of the second impurity region serving as the LDD region can be easily changed on the same substrate in consideration of the drive voltage of the n-channel TFT, and each circuit is constituted. An optimal shape for the TFT could be formed in the same process.

FIG. 24A shows the TF of the shift register circuit.
4 shows a configuration example of T. The n-channel TFT of the shift register circuit has a single gate, and a second impurity region serving as an LDD region is provided only on the drain side. Here, L which does not overlap with the LDD region (GOLD region) 206a which overlaps with the gate electrode is used.
The length of the DD region 206b may be, for example, in accordance with FIG. 26.

FIG. 24B shows a configuration example of TFTs of a level shifter circuit and a buffer circuit. The n-channel TFT of these circuits is a double gate, and a second impurity region serving as an LDD region is provided on the drain side. For example, an LDD that overlaps with the gate electrode
The length of the regions (GOLD regions) 205a and 205c is set to 2.
LDD region 205 having a thickness of 5 μm and not overlapping
The length of b, 205d can be 2.5 μm.

FIG. 24C shows a TFT of a sampling circuit.
Is shown. N-channel TFT of this circuit
Is a single gate, but the second is an LDD region on both the source side and the drain side because the polarity is inverted.
Impurity regions are provided. LDD regions (GOLD regions) 205a and 206 that overlap with the gate electrode
a, and non-overlapping LDD regions 205b and 2
06b are preferably equal in length,
For example, the length of the LDD regions (GOLD regions) 205a and 206a that overlap the gate electrode can be 1.5 μm, and the length of the LDD regions 205b and 206b that do not overlap can be 1.0 μm.

FIG. 24D shows a configuration example of a pixel portion. Although the n-channel TFT of this circuit is a multi-gate, since the polarity is inverted, second impurity regions serving as LDD regions are provided on both the source side and the drain side. For example, L overlapping the gate electrode
DD area (GOLD area) 205a, 205b, 206
a, 206c 1.5 μm, non-overlapping LD
The length of the D regions 206b and 206d can be 1.5 μm.

[Embodiment 8] In this embodiment, the TF of the present invention is used.
A semiconductor device incorporating an active matrix type liquid crystal display device using a T circuit will be described with reference to FIGS.

Such semiconductor devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV and the like. Examples of these are shown in FIGS.
3, shown in FIG.

FIG. 25A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 25B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention provides a voice input unit 9103,
910 provided with active matrix substrate
2. It can be applied to the image receiving unit 9106.

FIG. 25C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to the display device 9205 including the image receiving portion 9203 and the active matrix substrate.

FIG. 25D shows a head mounted display, which comprises a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 25E shows a portable book, and the main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 33A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display device 9.
603 and a keyboard 9604.

FIG. 33B shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 9701, a display device 9702, and a speaker section 97.
03, a recording medium 9704, and operation switches 9705. This device uses a DVD (Di) as a recording medium.
It is possible to watch music, watch a movie, play a game, or use the Internet by using a CD (g. Versatile Disc) or a CD.

FIG. 33C shows a digital camera, which includes a main body 9801, a display device 9802, an eyepiece 9803, operation switches 9804, and an image receiving unit (not shown).

FIG. 34A shows a front type projector, which comprises a display 3601 and a screen 3602. The present invention can be applied to a display device and other signal control circuits.

FIG. 34B shows a rear projector, which includes a main body 3701, a display device 3702, and a mirror 370.
3. It is composed of a screen 3704. The present invention can be applied to a display device and other signal control circuits.

Note that FIG. 34C is a diagram showing an example of the structure of the display devices 3601 and 3702 in FIGS. 34A and 34B. Display devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
10. An optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 34D is a diagram showing an example of the structure of the light source optical system 3810 in FIG. 34C. In this embodiment, the light source optical system 3810 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 34D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system. In addition, the present invention can be applied to an image sensor and an EL display device. Thus, the applicable range of the present invention is extremely wide,
It can be applied to electronic devices in all fields.

[Embodiment 9] In this embodiment, an example in which an EL (electroluminescence) display panel (also referred to as an EL display device) is manufactured by using the present invention will be described.

FIG. 27A is a top view of an EL display panel using the present invention. In FIG. 27A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a data line side driving circuit, 13 denotes a scanning line side driving circuit, and each driving circuit is a wiring 1
Through 4 to 16, the FPC 17 is reached and connected to an external device.

At this time, a sealing material 19 is provided so as to surround at least the pixel portion, preferably, the driving circuit and the pixel portion. Then, sealing is performed with the facing plate 80. The opposite plate 80 may be a glass plate or a plastic plate. Seal 19
An adhesive 81 is further provided on the outside of the substrate to firmly adhere the substrate 10 and the opposing plate 80, and also prevents the inside elements from being corroded due to entry of moisture or the like from the bonding end face. Thus, a closed space is formed between the substrate 10 and the opposing plate 80. At this time, the EL element is completely sealed in the closed space, and is completely shut off from the outside air.

Further, the space between the substrate 10 and the opposing plate 80 is filled with a sealing resin 83. As the sealing resin 83, an organic resin material selected from silicone, epoxy, acrylic, phenol, and the like is used. This improves the effect of preventing the EL element from being deteriorated by moisture or the like.

FIG. 27B shows a cross-sectional structure of the EL display panel of this embodiment, in which a TFT for a driving circuit (here, an n-channel type TFT) is provided on the substrate 10 and the base film 21.
2 shows a CMOS circuit combining a TFT and a p-channel TFT. 22) and a TFT 23 for the pixel portion (here, only the TFT for controlling the current to the EL element is shown). As the driving circuit TFT 22, the n-channel TF for the driving circuit described in the first embodiment is used.
A T or p-channel TFT may be used. The n-channel TFT shown in FIG.
Alternatively, a p-channel TFT may be used.

When the TFT 22 for the drive circuit and the TFT 23 for the pixel portion are completed by using the present invention, a transparent electrically connected to the drain of the TFT 23 for the pixel portion is formed on the interlayer insulating film (flattening film) 26 made of a resin material. Pixel electrode 27 made of conductive film
To form As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

Next, an EL layer 29 is formed. EL layer 29
Are known EL materials (a hole injection layer, a hole transport layer, a light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials.
When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 29, the cathode 3
0 is formed. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, the EL layer 29 and the cathode 30 are continuously formed in a vacuum,
It is necessary to devise that the EL layer 29 is formed in an inert atmosphere and the cathode 30 is formed without opening to the atmosphere. In this embodiment, a multi-chamber method (cluster tool method)
By using the film forming apparatus described above, the film forming as described above can be performed.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, one layer is formed on the EL layer 29 by vapor deposition.
A LiF (lithium fluoride) film having a thickness of 300 nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via a conductive paste material 32.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming an EL layer). Further, when etching the insulating film 28, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be made good.

The wiring 16 is electrically connected to the FPC 17 through a gap (but closed with an adhesive 81) between the seal 19 and the substrate 10. Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

The present invention can be applied to the EL display panel having the above configuration. FIG. 28 shows a more detailed sectional structure of the pixel portion, and FIG.
FIG. 29A shows a circuit diagram. FIG. 28, FIG.
9 (A) and FIG. 29 (B) use the same reference numerals, so they may be referred to each other.

In FIG. 28, the switching TFT 2402 provided on the substrate 2401 is the same as that of the present invention (for example,
N-channel type TF of the TFT shown in FIG.
It is formed using T. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, by adopting a double gate structure, a structure in which two TFTs are substantially connected in series,
There is an advantage that an off-current value can be reduced.
Although the double gate structure is used in this embodiment, a single gate structure may be used, or a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, it may be formed using the p-channel TFT of the present invention.

The current control TFT 2403 is formed using the n-channel TFT of the present invention. At this time, the drain wiring 35 of the switching TFT 2402
Is the gate electrode 37 of the current controlling TFT by the wiring 36.
Is electrically connected to A wiring indicated by 38 is a gate electrode 39 of the switching TFT 2402.
This is a gate wiring for electrically connecting a and 39b.

At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current control TFT 24
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 29A, the wiring to be the gate electrode 37 of the current controlling TFT 2403 has 24 wirings.
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 2403 via an insulating film. At this time, 2
In the region indicated by 404, a capacitor is formed. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain wiring 40 is connected to a current supply line (power supply line) 2501 and a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

The light emitting layer 44 is formed in a groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is an EL layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 2
405 is completed. Note that the EL element 2405 referred to here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment is similar to that of the first to sixth embodiments.
The present invention can be implemented by freely combining with the configurations of the first to sixth embodiments. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the tenth embodiment.

[Embodiment 10] In this embodiment, Embodiment 11 will be described.
A structure in which the structure of the EL element 2405 is inverted in the pixel portion shown in FIG. FIG. 30 is used for the description. Note that the point different from the structure of FIG. 29A is only the EL element portion and the current controlling TFT, and thus the other description is omitted.

In FIG. 30, the current control TFT 260
1 is formed using the p-channel TFT of the present invention. Embodiment 1 can be referred to for the manufacturing process.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of insulating films
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed.

In the case of this embodiment, the light generated in the light emitting layer 53 is radiated toward the substrate on which the TFT is formed as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The structure of this embodiment is similar to that of the first to sixth embodiments.
The present invention can be implemented by freely combining with the configurations of the first to sixth embodiments. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the eighteenth embodiment.

[Embodiment 11] In this embodiment, FIG.
FIG. 31 illustrates an example in which a pixel having a structure different from that of the circuit diagram illustrated in FIG. In this embodiment,
2701 is a source wiring of the switching TFT 2702, 2703 is a gate wiring of the switching TFT 2702, 2704 is a current control TFT, 2705 is a capacitor, 2706 and 2708 are current supply lines, and 2707 is E
L element.

FIG. 31A shows an example in which the current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 31B shows the current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that FIG. 31B illustrates a structure in which the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

In FIG. 31C, a current supply line 2708 is provided in parallel with the gate wiring 2703 as in the structure of FIG. 31B, and two pixels are connected to the current supply line 2708.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment can be implemented by freely combining with the structure of Embodiment 11 or 12. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 10.

[Embodiment 12] FIG. 29 shown in Embodiment 11
29A and 29B, a capacitor 240 is used to hold a voltage applied to the gate of the current control TFT 2403.
4, but the capacitor 2404 can be omitted.

In the case of the thirteenth embodiment, the current controlling TFT 24
Since the n-channel type TFT of the present invention as shown in FIG. 28 is used as 03, an LDD region provided so as to overlap with a gate electrode (via a gate insulating film) is provided. In this embodiment, a parasitic capacitance generally called a gate capacitance is formed. This embodiment is characterized in that this parasitic capacitance is positively used instead of the capacitor 2404.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

In the structure shown in FIGS. 31A, 31B and 31C, the capacitor 2705 can be omitted in the same manner.

The structure of this embodiment is similar to that of the first to sixth embodiments.
The present invention can be implemented by freely combining with the configurations of the first to sixth embodiments. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 10.

[Thirteenth Embodiment] In the liquid crystal display device described in the seventh embodiment, various liquid crystals can be used in addition to the nematic liquid crystal. For example, 1998, SID, "Characteristic
s and Driving Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Timeand High Con
trast Ratio with Gray-Scale Capability "by H. Furu
e et al., 1997, SID DIGEST, 841, "A Full-Color T
hresholdless AntiferroelectricLCD Exhibiting Wide
Viewing Angle with Fast Response Time "by T. Yoshi
da et al., 1996, J. Mater. Chem. 6 (4), 671-673,
"Thresholdless antiferroelectricity in liquid cry
stals and its application to displays "by S. Inui
et al., and the liquid crystal disclosed in US Pat. No. 5,594,569 can be used.

A ferroelectric liquid crystal (FLC) exhibiting an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 32 shows the electro-optical characteristics of a monostable FLC in which the cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 32 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 32 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Tsuki, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19, No. 19
See page 0 for details.

As shown in FIG. 32, it can be seen that when such a ferroelectric mixed liquid crystal is used, low-voltage driving and gradation display are possible. A ferroelectric liquid crystal having such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

Example 14 The stability of the TFTs described in Embodiment Modes 1 to 9 or Examples 1 to 5 was evaluated by a DC (direct current) bias stress test. The test conditions were such that the drain voltage (Vd) was constant at 1 V, a constant voltage was applied to the gate for one minute, and changes in the drain current and the field effect mobility before and after that were examined. The voltage applied to the gate is 0-7V
Changed. When the TFT is deteriorated due to the hot carrier effect, various characteristics such as an on-current and a field effect mobility are deteriorated by this test. The TFT used for the measurement is
A channel length of 8 μm, a channel width of 8 μm, and a structure in which Lov is 2 μm and Loff is 1.5 μm as an LDD were used.

FIG. 35 shows the characteristics (sample No. S665-14) of the gate voltage (Vg) versus the drain current (Id) of the n-channel type TFT having the above structure (sample No. S665-14).
The values measured under two conditions of applying V and 8V are shown. The characteristics shown in FIG. 35 are typical examples. The TFT of the present invention has the following characteristics as the characteristics of the ON region: the field-effect mobility is 90 to 300 cm ² / V · sec, and the drain current (Vd =
1 V, Vg = 1 V applied current) is 1 × 10 ⁻⁵ to 1 × 1
0 ^-3 A is obtained.

FIG. 36 shows the result of the DC bias stress test, and shows the rate of change of the drain current (when Vd = 1 V is applied) and the field-effect mobility (maximum value) with respect to the gate bias. FIG. 36A shows the result of the drain current, which shows almost no change. FIG. 36 (B)
Is the field-effect mobility, the maximum value of which is described here. The rate of change is 5% or less, which shows extremely excellent stability in any case, and there is no deterioration due to the hot carrier effect. It is shown that.

As shown in FIG. 35, the drain current in the off region (off current) is 0 to 0 V.
It is 1 × 10 ⁻⁹ A or less in the range of −20 V, and such a low value can be achieved only by providing Loff.

As described above, the LDD region (the second
Is formed of a region overlapping with the gate electrode and a region not overlapping with the gate electrode.
It has been confirmed that deterioration due to the hot carrier effect can be prevented and the drain current in the off region can be reduced.

[0269]

According to the present invention, a stable crystalline TFT operation can be obtained. As a result, the reliability of a semiconductor device including a CMOS circuit made of a crystalline TFT, and more specifically, a pixel portion of a liquid crystal display device and a driving circuit provided in the periphery thereof are improved, and the device can be used for a long time. A liquid crystal display device was obtained.

Further, according to the present invention, the n-channel type TF
In the second impurity region formed between the T channel formation region and the drain region, a region where the second impurity region overlaps the gate electrode (GOLD region)
It is possible to easily make the length of the region (LDD region) that does not overlap with the length. Specifically, TFT
It is also possible to determine the length of the region where the second impurity region overlaps with the gate electrode (GOLD region) and the region where the second impurity region does not overlap (LDD region) according to the driving voltage of the same. When TFTs are operated at different drive voltages, TFTs corresponding to the respective drive voltages can be manufactured in the same process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a TFT.

2A and 2B are a cross-sectional view illustrating a manufacturing process of a TFT and a plan view of a CMOS circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT.

4A and 4B are a cross-sectional view illustrating a manufacturing process of a TFT and a plan view of a CMOS circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 11 illustrates a manufacturing process of an active matrix substrate.

FIG. 12 illustrates a manufacturing process of an active matrix substrate.

FIG. 13 illustrates a manufacturing process of an active matrix substrate.

FIG. 14 illustrates a manufacturing process of a liquid crystal display device.

FIG. 15 is a cross-sectional view of a liquid crystal display device.

FIG. 16 is a perspective view of an active matrix substrate.

FIG. 17 is a top view illustrating a pixel structure of a pixel portion.

FIG. 18 is a diagram illustrating a manufacturing process of a crystalline silicon film.

FIG. 19 is a view showing a manufacturing process of a crystalline silicon film.

FIG. 20 illustrates a manufacturing process of a crystalline silicon film.

FIG. 21 is a diagram illustrating a manufacturing process of a crystalline silicon film.

FIG. 22 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 23 is a circuit block diagram of one embodiment of an active matrix liquid crystal display device.

FIG. 24 illustrates a structure of a TFT of the present invention.

FIG 25 illustrates an example of a semiconductor device.

FIG. 26 illustrates a relationship between a gate electrode and an LDD region of the present invention.

27A and 27B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 28 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 29 is a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 30 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 31 is a circuit diagram of a pixel portion of an EL display device.

FIG. 32 is a view showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

FIG. 33 illustrates an example of a semiconductor device.

FIG. 34 illustrates an example of a semiconductor device.

FIG. 35: Gate voltage (Vg) versus drain current (I
The figure which shows the characteristic of d).

FIG. 36 shows a result of a DC bias stress test.

[Explanation of symbols]

517, 622, 722, 822 first gate electrode 516, 621, 715, 821 second gate electrode 518, 623, 723, 823 gate wiring 519, 624, 724, 824 gate bus Lines 527, 528, 627, 628, 727, 728, 8
27, 828 ··· source electrode 529, 629, 729, 829 · · drain electrode 530, 533, 630, 633, 730, 733, 8
., 833... Channel forming regions 531, 532, 631, 632, 731, 732, 8
31, 832... Third impurity region 536, 537, 636, 637, 736, 737, 8
36, 837... First impurity regions 534, 535, 634, 635, 734, 735, 8
34, 835... Second impurity region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 H01L 29/78 613A 618F

Claims (25)

[Claims] A semiconductor layer on a substrate having an insulating surface;
In a semiconductor device having a gate insulating film formed in contact with the semiconductor layer, a gate electrode formed in contact with the gate insulating film, and a gate wiring connected to the gate electrode, the gate electrode and the gate The wiring includes a first conductive layer in contact with the gate insulating film. The semiconductor layer includes a channel forming region and a first conductive type first conductive layer.
And a second impurity region of one conductivity type sandwiched between the channel formation region and the first impurity region of one conductivity type and in contact with the channel formation region. A semiconductor device, wherein a part of a second impurity region of a mold overlaps with the gate electrode. 2. A semiconductor device having a pixel portion formed by an n-channel thin film transistor, wherein a gate electrode of the n-channel thin film transistor and a gate wiring connected to the gate electrode are connected to a first gate insulating film. A semiconductor layer of the n-channel thin film transistor is sandwiched between a channel formation region, a first impurity region of one conductivity type, and the channel formation region and the first impurity region of one conductivity type. And a second impurity region of one conductivity type in contact with the channel formation region, and a part of the second impurity region of one conductivity type overlaps with the gate electrode. Semiconductor device. 3. A semiconductor device having a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, wherein a gate electrode of the n-channel thin film transistor and a gate wiring connected to the gate electrode are provided with a gate insulation. A semiconductor layer of the n-channel type thin film transistor, wherein the semiconductor layer of the n-channel thin film transistor includes a channel formation region, a first impurity region of one conductivity type, the channel formation region, and a first impurity region of the one conductivity type. And a second impurity region of one conductivity type sandwiched between the first and second impurity regions and in contact with the channel formation region, and a part of the second impurity region of the one conductivity type overlaps with the gate electrode. A semiconductor device characterized in that: 4. A semiconductor device having a pixel circuit formed of an n-channel thin film transistor, a CMOS circuit formed of an n-channel thin film transistor and a p-channel thin film transistor, wherein: a gate electrode of the n-channel thin film transistor; The gate wiring connected to the gate electrode includes a first conductive layer in contact with a gate insulating film. The semiconductor layer of the n-channel thin film transistor includes a channel formation region, a first conductivity type first impurity region, And a second impurity region of one conductivity type sandwiched between the channel formation region and the first impurity region of one conductivity type and in contact with the channel formation region. A part of the impurity region overlaps with the gate electrode. 5. The p-channel thin film transistor according to claim 3, wherein a gate electrode of the p-channel thin film transistor and a gate wiring connected to the gate electrode are formed of a first conductive film in contact with a gate insulating film. A semiconductor layer of the p-channel thin film transistor includes a channel forming region and a third impurity region having a conductivity type opposite to the one conductivity type, and a third impurity region having a conductivity type opposite to the one conductivity type. 3. A semiconductor device according to claim 3, wherein a part of the impurity region overlaps with the gate electrode. 6. A semiconductor device having a first n-channel thin film transistor and a second n-channel thin film transistor in one pixel, wherein: a gate electrode of the first and second n-channel thin film transistors; The gate wiring connected to the electrode includes a first conductive layer in contact with a gate insulating film. The semiconductor layer of the first n-channel thin film transistor includes a channel formation region and a first impurity region of one conductivity type. And a second impurity region of one conductivity type sandwiched between the channel formation region and the first impurity region of one conductivity type, and in contact with the channel formation region. The semiconductor layer of the second n-channel type thin film transistor includes a channel formation region and a first impurity of one conductivity type. An object region, a second impurity region of one conductivity type sandwiched between the channel formation region and the first impurity region of one conductivity type and in contact with the channel formation region; Wherein the second impurity region overlaps with the gate electrode. 7. The semiconductor device according to claim 6, wherein the first n-channel thin film transistor has a multi-gate structure. 8. The semiconductor device according to claim 6, wherein an element having a light-emitting layer is connected to said second n-channel thin film transistor. 9. A semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor in one pixel, comprising: a gate electrode of the n-channel thin film transistor and a p-channel thin film transistor; and a gate wiring connected to the gate electrode. Comprises a first conductive layer in contact with a gate insulating film, wherein the semiconductor layer of the n-channel thin film transistor has a channel formation region, a first impurity region of one conductivity type, the channel formation region and the one conductivity type. A second impurity region of one conductivity type sandwiched between the first impurity region of the first conductivity type, and a second impurity region of one conductivity type in contact with the channel formation region; The semiconductor layer of the p-channel thin film transistor overlaps with a gate electrode, and has a channel formation region and a conductivity type opposite to the one conductivity type. And a third impurity region, wherein the third impurity region is provided outside the gate electrode. 10. A semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor in one pixel, comprising: a gate electrode of the n-channel thin film transistor and a p-channel thin film transistor; and a gate wiring connected to the gate electrode. Comprises a first conductive layer in contact with a gate insulating film, wherein the semiconductor layer of the n-channel thin film transistor has a channel formation region, a first impurity region of one conductivity type, the channel formation region and the one conductivity type. A second impurity region of one conductivity type sandwiched between the first impurity region of the first conductivity type, and a second impurity region of one conductivity type in contact with the channel formation region; The semiconductor layer of the p-channel thin film transistor overlaps with a gate electrode, and has a channel formation region and a conductivity type opposite to one conductivity type. And a third impurity region, wherein a part of the third impurity region overlaps with the gate electrode. 11. The semiconductor device according to claim 9, wherein the n-channel thin film transistor has a multi-gate structure. 12. The semiconductor device according to claim 9, wherein an element having a light emitting layer is connected to said p-channel thin film transistor. 13. The p-channel thin film transistor according to claim 3, wherein a gate electrode of the p-channel thin film transistor and a gate wiring connected to the gate electrode are connected to a first conductive film in contact with a gate insulating film. A semiconductor layer of the p-channel thin film transistor includes a channel forming region and a third impurity region having a conductivity type opposite to the one conductivity type, and a third impurity region having a conductivity type opposite to the one conductivity type. 3. The semiconductor device according to claim 3, wherein a part of the impurity region is provided outside the gate electrode. 14. The semiconductor device according to claim 1, wherein the first conductive layer is made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M).
A semiconductor device, which is one or more elements selected from (o) or a compound containing the above elements as a main component. 15. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 16. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a projector, a projection TV, a goggle type display, a car navigation, a personal computer, or a portable information terminal. A semiconductor device, which is one selected from the group consisting of: 17. A step of forming a semiconductor layer on a substrate having an insulating surface, and removing at least a part of the semiconductor layer to form at least a first island-shaped semiconductor layer and a second island-shaped semiconductor layer. A step of forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and selecting an impurity element of one conductivity type in the first island-shaped semiconductor layer. Forming a second impurity region by adding to the region that has been added; forming a first conductive layer in contact with the gate insulating film; and forming the second island-shaped semiconductor layer from the first conductive layer. Forming a second gate electrode overlapping with the first conductive layer; and adding an impurity element of a conductivity type opposite to the one conductivity type to a selected region of the second island-shaped semiconductor layer to form a third impurity region. And a first region overlapping the first conductive layer with the first island-shaped semiconductor layer. Forming a first impurity region by adding an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer. A method for manufacturing a semiconductor device. 18. A step of forming a semiconductor layer on a substrate having an insulating surface, and removing at least a part of the semiconductor layer to form at least a first island-like semiconductor layer and a second island-like semiconductor layer. A step of forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and selecting an impurity element of one conductivity type in the first island-shaped semiconductor layer. Forming a second impurity region by adding to the region that has been added; forming a first conductive layer in contact with the gate insulating film; and forming the first island-shaped semiconductor layer from the first conductive layer. Forming a first gate electrode overlapping with the first island-shaped semiconductor layer and a second gate electrode overlapping the second island-shaped semiconductor layer; and applying an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer. Forming a first impurity region by adding a first impurity region; and a conductivity type opposite to the one conductivity type. Forming a third impurity region by adding said impurity element to a selected region of said second island-shaped semiconductor layer. 19. A step of forming a semiconductor layer on a substrate having an insulating surface, and removing at least a part of the semiconductor layer to form at least a first island-like semiconductor layer and a second island-like semiconductor layer. Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and adding an impurity element having a conductivity type opposite to one conductivity type to the second island shape. Forming a third impurity region by adding to a selected region of the semiconductor island layer; and adding a second impurity element to a selected region of the first island-like semiconductor layer by forming a second impurity region. A step of forming an impurity region, a step of forming a first conductive layer in contact with the gate insulating film, a first gate electrode overlapping the first island-like semiconductor layer from the first conductive layer, Forming a second gate electrode overlapping the second island-shaped semiconductor layer; Forming a first impurity region by adding an impurity element of a type to a selected region of the first island-shaped semiconductor layer. 20. A step of forming a semiconductor layer on a substrate having an insulating surface, and removing at least a part of the semiconductor layer to form at least a first island-like semiconductor layer and a second island-like semiconductor layer. Forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and adding an impurity element having a conductivity type opposite to one conductivity type to the second island shape. Forming a third impurity region by adding to a selected region of the semiconductor island layer; and adding a first conductivity type impurity element to a selected region of the first island semiconductor layer to form a first impurity region. Forming an impurity region, adding a one-conductivity-type impurity element to a selected region of the first island-shaped semiconductor layer to form a second impurity region, and contacting the gate insulating film. Forming a first conductive layer; and forming the first island-shaped semiconductor from the first conductive layer. Forming a first gate electrode overlapping the body layer and a second gate electrode overlapping the second island-shaped semiconductor layer. 21. A step of forming a semiconductor layer on a substrate having an insulating surface; and removing at least a part of the semiconductor layer to form at least a first island-shaped semiconductor layer and a second island-shaped semiconductor layer. A step of forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and selecting an impurity element of one conductivity type in the first island-shaped semiconductor layer. Forming a first impurity region by adding the impurity region to the selected region, and forming a second impurity region by adding an impurity element of one conductivity type to a selected region of the first island-shaped semiconductor layer. Forming a first conductive layer in contact with the gate insulating film; forming a second gate electrode overlying the second island-shaped semiconductor layer from the first conductive layer; An impurity element of a conductivity type opposite to that of the second island-shaped semiconductor layer is added to a selected region of the second island-shaped semiconductor layer. Forming a third impurity region by adding to the region; and forming a first gate electrode overlapping the first island-shaped semiconductor layer from the first conductive layer. A method for manufacturing a semiconductor device. 22. A step of forming a semiconductor layer on a substrate having an insulating surface, and removing at least a part of the semiconductor layer to form at least a first island-like semiconductor layer and a second island-like semiconductor layer. A step of forming a gate insulating film in contact with the first island-shaped semiconductor layer and the second island-shaped semiconductor layer; and selecting an impurity element of one conductivity type in the first island-shaped semiconductor layer. Forming a first impurity region by adding the impurity element to the selected region of the second island-shaped semiconductor layer; and adding a third impurity element to the selected region of the second island-shaped semiconductor layer. Forming an impurity region, adding a one-conductivity-type impurity element to a selected region of the first island-shaped semiconductor layer to form a second impurity region, and contacting the gate insulating film. Forming a first conductive layer; and forming the first island-shaped semiconductor from the first conductive layer. Forming a first gate electrode overlapping the body layer and a second gate electrode overlapping the second island-shaped semiconductor layer. 23. The semiconductor device according to claim 17, wherein the first conductive layer is made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M).
o. A method for manufacturing a semiconductor device, which is formed using one or more kinds of elements selected from o), or a compound containing the above elements as a main component. 24. The method for manufacturing a semiconductor device according to claim 17, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 25. The semiconductor device according to claim 17, wherein the semiconductor device is a video camera, a digital camera, a projector, a projection TV, a goggle type display, a car navigation, a personal computer, or a portable information terminal. A method for manufacturing a semiconductor device, which is one selected from the group consisting of: