JP2003114515A - Mask and design method thereof - Google Patents

Abstract

(57) [Problem] To prevent a dimensional variation from occurring in a circuit pattern depending on a mask pattern layout. SOLUTION: A standard is set for a plurality of parameters affecting the dimensions of a circuit pattern, and a layout of a mask pattern provided on a mask in correspondence with the circuit pattern is determined. After that, based on the mask pattern layout, a dummy pattern disposable area in the mask is determined. Thereafter, when it is assumed that the dummy patterns are uniformly arranged over the entire dummy pattern allocable area, the values of the respective parameters calculated in consideration of the dummy circuit patterns formed corresponding to the dummy patterns and the circuit patterns. The layout of the dummy pattern is determined so that satisfies the standard.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask for forming a circuit pattern of a semiconductor integrated circuit device and a method for designing the mask.

[0002]

2. Description of the Related Art Conventionally, the shape or size of a pattern (hereinafter referred to as a processed pattern) obtained by etching a film to be processed using a mask pattern changes depending on the mask pattern layout. The phenomenon is known.

As an example thereof, there is a pattern proximity effect that occurs when a resist pattern is formed in a photolithography process. Another example is the loading effect or microloading effect in the dry etching process.

On the other hand, conventionally, a design rule is added to correct the variation of the pattern dimension only at the mask portion where the pattern dimension is considered to vary significantly depending on the mask pattern layout.

[0005]

However, in recent years,
With the progress of miniaturization of LSI, more precise dimension control is required. Therefore, in the conventional method, the dimension variation of the circuit pattern depending on the mask pattern layout is sufficiently caused. It is becoming less controllable.

FIG. 6 shows a dry etching process for a gate electrode when manufacturing different types of semiconductor integrated circuit devices (semiconductor chips) using two kinds of masks (mask A and mask B) having different mask pattern layouts. The frequency distribution of the CD (critical dimension) loss that occurred in FIG. The results shown in FIG. 6 are obtained by adopting the same gate electrode processing process in the manufacture of each type of semiconductor chip. Also, the CD loss calculation method is "dimension of resist pattern before etching"-
“Dimension of gate electrode pattern after etching”.

As shown in FIG. 6, although the same gate electrode processing process is used for each type, the pattern size has a mask pattern layout dependency, that is, a type dependency.

In view of the above, it is an object of the present invention to prevent dimensional variations in circuit patterns depending on the mask pattern layout.

[0009]

In order to achieve the above object, the inventors of the present application examined a phenomenon in which dimensional variation occurs due to a difference in mask pattern layout. As a result, it has been found that this phenomenon is caused by a difference in specific parameters (hereinafter referred to as mask parameters) that affect the dimensions of the circuit pattern provided on the semiconductor chip. Specifically, one mask parameter is “pattern occupancy area ratio (ratio of the area occupied by the circuit pattern to the chip area in a certain layer of the semiconductor chip)”. Further, another mask parameter is “a pattern peripheral length per unit area (a peripheral length per unit area of a circuit pattern in a layer having a semiconductor chip)”.

FIG. 7 shows the relationship between the gate electrode pattern occupation area ratio and the CD loss in various kinds of semiconductor chips having different gate electrode pattern occupation area ratios.

FIG. 8 shows the relationship between the gate electrode pattern peripheral length per unit area and the CD loss in various types of semiconductor chips having different gate electrode pattern peripheral lengths per unit area.

As shown in FIGS. 7 and 8, a change in CD loss, that is, a dimensional variation occurs due to the difference in the occupied area ratio of the gate electrode pattern or the difference in the peripheral length of the gate electrode pattern per unit area.

That is, the inventors of the present application have found that it is necessary to set a standard for the mask parameter in order to suppress the type dependency of the pattern size. still,
Usually, the standard for the mask parameter has a range (standard range).

Therefore, when the mask parameter value calculated in consideration of only the circuit pattern is out of the standard range, the inventors of the present invention insert the dummy pattern into the mask, and in addition to the semiconductor pattern corresponding to the dummy pattern. The method of adjusting the layout of the dummy pattern so that the value of the mask parameter calculated in consideration of the dummy circuit pattern formed on the chip and the circuit pattern falls within the standard range was conceived.

By the way, the mask parameters are not mutually independent. For example, if the “pattern occupying area ratio” and the “pattern peripheral length per unit area” are mask parameters that affect the pattern size product type dependency, both mask parameters simultaneously satisfy the standard. Needs to be created and inserted.

Therefore, the inventors of the present invention have come up with an idea of a mask designing algorithm as shown in the flowchart of FIG. 9 and have studied it.

That is, first, in step S1,
The layout of the mask pattern corresponding to the circuit pattern of the semiconductor chip to be formed is performed. Next, in step S2, the values of a plurality of mask parameters (for example, "pattern occupation area ratio" and "pattern peripheral length per unit area") are calculated in consideration of only the circuit pattern. Next, in step S3, it is determined whether the values of the mask parameters calculated in step S2 simultaneously satisfy the standard. It should be noted that it is assumed that standard settings have been made in advance for each mask parameter.

When all the mask parameter values satisfy the standard, in step S4, mask data corresponding to the mask pattern laid out in step S1 is created by computer processing and output (mask drawing).

If even one value of each mask parameter does not satisfy the standard, after selecting the placement position of the dummy pattern in the mask in step S5, in step S6, for example, various kinds of prepared types are prepared. One dummy pattern is selected from the dummy patterns and additionally inserted in the above-mentioned dummy pattern arrangement location. As a result, a layout of the composite pattern of the mask pattern and the dummy pattern (mask layout) is obtained. Then, again in step S2, the value of each mask parameter is calculated in consideration of the dummy circuit pattern and the circuit pattern formed on the semiconductor chip corresponding to the dummy pattern. Then, in step S3, step S5, step S6 and step S2 are repeated until it is determined that the values of the mask parameters recalculated in step S2 simultaneously satisfy the standard. As a result, the final mask layout is determined. When it is determined in step S3 that the values of the mask parameters satisfy the standard due to the additional insertion of the dummy pattern, in step S4, the mask data corresponding to the composite pattern of the mask pattern and the dummy pattern is obtained. Create and output by computer processing (mask drawing).

However, according to the mask design algorithm shown in the flowchart of FIG. 9, it is necessary to perform cut-and-try with human intervention in steps such as selection of dummy pattern placement location and selection of dummy pattern. The work time until drawing the mask becomes long, and a great deal of labor is devoted to the mask design.

Therefore, the inventors of the present invention have come up with an idea of a mask designing algorithm as shown in the flowchart of FIG. 1 and have studied it.

That is, first, in step S11, the layout of the mask pattern corresponding to the circuit pattern of the semiconductor chip to be formed is performed. Next, in step S12, a plurality of mask parameters (for example, "pattern occupation area ratio" and "pattern peripheral length per unit area") are calculated in consideration of only the circuit pattern. Next, in step S13, it is determined whether or not the values of the mask parameters calculated in step S12 simultaneously satisfy the standard. It should be noted that it is assumed that standard settings have been made in advance for each mask parameter.

If all the mask parameter values satisfy the standard, in step S14, step S1 is performed.
Mask data corresponding to the mask pattern laid out in 1 is created by computer processing and output (mask drawing).

If even one value of each mask parameter does not satisfy the standard, in step S15, the dummy pattern allocable area in the mask is determined based on the mask pattern layout. Next, step S16
In the above, assuming that the dummy patterns are uniformly arranged in the entire dummy pattern allocable region, the dummy circuit patterns formed on the semiconductor chip corresponding to the dummy patterns and the circuit patterns calculated in consideration of each The layout of the dummy pattern is determined so that the mask parameter value satisfies the standard, for example, the mask parameter value becomes equal to the standard center value (center value of the standard range). Next, in step S17, step S
The dummy pattern whose layout is determined in 16 is additionally inserted in the dummy pattern allocable area. As a result, a layout of the composite pattern of the mask pattern and the dummy pattern (mask layout) is obtained. Then, in step S18, mask data corresponding to the composite pattern of the mask pattern and the dummy pattern is created by computer processing and output (mask drawing).

The steps S13 and S14 may be omitted. In addition, step S12 and step S1
The order of 5 may be exchanged.

According to the mask design algorithm shown in the flow chart of FIG. 1, the value of each mask parameter when the dummy pattern allocable area is determined in advance and the dummy patterns are uniformly arranged in the entire area Generates a dummy pattern so as to satisfy the standard.
For this reason, the layout of the dummy pattern can be uniquely determined, whereby the mask design can be performed while the human intervention is suppressed to the minimum, so that the work time until the mask drawing can be shortened and the labor required for the mask design can be reduced. It can be reduced.

The present invention has been made based on the above knowledge, particularly the mask design algorithm shown in the flowchart of FIG. 1. Specifically, the mask design method according to the present invention is applied to a semiconductor integrated circuit device. Assuming a mask design method for designing a mask for forming a circuit pattern,
A step of setting a standard for a plurality of parameters that affect the dimensions of the circuit pattern, a step of determining the layout of the mask pattern provided on the mask corresponding to the circuit pattern, and a step of setting the mask pattern based on the layout of the mask pattern. A step of determining the dummy pattern allocable area, and a dummy circuit pattern formed in the semiconductor integrated circuit device corresponding to the dummy pattern when the dummy patterns are uniformly arranged in the entire dummy pattern allocable area. And a step of deciding the layout of the dummy pattern so that the values of the plurality of parameters calculated in consideration of the circuit pattern satisfy the standard.

According to the mask designing method of the present invention, the dummy pattern generated so that the values of the plurality of parameters affecting the dimensions of the circuit pattern of the semiconductor integrated circuit device satisfy the standard is arranged on the mask. It is possible to prevent dimensional variations in the circuit pattern depending on the mask pattern layout.

According to the mask designing method of the present invention,
A dummy pattern allocable area is determined in advance, and a dummy pattern is generated so that the values of the parameters satisfy the standard when the dummy pattern is uniformly arranged in the entire area. Therefore, the layout of the dummy pattern can be uniquely determined, and the human intervention in the mask design can be suppressed to the minimum, so that the time and labor required for the mask design can be reduced.

In the mask designing method of the present invention, it is preferable that the plurality of parameters include a pattern occupation area ratio and a pattern peripheral length per unit area.

By doing so, it is possible to surely prevent the mask pattern layout dependence from occurring in the gate electrode pattern dimension in the gate electrode processing, for example.

In the mask designing method of the present invention, it is preferable that the dummy pattern is composed of a plurality of partial patterns of the same shape which are arranged in a plurality of unit areas which partition the dummy pattern arrangeable area in a grid pattern.

By doing so, the dummy pattern can be easily generated.

The mask according to the present invention is premised on a mask for forming a circuit pattern of a semiconductor integrated circuit device,
A mask pattern corresponding to the circuit pattern and a dummy pattern uniformly arranged in the dummy pattern allocable area set based on the layout of the mask pattern are provided, and a plurality of parameters that affect the dimension of the circuit pattern are provided. The standard is set, and the dummy pattern layout has a plurality of parameter values calculated in consideration of the dummy circuit pattern and the circuit pattern formed in the semiconductor integrated circuit device corresponding to the dummy pattern satisfy the standard. Has been decided.

That is, since the mask of the present invention is a mask obtained by the mask designing method of the present invention, the same effect as the mask designing method of the present invention can be obtained. Here, the plurality of parameters may include the pattern occupation area ratio and the pattern peripheral length per unit area. Further, the dummy pattern may be composed of a plurality of partial patterns of the same shape arranged in a plurality of unit areas that partition the dummy pattern arrangeable area in a grid pattern.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION A mask and a method for designing the same according to one embodiment of the present invention will be described below with reference to the drawings by using a mask for forming a gate electrode pattern of a semiconductor integrated circuit device as an example.

In the present embodiment, there are two mask parameters that affect the dimensions of the gate electrode pattern to be formed: "pattern occupation area ratio" and "pattern peripheral length per unit area". The "pattern occupation area ratio" is 20 to 30% (standard center value: 25
%) And “pattern peripheral length per unit area” is 1.4 to 1.6 m / mm ² (standard center value: 1.5 m
/ Mm ² ) is set as a standard in advance. However, the area (chip area) of the semiconductor integrated circuit device (semiconductor chip) on which the gate electrode pattern is provided
Is 100 mm ² .

Hereinafter, description will be given with reference to the flowchart of FIG. However, in the present embodiment, steps S13 and S14 in the flowchart of FIG.
Shall be omitted.

First, in step S11, the layout of the mask pattern corresponding to the gate electrode pattern to be formed is performed. FIG. 2 shows an example of a circuit pattern including a gate electrode pattern to be formed. As shown in FIG. 2, the circuit pattern is composed of an active region pattern 1 and a gate electrode pattern 2 of a MOS transistor. Further, a dummy circuit pattern corresponding to a dummy pattern to be inserted on the mask in a later step is provided in the empty region 3 where the active region pattern 1 and the gate electrode pattern 2 are not provided.

Next, in step S12, the respective values of the "pattern occupation area ratio" and the "pattern peripheral length per unit area" are calculated by considering only the gate electrode pattern 2. Specifically, first, the area and the peripheral length of the gate electrode pattern 2 in the semiconductor chip are calculated by computer processing. Here, as a result of the computer processing, for example, the area and the peripheral length of the gate electrode pattern 2 are each 1
If it is 8 mm ² and 70 m, the chip area is 1
Since it is 00 mm ² , the value of “pattern occupation area ratio” and “pattern peripheral length per unit area” are 1 respectively.
It is found to be 8% and 0.7 m / mm ² . That is, the difference (deficiency) between the value of “pattern occupation area ratio” and the standard center value is 25−18 = 7%. Also,
The difference (deficiency) between the value of “pattern peripheral length per unit area” and the standard center value is 1.5−0.7 = 0.8 m /
mm ² . Therefore, the target area St and the target peripheral length Lt of the dummy pattern to be inserted in the mask are St respectively.
= 7 mm ² and Lt = 80 m.

In the present specification, all numerical values such as length and area on the mask are converted into numerical values on the semiconductor chip.

Next, in step S15, the dummy pattern allocable area in the mask is determined based on the mask pattern layout. In other words, estimate how much free space is available on the mask for placing the dummy pattern. Specifically, the entire area on the mask corresponding to the empty area 3 (area where the transistor including the active area pattern 1 and the gate electrode pattern 2 is not provided) of the semiconductor chip shown in FIG. Set as. Here, it is assumed that the area A of the dummy pattern allocable region is found to be, for example, A = 15 mm ² from the computer processing result based on the mask pattern layout.

Next, in step S16, assuming that the dummy patterns are uniformly arranged in the entire dummy pattern allocable region, the dummy circuit pattern and the gate electrode pattern formed on the semiconductor chip in correspondence with the dummy patterns. The layout of the dummy patterns is determined so that the values of the mask parameters calculated in consideration of 2 and 2 satisfy the standard. Specifically, for example, the value of each mask parameter is equal to the standard center value, that is, the area S of the dummy pattern and the peripheral length L are equal to the target area St (=
The dummy pattern layout is determined so as to be equal to 7 mm ² ) and the target peripheral length Lt (= 80 m).

Here, as a feature of this embodiment, a plurality of unit areas (hereinafter referred to as units) are set by partitioning the dummy pattern allocable area in a grid pattern, and a plurality of units of the same shape are formed in each unit. A dummy pattern is generated by arranging the partial patterns. In this way, dummy pattern generation becomes easy.

FIG. 3 shows an example of a unit and a partial pattern arranged therein.

As shown in FIG. 3, in the present embodiment, the vertical width of the unit and the vertical width of the partial pattern are fixed to 3.0 μm and 2.7 μm, respectively. In addition, the unit width (Wd (μm)) and the partial pattern width (Ld
(Μm)) as a variable.

At this time, the area S of the dummy pattern in the entire semiconductor chip can be expressed as S = A × (Ld / Wd) × (2.7 / 3.0).

Further, the peripheral length L of the dummy pattern in the entire semiconductor chip can be expressed as L = (A / (Wd × 3.0)) × (Ld + 2.7) × 2.

Here, assuming that the area S and the peripheral length L of the dummy pattern are equal to the target area St and the target peripheral length Lt of the dummy pattern, respectively, St = A × (Ld / Wd) × (2.7 / 3. 0) Lt = (A / (Wd × 3.0)) × (Ld + 2.7) ×
Since the simultaneous equations represented by 2 hold, the shapes of the unit and the partial pattern, that is, the layout of the dummy pattern can be determined by obtaining Ld and Wd that satisfy this simultaneous equation.

Specifically, when this simultaneous equation is solved, Ld = 2.7 × St / (0.15 × Lt-St) Wd = 2.43 × A / (0.15 × Lt-St) Therefore, St = 7 mm ² , Lt = 80 m, A =
Substituting 15 mm ² , Ld = 3.98 (μm) and W
d = 7.68 (μm) is obtained.

In the present embodiment, the arrangement position of the partial pattern in each unit is not particularly limited, but the arrangement position is common to all the units.

Further, in the present embodiment, the unit vertical width is set to 3.0 μm because if the unit vertical width is too large, the blank area where the unit cannot be set increases in the dummy pattern allocable area, while the unit vertical width increases. This is because if the width is too small, it becomes difficult to form a dummy circuit pattern corresponding to the dummy pattern arranged in the unit. Further, the unit vertical width and the partial pattern vertical width are fixed because, as described above, the unit horizontal width Wd and the partial pattern horizontal width Ld can be uniquely solved by using simultaneous equations. That is, by this, the layout of the dummy pattern is uniquely determined. However, as a solution of the simultaneous equations, the partial pattern lateral width Ld may be smaller than a predetermined minimum dimension. In this case, since the dummy pattern and the corresponding resist pattern may be peeled off, the partial pattern width L
It is preferable to solve the simultaneous equations by setting a lower limit (for example, 0.4 μm) with respect to d and resetting the dummy pattern allocable region to be narrow.

Further, in this embodiment, the unit vertical width (3.0 μm) and the partial pattern vertical width (2.7 μm) are set to different values because of this, the length of the four sides of the partial pattern corresponds to the dummy pattern. This is because the margin length can be earned. In addition, the partial pattern height is 90
% Is set so that when only the “pattern occupying area ratio” is insufficient, by increasing the partial pattern width, the “pattern occupying length per unit area” is suppressed and the “pattern occupying length” is suppressed. This is because the “area ratio” can be increased.

Further, in this embodiment, step S1
A fixed value (for example, unit vertical width) in the unit size may be set based on the shape of the dummy pattern allocable area determined in 5. Alternatively, step S1
The unit and the dummy pattern may be set (for example, all dimensions are used as variables) before the dummy pattern allocable area is determined in 5.

Next, in step S17, the dummy pattern whose layout is determined in step S16 is additionally inserted into the dummy pattern allocable area. This allows
A layout (mask layout) of a composite pattern of the mask pattern and the dummy pattern is obtained. FIG. 4 shows a state in which the dummy pattern generated in step S16 is transferred as a dummy circuit pattern to the empty area of the semiconductor chip shown in FIG. As shown in FIG. 4, in this embodiment, the dummy circuit pattern 4 transferred to the empty area 3 is composed of a plurality of partial transfer patterns 4a. Here, each partial transfer pattern 4a is a transfer of the partial pattern (see FIG. 3) arranged in each unit that partitions the dummy pattern arrangeable region in a grid pattern. Further, FIG. 5 shows an enlarged part of the dummy circuit pattern shown in FIG.

Finally, in step S18, mask data corresponding to the composite pattern of the mask pattern and the dummy pattern is created by computer processing and output (mask drawing). As a result, the dummy patterns are laid out so that the mask parameters that affect the dimensions of the gate electrode pattern to be formed, specifically, the “pattern occupied area ratio” and the “pattern peripheral length per unit area” satisfy the standards. The mask design for the completed semiconductor integrated circuit is completed.

As described above, according to the present embodiment, the values of a plurality of mask parameters that affect the dimensions of the gate electrode pattern of the semiconductor chip, specifically, "pattern occupation area ratio" and "per unit area" The dummy patterns generated so that the respective values of the "pattern peripheral length of" satisfy the standard are arranged on the mask. Therefore, it is possible to prevent dimensional variations in the gate electrode pattern due to the mask pattern layout.

Further, according to the present embodiment, the dummy pattern allocable area is determined in advance, and the values of the mask parameters satisfy the standard when the dummy patterns are uniformly arranged in the entire area. To generate a dummy pattern. Therefore, the layout of the dummy pattern can be uniquely determined, and the human intervention in the mask design can be suppressed to the minimum, so that the time and labor required for the mask design can be reduced.

Further, according to the present embodiment, since the dummy pattern is composed of a plurality of partial patterns of the same shape which are arranged in each unit which divides the dummy pattern allocable region into a grid pattern, the dummy pattern is easily generated. be able to.

In this embodiment, the mask used for the gate electrode processing is targeted, but instead of this, a mask used for fine processing of a layer mainly having a line-shaped pattern such as metal wiring is also targeted. The same effect can be obtained. At this time, for example, as the mask parameters that affect the dimensions of the metal wiring pattern, the “pattern occupation area ratio” and the “pattern peripheral length per unit area” can be used as in the present embodiment.

Further, in the present embodiment, steps S13 and S14 in the flowchart of FIG. 1 are omitted, but steps S13 and S14 may be performed instead (for details of steps S13 and S14, refer to "Problem"). "Means for solving the problem"). Further, the order of step S12 and step S15 may be exchanged.

Further, in this embodiment, in order to suppress the dimensional variation of the gate electrode pattern, standards are set for each of the “pattern occupied area ratio” and the “pattern peripheral length per unit area” as mask parameters. Alternatively, standards may be set for other combinations of parameters. For example, C which is widely used at present
It is known that in the planarization process using the MP (chemical mechanical polishing) technique, the amount of polishing by CMP varies depending on the “area ratio (ratio of the area occupied by the film to be processed to the area of a predetermined region)”. That is,
Since the flatness deteriorates when there are a plurality of portions having different polishing amounts in one semiconductor chip, a plurality of regions (hereinafter referred to as partition regions) partitioning the semiconductor chip.
In each case, it is necessary to keep the "area ratio" within a predetermined range. On the other hand, in order to suppress dimensional variation during processing, it is necessary to set the standard for the "area ratio" of the semiconductor chip as a whole. Therefore, in this case, the "area ratio of each divided area" and the "area ratio of the entire chip"
Standards are set for the two parameters and the dummy pattern is generated so that each parameter satisfies the standard.

[0063]

According to the present invention, the use of the dummy pattern can prevent the dimensional variation of the circuit pattern depending on the mask pattern layout. Also,
Since the layout of the dummy pattern can be uniquely determined, the mask design can be performed with the minimum human intervention, so that the time and labor required for the mask design can be reduced.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of an algorithm of a mask designing method according to the present invention.

FIG. 2 is a diagram showing an example of a circuit pattern including a gate electrode pattern to be formed in the mask designing method according to the embodiment of the present invention.

FIG. 3 is a diagram showing an example of a unit used in a mask designing method according to an embodiment of the present invention and a partial pattern arranged therein.

FIG. 4 is a diagram showing a state in which the dummy pattern generated in step S16 of the mask designing method according to the embodiment of the present invention is transferred as a dummy circuit pattern.

5 is an enlarged view of a part of the dummy circuit pattern shown in FIG.

FIG. 6 is a diagram showing a frequency distribution of CD loss caused by dry etching processing of gate electrodes when manufacturing different types of semiconductor integrated circuit devices using two kinds of masks having different mask pattern layouts.

FIG. 7 is a diagram showing the relationship between the gate electrode pattern occupation area ratio and the CD loss in various kinds of semiconductor integrated circuit devices having different gate electrode pattern occupation area ratios.

FIG. 8 is a diagram showing a relationship between a gate electrode pattern peripheral length per unit area and a CD loss in various kinds of semiconductor integrated circuit devices having different gate electrode pattern peripheral lengths per unit area.

FIG. 9 is a flowchart showing an example of an algorithm of a mask design method examined by the inventors of the present application.

[Explanation of symbols]

1 Active area pattern 2 Gate electrode pattern 3 free space 4 Dummy circuit pattern 4a Partial transfer pattern

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akio Miyajima             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 2H095 BB01 BB02                 5F064 CC09 EE15 EE51 GG03 HH06

Claims (6)

[Claims] 1. A mask design method for designing a mask for forming a circuit pattern of a semiconductor integrated circuit device, the method comprising: setting a standard for a plurality of parameters that influence the dimensions of the circuit pattern. Determining a layout of a mask pattern provided on the mask corresponding to the circuit pattern; determining a dummy pattern allocable area in the mask based on the layout of the mask pattern; When dummy patterns are uniformly arranged over the entire area, the plurality of dummy circuit patterns calculated in consideration of the dummy circuit pattern and the circuit pattern formed in the semiconductor integrated circuit device corresponding to the dummy pattern. Determine the layout of the dummy pattern so that the parameter values meet the standards. Mask design method characterized in that comprises the step of. 2. The mask design method according to claim 1, wherein the plurality of parameters include a pattern occupation area ratio and a pattern peripheral length per unit area. 3. The dummy pattern comprises a plurality of partial patterns of the same shape arranged in a plurality of unit areas partitioning the dummy pattern arrangeable area in a grid pattern. The described mask design method. 4. A mask for forming a circuit pattern of a semiconductor integrated circuit device, wherein a mask pattern corresponding to the circuit pattern and a dummy pattern allocable region set based on a layout of the mask pattern are uniformly formed. A dummy pattern arranged on the semiconductor integrated circuit, wherein a standard is set for a plurality of parameters that affect the dimensions of the circuit pattern, and the layout of the dummy pattern corresponds to the dummy pattern. A mask, wherein values of the plurality of parameters calculated in consideration of a dummy circuit pattern formed in the device and the circuit pattern are determined so as to satisfy the standard. 5. The mask according to claim 4, wherein the plurality of parameters include a pattern occupation area ratio and a pattern peripheral length per unit area. 6. The dummy pattern is composed of a plurality of partial patterns having the same shape and arranged in a plurality of unit areas that partition the dummy pattern arrangeable area in a grid pattern. The listed mask.