JP2003110064A - Semiconductor device - Google Patents

Abstract

(57) Abstract: When a large thermal stress acts on a semiconductor device, element destruction can be prevented, and the long-term reliability of the semiconductor device is improved. SOLUTION: A semiconductor device 1 according to the present invention includes a semiconductor chip 2 and a pair of heat sinks 3 and 4 for dissipating heat from both surfaces of the semiconductor chip 2, and substantially the entire device is molded with a resin 7. A configuration in which t2 / t1 ≧ 5 holds when the thickness of the semiconductor chip 2 is t1 and the thickness of at least one of the pair of heat sinks 3 and 4 is t2. It is. The present inventors have confirmed through trial production and experiments that element destruction does not occur even when a large thermal stress acts on the semiconductor device 1 having the above configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a heating element and a pair of heat radiating plates bonded to both sides of the heating element.

[0002]

2. Description of the Related Art For example, a semiconductor chip (heat generating element) for high breakdown voltage and large current generates a large amount of heat during use, and therefore, a structure for improving heat dissipation from the chip is required. As an example of this configuration, a configuration in which a pair of heat dissipation plates are joined to both sides of the chip via, for example, a solder layer has been considered in the past. With this configuration, heat can be dissipated from both sides of the chip. Is improved. The entire double-sided heat dissipation type semiconductor device is molded with resin.
The outer surfaces of the pair of heat dissipation plates are exposed so as to improve heat dissipation.

[0003]

In the semiconductor device having the above structure, since the semiconductor chips, the heat sink, and the resin have a large difference in coefficient of thermal expansion, a considerably large thermal stress acts on the contact portion between these three members, and The semiconductor chip may be destroyed by the stress. This tendency becomes more remarkable as the temperature difference of the heat cycle applied to the semiconductor device increases.

Therefore, an object of the present invention is to provide a semiconductor device capable of preventing element destruction even when a large thermal stress acts and improving the long-term reliability of the semiconductor device. .

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device including a heating element and a pair of heat radiating plates for radiating heat from both sides of the heating element, and substantially the entire device is molded with resin. In the above, when the thickness dimension of the heating element is t1 and the thickness dimension of at least one of the pair of heat radiation plates is t2, t2 / t1 ≧ 5 is satisfied. The present inventors can increase the compressive stress for holding the heat generating element and increase the shear stress of the surface of the heat generating element if the above conditional expression is satisfied by executing trial manufacture or experiments. It has been confirmed that can be reduced. Then, it was confirmed that even if a large thermal stress was applied to the semiconductor device having the above-mentioned structure, element destruction did not occur. Therefore, according to the above configuration, the long-term reliability of the semiconductor device can be improved.

According to a second aspect of the invention, when the coefficient of thermal expansion of the heat sink is α1 and the coefficient of thermal expansion of the resin is α2, 0.5α1 ≦ α2 ≦ 1.5α1 is satisfied. did. The inventors of the present invention have confirmed that the tensile stress to the heat generating element and the shear stress on the surface of the heat generating element can be reduced if the above conditional expressions are satisfied by performing trial manufacture and experiments. Therefore, according to the above configuration, long-term reliability can be improved even if a large thermal stress acts.

According to the third aspect of the invention, when the surface roughness of the back surface of the heating element is Ra, Ra ≦ 500 nm is satisfied. The inventors of the present invention have sufficient strength against the stress acting on the back surface of the heat generating element and do not cause element cracking if the above conditional expressions are satisfied by performing trial manufacture and experiments. It was confirmed. Therefore, according to the above configuration, long-term reliability can be improved even if a large thermal stress acts.

According to the invention of claim 4, claim 2
It is possible to obtain substantially the same operational effects as the invention of. According to the invention of claim 5 or 6, it is possible to obtain substantially the same effect as that of the invention of claim 3.

On the other hand, in the seventh aspect of the invention, the thickness of the semiconductor element is reduced so as to reduce the shear stress on the surface of the semiconductor element or the strain component in the joining layer for joining the semiconductor element and the metal body. At the same time, since the entire device is restrained and held by the mold resin, durability such as cold and heat cycle resistance and creep resistance can be improved.

In this case, it is preferable that the semiconductor element has a thickness of 250 μm or less.
It is also preferable that at least one of the three metal bodies has a thickness of 1.0 mm or more. Further, as in the tenth aspect of the invention, the thickness of the semiconductor element may be adjusted so that the plastic strain rate at the end of the bonding layer is 1% or less. Furthermore, the thickness of the semiconductor element may be adjusted so that the shear stress on the surface of the semiconductor element is 35 MPa or less.

According to the invention of claim 12, the bonding layer is made of Sn.
Since it is composed of the system solder, the strength of the joint is increased and the strain component in the joint layer can be reduced. Further, it is preferable that the device structure of the semiconductor element is of a trench gate type.

Furthermore, according to the inventions of claims 14, 15 and 16, it is possible to obtain substantially the same operational effects as those of the inventions of claims 1, 2, and 3.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to FIGS. First,
FIG. 1 is a sectional view showing a schematic configuration of the semiconductor device of this embodiment. As shown in FIG. 1, the semiconductor device 1 of this embodiment includes a semiconductor chip (heat generating element, semiconductor element) 2, a lower heat sink (heat sink, first metal body) 3, and an upper heat sink (heat sink). , Second metal body) 4 and a heat sink block 5 (third metal body).

In the case of this structure, the lower surface of the semiconductor chip 2 and the upper surface of the lower heat sink 3 are joined by a joining member such as solder (joining layer) 6. The upper surface of the semiconductor chip 2 and the lower surface of the heat sink block 5 are also joined by solder (joint layer) 6. Further, the upper surface of the heat sink block 5 and the lower surface of the upper heat sink 4 are also joined by solder (joint layer) 6. As a result, in the above configuration, heat is radiated from both surfaces of the semiconductor chip 2 via the heat sinks 3 and 4 (that is, the pair of heat radiating plates).

The semiconductor chip 2 is, for example, an IGB.
It is composed of a power semiconductor element such as a T or a thyristor. In this case, the device structure of the semiconductor chip 2 is preferably a trench gate type. Of course, other types of device structures may be used.

In the case of the present embodiment, the shape of the semiconductor chip 2 is, for example, a rectangular thin plate shape as shown in FIG. The lower heat sink 3, the upper heat sink 4, and the heat sink block 5 are made of a metal having good thermal conductivity and electrical conductivity, such as Cu or Al. In the case of this configuration, the lower heat sink 3 and the upper heat sink 4 are also electrically connected to each main electrode (for example, a collector electrode or an emitter electrode) of the semiconductor chip 2 via the solder 6.

The lower heat sink 3 is shown in FIG.
As shown in FIG. 3, the plate member is, for example, a substantially rectangular plate as a whole, and the terminal portion 3a is provided so as to extend rearward. Further, the heat sink block 5 is shown in FIG.
As shown in (1), the rectangular plate member is one size smaller than the semiconductor chip 2. Further, as shown in FIG. 2D, the upper heat sink 4 is composed of, for example, a substantially rectangular plate material as a whole, and the terminal portion 4a is provided so as to project rearward. The terminal portion 3a of the lower heat sink 3 and the terminal portion 4a of the upper heat sink 4 are configured so that their positions are displaced from each other, that is, they do not face each other.

In the case of the above construction, the distance between the upper surface of the lower heat sink 3 and the lower surface of the upper heat sink 4 is
For example, it is configured to be about 1 to 2 mm. In FIGS. 1 and 2, the distance is shown in a considerably enlarged manner.

Further, as shown in FIG. 1, a resin (for example, epoxy resin) 7 is filled and sealed in the gap between the pair of heat sinks 3 and 4, and in the peripheral portion of the chip 2 and the heat sink block 5. In this case, when molding the heat sinks 3, 4 and the like with the resin 7, a molding die (not shown) composed of upper and lower dies is used. Before the resin 7 is molded, in order to increase the adhesion between the resin 7 and the heat sinks 3 and 4, the adhesion between the resin 7 and the semiconductor chip 2, and the adhesion between the resin 7 and the heat sink block 5. In addition, it is preferable to apply a coating resin such as polyamide resin (not shown) to the surfaces of the heat sinks 3, 4, the heat sink block 5, and the chip 2.

Next, a manufacturing method (that is, a manufacturing process) of the semiconductor device 1 having the above structure will be briefly described with reference to FIG. First, as shown in FIGS. 2A and 2B, the step of soldering the semiconductor chip 2 and the heat sink block 5 to the upper surface of the lower heat sink 3 is performed.
In this case, the chip 2 is laminated on the upper surface of the lower heat sink 3 via the solder foil 8, and the heat sink block 5 is laminated on the chip 2 via the solder foil 8. Then, the solder foil 8 is heated by a heating device (reflow device),
Melt 8 and then cure.

Then, as shown in FIG. 2C, a step of wire-bonding the control electrodes (for example, gate pads) of the chip 2 and the lead frames 9a and 9b to each other is performed. Thereby, for example, the wire 1 made of Al or Au
The control electrode of the chip 2 and the lead frame 9a
9b is connected.

Then, as shown in FIGS. 2D and 2E, the upper heat sink 4 is placed on the heat sink block 5.
Perform the step of soldering. In this case, FIG. 2 (d)
As shown in FIG.
The upper heat sink 4 is placed via. Then, the solder foil 8 is melted by a heating device and then cured.

At this time, as shown in FIG. 2E, a weight 11 is placed on the upper heat sink 4 to press the upper heat sink 4 downward. Along with this, a spacer jig (not shown) is attached between the upper heat sink 4 and the lower heat sink 3 so that the distance between the upper heat sink 4 and the lower heat sink 3 is maintained at a set distance. is doing.

In this structure, the distance between the upper heat sink 4 and the lower heat sink 3 is larger than the set distance of the spacer jig before the solder foil 8 is melted. When the solder foil 8 melts,
The portion of the melted solder layer becomes thin due to the pressure applied by the weight 11, and the distance between the upper heat sink 4 and the lower heat sink 3 becomes equal to the set distance of the spacer jig. At this time,
The solder layer is configured to be thin to an appropriate thickness. Then, when the melted solder layer is hardened, the joining and electrical connection of the chip 2, the heat sinks 3, 4, and the heat sink block 5 are completed.

After that, a step of applying the polyamide resin to the surfaces of the heat sinks 3, 4, the heat sink block 5, the chip 2 and the like is executed. In this case, it may be applied by dipping, for example, or may be applied by dropping (or spraying) from a nozzle of a polyamide resin application dispenser. The polyamide resin may be applied as needed, and the application of the polyamide resin may be omitted.

After applying the polyamide resin,
A step of filling the gap between the heat sinks 3 and 4 and the outer peripheral portion with the resin 7 using a molding die (not shown) (molding step)
To execute. As a result, as shown in FIG. 1, the resin 7 is filled and sealed in the gaps and the outer peripheral portions of the heat sinks 3 and 4. Then, after the resin 7 is cured, the semiconductor device 1 is taken out from the molding die, and the semiconductor device 1 is completed. still,
In the case of the above configuration, the lower surface of the lower heat sink 3 and the upper surface of the upper heat sink 4 are resin-molded so as to be exposed. This enhances the heat dissipation of the heat sinks 3 and 4.

In the semiconductor device 1 having the above structure, t2 / t1 ≧ 5 is satisfied when the thickness dimension of the semiconductor chip 2 is t1 and the thickness dimension of the lower heat sink 3 is t2. Configured. In the case of this embodiment, the thickness dimension of the upper heat sink 4 is also t2.

Now, the reason why the conditional expressions for the thickness dimensions t1 and t2, that is, the thickness ratio (t2 / t1) is set as described above will be described. The present inventors can increase the compressive stress for holding the semiconductor chip 2 as long as the conditional expression of the thickness ratio is satisfied by executing trial manufacture and experiments, and at the same time, the semiconductor It was confirmed that the shear stress on the surface of the chip 2 can be reduced.

Specifically, semiconductor devices 1 having different thickness ratios were manufactured as prototypes, and the element compressive stress of each prototype was measured to obtain the graph shown in FIG. In the graph of FIG. 3, the horizontal axis represents the thickness ratio, the vertical axis represents the element compressive stress ratio, and the plot represents the actually manufactured semiconductor device 1. Here, the element compressive stress ratio is a numerical value when the element compressive stress of the semiconductor device 1 having a thickness ratio of 3.75 is defined as 1.00.

When a semiconductor device 1 having a thickness ratio of 3.75 (that is, a device compressive stress ratio of 1.00) is subjected to a thermal cycle with a large temperature difference, the semiconductor chip 2 is cracked. I'm confirming. The thickness ratio is 2.
5 (that is, a device compression stress ratio of 0.98) 1
It has been confirmed that the semiconductor chip 2 is broken even when a thermal cycle with a large temperature difference is applied.

On the other hand, the thickness ratio is 7.00 (that is, the element compressive stress ratio is 1.09) and the thickness ratio is 15.0.
Semiconductor device 1 having 0 (that is, element compression stress ratio of 1.13)
When a thermal cycle with a large temperature difference is applied to
It has been confirmed that the semiconductor chips 2 of both are not broken.
That is, the greater the thickness ratio and thus the element compression stress ratio,
It has been confirmed that the semiconductor chip 2 is less likely to break.

Therefore, from the graph of FIG. 3, the thickness ratio (t
If 2 / t1) is set to 5.00 or more, the element compressive stress can be kept sufficiently large, and even if a large thermal stress acts on the semiconductor device 1, it is possible to prevent the element destruction. Recognize. Thereby, the long-term reliability of the semiconductor device 1 can be improved.

Further, the shear stress on the element surface of each prototype of the semiconductor device 1 having a different thickness ratio was calculated by simulation, and the graph shown in FIG. 4 was obtained. In the graph of FIG. 4, the horizontal axis represents the thickness ratio, the vertical axis represents the shear stress ratio on the element surface, and the plot represents the actually manufactured semiconductor device 1. Here, as for the shear stress ratio, the shear stress of the semiconductor device 1 having a thickness ratio of 3.75 is 1.00.
It is a numerical value when it is defined as.

When a thermal cycle having a large temperature difference is applied to the semiconductor device 1 having a thickness ratio of 3.75 (that is, a shear stress ratio of 1.00), the resin near the surface of the semiconductor chip 2 peels off. I'm sure you'll do it. The thickness ratio is 2.5 (that is, the shear stress ratio is 1.0
It has been confirmed that the resin near the surface of the semiconductor chip 2 peels off even when the semiconductor device 1 of 2) is subjected to a thermal cycle with a large temperature difference.

On the other hand, the thickness ratio is 7.00 (that is, the shear stress ratio is 0.6) and the thickness ratio is 15.00.
It has been confirmed that when a semiconductor device 1 having a shear stress ratio of 0.15 is subjected to a thermal cycle with a large temperature difference, the resin in the vicinity of the surfaces of the semiconductor chips 2 does not peel off. That is, it has been confirmed that the larger the thickness ratio (that is, the smaller the shear stress ratio), the more difficult the resin on the surface of the semiconductor chip 2 is to peel off.

Therefore, from the graph of FIG. 4, the thickness ratio (t
When 2 / t1) is set to 5.00 or more, the shear stress can be sufficiently reduced, and the resin on the element surface can be prevented from peeling off even when a large thermal stress acts on the semiconductor device 1. Recognize. Thereby, the long-term reliability of the semiconductor device 1 can be improved.

In the case of the above embodiment, it is known that a good effect can be obtained by increasing the thickness ratio, but it is difficult to increase the thickness ratio too much. This is because there are two methods of increasing the thickness ratio, one method is to reduce the thickness dimension t1 of the semiconductor chip 2, and another method is to reduce the thickness dimension t of the heat sinks 3 and 4.
2 is to thicken.

However, when the thickness t1 of the semiconductor chip 2 is reduced, the processing limit is about 0.1 mm. If the thickness t2 of the heat sinks 3 and 4 is fixed to about 1.0 mm, the thickness ratio becomes 15. It will be the limit. On the other hand, when the thickness dimension t2 of the heat sinks 3 and 4 is increased, the overall thickness dimension of the semiconductor device 1 is increased, which is a practical (product) limitation. Therefore, the thickness ratio is limited to about 15, and the thickness ratio of the vest is about 7 to 8 in view of the ease of processing the chip and practical restrictions.

Further, in the above embodiment, the Young's modulus is 100 GPa at room temperature as the material of the heat sinks 3 and 4.
It is preferable to use materials such as the above metals and alloys.
This is because the material having a Young's modulus of 100 GPa or more is hard and has sufficient rigidity, so that a sufficient amount of compressive stress can be obtained. In order to increase the compressive stress, it is preferable that the rigidity of the material is large.

Examples of materials for the heat sinks 3 and 4 which satisfy the Young's modulus include Cu, Cu-based alloys, Al and Al-based alloys, and these metals or alloys may be used.

Further, in the above embodiment, as a concrete material of the solder 6 for joining the semiconductor chip 2 to the heat sinks 3, 4 and the heat sink block 5, for example, Sn--
A binary system such as a Pb system, a Sn-Ag system, a Sn-Sb system, a Sn-Cu system, or a multi-component system may be appropriately selected. Further, the resin 7 for molding may be appropriately selected from appropriate materials such as epoxy series.

In the above embodiment, the thickness dimensions of both the lower heat sink 3 and the upper heat sink 4 are t2.
However, the thickness of the lower heat sink 3 is not limited to this, and the thickness dimension of the lower heat sink 3 is t2.
May be different from t2, or conversely, only the thickness of the upper heat sink 4 may be t2 and the thickness of the lower heat sink 3 may be different from t2.

FIGS. 5 to 7 are views showing a second embodiment of the present invention. In the second embodiment, when the heat expansion coefficient of the heat sinks 3 and 4 is α1 and the heat expansion coefficient of the resin 7 is α2 in the semiconductor device 1 of the first embodiment, 0.5α1 ≦ α2 ≦ The configuration is such that 1.5α1 holds.

The inventors of the present invention have conducted the trial manufacture and the experiment etc., and if the semiconductor device 1 is constructed so that the conditional expression of the thermal expansion coefficient is satisfied, the surface of the semiconductor chip (heating element) 2 It was confirmed that the tensile stress on the edge and the shear stress on the surface of the semiconductor chip 2 can be reduced.
Hereinafter, based on experimental results and the like, it will be specifically described that the conditional expression of the thermal expansion coefficient is effective.

First, the tensile force at the end of the surface of the semiconductor chip 2 of each prototype of the semiconductor device 1 in which the thermal expansion coefficient α2 of the resin 7 was changed, that is, the stress in the Z direction was calculated by simulation, and FIG. The graph shown in is obtained. In the graph of FIG. 5, the horizontal axis represents the thermal expansion coefficient α2 of the resin 7, the vertical axis represents the stress in the Z direction, and the plot shows the actually manufactured semiconductor device 1. The Z direction is the direction orthogonal to the semiconductor chip 2, that is, the vertical direction in FIG. The heat sinks 3 and 4 of each prototype of the semiconductor device 1 are made of Cu, for example, and the thermal expansion coefficient α1 of Cu is 17 ppm.

From FIG. 5 described above, as the thermal expansion coefficient α2 of the resin 7 increases, the stress in the Z direction, that is, the semiconductor chip 2 is increased.
The tensile force at the edge of the surface of the
It can be seen that can be firmly held.

Next, the shear stress on the surface of the semiconductor chip 2 of each prototype of the semiconductor device 1 in which the thermal expansion coefficient α2 of the resin 7 was changed was calculated by simulation, and FIG.
The graph shown in is obtained. In the graph of FIG. 6, the horizontal axis represents the thermal expansion coefficient α2 of the resin 7, the vertical axis represents the shear stress, and the plot represents the actually manufactured semiconductor device 1.

In this case, it has been found that the closer the shear stress is to 0, the better, and the larger the absolute value, the worse the shear stress. With respect to the five prototypes shown in FIG. 6, the occurrence of peeling of the resin 7 was not confirmed even when a large thermal stress was applied, and the thermal expansion coefficient α2 was 25 ppm.
Even then, it has been confirmed that the shear stress at that time is not a problem.

Here, the coefficient of thermal expansion α2 of the resin 7 is expressed by the coefficient of thermal expansion α1 of the heat sinks 3 and 4, and this is taken as the horizontal axis, and the vertical axis is taken as the stress in the Z direction (that is, the yield stress of the solder). ) And the absolute value of the shear stress, two graphs (curves) A and B shown in FIG. 7 were obtained. In this case, curve A is Z
The relationship between the directional stress and the thermal expansion coefficient of the resin 7 is shown, and the curve B shows the relationship between the shear stress and the thermal expansion coefficient of the resin 7.

In FIG. 7, the upper limit value of the stress in the Z direction is about 35 to 40 MPa, and the stress in the Z direction must be smaller than the above upper limit value. Therefore, the thermal expansion coefficient α2 of the resin 7 must be 0.5α1 or more. The upper limit of shear stress is about 50 MPa, and the shear stress must be smaller than the above upper limit. Therefore, the thermal expansion coefficient α2 of the resin 7 is set to 1.
Must be 5α1 or less.

As a result, the above-mentioned conditional expression of the coefficient of thermal expansion,
That is, 0.5α1 ≦ α2 ≦ 1.5α1 is obtained. If the semiconductor device 1 is configured to satisfy the conditional expression of the coefficient of thermal expansion, the semiconductor chip 2 will not be cracked even if a large thermal stress acts, and long-term reliability can be improved. it can.

The upper limit of the Z-direction stress is 35 to 40M.
The reason why it is about Pa is that the tensile strength of the solder (for example, Sn—Pb based solder) that joins the semiconductor chip 2 and the heat sinks 3 and 4 is about 35 to 40 MPa. This is because it cannot be secured. This is described in the literature (for example, high reliability micro soldering technology, industrial research committee).

The reason why the upper limit of the shear stress is about 50 MPa is that the adhesion strength between the Cu frame and the general molding resin is about 50 MPa, and when a shear stress exceeding this is applied, This is because resin peeling occurs. This was confirmed by the applicant's experiment.

In the above embodiment, when the heat sinks 3 and 4 are made of, for example, Cu or a Cu-based alloy (in this case, the thermal expansion coefficient α1 of the heat sinks 3 and 4 is 17 pp.
m)), the thermal expansion coefficient α2 of the resin 7 is 10 p
The present inventors have confirmed through experiments and the like that it is preferable to set to pm or more.

When the heat sinks 3 and 4 are made of, for example, a Cu-based sintered alloy or a Cu-based composite material (in this case, the thermal expansion coefficient α1 of the heat sinks 3 and 4 is about 8 ppm), the resin 7 The present inventors have confirmed through experiments and the like that it is preferable to set the thermal expansion coefficient α2 to 6 ppm or more.

Further, in the above embodiment, the resin 7 having a Young's modulus of 10 GPa or more was used. This is because, considering the balance of the overall stress, the semiconductor device 1
This is because it is preferable that the Young's modulus of the resin 7 that molds and protects almost all of the above is 10 GPa or more.

In the second embodiment, in the semiconductor device 1 of the first embodiment, the above conditions are satisfied between the coefficient of thermal expansion of the heat sinks 3 and 4 being α1 and the coefficient of thermal expansion of the resin 7 being α2. However, the present invention is not limited to this. In a semiconductor device having a thickness ratio (t2 / t1) of less than 5, the conditional expression for the coefficient of thermal expansion is satisfied. However, even in the case of this configuration, substantially the same operational effect can be obtained.

FIG. 8 is a diagram showing a third embodiment of the present invention. The third embodiment is configured such that Ra ≦ 500 nm is established when the surface roughness of the back surface of the semiconductor chip 2 is Ra in the semiconductor device 1 of the first embodiment or the second embodiment. It was done.

By setting the surface roughness Ra of the back surface of the semiconductor chip 2 in this way, the strength against element destruction can be improved, and the semiconductor chip 2 is surely cracked when a large thermal stress acts. It can be prevented.

Here, when the present inventors apply thermal stress to each prototype of the semiconductor device 1 in which the surface roughness Ra is changed, the rate at which the semiconductor chip 2 is cracked occurs. The result was shown in FIG. In FIG. 8, the horizontal axis represents the surface roughness Ra of the back surface of the semiconductor chip 2, and the vertical axis represents the crack occurrence rate of the semiconductor chip 2.

From FIG. 8, it can be seen that when the surface roughness Ra is set to 500 nm or less, the strength of the semiconductor chip 2 increases and the semiconductor chip 2 is hardly cracked. The case where the surface roughness Ra is set to 2000 nm is a general case of a small chip.

In the third embodiment, the surface roughness Ra of the back surface of the semiconductor chip 2 is set to 500 nm or less in the semiconductor device 1 of the first or second embodiment. The present invention is not limited to this, and a semiconductor device having a thickness ratio (t2 / t1) of less than 5 according to the first embodiment,
In a semiconductor device or the like having a structure in which the conditional expression of the thermal expansion coefficient of the second embodiment is not satisfied, the surface roughness Ra of the back surface of the semiconductor chip 2 may be set to 500 nm or less. Also in the case of such a configuration, substantially the same operational effect can be obtained.

9 and 10 are diagrams showing a fourth embodiment of the present invention. In the fourth embodiment, in the semiconductor device 1 of the first embodiment, the thickness dimension (t2) of the heat sinks 3 and 4 is fixed to about 1.5 mm, and the thickness dimension (t1) of the semiconductor chip 2 is changed. It is configured to allow. Then, in the second embodiment, the semiconductor chip 2
By setting the thickness of the
The resin 7 is prevented from peeling off at the end portion 2a (see FIG. 9).

Specifically, in the case of the fourth embodiment, the shear stress on the element surface of each prototype of the semiconductor device 1 in which the thickness dimension of the semiconductor chip 2 is changed is calculated by simulation, and the graph shown in FIG. Got In the graph of FIG. 10, the horizontal axis represents the thickness dimension of the semiconductor chip 2, the vertical axis represents the shear stress ratio on the element surface, and the plot shows the actually manufactured semiconductor device 1. Here, regarding the shear stress ratio, the thickness dimension of the semiconductor chip 2 is 400 μm (first
When converted to the thickness ratio (t2 / t2) in the example of 3.
This is a numerical value when the shear stress of the semiconductor device 1 of 75) is defined as 1.00.

The thickness dimension of this semiconductor chip 2 is 400 μm.
When a thermal cycle with a large temperature difference is applied to the semiconductor device 1 having m (that is, a shear stress ratio of 1.00), the resin in the vicinity of the surface end portion 2a of the semiconductor chip 2 peels off. The present inventors have confirmed.

On the other hand, when the semiconductor chip 2 has the thickness dimension of 200 μm (the thickness ratio is 7.00 and the shear stress ratio is 0.6), the temperature difference with respect to the semiconductor device 1 is increased. The present inventors have confirmed that the life of resin peeling is extended ten times or more when a large heat cycle of is applied. The thickness dimension of the semiconductor chip 2 is 1
It has been confirmed that the resin does not peel off even when a thermal cycle with a large temperature difference is applied to the semiconductor device 1 of 00 μm (thickness ratio is 15.00 and shear stress ratio is 0.15).

Therefore, it is understood that the thinner the thickness of the semiconductor chip 2 (the larger the thickness ratio, that is, the smaller the shear stress ratio), the more difficult the resin on the surface of the semiconductor chip 2 is to peel off.

In each of the above embodiments, the heat sink 3,
Although the solder foil 8 is used as a joining member for joining the semiconductor chip 4, the semiconductor chip 2, and the heat sink block 5, a solder paste or the like may be used instead.

Further, in each of the above embodiments, one semiconductor chip (heat dissipation element) 2 is sandwiched between the heat sinks 3 and 4, but the present invention is not limited to this, and two or more chips (or It may be configured to sandwich two or more types of chips).

Next, the inventors of the present invention filed an earlier application (Japanese Patent Application No. 20).
01-225963) about the research results after
This will be described with reference to FIGS. 11 to 16. First, in order to improve the durability of the semiconductor device 1 of each of the above-described embodiments against a cooling / heating cycle or the like, the strain at the joint between the semiconductor chip (semiconductor element) 2 and the heat sink (metal body) 3, 4, 5 is reduced. It has been found that it is preferable to reduce the shear stress on the surface of the semiconductor chip 2.

Then, as a measure for reducing the strain of the joint portion and preventing the element destruction, (1) applying compressive stress to the semiconductor chip 2 to hold the displacement due to compression and not to generate tensile stress; 2) It has been found that the rigidity of the semiconductor chip 2 may be reduced in order to facilitate the compressive displacement of the semiconductor chip 2. Hereinafter, it will be specifically described that the durability of the semiconductor device 1 is increased while numerically defining these conditions.

The present inventors have found that the requirements necessary for improving the durability of the semiconductor device 1 can be summarized into the following four.

(A) It is known that the silicon constituting the semiconductor element (semiconductor chip 2) does not break even when a compressive stress of 600 MPa or more is applied, but it breaks only when a tensile stress of about 100 MPa is applied. That is, the compressive stress is always applied to the semiconductor element even in the manufacturing process or in the usage environment.

(B) The source of the compressive stress on the semiconductor element is the thermal stress due to the difference in the coefficient of thermal expansion between the metal body and the semiconductor element (silicon). Then, in order to apply the compressive stress to the semiconductor element, it is necessary to surely transmit the thermal stress to the semiconductor element and to maintain the compressed state. Therefore, as a bonding material between the metal body and the semiconductor element, from the viewpoint of transmission of compressive stress, the conventionally known Pb-Sn is known.
It is necessary to use a solder which has higher strength than that of the system-based solder and which has excellent creep resistance as compared with the conventionally known Pb-Sn-based solder from the viewpoint of retaining compressive stress.

(C) In order to increase the compressive stress of the semiconductor element, facilitate the displacement, and reduce the repulsive force from the semiconductor element against the compressive stress, it is necessary to reduce the thickness of the semiconductor element.

(D) Another structure for effectively applying compressive stress to the semiconductor element and holding the compressive stress is to mold the semiconductor element and the metal body with resin. In the case of this configuration, by setting the thermal expansion coefficient of the molding resin to be equal to or higher than the thermal expansion coefficient of the metal body, the state of compressive stress can be maintained.

The operational effects (and experimental data, etc.) of the above requirements will be described below in order.

First, FIG. 11 is a diagram for explaining a process in which a compressive stress is applied to a semiconductor element. When joining a front surface and a back surface of a semiconductor element to a metal body, a reflow process is generally adopted in which the semiconductor element, the metal body, and the bonding material (solder) are heated to a predetermined temperature to melt and cure the bonding material. . In this case, when the joining material is melted and then cooled, the joining is completed, but in this process, compressive stress is generated.

For example, when the semiconductor element is silicon and the metal body is Cu, the difference in thermal expansion coefficient between the two is quite large. In general, the larger the difference in thermal expansion coefficient, the higher the compressive stress, but the compressive stress does not increase linearly due to the yielding and plastic deformation of the bonding material and the metal body. The thermal expansion coefficients of the main materials are shown in Table 1 below.

[0080]

[Table 1] Then, if left standing after cooling, the compressive stress relaxes due to creep of the bonding material. As the relaxation progresses, the internal stress of the semiconductor element eventually becomes zero. In this state, if the semiconductor element generates heat or the ambient temperature rises, tensile stress is applied to the semiconductor element, which may cause the semiconductor element to be broken.

The relaxation behavior of the compressive stress is mainly due to the creep characteristics of the bonding material. Therefore, the strength and relaxation of the bonding material will be described below. The strengths of the main joining materials are shown in Table 2 below.

[0082]

[Table 2] It is generally known that Sn-based solder based on Sn has higher mechanical strength than Pb-based solder. For this reason, it is preferable to use Sn-based solder as the joining material, and thereby, the thermal stress generated in the cooling process can be surely applied to the semiconductor element, and the compressive stress can be generated in the element. Although there are many types of Sn-based solders and various compositions have been proposed, the breaking strength, the yield stress, etc. are higher than those of Pb-based solders regardless of whether they are binary or ternary. Just select the solder.

In this way, even if the compressive stress can be applied to the semiconductor element, if it is relaxed, it leads to the destruction of the semiconductor element. Therefore, next, the requirements for maintaining the compressed state of the semiconductor element will be considered. When stress is applied to the material, the material is displaced in the direction of relaxing the stress. This behavior is called creep and is remarkable in Pb. The relaxation rates of the main bonding materials are shown in Table 3 below.

[0084]

[Table 3] From the above table, it can be seen that the Sn solder has a slower strain rate due to creep than the Pb solder and is effective in retaining the compressive stress of the element.

FIG. 12 is a graph comparing changes over time in the compressive stress value at the center of the semiconductor element (when left at room temperature after joining) when Pb-based solder and Sn-based solder were used. It can be seen from FIG. 12 that the compressive stress can be increased and the state can be maintained by using the Sn-based solder as the bonding material.

Next, it is possible to increase the compressive stress of the element and suppress the relaxation behavior by a method different from the above-mentioned method. This method will be described below. It was found that the compressive stress applied to the element depends on the rigidity of each part, other than the physical property values of the material such as the difference in thermal expansion coefficient between the semiconductor element and the metal body.

For example, assuming that the joint does not undergo plasticity or yielding, if the thickness of the semiconductor element is reduced relative to the metal body, the semiconductor element is more easily displaced and the compressive stress is reduced. Increase. FIG. 13 is a diagram showing the result of calculation of the compressive stress applied to the semiconductor element by simulation, that is, the stress distribution. FIG. 13A shows the case where the thickness of the semiconductor element is 0.4 mm.
(B) is the case where the thickness of the semiconductor element is 0.2 mm.
From FIG. 13, it is understood that the compressive stress can be increased by reducing the heat of the semiconductor element.

The result is that the thickness of the semiconductor element is reduced,
Reducing the rigidity of the semiconductor element means that the element has a greater tendency to displace with the metal body. Therefore,
When the thickness of the semiconductor element is reduced, the semiconductor element behaves as if it "fits" into the metal body, so that the shear stress on the front and back surfaces of the semiconductor element is reduced, and the distortion component of the joint part related to the durability of the semiconductor device is reduced. Can be expected to shrink.

FIG. 14 is a graph obtained by actually measuring the relationship between the thickness of the semiconductor element and the shear plastic strain. This FIG.
From the above, it can be seen that when the thickness of the semiconductor element is reduced, the shear strain of the joint portion is reduced.
It can be seen that the plastic strain value in the shear direction is 1% or less when the thickness is less than μm. And, in this case, it is understood that the durability performance represented by the thermal shock test is improved.

Next, the relationship between the mold resin and the compressive stress (durability) will be described. Basically, the mold resin preferably has a coefficient of thermal expansion equivalent to that of the metal body. For example, when Cu is used as the metal body, it has been confirmed by experiments that sufficient durability performance can be obtained if the thermal expansion coefficient of the mold resin is about 11 to 20 ppm.

FIG. 15 shows the thermal expansion coefficient of the mold resin,
It is a characteristic view which shows the result of having evaluated the relationship with the stress of the Z direction with respect to a semiconductor element by simulation. From FIG. 15, it can be seen that the compressive stress can be increased in the Z direction as well by increasing the thermal expansion coefficient of the resin. It is known that when the coefficient of thermal expansion of the resin is 25 ppm or more, the shear stress at the interface with Cu becomes high and the resin and the metal body may be separated from each other in the simulation. However, since the influence of the resin is not so large, it is estimated that it is a secondary parameter.

Now, based on the above-mentioned requirements, a semiconductor device was prototyped and the durability was evaluated.
6 shows. In FIG. 16, the thickness of the semiconductor element is taken in the vertical direction and the thickness of the metal body is taken in the horizontal direction. In addition, "Batsutsu" is a cracked semiconductor element of all prototypes, "Triangle" is a cracked semiconductor element of some prototypes, and "Circle" is all prototypes. The semiconductor element of was not broken. The straight line on FIG. 16 shows the case where the ratio (t2 / t1) is 5. Therefore, it is understood that if the ratio (t2 / t1) is 5 or less, sufficient durability can be obtained.

Regarding the thickness of the metal body, it is easily understood that the thicker it is, the better from the viewpoint of heat dissipation.
The thickness of what is available as a general frame material,
Up to about 2.5 mm, actually 1.0-2.0 m
Those of about m are suitable for mass production.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 3 is a characteristic diagram showing the relationship between the thickness ratio and the compressive stress ratio.

FIG. 4 is a characteristic diagram showing the relationship between the thickness ratio and the shear stress ratio.

FIG. 5 is a characteristic diagram showing a second embodiment of the present invention and showing the relationship between the coefficient of thermal expansion of resin and the stress in the Z direction.

FIG. 6 is a characteristic diagram showing the relationship between the thermal expansion coefficient of resin and shear stress.

FIG. 7 is a characteristic diagram showing the relationship between the coefficient of thermal expansion and the absolute values of Z-direction stress and shear stress.

FIG. 8 is a characteristic diagram showing a third embodiment of the present invention and showing the relationship between the surface roughness of the back surface of the semiconductor chip and the crack occurrence rate.

FIG. 9 is a partial vertical sectional view of a semiconductor device showing a fourth embodiment of the present invention.

FIG. 10 is a characteristic diagram showing a relationship between a thickness dimension of a semiconductor chip and a shear stress ratio.

FIG. 11 is a diagram illustrating a compressive stress generation process and a compressive stress relaxation process in a semiconductor element.

FIG. 12 is a characteristic diagram showing changes over time in compressive stress applied to a semiconductor element.

13A is a diagram showing a distribution of compressive stress applied to a semiconductor element having a thickness of 0.4 mm, and FIG. 13B is a diagram showing a distribution of compressive stress applied to a semiconductor element having a thickness of 0.2 mm.

FIG. 14 is a characteristic diagram showing the relationship between the thickness of a semiconductor element and the shear plastic strain of a joint.

FIG. 15 is a characteristic diagram showing the relationship between the coefficient of thermal expansion of resin and the stress applied to the semiconductor element in the Z direction.

FIG. 16 is a diagram showing the relationship between the thickness of a semiconductor element, the thickness of a metal body, and the durability evaluation result.

[Explanation of symbols]

1 is a semiconductor device, 2 is a semiconductor chip (heating element, semiconductor element), 3 is a lower heat sink (heat sink, first metal body), 4 is an upper heat sink (heat sink, second metal body), 5 is Heat sink block (third metal body), 6
Indicates solder (bonding layer), and 7 indicates resin.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kuniaki Mahikari             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Kenji Yagi             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Yoshimi Nakase, the inventor             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Yasutsugu Okura             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Kazuhito Nomura             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Yutaka Fukuda             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO F-term (reference) 5F036 AA01 BA23 BC06 BD01 BD21                       BE01

Claims (16)

[Claims] 1. A semiconductor device comprising a heating element and a pair of heat radiating plates for radiating heat from both surfaces of the heating element, wherein substantially the entire device is molded with resin, and the thickness dimension of the heating element is t1. The semiconductor device is configured such that t2 / t1 ≧ 5 holds when the thickness dimension of at least one of the pair of heat sinks is t2. 2. When the coefficient of thermal expansion of the heat dissipation plate is α1 and the coefficient of thermal expansion of the resin is α2, 0.5α1 ≦ α2 ≦ 1.5α1 is satisfied. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein Ra ≦ 500 nm is established when the surface roughness of the back surface of the heating element is Ra. 4. A semiconductor device comprising a heat-generating element and a pair of heat-radiating plates for radiating heat from both sides of the heat-generating element, wherein substantially the entire device is molded with resin, wherein the heat-expanding plate has a coefficient of thermal expansion of α1. The semiconductor device is configured such that 0.5α1 ≦ α2 ≦ 1.5α1 is satisfied when the thermal expansion coefficient of the resin is α2. 5. The semiconductor device according to claim 4, wherein Ra ≦ 500 nm is established when the surface roughness of the back surface of the heating element is Ra. 6. A semiconductor device comprising a heating element and a pair of heat radiating plates for radiating heat from both sides of the heating element, wherein substantially the entire device is molded with resin. A semiconductor device characterized in that, when Ra, Ra ≦ 500 nm is established. 7. A semiconductor element, a first metal body joined to the back surface of this semiconductor element to serve as an electrode and heat dissipation, and a second metal body joined to the front surface side of the semiconductor element to serve as an electrode and heat dissipation. A semiconductor device comprising a third metal body bonded between the surface of the semiconductor element and the second metal body, wherein almost the entire device is molded with resin, wherein the shear stress on the surface of the semiconductor element, or The semiconductor device is configured to be thin and to restrain and hold the entire device by the molding resin so as to reduce a strain component or the like in a bonding layer that bonds the semiconductor device and the metal body. A semiconductor device characterized by: 8. The semiconductor device according to claim 7, wherein the semiconductor element has a thickness of 250 μm or less. 9. At least one of the three metal bodies
9. The semiconductor device according to claim 7, wherein the thickness of each metal body is 1.0 mm or more. 10. The semiconductor device according to claim 7, wherein the thickness of the semiconductor element is adjusted so that the plastic strain rate at the end of the bonding layer is 1% or less. 11. The shear stress on the surface of the semiconductor element is 3
8. The semiconductor device according to claim 7, wherein the thickness of the semiconductor element is adjusted to be 5 MPa or less. 12. The semiconductor device according to claim 7, wherein the bonding layer is made of Sn-based solder. 13. The semiconductor device according to claim 7, wherein the device structure of the semiconductor element is a trench gate type. 14. When the thickness dimension of the semiconductor element is t1 and the thickness dimension of the heat dissipation plate of at least one of the first metal body and the second metal body is t2, t2 / 8. The semiconductor device according to claim 7, wherein t1 ≧ 5 is established. 15. The thermal expansion coefficient of the metal body is α1,
15. When the coefficient of thermal expansion of the resin is α2, 0.5α1 ≦ α2 ≦ 1.5α1 is established.
The semiconductor device described. 16. The surface roughness of the back surface of the semiconductor element is Ra.
15. It is configured such that Ra ≦ 500 nm is satisfied when the above condition is satisfied.
Alternatively, the semiconductor device according to item 15.