JP2003110058A - Semiconductor package and method of manufacturing the same Circuit member for body device - Google Patents

Abstract

(57) [Problem] To provide an inexpensive and multi-pin region semiconductor package while using a lead frame having a smaller thickness than a conventional one. A semiconductor element mounted on a die pad supported by suspension leads of a lead frame.
A wire 15 for electrically connecting the electrode on the upper surface of the semiconductor element 13 to the tip end portion 14 of the inner lead; and a sealing resin 16 for sealing an area surrounding the semiconductor element including the wire 15. Bulge portion 17a serving as a connection terminal on the extension of inner lead 17
Are provided alternately for each adjacent inner lead 17, and a solder resist 18 is provided on the back surface of the package only at a portion to be a connection terminal portion, and a solder land 19 is provided at the opening. I do. Using a thin material such as 0.1 mm in thickness for the lead frame material, QFN could not cover 100
The area larger than the pins can be realized at a low cost and in a small size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of semiconductor packages, and more specifically, a resin in which a semiconductor element is mounted on a lead frame and the outer periphery thereof, particularly the upper surface side of the semiconductor element, is sealed with a molding resin. The present invention relates to a sealed semiconductor package.

[0002]

2. Description of the Related Art In recent years, along with the trend toward higher performance and miniaturization of electronic equipment, semiconductor packages used therein are also required to be miniaturized. Recently, in order to secure the space of the board on which electronic parts are mounted, downsizing including the footprint is progressing, and QFN (Quad Flat
Semiconductor packages such as non-leaded packages) have been mass-produced. This is considered to be one of the reasons why the mass production of the packaged type enables assembly at a cost equal to or lower than that of the conventional QFP (QuadFlat Package). Further, the area of the organic substrate, which has been frequently used, tends to be replaced. FIG. 1 is a sectional view showing the structure of this QFN. In FIG. 1, 1 is a lead frame, 2 is a semiconductor element mounted on a die pad, 3 is a bonding wire, 4 is a sealing resin, and 5 is a solder land.

However, when the number of pins exceeds 100,
In the case of the QFN structure, since the package size is large and the chip size is smaller than that, the bonding wire becomes long, and there is a problem that the resin sealing cannot be performed well. On the other hand, multi-row external terminals have been proposed, and at present, L is a package having a QFN structure of two-row or three-row arrangement.
Development of LGA (Leadflame Land Grid Array) is under consideration. FIG. 2 is a sectional view showing the structure of a LLGA having a two-row arrangement.

[0004]

By adopting a thin lead frame, the design rule of the lead frame tends to become finer. However, with the QFN, the lead frame has a thickness of 0.2 mm. Since the reason for using the above material is the adhesiveness between the sealing resin and the individualized terminals, the plate thickness cannot be reduced. That is, by making the cross-sectional shape of the lead frame terminal an inverted trapezoidal shape, the adhesion with the sealing resin is improved, and the QFN
Although the connection strength is maintained when the board is mounted on the board, if a material having a plate thickness of 0.15 mm or 0.125 mm is used, the material plate thickness is thin, no matter how much the cross-sectional shape is maintained in an inverted trapezoidal shape. Since the strength of the taper part of the cross section is weak and only the terminal remains on the board side and the resin side falls off after connecting the QFN to the board, the material plate thickness of the lead frame could not be thinned with the QFN. .

On the other hand, even if multiple rows of external terminals are implemented, the conventional Q
With FN, it was possible to manufacture a terminal pitch up to 0.4 mm, but now it is 0.65 mm pitch. The effect of reducing the package size is not so great, and when the number of pins increases, the problem of wire length cannot be solved.

Further, a QFN structure in which the inner leads are laid out by half etching as shown in FIG. 3 has also been studied. However, when a material having a plate thickness of 0.2 mm is used for the lead frame, the tip pitch is 0. The limit is 28 mm. Further, as described above, there is a problem that the design rule cannot be revised by reducing the material plate thickness of the lead frame.

The present invention has been made in view of the above problems, and an object thereof is to use a lead frame having a thinner plate thickness than that of a conventional one, but at a low cost and in a multi-pin area. To provide a semiconductor package.

[0008]

To achieve the above object, a semiconductor package of the present invention is a semiconductor package mounted on a die pad supported by suspension leads of a lead frame, and electrodes on the upper surface of the semiconductor chip. In a semiconductor package including a wire that electrically connects the tip of the inner lead of the lead frame and a sealing resin that seals the surrounding area of the semiconductor element including the wire, on the extension of the inner lead, The bulging portions that will be the connection terminals are provided alternately for each adjacent inner lead, and the solder resist that opens only at the portions that will be the connection terminals is provided on the back surface of the package, and the solder lands are provided in the openings. It is characterized by

The semiconductor package having the above structure is
Prepare a lead frame in which swelling parts that will be connection terminals are provided alternately on the extension of the inner lead for each inner lead, and after the resin burr prevention tape is attached to the back surface of the lead frame, , Mounting a semiconductor element on the die pad, wire-bonding the electrode on the upper surface of the semiconductor element and the tip of the inner lead, and then collectively molding those semiconductor elements on one side,
After peeling off the tape on the back side, an opening is formed on the exposed back side only with the solder resist where it will become the connection terminal part, solder plating is performed there to form solder lands, and then multiple semiconductor packages are formed by dicing. It can be manufactured by dividing into.

[0010]

FIG. 4 is a schematic cross-sectional view showing the structure of a semiconductor package according to the present invention, and FIG. 5 is a partially enlarged plan view of a lead frame used for manufacturing this semiconductor package. .

As shown, the semiconductor package is
The semiconductor element 13 mounted on the die pad 12 supported by the suspension lead 11 of the lead frame 10, the wire 15 electrically connecting the electrode on the upper surface of the semiconductor element 13 and the inner lead tip portion 14, and the wire 15 Sealing resin 1 obtained by sealing the surrounding area of the semiconductor element 13 including
6 and.

As shown in FIG. 5, bulging portions 17a serving as connection terminals are provided on the inner leads 17 in a staggered manner so as to alternate between the adjacent inner leads 17. In addition, a solder resist 18 is provided on the back surface of the package, the solder resist 18 having openings only at portions to be connection terminals, and solder lands 19 to be substrate connection terminals are provided at the openings.

Next, the manufacturing procedure of the semiconductor package having such a structure will be described with reference to specific examples.

First, a lead frame having a design as shown in FIG. 5 is etched using a material having a plate thickness of 0.1 mm (for example, "EFTEC64T" manufactured by Furukawa Electric Co., Ltd.). That is, a lead frame in which bulged portions 17a serving as connection terminals are provided on the extension of the inner leads 17 alternately for each inner lead is prepared. At that time, in order to have an anchor effect with the sealing resin as much as possible, it is preferable to perform etching by tapering so that the flat width of the back surface is wider than the front surface.

Next, a resin burr-preventing tape (for example, "TRM625 manufactured by Nitto Denko Corporation" is formed on the back surface of the lead frame.
0 "), the semiconductor element 13 is placed on the die pad 12 and die-bonded, and then the electrode on the upper surface of the semiconductor element 13 and the routed inner lead tip 14 are wire-bonded. At this time, the wire length was 3 mm in the case of the LLGA structure in which the inner leads in the two-row arrangement were not routed, but the wire length could be set to 1 mm in the package structure of the present invention.

Then, one side is collectively sealed with the sealing resin 16, and the resin burr-preventing tape on the back side is peeled off. After peeling off the tape in this way, apply a photo-curable solder resist to the exposed back surface all at once using the printing method, perform exposure and subsequent development, and open openings only in the areas corresponding to the connection terminals. Then, solder plating is applied to the openings to form solder lands 19 as board connecting terminals. Subsequently, the resultant was attached to a dicing tape for dicing, batch testing was performed, and then irradiation with ultraviolet rays was performed to perform individualization.

As described above, by using a thin material for forming the connection terminal, the design rule can be further refined without the need for half etching, and the lead frame which becomes a problem at this time can be obtained. Regarding the adhesion with the encapsulation resin, it is possible to prevent the lead frame from falling off by protecting the back surface of the semiconductor package molded on one side with a solder resist. You can The obtained semiconductor package is a good one that does not have a short circuit due to wire flow such as resin encapsulation because only the board connecting terminals are exposed and the bonding wires are short without exposing the inner lead routing on the back surface. Becomes

Since the lead frame is made of a material having a plate thickness of 0.1 mm, the tip pitch of the inner leads can be 0.15 mm. Since the tip pitch depends on the plate thickness of the lead frame, if the chip size is large, 0.125 material or 0.15 material may be used. However, the limit of the tip pitch of each inner lead is 0.16m.
m and 0.18 mm.

Although the embodiments of the present invention have been described in detail above, the semiconductor package and the method for manufacturing the same according to the present invention are not limited to the above embodiments, and do not depart from the spirit of the present invention. It goes without saying that various changes can be made in the range.

[0020]

As described above, the semiconductor package of the present invention uses the lead frame in which the bulging portions serving as connection terminals are alternately provided on the extension of the inner leads for every adjacent inner leads. By using a thin material such as a plate thickness of 0.1 mm for the lead frame material, the region of 100 pins or more, which cannot be covered by the QFN, can be realized at low cost and in a small size. In addition, the inner lead routing is not exposed on the back surface of the package, only the substrate connecting terminals are exposed, and the bonding wire is short, so a good semiconductor package free from short circuits due to wire flow during resin sealing can be obtained. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a conventional semiconductor package QFN.

FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor package LLGA.

FIG. 3 is a cross-sectional view showing a structure of a QFN having a structure in which inner leads are routed by half etching.

FIG. 4 is a schematic cross-sectional view showing the structure of a semiconductor package according to the present invention.

5 is a partially enlarged plan view showing a lead frame used for manufacturing the semiconductor package of FIG.

[Explanation of symbols]

10 lead frame 11 hanging lead 12 die pad 13 Semiconductor elements 14 Inner lead tip 15 wires 16 Sealing resin 17 Inner lead 18 Solder resist 19 Handa Land

Claims (2)

[Claims] 1. A semiconductor element mounted on a die pad supported by suspension leads of a lead frame, a wire electrically connecting an electrode on an upper surface of the semiconductor element and a tip of an inner lead of the lead frame, and a wire. In a semiconductor package provided with a sealing resin that seals the surrounding area of a semiconductor element including, a bulge portion that serves as a connection terminal is provided alternately on the extension of the inner lead for each adjacent inner lead. In addition, the semiconductor package is characterized in that a solder resist is provided on the back surface of the package, the solder resist opening only at the connection terminal portion, and the solder land is provided in the opening. 2. The method of manufacturing a semiconductor package according to claim 1, wherein a lead frame is provided in which swelled portions serving as connection terminals are alternately provided on adjacent inner leads on the extension of the inner leads. , With the tape for resin burr prevention attached to the back surface of the lead frame, mount the semiconductor element on the die pad, wire bond the electrode on the upper surface of the semiconductor element and the inner lead tip, and then After molding the semiconductor element on one side at once and peeling off the tape on the back side, form an opening on the exposed back side only with the solder resist where it will become the connection terminal part, and then perform solder plating and form the solder land. A method of manufacturing a semiconductor package, characterized by dividing the semiconductor package into a plurality of semiconductor packages by dicing.