JP2003179211A - Ferroelectric nonvolatile semiconductor memory and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A method for manufacturing a ferroelectric nonvolatile semiconductor memory having high reliability is provided. A method of manufacturing a ferroelectric nonvolatile semiconductor memory includes the steps of (a) selecting a transistor TR on a semiconductor substrate 10;
And forming the insulating layer 17 on the entire surface, and then forming one of the source / drain regions 1 of the selection transistor TR.
Forming an opening 18 in the portion of the insulating layer 17 above 5B, and (c) plugging a plug 19 made of a platinum group metal or an alloy thereof excluding Os based on a plating method.
And (d) forming a first electrode 21, a ferroelectric layer 22, and a second electrode 23 on the insulating layer 17, and the first electrode 21 is connected to the plug 19. Forming a memory cell MC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric non-volatile semiconductor memory (so-called FERAM) and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, much research has been conducted on large-capacity ferroelectric non-volatile semiconductor memories. A ferroelectric non-volatile semiconductor memory (hereinafter, may be abbreviated as a non-volatile memory) can be accessed at high speed and
It is non-volatile, small in size, low in power consumption, and resistant to shocks. It is expected to be used as a storage device or a recording medium for recording audio and video.

This non-volatile memory utilizes a high-speed polarization reversal of a ferroelectric thin film and its residual polarization to detect a change in the amount of accumulated charge in a capacitor section having a ferroelectric layer.
It is a high-speed rewritable non-volatile memory, and basically includes a memory cell (capacitor portion) and a selection transistor. Memory cell (capacitor section)
Is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between these electrodes. Writing and reading of data in this non-volatile memory is performed by using FIG.
This is performed by applying the PE hysteresis loop of the ferroelectric substance shown in FIG. That is, when the external electric field is removed after the external electric field is applied to the ferroelectric layer, the ferroelectric layer exhibits remanent polarization. The remanent polarization of the ferroelectric layer becomes + P _r when an external electric field in the positive direction is applied, and −P _r when an external electric field in the negative direction is applied. Here, the case where the remanent polarization is + P _r (see “D” in FIG. 35) is “0”, and the case where the remanent polarization is −P _r (see “A” in FIG. 35) is “1”. And

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state of "C" in FIG. At this time, if the data is "0", the polarization state of the ferroelectric layer changes from "D" to "C". On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is "0", polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is "1", polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cell (capacitor section). By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 35 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is once destroyed. Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written again.

Usually, the selection transistor is formed on a semiconductor substrate, the memory cell is formed on an insulating layer, and the lower electrode is connected to one source / drain region of the selection transistor through a plug. There is. The plug usually has an opening formed in the insulating layer above one of the source / drain regions of the selection transistor, and is formed by chemical vapor deposition (CVD) on the insulating layer including the inside of the opening. For example, a tungsten layer is formed and then the tungsten layer over the insulating layer is removed.

As a ferroelectric material forming the ferroelectric layer, an oxide having a perovskite structure [eg,
Pb (Zr, Ti) O ₃ , (Ba, Sr) TiO ₃ etc.]
Or an oxide having a bismuth-based layered perovskite structure [eg, Bi ₂ Sr (Ta, Nb) ₂ O ₉ , (Bi, L
a) ₄ Ti ₃ O ₁₂ etc.] is used. Then, in order to obtain good characteristics, it is necessary to perform oxidation heat treatment at a high temperature to form a ferroelectric layer having no oxygen deficiency.

[0007]

When forming a plug made of tungsten by the CVD method, a large amount of hydrogen gas is used. Therefore, depending on the structure of the non-volatile memory, the oxide as the ferroelectric material forming the ferroelectric layer is exposed to the hydrogen gas atmosphere to be reduced, and the ferroelectric characteristics are deteriorated or the ferroelectric material is damaged. There is a problem that the dielectric layer peels off. There is also a problem that the plug made of tungsten is oxidized by the oxidation heat treatment in the oxygen gas atmosphere. Further, when the oxidation heat treatment is performed, there is a problem that the atoms of the material forming the lower electrode and the atoms of the conductive material forming the plug (for example, tungsten atoms) mutually diffuse. Then, when these phenomena occur, the reliability of the non-volatile memory is deteriorated and conduction failure is caused.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems and to provide a highly reliable ferroelectric non-volatile semiconductor memory and a manufacturing method thereof.

[0009]

A method of manufacturing a ferroelectric non-volatile semiconductor memory according to a first aspect of the present invention for achieving the above object comprises (a) forming a selection transistor on a semiconductor substrate. And (b) forming an insulating layer over the entire surface, and then forming an opening in the insulating layer above one of the source / drain regions of the selecting transistor, and (c) platinum, iridium, or palladium. Forming a plug made of a metal selected from the group consisting of rhodium and ruthenium or an alloy thereof in the opening by a plating method; and (d) forming a first electrode and a ferroelectric on the insulating layer. A layer and a second electrode, the first electrode forming a memory cell connected to the plug.

A second aspect of the present invention for achieving the above object.
The method for manufacturing a ferroelectric non-volatile semiconductor memory according to the aspect (1) comprises (A) a bit line, (B) a selection transistor, and (C) M memory cells (where M ≧ 2). A memory unit and (D) M plate lines, each memory cell including a first electrode, a ferroelectric layer, and a second electrode, and in the memory unit, the first electrode of the memory cell. Are common, and the common first electrode is
It is connected to the bit line, and in the memory unit,
The second electrode of the m-th (where m = 1, ..., M) memory cell is the manufacturing method of the ferroelectric non-volatile semiconductor memory connected to the m-th plate line. And (a) a step of forming a selection transistor on a semiconductor substrate, and (b) a lower insulating layer is formed on the entire surface, and then a connection hole is formed on one of the source / drain regions of the selection transistor on the lower insulating layer. A step of forming a bit line electrically connected through the insulating layer, and (c) forming an upper insulating layer on the entire surface, and then forming the upper insulating layer and the lower insulating layer above the other source / drain region of the selecting transistor. A step of forming an opening in a portion of the layer, and (d) forming a plug made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof in the opening by plating. And that step, characterized by comprising the steps of forming a (e) the upper layer insulating layer, a memory unit common first electrode is connected to the plug.

A third aspect of the present invention for achieving the above object.
In the method for manufacturing a ferroelectric non-volatile semiconductor memory according to this aspect, (A) a bit line, (B) a selection transistor, and (C) each of M memory cells (where M ≧ 2) are configured. N (where N ≧ 2) memory units and (D) M × N plate lines, the N memory units are stacked via an interlayer insulating layer. The memory cell includes a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first electrode of the memory cell is common, and the common first electrode is
It is connected to the bit line through the plug, the selection transistor, and the connection hole, and the nth layer (where n = 1, 2 ,.
.., N), the second electrode of the m-th (where m = 1, 2 ..., M) memory cell is the [(n-1) M + m] -th plate line. A method of manufacturing a ferroelectric non-volatile semiconductor memory connected to, comprising: (a) a step of forming a selection transistor on a semiconductor substrate; and (b) a lower insulating layer formed on the entire surface and then the lower insulating layer. One of the sources of the selection transistor on the layer /
Forming a bit line electrically connected to the drain region through a connection hole; and (c) forming an upper insulating layer over the entire surface and then forming the upper layer above the other source / drain region of the selecting transistor. First in the insulating layer and the lower insulating layer
Forming the opening of the first layer, and (d) forming a plug of the first layer made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof by a plating method. A step of forming in the opening of the first layer, and (e) forming a memory unit of the first layer in which the common first electrode is connected to the plug of the first layer on the upper insulating layer. And (f)
The n'th layer (where n '= 1, 2, ..., N-
1) forming an interlayer insulating layer, forming an opening of the (n ′ + 1) th layer in the n′th interlayer insulating layer, and selecting from the group consisting of platinum, iridium, palladium, rhodium and ruthenium. A plug of the (n '+ 1) th layer, which is made of a metal or an alloy thereof and is electrically connected to the plug of the nth'th layer, in the opening of the (n' + 1) th layer by plating. , The common first electrode is connected to the (n ′ + 1) th layer plug on the (n ′ + 1) th layer interlayer insulating layer.
1) In the step of forming the memory unit of the first layer, n ′ is set to 1
It is characterized by repeating from 1 to (N-1) while incrementing by one.

A fourth aspect of the present invention for achieving the above object.
In the method for manufacturing a ferroelectric non-volatile semiconductor memory according to the above aspect, (A) bit lines and (B) N pieces (however, N ≧ 2)
Selection memory transistors, and (C) N memory units each composed of M memory cells (where M ≧ 2), and (D) M plate lines. Is composed of a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first electrode of the memory cell is common and the n-th (where n = 1, 2 ,.
.., N), the common first electrode in the memory unit is connected to the bit line through the plug, the nth selection transistor, and the connection hole, and in the nth memory unit, m-th (however, m = 1, 2 ...
, M) the second electrode of the memory cell is connected to the m-th plate line common to the memory units. A step of forming N selection transistors on the semiconductor substrate, and (b) forming a lower insulating layer on the entire surface,
A step of forming a bit line electrically connected to one source / drain region of each selection transistor through a connection hole on the lower insulating layer; and (c) after forming an upper insulating layer on the entire surface. A step of forming an opening in the upper insulating layer and the lower insulating layer above the other source / drain region of each selection transistor, and (d) platinum, iridium,
It is made of a metal selected from the group consisting of palladium, rhodium and ruthenium or an alloy thereof, and the nth plug is the other source / source of the nth selection transistor.
A step of forming a plug connected to the drain region in the opening by plating, and (e) an n-th plug in which a common first electrode is connected to the n-th plug on the upper insulating layer. Forming a second memory unit.

A fifth aspect of the present invention for achieving the above object.
In the method for manufacturing a ferroelectric non-volatile semiconductor memory according to the above aspect, (A) bit lines and (B) N pieces (however, N ≧ 2)
Selection memory transistors, and (C) N memory units each including M memory cells (where M ≧ 2), and (D) M plate lines.
The individual memory units are stacked via an interlayer insulating layer, and each memory cell includes a first electrode, a ferroelectric layer, and a second electrode.
In each memory unit, the first electrode of the memory cell is common, and the n-th layer (where n =
1, 2, ..., N), the common first electrode in the memory unit is connected to the bit line through the plug, the nth selection transistor, and the connection hole. In the memory unit, the m-th (however, m =
The second electrode of each of the memory cells 1, 2, ..., M) is a method for manufacturing a ferroelectric non-volatile semiconductor memory in which the second electrode is connected to the m-th plate line common to the memory units. (A) a step of forming N selection transistors on the semiconductor substrate, and (b) after forming a lower insulating layer on the entire surface, one source / drain of each selection transistor is formed on the lower insulating layer. Forming a bit line electrically connected to the region through a connection hole; and (c) forming an upper insulating layer on the entire surface, and then forming the upper layer above the other source / drain region of each selection transistor. A step of forming a first-layer opening in the insulating layer and the lower insulating layer, and (d)
A first layer made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, wherein the nth plug is connected to the other source / drain region of the nth selection transistor. A step of forming an eye plug in the opening of the first layer by a plating method, and (e) a common first layer on the upper insulating layer.
Forming the memory unit of the first layer connected to the first plug of the first layer, and (f) the n'th layer (however, n '= 1, 2 ・
.., N-1) interlayer insulating layers are formed, and (N-n ') th (n' + 1) th opening portions are formed in the n'th interlayer insulating layer. A metal selected from the group consisting of iridium, palladium, rhodium and ruthenium, or an alloy thereof, and the second to (N−n ′ + 1) th n′th layers
Each of the first to (N-n ') th plugs of the (n' + 1) th layer electrically connected to each of the plugs up to the (n'th) th plug-
After being formed in the opening of the +1) th layer, the common first electrode is connected to the first plug of the (n ′ + 1) th layer on the n′th interlayer insulating layer. The step of forming the memory unit of the (n ′ + 1) th layer is
It is characterized in that n'is repeated while incrementing by 1 from 1 to (N-1).

A sixth aspect of the present invention for achieving the above object.
A method of manufacturing a ferroelectric non-volatile semiconductor memory according to the above aspect, comprises (A) N (where N ≧ 2) bit lines,
(B) N selection transistors and (C) each of M memory cells (where M ≧ 2)
Memory units and (D) M plate lines, N memory units are stacked via an interlayer insulating layer, and each memory cell has a first electrode and a ferroelectric layer. And a second electrode, the first electrode of the memory cell is common in each memory unit, and is common in the memory unit of the nth layer (where n = 1, 2, ..., N). The first electrode is connected to the nth bit line through the plug, the nth selection transistor, and the connection hole, and in the nth layer memory unit,
The second electrode of the m-th (where m = 1, 2, ..., M) memory cell has the second m-th electrode common to the memory units.
A method of manufacturing a ferroelectric non-volatile semiconductor memory connected to a th plate line, comprising: (a) forming N selection transistors on a semiconductor substrate; and (b) forming a lower insulating layer on the entire surface. After the formation, the n-th layer is formed on the lower insulating layer.
A step of forming an nth bit line electrically connected to one of source / drain regions of the th select transistor through a connection hole; and (c) forming an upper insulating layer over the entire surface, Forming a first layer opening in the upper insulating layer and lower insulating layer above the other source / drain region of the selection transistor; and (d) from platinum, iridium, palladium, rhodium and ruthenium. A first layer plug made of a metal or an alloy thereof selected from the group consisting of an nth plug connected to the other source / drain region of the nth selection transistor;
A step of forming in the opening of the first layer based on a plating method, and (e) a common first electrode is connected to the first plug of the first layer on the upper insulating layer. A step of forming a first-layer memory unit, and (f)
The n'th layer (where n '= 1, 2, ..., N-
1) The interlayer insulating layer is formed, and (N-n ') th (n' + 1) th opening is formed in the n'th interlayer insulating layer, and platinum, iridium, palladium, and rhodium are formed. And a metal selected from the group consisting of ruthenium or an alloy thereof, and the second to the (N−n ′ + 1) th n′th layer
Each of the first to (N-n ') th plugs of the (n' + 1) th layer electrically connected to each of the plugs up to the (n'th) th plug-
After being formed in the opening of the +1) th layer, the common first electrode is connected to the first plug of the (n ′ + 1) th layer on the n′th interlayer insulating layer. The step of forming the memory unit of the (n ′ + 1) th layer is
It is characterized in that n'is repeated while incrementing by 1 from 1 to (N-1).

A first aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) a selection transistor formed on a semiconductor substrate,
(B) is formed on an insulating layer and includes a first electrode, a ferroelectric layer, and a second electrode, and the first electrode is connected to one source / drain region of the selection transistor via a plug. A ferroelectric non-volatile semiconductor memory composed of: It is characterized by being formed.

Second aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) bit line, (B) selection transistor,
(C) A memory unit composed of M (M ≧ 2) memory cells, and (D) M plate lines, each memory cell including a first electrode and a ferroelectric layer. A second electrode, the first electrode of the memory cell is common in the memory unit, and the common first electrode is connected to the bit line through the plug, the selection transistor, and the connection hole. In the memory unit, the second memory cell of the m-th memory cell (where m = 1, 2, ..., M)
Is a ferroelectric non-volatile semiconductor memory connected to the m-th plate line, and the plug is
It is characterized in that it is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, and is formed by a plating method.

A third aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) bit line, (B) selection transistor,
(C) Each is composed of N (however, N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells, and (D) M × N plate lines, N memory units are stacked via an interlayer insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first electrode of the memory cells is common, and the common first electrode is a plug. , The n-th layer (where n = 1, 2, ...
., N) memory unit, m-th (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A ferroelectric non-volatile semiconductor memory connected to the [(n-1) M + m] th plate line, wherein the plug is a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium. Alternatively, it is made of an alloy thereof and is formed by a plating method.

A fourth aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) each for M (where M ≧)
2) N memory units composed of memory cells and (D) M plate lines, each memory cell comprising a first electrode, a ferroelectric layer and a second electrode. In each memory unit, the first electrode of the memory cell is common, and the n-th (where n = 1, 2, ...,
The common first electrode in the memory unit N) is connected to the bit line via the plug, the n-th selection transistor, and the connection hole, and is connected to the m-th (n-th) memory unit. However, m = 1, 2 ...
The second electrode of the memory cell of M) is a ferroelectric non-volatile semiconductor memory connected to the m-th plate line common to the memory units, and the plug is platinum, iridium, It is characterized in that it is made of a metal selected from the group consisting of palladium, rhodium and ruthenium or an alloy thereof, and is formed by a plating method.

In the ferroelectric non-volatile semiconductor memory according to the fourth aspect of the present invention, the N memory units may be formed on the same insulating layer or may be laminated via an interlayer insulating layer. May be.

A fifth aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells, N memory units and (D) M plate lines,
The individual memory units are stacked via an interlayer insulating layer, and each memory cell includes a first electrode, a ferroelectric layer, and a second electrode.
In each memory unit, the first electrode of the memory cell is common, and the n-th layer (where n =
1, 2, ..., N), the common first electrode is connected to the nth bit line through the plug, the nth selection transistor, and the connection hole, In the memory unit of the n-th layer, the second electrode of the m-th (where m = 1, 2 ..., M) memory cell is connected to the m-th plate line common to the memory units. A connected ferroelectric non-volatile semiconductor memory, wherein the plug is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, and is formed by a plating method. It is characterized by

A method of manufacturing a ferroelectric non-volatile semiconductor memory according to any one of the first to sixth aspects of the present invention, or a ferroelectric non-volatile according to any one of the first to fifth aspects of the present invention. A combination of electroless plating, seed layer formation, and electroplating may be mentioned as a plating method for a semiconductor memory (hereinafter, these may be collectively referred to simply as the present invention). Here, examples of the method for forming the seed layer include an electroless plating method, a physical vapor deposition method (PVD method) including a sputtering method, an evaporation method, and the like, and a chemical vapor deposition method (CVD method).

A method for manufacturing a ferroelectric non-volatile semiconductor memory according to the second to sixth aspects of the present invention, or a ferroelectric non-volatile according to the second to fifth aspects of the present invention. In the semiconductor memory, it is sufficient to satisfy M ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...) Can be cited. Further, the method for manufacturing a ferroelectric non-volatile semiconductor memory according to the third to sixth aspects of the present invention, or the ferroelectric non-volatile semiconductor according to the third to fifth aspects of the present invention. In the memory, it is only necessary to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2, 4, 8, ...
・ ・) Can be mentioned.

The method of manufacturing a ferroelectric non-volatile semiconductor memory according to the third, fifth and sixth aspects of the present invention, or the third and fourth aspects of the present invention are preferable. In the ferroelectric non-volatile semiconductor memory according to the fifth aspect, the memory unit has a three-dimensional laminated structure, so that the number of transistors occupying the surface of the semiconductor substrate is not restricted and the conventional ferroelectric The storage capacity can be dramatically increased as compared with the dielectric type nonvolatile semiconductor memory, and the effective occupied area of the bit storage unit can be significantly reduced.

The method for manufacturing a ferroelectric non-volatile semiconductor memory according to the second to sixth aspects of the present invention, or the ferroelectric non-volatile according to the second to fifth aspects of the present invention. Further, in the semiconductor memory, it is preferable that the address selection in the row direction is performed by a two-dimensional matrix composed of selection transistors and plate lines. For example, eight selection transistors and a plate line 8
If a row address selection unit is configured with a book, 16 decoder / driver circuits can select, for example, 64-bit or 32-bit memory cells.
Therefore, the storage capacity can be quadrupled or doubled even if the degree of integration of the ferroelectric non-volatile semiconductor memory is the same as the conventional one. In addition, the number of peripheral circuits and drive wiring in address selection can be reduced.

A method for manufacturing a ferroelectric non-volatile semiconductor memory according to the third, fifth and sixth aspects of the present invention, or preferably the third and fourth aspects of the present invention. In the ferroelectric non-volatile semiconductor memory according to the third aspect, the crystallization temperature of the ferroelectric layer forming the memory cell of the memory unit located above is higher than that of the memory cell of the memory unit located below. It is preferably lower than the crystallization temperature of the constituent ferroelectric layer. Here, the crystallization temperature of the ferroelectric layer forming the memory cell is
For example, it can be examined using an X-ray diffractometer or a surface scanning electron microscope. Specifically, for example, after the ferroelectric material layer is formed, the heat treatment temperature for performing crystallization of the ferroelectric material layer is variously changed to perform heat treatment for promoting crystallization, and The crystallization temperature of the ferroelectric layer can be obtained by performing X-ray diffraction analysis of the body material layer and evaluating the diffraction pattern intensity (diffraction peak height) peculiar to the ferroelectric material.

By the way, when a ferroelectric non-volatile semiconductor memory having a structure in which memory units are stacked is manufactured, it is necessary to crystallize a ferroelectric layer or a ferroelectric thin film constituting the ferroelectric layer. , Heat treatment (referred to as crystallization heat treatment) must be performed for the number of stacked memory units. Therefore, the lower memory unit is subjected to the crystallization heat treatment for a longer time, and the upper memory unit is subjected to the crystallization heat treatment for a shorter time. Therefore, when the optimum crystallization heat treatment is performed on the memory unit located on the upper stage, the memory unit located on the lower stage may be subjected to an excessive heat load, and the characteristics of the memory unit located on the lower stage may deteriorate. There is. Although it is possible to perform a crystallization heat treatment at once after manufacturing a multi-stage memory unit, a large volume change occurs in the ferroelectric layer during crystallization, and degassing from each ferroelectric layer occurs. It is likely to occur, and problems such as cracks and peeling of the ferroelectric layer are likely to occur. If the crystallization temperature of the ferroelectric layer forming the memory unit located above is set lower than the crystallization temperature of the ferroelectric layer forming the memory unit located below, only the number of stacked memory units will be increased. Even if the crystallization heat treatment is performed, there is no problem such as characteristic deterioration of the memory cells forming the memory unit located below. Further, the crystallization heat treatment under the optimum conditions can be performed on the memory cells forming the memory unit in each stage, and the ferroelectric non-volatile semiconductor memory having excellent characteristics can be obtained. Table 1 below shows crystallization temperatures of typical materials constituting the ferroelectric layer.
The material forming the ferroelectric layer is not limited to such a material.

[Table 1] Material name Crystallization temperature Bi ₂ SrTa ₂ O ₉ 700 to 800 ° C Bi ₂ Sr (Ta _1.5 , Nb _0.5 ) O ₉ 650 to 750 ° C Bi ₄ Ti ₃ O ₁₂ 600 to 700 ° _{C Pb (Zr 0.48, Ti 0.52} ) O 3 550~650 ° C PbTiO ₃ 500 to 600 ° C

Examples of the material constituting the ferroelectric layer in the present invention include a bismuth layered compound, more specifically, a Bi type layered structure perovskite type ferroelectric material. The Bi-based layered structure perovskite type ferroelectric material belongs to a so-called non-stoichiometric compound, and is tolerant of composition shifts at both sites of a metal element and an anion (O etc.) element. In addition, it is not uncommon to show optimum electrical characteristics when the composition deviates slightly from the stoichiometric composition. The Bi-based layered structure perovskite type ferroelectric material can be represented by, for example, the general formula (Bi ₂ O ₂ ) ²⁺ (A _m-1 B _m O _{3m + 1} ) ^2- . Here, “A” means Bi, Pb, Ba, Sr,
Represents one kind of metal selected from the group consisting of metals such as Ca, Na, K and Cd, and “B” represents Ti, Nb,
It represents a combination of one kind or a plurality of kinds selected from the group consisting of Ta, W, Mo, Fe, Co and Cr at an arbitrary ratio. Further, m is an integer of 1 or more.

Alternatively, the material forming the ferroelectric layer is (Bi _X , Sr _1-X ) ₂ (Sr _Y , Bi _1-Y ) (Ta _Z , Nb _1-Z ) ₂ O _d formula (1 (However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0
≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) is preferably contained as the main crystal phase. Alternatively, the material forming the ferroelectric layer is Bi _X Sr _Y Ta ₂ O _d formula (2) (where X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d
It is preferable that the crystal phase represented by ≦ 9.3) is contained as a main crystal phase. In these cases, the crystal phase represented by the formula (1) or (2) is used as the main crystal phase.
% Or more is more preferable. The formula (1)
In the meaning, (Bi _X , Sr _1-X ) means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). . Further, the meaning of (Sr _Y , Bi _{1 -Y} ) means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). . Examples of the material forming the ferroelectric layer containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include Bi oxide, Ta or Nb oxide, and Bi, Ta or Nb oxide. In some cases, a small amount of complex oxide may be contained.

Alternatively, the material forming the ferroelectric layer is as follows: Bi _X (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d Formula (3) (where 1.7 ≦ X ≤2.5, 0.6≤Y≤1.2,0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) may be included. In addition, "(Sr, Ca, Ba)"
Means one kind of element selected from the group consisting of Sr, Ca and Ba. If the composition of the material constituting the ferroelectric layer represented by each of these formulas is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ (strontium bismuth tantalate), Bi ₂ SrNb ₂ O ₉ ( Strontium bismuth niobate), Bi ₂ BaTa ₂ O ₉ (barium bismuth tantalate), Bi ₂ BaNb ₂ O ₉ (barium bismuth niobate), Bi ₂ Sr (Ta, Nb) ₂ O
₉ (strontium bismuth tantalate niobate) and the like. Alternatively, as the ferroelectric material, Bi ₄ SrTi ₄ O ₁₅ (strontium bismuth titanate), Bi ₃ TiNbO ₉ (bismuth titanium niobate), Bi ₃ TiTaO ₉ (bismuth titanium tantalate), Bi ₄ Ti ₃ O _{12 is used.} (Bismuth titanate), (Bi,
La) ₄ Ti ₃ O ₁₂ (lanthanum bismuth titanate), Bi
₂ PbTa ₂ O ₉ (lead bismuth tantalate) and the like can be exemplified, but in these cases, the ratio of each metal element can be changed to the extent that the crystal structure does not change.
That is, there may be a compositional shift at both the metal element and oxygen element sites.

Alternatively, as the ferroelectric material, PbT
iO ₃ (lead titanate), BaTiO ₃ (barium titanate), LiNbO ₃ (lithium niobate), LiTaO ₃
(Lithium tantalate), YMnO ₃ (yttrium manganate), PbZrO having a perovskite structure
₃ and lead zirconate titanate is a solid solution of _{PbTiO 3 [PZT, Pb (Zr} 1-y, Ti y) O 3 ( where, 0 <y
<1)], P which is a metal oxide obtained by adding La to PZT
LZT [(Pb, La) (Zr, Ti) O ₃ (lead lanthanum zirconate titanate)] or PZT, a metal oxide obtained by adding Nb to PZT, or a metal oxide obtained by adding strontium (Sr) to PZT. PSZT which is
[(Pb, Sr) (Zr _X , Ti _Y ) O ₃ ], and a mixture thereof can be mentioned.

In the materials constituting the ferroelectric layer explained above, the crystallization temperature can be changed by removing these compositions from the stoichiometric composition.

In order to obtain the ferroelectric layer, the ferroelectric thin film may be patterned in a step after the ferroelectric thin film is formed. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film is formed by, for example, MOCVD method, MOD (Metal Organic Decomposition) method using a bismuth organic metal compound (bismuth alkoxide compound) having a bismuth-oxygen bond as a raw material,
LSMCD (Liquid Source Mist Chemical Depositio)
n) method, pulse laser ablation method, sputtering method, sol-gel method or the like, which is suitable for the material forming the ferroelectric thin film. The ferroelectric thin film can be patterned by, for example, anisotropic ion etching (RIE) method.

The method for manufacturing a ferroelectric non-volatile semiconductor memory according to the second to sixth aspects of the present invention, or the ferroelectric non-volatile according to the second to fifth aspects of the present invention. In a semiconductor memory, a first electrode is formed below a ferroelectric layer, and a second electrode is formed above the ferroelectric layer (that is, the first electrode corresponds to a lower electrode, Two
Of the electrode corresponds to the upper electrode),
A structure in which a first electrode is formed on the ferroelectric layer and a second electrode is formed under the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode corresponds to the lower electrode). (Corresponding to an electrode). The plate line preferably extends from the second electrode from the viewpoint of simplifying the wiring structure. As a structure in which the first electrode is common,
Specifically, a structure in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer and the second electrode corresponds to the memory cell. As a structure in which the first electrode is common, in addition, a structure in which each ferroelectric layer is formed in a predetermined region of the first electrode and a second electrode is formed on the ferroelectric layer, or Further, each first electrode is formed on a predetermined surface area of the wiring, and a ferroelectric layer is formed on each of the first electrodes,
A structure in which the second electrode is formed on the ferroelectric layer can be mentioned, but the structure is not limited to these.

Further, in the present invention, when the first electrode is formed below the ferroelectric layer and the second electrode is formed above the ferroelectric layer, the first electrode forming the memory cell is formed. Has a so-called damascene structure, and when the first electrode is formed on the ferroelectric layer and the second electrode is formed under the ferroelectric layer, a memory cell is formed. It is preferable that the second electrode has a so-called damascene structure from the viewpoint that the ferroelectric layer can be formed on a flat base.

In the present invention, the first electrode or the second electrode
Examples of the material forming the electrodes of Ir include Ir and IrO.
_2-X , IrO _2-X / Ir, SrIrO ₃ , Ru, Ru
_{O 2-X, SrRuO 3,} Pt, Pt / IrO 2-X, Pt /
RuO _2-X , Pd, Pt / Ti laminated structure, Pt / Ta
Laminated structure, Pt / Ti / Ta laminated structure, La _0.5 S
Examples thereof include r _0.5 CoO ₃ (LSCO), a Pt / LSCO laminated structure, and YBa ₂ Cu ₃ O ₇ . here,
The value of X is 0 ≦ X <2. In the laminated structure, the material described before “/” is in contact with the ferroelectric layer. The first electrode and the second electrode may be made of the same material, may be made of the same kind of material, or may be made of different kinds of materials. In order to form the first electrode or the second electrode, the conductive material layer is patterned in a step after forming the conductive material layer forming the first electrode or the conductive material layer forming the second electrode. do it. The conductive material layer can be formed by a method suitable for the material forming the conductive material layer, such as a sputtering method, a reactive sputtering method, an electron beam evaporation method, a MOCVD method, or a pulse laser ablation method. The patterning of the conductive material layer can be performed by, for example, the ion milling method or the RIE method. In some cases, the first electrode may be simultaneously formed by plating when forming the plug.

The selection transistor and various types of transistors can be composed of, for example, a well-known MIS type FET or MOS type FET. Examples of the material forming the bit line include polysilicon doped with impurities and a refractory metal material. The connection hole for connecting the selection transistor and the bit line can be obtained, for example, by burying a tungsten plug or impurity-doped polysilicon.

In the present invention, silicon oxide (SiO ₂ ), silicon nitride (SiN), SiON, SOG, NSG and BPS are used as materials for forming the insulating layer and the interlayer insulating layer.
G, PSG, BSG or LTO can be exemplified. Also, the memory cell may be covered with a hydrogen gas impermeable layer made of, for example, aluminum oxide (Al ₂ O ₃ ).

According to the present invention, one bit can be stored in each of a pair of memory cells that form a pair of ferroelectric non-volatile semiconductor memories and have a common plate line. In this case, for example, a pair of ferroelectric non-volatile semiconductor memories (for convenience, the non-volatile memory-
A, non-volatile memory-B), a pair of non-volatile memory-A and a non-volatile memory-B constituting the bit line,
The configuration may be such that they are connected to the same sense amplifier, but the configuration is not limited to this. Then, in this case, the selection transistor forming the non-volatile memory-A and the selection transistor forming the non-volatile memory-B are connected to different word lines. The non-volatile memory-A and the non-volatile memory-B are paired, and the selection transistor forming the non-volatile memory-A and the selection transistor forming the non-volatile memory-B are independently driven. 1-bit data is stored in each of the paired memory cells.

Alternatively, according to the present invention, a pair of ferroelectric non-volatile semiconductor memories are configured and one bit is complementarily stored in a pair of memory cells having a common plate line. can do. That is, a pair of ferroelectric non-volatile semiconductor memory (non-volatile memory-
A and non-volatile memory-B), a pair of non-volatile memory-
The bit lines forming A and the non-volatile memory-B may be connected to the same sense amplifier. In this case, the selection transistor forming the nonvolatile memory-A and the selection transistor forming the nonvolatile memory-B may be connected to the same word line or different word lines. It may have been done. However, in the latter case, the selection transistor forming the non-volatile memory-A and the selection transistor forming the non-volatile memory-B are simultaneously driven. Then, the nonvolatile memory-A and the nonvolatile memory-B are paired, and complementary data is stored in the paired memory cells.

In the present invention, since a plug made of a platinum group metal other than osmium (Os) or an alloy thereof is formed by a plating method, a highly reliable ferroelectric non-volatile semiconductor memory can be obtained. .

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings on the basis of an embodiment of the invention (hereinafter, simply referred to as an embodiment).

(Embodiment 1) Embodiment 1 relates to a ferroelectric non-volatile semiconductor memory (hereinafter, abbreviated as non-volatile memory) according to the first aspect of the present invention and a manufacturing method thereof. The non-volatile memory according to the first embodiment is a so-called stack non-volatile memory.

As shown in the schematic partial sectional view of FIG. 5, the nonvolatile memory according to the first embodiment has a selection transistor TR formed on a semiconductor substrate 10 made of a silicon semiconductor substrate and a memory cell MC. It consists of
Note that FIG. 5 shows two non-volatile memories. MOS
The selection transistor TR including a type FET includes a gate insulating film 12, a gate electrode 13, a gate sidewall 14, and source / drain regions 15A and 15B. The memory cell MC is formed on the insulating layer 17 that covers the selection transistor, and includes a first electrode 21, a ferroelectric layer 22, and a second electrode 23. The first electrode 21 is connected to one source / drain region 15B of the selection transistor via a plug 19 provided in the opening 18 formed in the insulating layer 17. The plug 19 is made of platinum (Pt), for example, and is formed by a plating method.

A circuit diagram of a memory array composed of a plurality of nonvolatile memories according to the first embodiment is illustrated in FIG. In this memory array, for example, one bit is complementary stored in two non-volatile memories forming a pair.
In addition, in FIG. 6, two nonvolatile memories forming a pair are surrounded by a dotted line. Each nonvolatile memory has, for example, selection transistors TR ₁₁ and TR ₁₂ , memory cells MC ₁₁ and MC ₁₂
It consists of In FIG. 6, reference numeral “WL” indicates a word line, reference numeral “BL” indicates a bit line, and reference numeral “PL” indicates a plate line. Focusing on the paired nonvolatile memory, the word line WL ₁ is connected to the word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to the sense amplifier SA. Further, the plate line PL ₁ is connected to the plate line decoder / driver PD.

In the nonvolatile memory having such a structure, when reading the stored data, the word line W
When L ₁ is selected and the plate line PL ₁ is driven,
Complementary data is stored in the paired memory cells MC ₁₁ and MC.
_It appears as a voltage (bit line potential) from ₁₂ to the paired bit lines BL ₁ and BL ₂ through the selection transistors TR ₁₁ and TR ₁₂ . The voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ is detected by the sense amplifier SA. The operation of the non-volatile memory is an example, and the operation is not limited to the above.

A method of manufacturing the nonvolatile memory according to the first embodiment will be described below with reference to FIGS. 1 to 5 which are schematic partial cross-sectional views of a semiconductor substrate and the like.

[Step-100] First, the nonvolatile memory M
MO that functions as the selection transistor TR in _A
An S-type transistor is formed on the silicon semiconductor substrate 10. Therefore, the element isolation region 11 having, for example, a LOCOS structure is formed by a known method. Incidentally, the element isolation region may have a trench structure, or the LOC
A combination of the OS structure and the trench structure may be used. Then, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12. Then
A polysilicon layer doped with impurities is formed on the entire surface by a CVD method, and then the polysilicon layer is patterned to form a gate electrode 13. The gate electrode 13 also serves as the word line WL. The gate electrode 13 may be made of polycide or metal silicide instead of being made of a polysilicon layer. Next, the semiconductor substrate 10 is ion-implanted to form an LDD structure. After that, a SiO ₂ layer is formed on the entire surface by the CVD method, and then the SiO ₂ layer is etched back to form the gate sidewall 14 on the side surface of the gate electrode 13.
Then, after ion-implanting the semiconductor substrate 10, activation / annealing treatment of the ion-implanted impurities is performed to form the source / drain regions 15A and 15B.

[Step-110] Next, an insulating layer is formed on the entire surface. Specifically, after a lower insulating layer made of SiO ₂ is formed by the CVD method, an opening is formed in the lower insulating layer above the other source / drain region 15A based on the lithography technique and the RIE method. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. Next, by patterning the polysilicon layer on the lower insulating layer,
The bit line BL is formed. The bit line BL and the source / drain region 15A are connected via a connection hole (contact hole) 16 formed in the lower insulating layer. After that, an upper insulating layer made of BPSG is formed on the entire surface by the CVD method. After forming the upper insulating layer made of BPSG, for example, 900 ° C. × 20 minutes in a nitrogen gas atmosphere,
It is preferable to reflow the upper insulating layer. Furthermore,
If necessary, for example, a chemical mechanical polishing method (CMP method)
It is desirable to chemically and mechanically polish the top surface of the upper insulating layer to flatten the upper insulating layer, or to flatten the upper insulating layer by a resist etch back method. The lower insulating layer and the upper insulating layer are collectively referred to as the insulating layer 17 below. Thus, the structure shown in the schematic partial cross-sectional view of FIG. 1A can be obtained.

[Step-120] Next, the opening 1 is formed in the insulating layer 17 above one of the source / drain regions 15B.
8 is formed based on the lithography technique and the RIE method (see FIG. 1B).

[Step-130] After that, the plug 19 made of platinum (Pt) is formed in the opening 18 by a plating method. Specifically, the insulating layer 17 including the inside of the opening 18
Platinum (P
t) Form the layer. The illustration of the seed layer is omitted. After that, the insulating layer 17 including the inside of the opening 18 is formed by electroplating.
A platinum layer is formed on the upper seed layer (see FIG. 2A). Then, the platinum layer on the insulating layer 17 is removed by a chemical mechanical polishing method (CMP method) or a sputter etching method. Thus, the structure shown in the schematic partial cross-sectional view of FIG. 2B can be obtained. The electroplating conditions for the platinum layer are illustrated in Table 2 below. Here, the bit line BL is
Although extending over the lower insulating layer in the left-right direction in the drawing so as not to come into contact with the plug 19, the illustration of the bit line portion is omitted.

[0052]

Alternatively, the insulating layer 1 including the inside of the opening 18
An iridium (Ir) layer corresponding to a seed layer is formed on 7 by a sputtering method. Then, an iridium layer is formed on the seed layer on the insulating layer 17 including the inside of the opening 18 by electroplating. After that, the iridium layer on the insulating layer 17 is removed by a chemical mechanical polishing method (CMP method) or a sputter etching method. The electroplating conditions for the iridium layer are illustrated in Table 3 below.

[Table 3] Plating bath: (NH ₄ ) ₂ IrCl ₆ or IrCl ₃ · 3H ₂ O 5 to 50 g / liter pH 1 to 6 Plating bath temperature: 30 to 60 ° C Current density: 0.5 to 50 A / cm ²

Alternatively, the insulating layer 1 including the inside of the opening 18
A rhodium (Rh) layer corresponding to a seed layer is formed on 7 by a sputtering method. After that, a rhodium layer is formed on the seed layer on the insulating layer 17 including the inside of the opening 18 by electroplating. After that, the rhodium layer on the insulating layer 17 is removed by a chemical mechanical polishing method (CMP method) or a sputter etching method. The electroplating conditions for the rhodium layer are illustrated in Table 4 below.

[Table 4] Plating bath: Rh (SO ₄ ) ₃ or RhCl ₃ · 3H ₂ O 5 to 50 g / liter pH 1 to 6 Plating bath temperature: 30 to 60 ° C Current density: 0.5 to 50 A / Cm ²

Alternatively, the insulating layer 1 including the inside of the opening 18
A palladium (Pd) layer corresponding to a seed layer is formed on 7 by a sputtering method. After that, a palladium layer is formed on the seed layer on the insulating layer 17 including the inside of the opening 18 by electroplating. Then, the palladium layer on the insulating layer 17 is removed by a chemical mechanical polishing method (CMP method) or a sputter etching method. The electroplating conditions for the palladium layer are illustrated in Table 5 below.

[Table 5] Plating bath: PdSO ₄ .2H ₂ O or PdCl ₂ .4H ₂ O 5 to 50 g / liter pH 1 to 6 Plating bath temperature: 30 to 60 ° C Current density: 0.5 to 50 A / Cm ²

Alternatively, the insulating layer 1 including the inside of the opening 18
A ruthenium (Ru) layer corresponding to a seed layer is formed on 7 by a sputtering method. Then, a ruthenium layer is formed on the seed layer on the insulating layer 17 including the inside of the opening 18 by electroplating. After that, the ruthenium layer on the insulating layer 17 is removed by a chemical mechanical polishing method (CMP method) or a sputter etching method. The electroplating conditions for the ruthenium layer are illustrated in Table 6 below.

[0060]

[Step-140] Next, it is preferable to form an adhesion layer 20 of, for example, TiN having a thickness of about 40 nm on the insulating layer 17 and the plug 19 by a sputtering method. Then, the first electrode material layer 21A made of iridium (Ir) and having a thickness of about 100 nm is formed on the adhesion layer 20 by the sputtering method (see FIG. 3A).

[Step-150] Then, for example, MOD
A ferroelectric thin film 22A made of a Bi-based layered structure perovskite type ferroelectric material is formed on the entire surface by the MOCVD method or the MOCVD method. For example, Table 7 below exemplifies the formation conditions based on the MOCVD method for the ferroelectric thin film 22A made of Bi ₂ SrTa ₂ O ₉ . In Table 7, "thd" is an abbreviation for tetramethylheptanedinate. The source materials shown in Table 7 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.

[Table 7] Formation by MOCVD Source material: Sr (thd) ₂ -tetraglyme Bi (C ₆ H ₅ ) ₃ Ta (O-iC ₃ H ₇ ) ₄ (thd) Formation temperature: 400 to 700 ° C Process gas: Ar / O ₂ = 1000/1000 cm ³ Formation rate: 5 to 20 nm / min

Alternatively, a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ is formed by pulse laser ablation method, sol-
It can also be formed on the entire surface by a gel method or an RF sputtering method. The forming conditions in these cases are illustrated in Tables 8, 9 and 10 below. In addition, sol
When forming a thick ferroelectric thin film by the gel method, spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated a desired number of times.

[Table 8] Target formed by pulse laser ablation method: Bi ₂ SrTa ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz) Forming temperature: 400 to 800 ° C Oxygen concentration: 3 Pa

[0066] [Table 9] sol - gel method by forming _{ingredients: Bi (CH 3 (CH 2} ) 3 CH (C 2 H 5) COO) 3 [ bismuth _{2-ethylhexanoate, Bi (OOc) 3] Sr} ( CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [strontium.2-ethylhexanoic acid, Sr (OO
c) ₂ ] Ta (OEt) ₅ [tantalum ethoxide] Spin coating conditions: 3000 rpm x 20 seconds Drying: 250 ° C x 7 minutes Firing: 700 to 800 ° C x 1 hour (RT if necessary
A processing is added)

[Table 10] Formation target by RF sputtering method: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Formation temperature: Room temperature ˜600 ° C. Process gas: Ar / O ₂ flow rate ratio = 2/1 to 9/1

Table 11 below shows the conditions for forming PZT or PLZT by magnetron sputtering when the ferroelectric layer is composed of PZT or PLZT. Alternatively, PZT or PLZT can be formed by a reactive sputtering method, an electron beam evaporation method, a sol-gel method, or a MOCVD method.

[Table 11] Target: PZT or PLZT Process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Formation temperature: 500 ° C

Further, PZT or PLZT can be formed by the pulse laser ablation method. The forming conditions in this case are illustrated in Table 12 below.

[Table 12] Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

[Step-160] After that, the ferroelectric thin film 2
The second electrode material layer 23A is formed on 2A. Specifically, by sputtering on the ferroelectric thin film 22A,
A second electrode material layer 23A made of iridium (Ir) and having a thickness of 100 nm is formed (see FIG. 3B). Next, the second electrode material layer 23A, the ferroelectric thin film 22A, the first electrode material layer 21A, and the adhesion layer 20 are patterned based on the photolithography technique and the RIE method. Thus, the first electrode 21 (comprising an Ir layer) on the insulating layer 17 and the ferroelectric layer 22 formed on the first electrode 21.
(Composed of Bi ₂ SrTa ₂ O ₉ ) and the ferroelectric layer 2
It is possible to obtain the memory cell MC composed of the second electrode 23 (comprising an Ir layer) formed on the second electrode 2 (FIG. 4).
(A)).

Next, in order to recover etching damage, in an inert gas atmosphere containing a trace amount of oxidizing gas, specifically, in a nitrogen gas atmosphere containing 1 volume% of oxygen gas (nitrogen gas: 99 volume%). Alternatively, heat treatment may be performed at 700 ° C. for 1 hour.

[Step-170] Next, the insulating film 24 is formed on the entire surface.
Are formed (see FIG. 4B). Next, an opening is formed in the insulating film 24 on the second electrode 23 based on the lithography technique and the RIE method. After that, a wiring material layer made of aluminum is formed on the insulating film 24 including the inside of the opening by a sputtering method, and then the wiring material layer on the insulating film 24 is patterned to form a plate line PL (see FIG. 5). Thus, the nonvolatile memory can be completed.

(Embodiment 2) Embodiment 2 relates to a nonvolatile memory according to the second aspect of the present invention and a method for manufacturing the same. FIG. 7 is a circuit diagram of the nonvolatile memory according to the second embodiment.
10 and FIG. 9 is a schematic partial sectional view.
7 and 10 show two adjacent non-volatile memories M _A and M _B sharing the plate line. On the other hand, in FIG. 9, the selection transistor TR _A and the memory cell MC _Am that configure the nonvolatile memory M _A , and the selection transistor TR ′ _A that configures the nonvolatile memory adjacent in the direction in which the bit line BL _A extends. And memory cell MC ' _Am
Is also shown in part. The bit lines BL _{A in} the memory cells MC _Am , MC ′ _Am ... Adjacent to the extending direction of the bit lines BL _A are shared. Since these nonvolatile memories have the same structure, the nonvolatile memory M _A will be described below.

The nonvolatile memory M _{A according to the} second embodiment is
(A) Bit line BL _A and (B) selection transistor T
R _A , (C) M memory cells (where M ≧ 2, and M = 4 in the second embodiment) M U _A configured of memory cells MC _AM , and (D) M memory units. It is composed of plate lines PL _m (m = 1, 2 ... M).

Then, each memory cell MC _Am (m = 1, 2,
... M) is the first electrode 21, the ferroelectric layer 22 and the second electrode 21.
Electrode 23. In addition, the first electrode 21 of the memory cell MC _Am that constitutes the memory unit MU _A
Is common in the memory unit MU _A , and the common first electrode 21 (which may be referred to as a common node CN _A ) is connected to the bit line BL via the plug 19, the selection transistor TR _A , and the connection hole 16. The second electrode 23 is connected to _A and the second electrode 23 is connected to the plate line PL _m . Specifically, the plate line PL _m extends from the second electrode 23 forming the memory cell MC _Am and is connected to the second electrode 23 forming the memory cell MC _Bm of the adjacent nonvolatile memory M _B. It is common.

The plate line PL _m is connected to the plate line decoder / driver PD. The gate electrode of the selection transistor TR _A is connected to the word line WL,
The word line WL is connected to the word line decoder / driver WD. Furthermore, the bit line BL _A is connected to the sense amplifier SA. The sense amplifier SA is, for example,
It can be composed of a current mirror sense amplifier.

With such a structure, since one selecting transistor TR _A is shared by the four memory cells MC _Am , it is possible to effectively reduce the size of the nonvolatile memory as a whole. The value of M is not limited to 4. As a practical value of M, for example, a power of 2 (2,
4, 8, 16 ...).

In the nonvolatile memory of the second embodiment whose circuit diagram is shown in FIG. 7, paired memory cells MC _Am and M
One bit is stored by writing complementary data to C _Bm . In addition, the two selection transistors TR _A and TR
_B and eight memory cells MC _Am and MC _{Bm form} one memory unit (access unit unit) and store 4 bits. In an actual non-volatile memory, a set of memory units storing these 4 bits is arranged in an array as an access unit unit.

A method of reading data from such a non-volatile memory and rewriting the data will be described below. As an example, the paired memory cells MC _A1 , M
It is assumed that complementary 1-bit data is read from C _B1, data “1” is stored in the memory cell MC _A1 , and data “0” is stored in the memory cell MC _B1 . Figure 8
Shows the operation waveform. In FIG. 8, the numbers in parentheses correspond to the numbers of the steps described below.

(1) In the standby state, the bit line BL_A, B
L_B, Word lines WL, all plate lines PL _mIs 0 volts
ing. Furthermore, the common node CN_A, CN_BAlso 0 volts
It is in a floating state.

(2) When reading data, V _cc is applied to the selected plate line PL ₁ . At this time, the selected memory cell M
Since data "1" is stored in C _A1 , polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the potential of the common node CN _A rises. On the other hand, the selected memory cell MC _B1
Since the data "0" is stored in, the polarization inversion does not occur in the ferroelectric layer, and the potential of the common node CN _B hardly rises. That is, the common nodes CN _A and CN _B are connected to the plurality of non-selected plate lines P via the ferroelectric layers of the non-selected memory cells.
Since it is coupled to L _j (j = 2, 3, 4), the potential of the common node CN _B is kept at a level relatively close to 0 volt. In this way, the selected memory cell MC
Common node C depending on the data stored in _A1 and MC _B1
A change occurs in the potentials of N _A and _C N _B. Therefore, a sufficient electric field for polarization reversal can be applied to the ferroelectric layer of the selected memory cell MC _A1 .

(3) Next, the bit lines BL _A and BL _B are brought into a floating state and the word line WL is brought to a high level to turn on the selection transistors TR _A and TR _B. As a result, the common first electrode (common node CN _A ) based on the data stored in the selected memory cell MC _A1.
The potential generated on the bit line causes a potential on the bit line BL _A.
On the other hand, the potential of the bit line BL _B rises only slightly.

(4) Next, the word line WL is set to the low level to select transistors TR _A and TR _B.
Is turned off.

(5) Thereafter, the potentials of the bit lines BL _A and BL _B are latched by the sense amplifier SA, and the sense amplifier SA
Are activated to amplify the data, and the data read operation is completed.

Since the data stored in the selected memory cell is once destroyed by the above operation, the data rewriting operation is performed.

(6) Therefore, first, the bit line B
L _A, the BL _B is charged and discharged by the sense amplifier SA, the V _cc is applied to the bit line BL _A, applying 0 volts to the bit line BL _B. On the other hand, the non-selected plate line PL _j (j = 2,
The potential of (3, 4) is set to (1/2) _Vcc .

(7) After that, the word line WL is set to the high level to select transistors TR _A and TR _B.
Is turned on. This allows the common node CN _A ,
The potential of CN _B becomes equal to the potentials of bit lines BL _A and BL _B. That is, since the data stored in the selected memory cell MC _A1 is “1”, the potential of the common node CN _A is V _cc.
Becomes On the other hand, since the data stored in the selected memory cell MC _B1 is “0”, the potential of the common node CN _B becomes 0 volt. Since the potential of the selected plate line PL ₁ is still V _cc , the potential of the common node CN _B is also 0.
Since the voltage is volt, the data “0” is rewritten in the selected memory cell MC _B1 .

(8) Next, the potential of the selected plate line PL ₁ is set to 0 volt. As a result, the selected memory cell MC
_Since the data stored in _A1 is "1", the potential of the common node CN _A is V _cc , and the data "1" is rewritten in the memory cell MC _A1 . Selected memory cell MC
_B1 data "0" has already been re-written to, there is no change to the selected memory cell MC _B1.

(9) After that, the bit lines BL _A and BL _B are set to 0.
Let it be a bolt.

(10) Finally, the non-selected plate line PL _j
Is set to 0 volt and the word line WL is set to a low level to turn off the selection transistors TR _A and TR _B.

Other memory cells MC _Aj , MC _Bj (j = 2,
When the data is read from 3, 4) and the data is rewritten, the same operation is repeated.

[0094] As shown in a circuit diagram of FIG. 10, the selection transistor TR _A constituting the nonvolatile memory M _A, selection transistor TR _B and the word lines WL ₁ and word line constituting the nonvolatile memory M _B When independently controlled by WL ₂ , 1-bit data can be stored in each of the memory cell MC _Am and the memory cell MC _Bm . Hereafter, the data is read from the nonvolatile memory having such a configuration,
A method of rewriting will be described. As an example, it is assumed that 1-bit data is read from the memory cell MC _A1 . FIG. 11 shows operation waveforms. In addition, in FIG.
The numbers in parentheses correspond to the process numbers described below.

(1) In the standby state, the bit lines BL _A , B
L _B , word lines WL ₁ and WL ₂ , and all plate lines PL _m are at 0 volt. Further, the common nodes CN _A and CN _B are also in a floating state at 0 volt.

(2) When data reading is started,
The selected memory unit (access unit
All plate lines PL in_m(M = 1, 2, 3,
4) to (1/2) V_cc(However, V_ccIs the power supply voltage)
Charge and then bit line BL_A, BL_B(1/2)
V_ccPrecharge to. Then word line WL₁, W
L₂To a high level,
Star TR_A, TR_BIs turned on. By this,
Common first electrode 21 (common node CN_A, CN_B) Is a bit
Line BL_A, BL_BConnected to the common node CN_A, CN_B
Potential is (1/2) V _ccBecomes

(3) Next, the non-selected word line WL _{2 is set} to the low level to select the selection transistor T.
And turn off the R _B. Thus, the common node CN _B the non-selected, while the potential of (1/2) V _cc, a floating state.

(4) After that, the selected plate line PL ₁ and the bit line BL _A are discharged to 0 volt through the ground line (not shown). At this time, the common node CN _A also 0 volt, which is connected to the bit line BL _A. When the discharge of the bit line BL _A is completed, the ground line and the bit line B
The electrical connection with L _A is released to bring the bit line BL _A into a floating state.

(5) Next, V _{cc is applied} to the selected plate line PL _1.
On the other hand, a reference potential intermediate between the read potential of the data “1” and the read potential of the data “0” is applied to the bit line BL _B (that is, the reference side bit line). As a result, the memory cell MC storing the data "1"
Inversion charges are emitted from _A1 . As a result, a potential difference occurs between the bit lines BL _A and BL _B. Next, the sense amplifier SA is activated to read the potential difference between the bit lines BL _A and BL _B as data.

By the above operation, the data stored in the selected memory cell is once destroyed, so the data rewriting operation is performed.

(6) After that, the bit lines BL _A and BL _B are
The memory cell MC is charged and discharged by the sense amplifier SA.
_When data "1" is stored in _A1 , V _cc is applied to the bit line BL _A , and when data "0" is stored in the memory cell MC _A1 , 0 is written in the bit line BL _A.
Apply a volt. On the other hand, 0 volt is applied to the bit line BL _B. As a result, when the data “0” is stored in the memory cell MC _A1 , the data “0” is written again.

(7) After that, the selected plate line PL _{1 is set} to 0.
By setting the voltage to Volt, when the data “1” is stored in the memory cell MC _A1 , the data “1” is written again.

(8) When the data reading is completed, then the bit lines BL _A and BL _B are discharged to 0 volt. Next, the plate line PL _m (m = 1, 2, 3, 4)
After the discharge to 0 volt, the non-selected word line WL ₂ is set to the high level again and the selection transistors TR _A and TR _{B are selected.}
Is turned on, and all the common nodes CN _A and CN _B of the memory unit (access unit unit) are set to 0 volt.

When the data of the next memory cell is read out continuously, all plate lines PL _m (m = m
1, 2, 3, 4) is precharged to (1/2) V _cc ,
The above operations (2) to (7) are repeated.

The method of manufacturing the nonvolatile memory according to the second embodiment will be described below.

[Step-200] First, in the same manner as in [Step-100] of the first embodiment, a MOS transistor that functions as the selection transistor TR _A in the nonvolatile memory is formed on the semiconductor substrate 10.

[Step-210] Then, a lower insulating layer is formed on the entire surface, and then electrically connected to the one source / drain region 15A of the selecting transistor TR _A through the connection hole 16 on the lower insulating layer. Form a connected bit line BL _A. Specifically, the lower insulating layer made of SiO ₂ is C
After forming by the VD method, one of the source / drain regions 1
An opening is formed in the lower insulating layer above 5A by the RIE method. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. As a result, the connection hole (contact plug) 1
6 is formed. Then, the bit line BL _A is formed by patterning the polysilicon layer on the lower insulating layer. Then, CVD is applied to the upper insulating layer made of BPSG.
It is formed on the entire surface by the method. After forming the upper insulating layer made of BPSG, for example, 900 ° C. × 2 in a nitrogen gas atmosphere.
It is preferable to reflow the upper insulating layer for 0 minutes.
Further, if necessary, for example, a chemical mechanical polishing method (C
It is desirable that the top surface of the upper insulating layer is polished chemically and mechanically by the MP method) to flatten the upper insulating layer. The lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 17.

[Step-220] Next, the opening 1 is formed in the insulating layer 17 above the other source / drain region 15B.
8 is formed by the RIE method, and then, in the opening 18,
Similar to [Step-130] of the first embodiment, the plug 1
9 is formed.

[Step-230] After that, it is desirable to form the adhesion layer 20 made of titanium oxide on the insulating layer 17 and the plug 19 in the same manner as in [Step-140] of the first embodiment. Then, the first layer of Ir is formed on the adhesion layer 20.
The first electrode material layer constituting the electrode (lower electrode) 21 of
For example, the first electrode 2 is formed by a sputtering method, and the first electrode material layer and the adhesion layer are patterned by a photolithography technique and a dry etching technique.
1 can be obtained.

[Step-240] Then, in the same manner as in [Step-150] and [Step-160] of the first embodiment, the ferroelectric thin film and the second electrode material layer are sequentially formed, and then the second electrode is formed. The ferroelectric layer 22 and the second electrode 23 are obtained by patterning the material layer and the ferroelectric thin film. [Step-250] After that, an insulating film 27A is formed on the entire surface,
Complete the non-volatile memory.

Each second electrode may not also serve as a plate line. In this case, after the formation of the insulating film 27A is completed,
An opening may be formed in the insulating film 27A above the second electrode 23, and then a plate line extending into the opening may be formed on the insulating film 27A.

(Third Embodiment) A third embodiment of the present invention
To a non-volatile memory and a method for manufacturing the same according to the third aspect
Concerned. 1 is a circuit diagram of a nonvolatile memory according to a third embodiment.
2 and FIG. 13, and a schematic partial sectional view is shown in FIG.
You 12 and 13, the plate line is shared.
Two adjacent non-volatile memories M_A, M_BIndicates. on the other hand,
In FIG. 14, the nonvolatile memory M_AThe choices that make up
Transistor TR_AAnd memory cell MC _AmIllustrates
It These non-volatile memory M_A, M_BHave the same structure
Therefore, the non-volatile memory M_AExplain about
It

The nonvolatile memory M _{A according to the} third embodiment is
(A) Bit line BL _A and (B) selection transistor T
R _A and (C) are each M (provided that M ≧ 2,
In the third embodiment, M = 4) memory cells MC _AM
N (where N ≧ 2, and N = 2 in the third embodiment) memory units MU _{AN configured} from
(D) M × N plate lines.

Then, the N memory units MU _An are
Each memory cell is laminated through an interlayer insulating layer,
It is composed of the first electrodes 21 and 31, the ferroelectric layers 22 and 32, and the second electrodes 23 and _{33. In} each memory unit MU _An , the first electrode of the memory cell MC _Anm is common and common. The first electrode is connected to the bit line BL _A via the plug, the selection transistor TR _A , and the connection hole. Specifically, in the memory unit MU _A1 , the first electrode 21 of the memory cell MC _A1m is common (this common first electrode 21 is referred to as the first common node CN _A1 ) and the common first electrode 21. Electrode 21 (first common node C
N _A1 ) is the opening 1 of the first layer formed in the insulating layer 17.
8 is connected to the bit line BL _A via the plug 19 of the first layer provided on the No. 8, the selection transistor TR _A , and the connection hole 16. In the memory unit MU _A2 , the first electrode 31 of the memory cell MC _A2m is common (this common first electrode is referred to as the second common node CN _A2 ), and the common first electrode 31 ( The second common node CN _A2 ) is the second-layer plug 29 provided in the second-layer opening 28 formed in the first-layer interlayer insulating layer 27 and the first-layer plug 19. , The selection transistor TR _A , and the bit line BL _A via the connection hole 16. Furthermore, the memory unit M of the nth layer (where n = 1, 2, ..., N)
In U _An , the m-th (however, m = 1, 2 ...
The second electrodes 23 and 33 of the memory cell MC _Anm of M) are
[(N-1) M + m] th plate line PL _{(n-1) M + m}
It is connected to the. In addition, this plate line PL
_{The (n-1) M + m} is also connected to the second electrodes 23 and 33 of each memory cell forming the nonvolatile memory M _B.

One source / drain region 15A of the selecting transistor TR _A is connected to the bit line B through the connection hole 16.
The other source / drain region 15B of the selection transistor TR _A , which is connected to L _A , has a first layer plug 19 provided in the first layer opening 18 formed in the insulating layer 17.
Via a common first electrode 21 (first common node CN _A1 ) in the first-layer memory unit MU _A1 . Further, the other source / drain region 15B of the selection transistor TR _A includes the first-layer plug 19 provided in the first-layer opening 18 formed in the insulating layer 17, and the interlayer insulating layer. The common first electrode 31 (second common) in the memory unit MU _A2 of the second layer is inserted through the plug 29 of the second layer formed in the opening portion 28 of the second layer formed in 27. Node CN _A2 ). In the figure, reference numeral 37A is an insulating film.

The bit line BL _A is connected to the sense amplifier SA. The plate line PL _{( n-1) M + m} is connected to the plate line decoder / driver PD. Furthermore,
The word line WL is connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIG. The second electrode 23 of the memory cell MC _A1m forming the non-volatile memory M _A is common to the second electrode of the memory cell MC _B1m forming the non-volatile memory M _B adjacent in the direction perpendicular to the paper surface of FIG. And the plate line P
Also serves as L _{(n-1) M + m} . Furthermore, a non-volatile memory M _A
The second electrode 33 of the memory cells MC _A2m constituting a is common and second electrodes of the memory cells MC _B2m constituting the nonvolatile memory M _B which is adjacent in the direction perpendicular to the paper surface in FIG. 14,
It also serves as the plate line PL _{(n-1) M + m} . The word line WL is common for selection transistors TR _A constituting the nonvolatile memory M _A, the selection transistor TR _B constituting the nonvolatile memory M _B which is adjacent in the direction perpendicular to the paper surface in FIG. 14.

In the nonvolatile memory whose circuit diagram is shown in FIG. 12, the selection transistors TR _A and TR _B forming the nonvolatile memories M _A and M _B are connected to the same word line WL. And the paired memory cells MC _Anm , MC
_Bnm (n = 1, 2, ..., N, and m = 1, 2 ...
., M) is stored as complementary 1-bit data. The method of reading data from the nonvolatile memory of the third embodiment and rewriting the data may be substantially the same as the operation of the nonvolatile memory of the second embodiment described with reference to FIG. Therefore, detailed description is omitted.

In addition, a third embodiment whose circuit diagram is shown in FIG.
In the non-volatile memory, the selection transistor TR _A forming the non-volatile memory M _A is connected to the word line WL ₁ , and the selection transistor TR _B forming the non-volatile memory M _B is connected to the word line WL _2. ing. Word line W
L ₁ and WL ₂ are connected to the word line decoder / driver WD. The memory cell MC _Anm and the memory cell MC _Bnm are independently controlled to form a pair of bit lines B.
By applying a reference voltage to one of L _A and BL _B ,
1-bit data is read from each of the memory cells MC _Anm and MC _Bnm . A method of reading data from the nonvolatile memory of the third embodiment and rewriting the data is as follows.
Since the operation can be substantially the same as that of the nonvolatile memory according to the second embodiment described with reference to FIG. 11, detailed description thereof will be omitted.

The method of manufacturing the nonvolatile memory according to the third embodiment will be described below.

[Step-300] First, in the same manner as in [Step-100] of the first embodiment, a MOS transistor that functions as the selection transistor TR _A in the nonvolatile memory is formed on the semiconductor substrate 10.

[Step-310] Then, in the same manner as in [Step-210] of the second embodiment, a lower insulating layer is formed on the entire surface, and then the selection transistor T is formed on the lower insulating layer.
_A connection hole 16 is formed in one source / drain region 15A of R _A.
To form a bit line BL _A electrically connected to each other. Then, after forming an upper insulating layer on the entire surface, the upper insulating layer and the lower insulating layer above the other source / drain region 15B of the selecting transistor TR _A are formed in the same manner as in [Step-220] of the second embodiment. The first layer opening 18 is formed in the (insulating layer 17) portion.

[Step-320] Next, in the same manner as in [Step-130] of the first embodiment, the plug 19 of the first layer is formed.
Is formed in the opening 18 of the first layer by a plating method.

[Step-330] Then, in the same manner as in [Step-230] and [Step-240] of the second embodiment,
On the upper insulating layer (insulating layer 17), a first electrode 21, a ferroelectric layer 22 and a second electrode 23 are formed, and the common first electrode 21 (common node CN _A1 ) is the first layer. The plug 19
It is possible to obtain the memory unit MU _A1 of the first layer connected to.

[Step-340] After that, the n'th layer (where n '= 1, 2, ..., N-
1) forming an interlayer insulating layer, forming an opening of the (n ′ + 1) th layer in the n′th interlayer insulating layer, and selecting from the group consisting of platinum, iridium, palladium, rhodium and ruthenium. A plug of the (n ′ + 1) th layer, which is made of a metal or an alloy thereof and is electrically connected to the plug of the n′th layer, is placed in the opening of the (n ′ + 1) th layer by the plating method. After the formation, the common first electrode is connected to the (n '+ 1) th layer plug on the (n' + 1) th layer interlayer insulating layer.
The process of forming the memory unit of the layer is repeated while incrementing n ′ by 1 from 1 to (N−1).

In the third embodiment, since N = 2, n '= 1.

Therefore, A first interlayer insulating layer 27 is formed on the entire surface, The opening 28 of the second layer is formed in the interlayer insulating layer 27 of the first layer.
Formed, Platinum, iridium, palladium, rhodium and rutheni
A metal or its alloy selected from the group consisting of um
And a first layer electrically connected to the plug 19 of the first layer.
The second layer plug 29 is opened by the plating method for the second layer.
After forming in the mouth 28, The common first electrode 3 is formed on the first interlayer insulating layer 27.
1 (common node CN_A2) Is connected to the plug 29 of the second layer
Second layer memory unit MU_A2(First electrode 3
1, a ferroelectric layer 32, and a second electrode 33.
Memory cell MC _A2m) Is formed. Then insulated over the entire surface
A non-volatile memory M is formed by forming the film 37A._AComplete
It

The ferroelectric material forming the ferroelectric layer 32 is, for example, Bi ₂ Sr (T) at a crystallization temperature of 700 ° C.
It is preferable that the ferroelectric layer 32 is made of a _1.5 Nb _0.5 ) O _{9. In} this case, the ferroelectric layer 32 may be heat-treated for promoting crystallization in an oxygen gas atmosphere at 700 ° C. for 1 hour. Further, each second electrode may not also serve as a plate line. In this case, after the formation of the insulating film 37A is completed,
Insulating film 37 above the second electrode 23 and the second electrode 33
The opening may be formed in A, and then the plate line extending into the opening may be formed on the insulating film 37A.

(Embodiment 4) Embodiment 4 relates to a nonvolatile memory according to a fourth aspect of the present invention and a manufacturing method thereof. 1 is a circuit diagram of a nonvolatile memory according to a fourth embodiment.
5 and FIG. 16, and a schematic partial sectional view is shown in FIG. 15 and 16 show two adjacent non-volatile memories M _A and M _B sharing a plate line. on the other hand,
In FIG. 17, the selection transistor TR _A1 and the memory cell MC _A1m that form the nonvolatile memory M _A are illustrated. The selection transistor TR _A2 and the memory cell MC _A2m forming the nonvolatile memory M _A are provided adjacent to each other in the direction perpendicular to the paper surface of FIG. Since the nonvolatile memories M _A and M _B have the same structure, the memory unit MU _A2 and the selection transistor TR _A2 also have the same structure as the memory unit MU _A1 and the selection transistor TR _A1 . Hereinafter, the nonvolatile memory M _A , the memory unit MU _A1 , and the selection transistor TR _A1 will be described.

The nonvolatile memory M _{A according to the} fourth embodiment is
(A) a bit line BL _A, (B) N pieces (N ≧ 2, and in the fourth embodiment, N = 2) and the selection transistor TR _AN, (C), respectively are M ( However, M ≧
2 and, in the fourth embodiment, N memory units M each composed of M = 4) memory cells MC _ANM.
It consists of U _AN and (D) M plate lines PL _M.

Then, the N memory units MU _An are
It is formed on the insulating layer 17. Each memory cell has a first
Electrode, the ferroelectric layer, and the second electrode. Specifically, each memory cell MC _A1m that constitutes the first memory unit MU _A1 includes a first electrode 21, a ferroelectric layer 22 and a second electrode 23, and a second memory unit. Each memory cell MC _A2m forming the MU _A2 also includes a first electrode 21, a ferroelectric layer 22, and a second electrode 23. Furthermore, in each memory unit MU _An , the memory cell M
The first electrode 21 of C _Anm is common. Specifically, in the first memory unit MU _A1 , the memory cell M
The first electrode 21 of C _A1m is common. This common first
21 may be referred to as a first common node CN _A1 . In the second memory unit MU _A2 ,
The first electrode 21 of the memory cell MC _A2m is common. This common first electrode 21 may be referred to as a second common node CN _A2 . Furthermore, the nth (however, n = 1, 2 ...
..., in the memory unit MU _An of N), the m-th (where the second electrode 23 of m = 1, 2 · · ·, M) memory cells are common to the memory units MU _An It is connected to the m-th plate line PL _m . In the fourth embodiment, more specifically, each plate line is the second
Extending from the electrode 23.

Nth (however, n = 1, 2, ..., N)
Common first electrode 21 in the memory unit MU _An of
The (common node CN _An ) is connected to the bit line B via the plug 19, the nth selection transistor TR _An , and the connection hole 16.
Connected to L _A. Specifically, one source / drain region 15 of each of the selection transistors TR _A1 and TR _A2 is selected.
A is connected to the bit line BL _A , and each of the other source / drain regions 15B of the selection transistors TR _A1 and TR _A2 is connected via a plug 19 provided in an opening 18 formed in the insulating layer 17. , Memory units MU _A1 , M
It is connected to each of the common first electrodes 21 (first common nodes CN _A1 , CN _A2 ) in U _A2 .

Bit line BL_AConnected to the sense amplifier SA
Has been done. Also, the plate line PL_MIs plate line deco
Connected to the driver / driver PD. Furthermore, the word
Line WL ₁, WL₂Is the word line decoder / driver WD
It is connected. Word line WL ₁, WL₂Is the paper in Figure 17
It extends in the direction perpendicular to the plane. In addition, the nonvolatile memory M_ATo
Memory cell MC_A1mThe second electrode 23 of is a memo
Resel MC_A2mSecond electrode 23, perpendicular to the paper surface of FIG.
Adjacent to the non-volatile memory M_BMemory cells that make up
MC_B1m, MC_B2mCommon to the second electrode of the plate
Line PL_mDoubles as Also, the word line WL₁Is non-volatile
Sex memory M_ASelection transistor TR_A1When,
Nonvolatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BTo
Selection transistor TR to be configured_B1And are common. Change
The word line WL₂Is a non-volatile memory M_AMake up
Selection transistor TR_A2And in the direction perpendicular to the paper surface of FIG.
Adjacent non-volatile memory M_BSelection transitions that make up
Star TR_B2And are common.

In the nonvolatile memory of the fourth embodiment whose circuit diagram is shown in FIG. 15, the selection transistors TR _A1 and TR _B1 forming the nonvolatile memories M _A and M _B are connected to the same word line WL _1. , Selection transistors TR _A2 , TR
_B2 is connected to the same word line WL ₂ . And
_Paired memory cells MC _Anm , MC _Bnm (n = 1, 2 _...
.., N, and 1 complementary to m = 1, 2, ..., M)
Bit data is stored. Embodiment 4 as described above
The method of reading data from the non-volatile memory and rewriting the data can be substantially the same as the operation of the non-volatile memory of the second embodiment described with reference to FIG. Omit it.

Further, a fourth embodiment whose circuit diagram is shown in FIG.
In the non-volatile memory of, the non-volatile memory M_AConstruct
Selection transistor TR_A1Is the word line WL₁₁Contact
Followed by selection transistor TR_A2Is the word line WL₁₂To
Connected, non-volatile memory M _BSelectable tran composing
Dista TR_B1Is the word line WL_{twenty one}Connected to the selection tiger
Register TR_B2Is the word line WL_{twenty two}It is connected to the. Wa
Wire line WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}Is the word line
It is connected to the coder / driver WD. And a note
Resel MC_AnmAnd memory cell MC_BnmControl independently
And paired bit lines BL_A, BL_BReference voltage on one side
Memory cell MC by applying _Anm, MC_Bnm
1-bit data is read from each. like this
Data from the nonvolatile memory according to the fourth embodiment
Refer to FIG. 11 for the method of rewriting.
Similar to the operation of the nonvolatile memory according to the second embodiment described above.
Therefore, detailed description will be omitted.

The method of manufacturing the nonvolatile memory according to the fourth embodiment will be described below.

[Step-400] First, in the same manner as in [Step-100] of the first embodiment, N which functions as the selection transistors TR _A1 and TR _A2 in the non-volatile memory.
Individual MOS type transistors are formed on the semiconductor substrate 10.

[Step-410] Next, in the same manner as in [Step-210] of the second embodiment, a lower insulating layer is formed on the entire surface, and then the selecting transistor T is formed on the lower insulating layer.
_A bit line BL _A electrically connected to one of the source / drain regions 15A of R _A1 and TR _A2 via the connection hole 16 is formed. Then, after forming an upper insulating layer on the entire surface, the upper insulating layer above the other source / drain region 15B of the selecting transistors TR _A1 and TR _A2 and the upper insulating layer are formed in the same manner as in [Step-220] of the second embodiment. Lower insulation layer (insulation layer 1
The opening 18 is formed in the portion 7).

[Step-420] Next, similarly to [Step-130] of the first embodiment, the plug 19 is formed in the opening 18 by a plating method.

[Step-430] Then, in the second embodiment,
Similar to [Step-230] and [Step-240],
On the upper insulating layer (insulating layer 17), the first electrode 21 and
It is composed of an electric conductor layer 22 and a second electrode 23, and has a common first
Electrode 21 (common node CN_A1) Is the first plug 19
Memory unit MU connected to_A1, And common first
Electrode 21 (common node CN_A2) Is the second plug 1
Memory unit MU connected to 9_A2Can get
It After that, an insulating film 27A is formed on the entire surface to make the nonvolatile
Memory M _ATo complete.

(Fifth Embodiment) The fifth embodiment is a preferred form of the non-volatile memory according to the fourth aspect of the present invention, that is, a structure in which N memory units are stacked with an interlayer insulating layer interposed therebetween. And a method for manufacturing the nonvolatile memory according to the fifth aspect of the present invention.
The circuit diagram of the nonvolatile memory according to the fifth embodiment is similar to that shown in FIGS. 15 and 16. FIG. 18 shows a schematic partial cross-sectional view of the nonvolatile memory M _{A according to} the fifth embodiment. Since the nonvolatile memory M _B and the nonvolatile memory M _A which are adjacent to each other in the plate line extending direction have the same structure,
The nonvolatile memory M _A will be described.

The nonvolatile memory M _A of the fifth embodiment is also
(A) a bit line BL _A, (B) N pieces (N ≧ 2, and in the fifth embodiment, N = 2) and the selection transistor TR _AN, (C), respectively are M ( However, M ≧
2 and, in the fifth embodiment, N memory units M each composed of M = 4) memory cells MC _ANM.
It consists of U _AN and (D) M plate lines PL _M.

Then, N memory units MU_AnIs
They are laminated with an interlayer insulating layer interposed therebetween. Each memory cell is
It is composed of a first electrode, a ferroelectric layer and a second electrode. Concrete
Specifically, the first (first layer) memory unit MU_A1
Memory cells MC configuring _A1mIs the first electrode 21
It consists of a ferroelectric layer 22 and a second electrode 23.
(Second layer) memory unit MU_A2Each note that makes up
Resel MC_A2mIs the first electrode 31 and the ferroelectric layer 32
And a second electrode 33. Furthermore, each memory unit
MU_AnIn the memory cell MC_AnmFirst electrode 2
1 and 31 are common. Specifically, the first layer memory
Unit MU_A1In the memory cell MC _A1mThe first of
The electrode 21 is common. This common first electrode 21
1 common node CN_A1Sometimes called. Also, the second layer
Eye memory unit MU_A2In the memory cell MC
_A2mThe first electrode 31 of is common. This common first
The electrode 31 is connected to the second common node CN_A2Sometimes called.
Furthermore, the nth (nth layer) (where n = 1, 2 ...
., N) memory unit MU_AnIn the m-th
(However, m = 1, 2 ..., M)
The electrodes 23 and 33 are connected to the memory unit MU._AnCommon between
M-th plate line PL_mIt is connected to the. Fruit
In the fifth embodiment, more specifically, each plate line
Extend from the second electrodes 23, 33.

Nth (nth layer) (where n = 1, 2
..., N) memory unit MU _AnCommon first in
The first electrode is a plug, and the nth selection transistor T
R_An, Bit line BL through connection hole 16_AConnected to
There is. Specifically, each selection transistor TR_A1, TR
_A2One source / drain region 15A has a connection hole 16
Through bit line BL_AIt is connected to the. Also, the first
Eye selection transistor TR_A1Other source / dray
The region 15B is formed by opening the first layer formed on the insulating layer 17.
The plug 19 of the first layer provided in the mouth portion 18₁Through
The first layer memory unit MU_A1Common first in
1 electrode 21 (first common node CN_A1) Connected to
There is. In addition, the second selection transistor TR_A2Other
The other source / drain region 15B is formed in the insulating layer 17.
Of the first layer provided in the opening 18 of the first layer
Rug 19₂The pad portion 26 and the interlayer insulating layer 27.
The second layer provided in the formed opening 28 of the second layer
Plug 29₁Through the second layer memory unit MU
_A2Common first electrode 31 (second common node C
N_A2)It is connected to the.

Bit line BL_AConnected to the sense amplifier SA
Has been done. Also, the plate line PL_MIs plate line deco
Connected to the driver / driver PD. Furthermore, the word
Line WL ₁, WL₂Is the word line decoder / driver WD
It is connected. Word line WL ₁, WL₂Is the paper of Figure 18
It extends in the direction perpendicular to the plane. In addition, the nonvolatile memory M_ATo
Memory cell MC_A1mThe second electrode 23 of FIG.
8 non-volatile memory M adjacent in the direction perpendicular to the paper surface_BMake up
Memory cell MC_B1mCommon to the second electrode of
Rate line PL_mDoubles as Furthermore, non-volatile memory
M_AMemory cell MC constituting the_A2mThe second electrode 33 of
Nonvolatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BTo
Memory cell MC_B2mCommon to the second electrode of
, Plate line PL_mDoubles as These plates
Line PL_mAre connected in a region not shown.
Also, the word line WL₁Is a non-volatile memory M_AMake up
Selection transistor TR_A1And in the direction perpendicular to the paper surface of FIG.
Adjacent non-volatile memory M_BSelection transitions that make up
Star TR_B1And are common. Furthermore, the word line WL
₂Is a non-volatile memory M_ASelection transistor
TR_A218 and non-volatile memory adjacent in the direction perpendicular to the paper surface of FIG.
Mori M_BSelection transistor TR_B2Common with
Is.

The method of reading data from the non-volatile memory and rewriting it in the fifth embodiment can be the same as the method of reading data from the non-volatile memory and rewriting it in the fourth embodiment. , Detailed description is omitted.

The method of manufacturing the nonvolatile memory according to the fifth embodiment will be described below.

[Step-500] First, in the same manner as in [Step-100] of the first embodiment, N which functions as the selection transistors TR _A1 and TR _A2 in the nonvolatile memory.
Individual MOS type transistors are formed on the semiconductor substrate 10.

[Step-510] Next, in the same manner as in [Step-210] of the second embodiment, a lower insulating layer is formed on the entire surface, and then the selecting transistor T is formed on the lower insulating layer.
_A bit line BL _A electrically connected to one of the source / drain regions 15A of R _A1 and TR _A2 via the connection hole 16 is formed. Then, after forming an upper insulating layer on the entire surface, the upper insulating layer above the other source / drain region 15B of the selecting transistors TR _A1 and TR _A2 and the upper insulating layer are formed in the same manner as in [Step-220] of the second embodiment. Lower insulation layer (insulation layer 1
The opening 18 of the first layer is formed in the portion 7).

[Step-520] Next, similarly to [Step-130] of the first embodiment, the n-th plug is formed in the other source / drain region 15B of the n-th selection transistor TR _An. Connected first layer plug 1
9 ₁ and 19 ₂ are formed on the opening 18 of the first layer by plating.
Form inside.

[Step-530] Then, in the same manner as in [Step-230] and [Step-240] of the second embodiment,
On the upper insulating layer (insulating layer 17), a first electrode 21, a ferroelectric layer 22 and a second electrode 23 are formed, and the common first electrode 21 (common node CN _A1 ) is the first layer. The memory unit MU _A1 connected to the _first plug 19 ₁ of the above can be obtained.

[Step-540] After that, the n'th layer (where n '= 1, 2, ..., N-
1) The interlayer insulating layer is formed, and (N-n ') th (n' + 1) th opening is formed in the n'th interlayer insulating layer, and platinum, iridium, palladium, and rhodium are formed. And a metal selected from the group consisting of ruthenium or an alloy thereof, and the second to the (N−n ′ + 1) th n′th layer
Each of the first to (N-n ') th plugs of the (n' + 1) th layer electrically connected to each of the first to (n '+) th plugs is subjected to (n' +
1) After being formed in the opening of the 1st layer, the common first electrode is connected to the 1st plug of the (n '+ 1) th layer on the n'th interlayer insulating layer. The step of forming the memory unit of the (n ′ + 1) th layer is
n ′ is incremented by 1 from 1 to (N−1) and repeated.

In the fifth embodiment, since N = 2, n '= 1.

Therefore, the first interlayer insulating layer 27 is formed on the entire surface, and (N−n ′ = 1) second layer openings 28 are formed in the first interlayer insulating layer 27. Of the second layer, which is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium, and ruthenium or an alloy thereof, and is electrically connected to the second plug 19 ₂ of the first layer. After forming the _first plug 29 ₁ in the opening 28 of the second layer by the plating method, the common first electrode 3 is formed on the interlayer insulating layer 27 of the first layer.
1 is a memory unit MU _A2 of the second layer connected to the _first plug 29 ₁ of the second layer (composed of the first electrode 31, the ferroelectric layer 32, and the second electrode 33). The memory cell MC _A2m ) is formed. After that, the insulating film 37A is formed on the entire surface.
Are formed to complete the nonvolatile memory M _A.

FIG. 19 shows a modification of the nonvolatile memory according to the fifth embodiment. In the nonvolatile memory shown in FIG. 19, first memory unit MU _A1 constituting the nonvolatile memory M _A is formed on the insulating layer 17, second memory constituting the nonvolatile memory M _A Unit MU _A2
Are formed on the memory unit MU _A1 via the interlayer insulating layer 27, and the first memory unit MU _{B 1} forming the nonvolatile memory M _B is formed on the memory unit MU _A2 via the interlayer insulating layer 37. The second memory unit MU _{B2 that} is formed and constitutes the nonvolatile memory M _B is formed on the memory unit MU _B1 via the interlayer insulating layer 47. The memory cell MC _A1m in the first memory unit MU _A1 forming the nonvolatile memory M _A has a first
Memory cell MC _A2m in the second memory unit MU _A2 is _composed of the first electrode 31 and the ferroelectric layer 3.
2 and the second electrode 33. The memory cell MC _B1m in the first memory unit MU _B1 forming the non-volatile memory M _B is composed of the first electrode 41, the ferroelectric layer 42 and the second electrode 43, and the second electrode Memory cell MC in memory unit MU _B2
B2m is _composed of a first electrode 51, a ferroelectric layer 52, and a second electrode 53.

Then, the other source / drain region 15B of the selection transistor TR _A1 is connected via the plug 19 ₁ provided in the opening 18 formed in the insulating layer 17,
It is connected to the common node CN _A1 of the first memory unit MU _A1 forming the nonvolatile memory M _A. Also,
The other source / drain region 15B of the selection transistor TR _A2, the plug 19 _2, pad portions 26, the plug 29 provided in the interlayer insulating layer 27 in the opening 28 formed
_It is connected via ₁ to the common node CN _A2 of the second memory unit MU _A2 forming the non-volatile memory M _A. Further, the other source of the selection transistor TR _B1 /
The drain region 15B includes a plug 19 ₃ , a pad portion 26,
Via the plug 29 ₂ , the pad portion 36, and the plug 39 ₁ provided in the opening portion 38 formed in the interlayer insulating layer 37,
It is connected to the common node CN _B1 of the first memory unit MU _B1 forming the nonvolatile memory M _B. Also,
The other source / drain region 15B of the selection transistor TR _B2 has a plug 19 ₄ , a pad portion 26, and a plug 2
9 _3, the pad portion 36, the plug 39 _2, pad portions 46, via a plug 49 ₁ provided in the interlayer insulating layer openings 48 formed in the 47, of the second constituting the nonvolatile memory M _B It is connected to the common node CN _B2 of the memory unit MU _B2 .

A modification of the nonvolatile memory shown in FIG. 19 is shown in FIG. In this non-volatile memory, the memory cell MC _A1m forming the first memory unit MU _A1 of the non-volatile memory M _A includes a first electrode 21A, a ferroelectric layer 22A and a second electrode 23. The memory cell MC _B1m forming the first memory unit MU _B1 of the non-volatile memory M _B includes the first electrode 21B and the ferroelectric layer 2.
2B and the second electrode 23. In addition, the memory cell MC _A2m forming the second memory unit MU _A2 of the nonvolatile memory M _A includes the first electrode 31A and the ferroelectric layer 3.
2A and the second electrode 33, and the nonvolatile memory M _B
The memory cell MC _B2m that constitutes the second memory unit MU _B2 includes a first electrode 31B, a ferroelectric layer 32B, and a second electrode 33.

[0157] Furthermore, the first electrode 21A of the memory cells MC _A1m in the memory unit MU _A1 is common in the memory unit MU _A1, common first electrode 21A
The (common node CN _A1 ) is connected to the bit line BL _A via the plug 19 ₁ and the selection transistor TR _A1 . In addition, the memory cell M in the memory unit MU _A2
The first electrode 31A of C _{A 2m} is common in the memory unit MU _A2 , and the common first electrode 31A (common node CN _A2 ) is the plug 29 ₁ , the pad portion 26, the plug 1
9 ₂ , bit line BL _A via selection transistor TR _A2
It is connected to the.

On the other hand, the first electrode 21B of the memory cell MC _B1m in the memory unit MU _B1 is the memory unit M _B1m .
A common first electrode 21B (common node CN _B1 ) common to U _B1 is connected to the bit line BL _B via the plug 19 ₃ and the selection transistor TR _B1 . In addition, the memory cell MC _B2m in the memory unit MU _B2
The first electrode 31B is common to the memory unit MU _B2 , and the common first electrode 31B (common node C
N _B2 ) is a plug 29 ₂ , a pad portion 26, a plug 19 ₄ ,
It is connected to the bit line BL _B via the selection transistor TR _B2 .

The memory cell MC _A1m forming the first memory unit MU _A1 of the non-volatile memory M _A includes the first electrode 21A, the ferroelectric layer 22A and the second electrode 23. The memory cell MC _A2m forming the second memory unit MU _A2 includes the first electrode 21B, the ferroelectric layer 22B, and the second electrode 23, and has a nonvolatile memory M
_The memory cell MC _B1m forming the first memory unit MU _B1 of _B includes a first electrode 31A and a ferroelectric layer 32A.
When composed of a second electrode 33, the memory cell MC _B2m constituting the second memory unit MU _B2 has a structure comprising a first electrode 31B and the ferroelectric layer 32B and a second electrode 33 You can also

[0160] In this case, the first electrode 21A of the memory cells MC _A1m in the memory unit MU _A1 is common in the memory unit MU _A1, common first electrode 21A
The (common node CN _A1 ) is connected to the bit line BL _A via the plug 19 ₁ and the selection transistor TR _A1 . In addition, the memory cell M in the memory unit MU _A2
The first electrode 21B of C _A2m is common in the memory unit MU _A2 , and the common first electrode 21B (common node CN ₂ ) is connected to the bit line BL _A via the plug 19 ₂ and the selection transistor TR _A2. It is connected. Furthermore, the first electrode 31A of the memory cells MC _B1m in the memory unit MU _B1 is common in the memory unit MU _B1, the common first electrode 31A (common node CN _B1) is
It is connected to the bit line BL _B via the plug 29 ₁ , the pad portion 26, the plug 19 ₃ , and the selection transistor TR _B1 . Further, the memory cell M in the memory unit MU _B2
The first electrode 31B of C _B2m is common in the memory unit MU _B2 , and the common first electrode 31B (common node CN _B2 ) is the plug 29 ₂ , the pad portion 26, the plug 1
9 ₄ , bit line BL _B via selection transistor TR _B2
It is connected to the.

FIG. 21 shows a circuit diagram of the nonvolatile memory of the fifth embodiment in the case of N = 4, and FIG. 22 shows a schematic partial sectional view of the nonvolatile memory. In this non-volatile memory, the memory cell MC _1m forming the first (first layer) memory unit MU ₁ of the non-volatile memory M includes a first electrode 21, a ferroelectric layer 22, and a second electrode. consists electrode 23, the memory cell MC _2m constituting the memory unit MU ₂ of the second (second layer) comprises a first electrode 31 and the ferroelectric layer 32 and the second electrode 33. Further, the memory cell MC _3m constituting the memory unit MU ₃ of the third (third layer) includes a first electrode 41 and the ferroelectric layer 42 second
Consists of the electrode 43, the memory cell MC _4m constituting the memory unit MU ₄ of the fourth (fourth layer) is composed of the first electrode 51 and the ferroelectric layer 52 and the second electrode 53 .

The first-layer memory unit MU ₁ is formed on the insulating layer 17. The second-layer memory unit MU ₂ is formed above the first-layer memory unit MU ₁ with the first-layer interlayer insulating layer 27 interposed therebetween. Third
The memory unit MU ₃ of the layer is formed above the memory unit MU ₂ of the second layer with the interlayer insulating layer 37 of the second layer interposed therebetween. The memory unit MU ₄ of the fourth layer is
It is formed above the third-layer memory unit MU ₃ via the third-layer interlayer insulating layer 47.

Furthermore, the first electrode 21 of the memory cell MC _1m in the memory unit MU ₁ is the memory unit MU.
_The common first electrode 21 (common node CN ₁ ) is connected to the bit line BL via the _first plug 19 ₁ of the first layer and the selection transistor TR ₁ . The first electrode 31 of the memory cells MC _2m in the memory unit MU ₂ is common in the memory unit MU _2, the common first electrode 31 (common node CN _2), the 1st second layer 29 ₁ , the pad portion 26, the second plug 19 ₂ of the first layer, and the selection transistor TR ₂ are connected to the bit line BL. Further, the memory cell M in the memory unit MU ₃
The first electrode 41 of C _3m is common in the memory unit MU ₃ , and the common first electrode 41 (common node C
N ₃ ) is the first plug 39 ₁ of the third layer, the pad portion 36, the second plug 29 ₂ of the second layer, the pad portion 2
6, the third plug 19 ₃ of the first layer, and the selection transistor TR ₃ are connected to the bit line BL.
The memory cells MC _4m in the memory unit MU ₄
The first electrode 51 of the memory unit MU ₄ is common, and the common first electrode 51 (common node CN ₄ )
Is the first plug 49 ₁ of the fourth layer and the pad portion 4
6, the second plug 39 ₂ of the third layer, the pad portion 3
6, third plug 29 ₃ of the second layer, pad portion 2
6, the fourth plug 19 ₄ of the first layer, and the selection transistor TR ₄ are connected to the bit line BL.

Here, since N = 4, n '= 1,
It becomes a few.

Therefore, in the manufacture of this non-volatile memory, in [Step-540], the first interlayer insulating layer 27 is formed on the entire surface, and (N−n ′ = 3) second insulating layers 27 are formed. The opening 28 of the first layer is formed in the interlayer insulating layer 27 of the first layer and is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, and the second layer of the first layer is formed. From th to (N-n '+ 1 =
4) Each of the first to third plugs 29 ₁ , 29 ₂ , 29 ₃ of the second layer, which are electrically connected to each of the plugs 19 ₂ , 19 ₃ , 19 _{4 up to} the _4th , The common first electrode 3 is formed on the first-layer interlayer insulating layer 27 after the second-layer opening 28 is formed by the plating method.
1 (common node CN ₂ ) forms the second layer memory unit MU ₂ connected to the _first plug 29 ₁ of the second layer.

Next, a second interlayer insulating layer 37 is formed on the entire surface, and (N−n ′ = 2) third layer openings 38 are formed in the second interlayer insulating layer 37. A metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, and the second to second (N−n ′ + 1 =
3) Each of the first to second plugs 39 ₁ and 39 ₂ of the third layer, which is electrically connected to each of the plugs 29 ₂ and 29 ₃ up to the third, is connected to the third plug based on the plating method.
After being formed in the opening 38 of the first layer, the common first electrode 4 is formed on the interlayer insulating layer 37 of the second layer.
1 (common node CN ₃ ) forms the memory unit MU ₃ of the third layer, which is connected to the _first plug 39 ₁ of the third layer.

Then, a third interlayer insulating layer 47 is formed on the entire surface, and (N−n ′ = 1) fourth layer openings 48 are formed in the third interlayer insulating layer 47. Of the fourth layer, which is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium, and ruthenium or an alloy thereof, and which is electrically connected to the second plug 39 ₂ of the third layer. After forming the _first plug 49 ₁ in the opening 48 of the fourth layer by plating, the common first electrode 5 is formed on the interlayer insulating layer 47 of the third layer.
1 (common node CN ₄ ) forms a fourth layer memory unit MU ₄ connected to the _first plug 49 ₁ of the fourth layer.

A modification of the nonvolatile memory shown in FIG. 22 is shown in FIG. In this non-volatile memory, the memory cell MC _1m forming the first-layer memory unit MU ₁ of the non-volatile memory M includes a first electrode 21A, a ferroelectric layer 22A, and a second electrode 23. , the memory cell MC _2m constituting the memory unit MU ₂ of the second layer is composed of a first electrode 21B and the ferroelectric layer 22B and a second electrode 23. Further, the memory cell MC _3m constituting the memory unit MU ₃ of the third layer comprises a first electrode 31A and the ferroelectric layer 32A and a second electrode 33, the fourth layer of the memory unit MU ₄ The memory cell MC _4m constituting the above is composed of a first electrode 31B, a ferroelectric layer 32B and a second electrode 33.

Further, the first electrode 21A of the memory cell MC _1m in the memory unit MU ₁ is the memory unit M 1
A common first electrode 21A (common node CN ₁ ) common to U ₁ is connected to the bit line BL via the plug 19 ₁ and the selection transistor TR ₁ . Also,
First memory cell MC _2m in the memory unit MU ₂
Electrode 21B of the memory unit MU ₂ is common, and the common first electrode 21B (common node CN ₂ ) is
It is connected to the bit line BL via the plug 19 ₂ and the selecting transistor TR ₂ .

On the other hand, the first electrode 31A of the memory cell MC _3m in the memory unit MU ₃ is the memory unit MU.
_The common first electrode 31A (common node CN ₃ ) is common to all bit lines ₃ via the plug 29 ₁ , the pad section 26, the plug 19 ₃ and the selection transistor TR _3.
It is connected to the. Furthermore, the first electrode 31B of the memory cell MC _4m in the memory unit MU ₄ is common in the memory unit MU _4, the common first electrode 31B
The (common node CN ₄ ) includes a plug 29 ₂ , a pad portion 26,
It is connected to the bit line BL via the plug 19 ₄ and the selection transistor TR ₄ .

(Embodiment 6) Embodiment 6 relates to a nonvolatile memory according to a fifth aspect of the present invention and a method for manufacturing a nonvolatile memory according to the sixth aspect of the present invention. 24 and 25 are schematic circuit diagrams of the nonvolatile memory according to the sixth embodiment, FIG. 26 is a circuit diagram of the memory unit, and FIG. 27 is a schematic partial cross-sectional view of the nonvolatile memory. In FIG. 27, the nonvolatile memory M _A is illustrated. Since the nonvolatile memory M _B and the nonvolatile memory M _A which are adjacent to each other in the plate line extending direction have the same structure,
The nonvolatile memory M _A will be described below.

The nonvolatile memory M _{A according to the} sixth embodiment is
(A) N present (N ≧ 2, and in the sixth embodiment, N = 2) and the bit line BL _AN of, and (B) N number of selection transistors TR _AN, respectively (C) M (however, M ≧ 2, and M = 8 in the sixth embodiment)
Memory cells MC _{ANM of} N memory units MU _AN and (D) M plate lines PL _M.

Then, N memory units MU_AnIs
They are laminated with an interlayer insulating layer interposed therebetween. Each memory cell is
It is composed of a first electrode, a ferroelectric layer and a second electrode. Concrete
Specifically, the first-layer memory unit MU_A1Each of the
Memory cell MC_A1mIs the first electrode 21 and the ferroelectric layer 2
2 and the second electrode 23, the memory unit of the second layer.
MU_A2Memory cells MC configuring_A2mIs the first
It is composed of an electrode 31, a ferroelectric layer 32 and a second electrode 33.
It Furthermore, each memory unit MU_AnAt the memory
Cell MC_AnmThe first electrodes 21 and 31 of are common. Ingredient
Physically, the memory unit MU of the first layer_A1At
Memory cell MC_A1mThe first electrode 21 of is common. This
Of the common first electrode 21 of the first common node CN_A1Call
There are cases where In addition, the memory unit MU of the second layer_A2
In the memory cell MC_A2mThe first electrode 31 of is common
Is. This common first electrode 31 is connected to the second common node
CN _A2Sometimes called. Furthermore, the nth layer (however, n
= 1, ..., N) memory unit MU_Ansmell
The m-th memory (however, m = 1, 2, ..., M)
The second electrodes 23 and 33 of the cell are connected to the memory unit MU._An
The m-th plate line PL that is common between_mConnected to
Has been. In the sixth embodiment, more specifically,
Each plate line extends from the second electrode 23, 33.
And are connected in a region (not shown).

The nth layer (however, n = 1, 2, ..., N)
The common first electrode in the memory unit MU _An of
It is connected to the n-th bit line BL _An via the plug, the n-th selection transistor TR _An , and the connection hole 16. Specifically, the nth selection transistor TR _An
One of the source / drain regions 15A is connected to the n-th bit line BL _An via the connection hole 16. On the other hand, the other source / drain region 15B of the first selection transistor TR _A1 is the first plug of the first layer provided in the opening 18 of the first layer formed in the insulating layer 17. 19 ₁ via the first layer memory unit MU
Common first electrode 21 at _A1 (first common node C
N _A1 ). Also, the other source / drain region 15B of the second selection transistor TR _A2
Is the second plug 19 ₂ of the first layer provided in the insulating layer 17, the pad portion 26, and the second plug 28 provided in the opening portion 28 of the second layer formed in the interlayer insulating layer 27. It is connected to the common first electrode 31 (second common node CN _A2 ) in the memory unit MU _A2 of the second layer via the _first plug 29 ₁ of the layer.

Bit line BL_AnConnected to the sense amplifier SA
Has been done. Also, the plate line PL _MIs plate line deco
Connected to the driver / driver PD. Furthermore, the word
Line WL₁, WL₂Is the word line decoder / driver WD
It is connected. Word line WL₁, WL₂Is the paper in Figure 27
It extends in the direction perpendicular to the plane. In addition, the nonvolatile memory M_ATo
Memory cell MC_A1mThe second electrode 23 of FIG.
7 non-volatile memory M adjacent in the direction perpendicular to the paper surface_BMake up
Memory cell MC_B1mCommon to the second electrode of
Rate line PL_mDoubles as Furthermore, non-volatile memory
M_AMemory cell MC constituting the_A2mThe second electrode 33 of
Nonvolatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BTo
Memory cell MC_B2mCommon to the second electrode of
, Plate line PL_mDoubles as These plates
Line PL_mAre connected in a region not shown.
Also, the word line WL₁Is a non-volatile memory M_AMake up
Selection transistor TR_A1And in the direction perpendicular to the paper surface of FIG.
Adjacent non-volatile memory M_BSelection transitions that make up
Star TR_B1And are common. Furthermore, the word line WL
₂Is a non-volatile memory M_ASelection transistor
TR_A2And non-volatile memory adjacent in the direction perpendicular to the paper surface of FIG.
Mori M_BSelection transistor TR_B2Common with
Is.

In the nonvolatile memory according to the sixth embodiment whose circuit diagrams are shown in FIGS. 24 and 25, the selection transistors TR _A1 and TR _B1 forming the nonvolatile memories M _A and M _B are selected.
Are connected to the same word line WL ₁ , and the selection transistors TR _A2 and TR _B2 are connected to the same word line WL ₂ .

In the nonvolatile memory whose circuit diagram is shown in FIG. 24, a pair of memory cells MC _A1m , MC
1-bit data complementary to _A2m (m = 1, 2, ..., M) is stored. A method of reading data from the nonvolatile memory of the sixth embodiment and rewriting the data is as follows.
Since the operation can be substantially the same as that of the nonvolatile memory according to the second embodiment described with reference to FIG. 8, detailed description will be omitted. Alternatively, by independently controlling the memory cell MC _A1m and the memory cell MC _A2m and applying the reference voltage to one of the paired bit lines BL _A1 and BL _A2 , the memory cells MC _A1m and MC _A2m are respectively _supplied . 1-bit data is read from. Embodiment 6 as described above
The method of reading data from the non-volatile memory and rewriting the data can be substantially the same as the operation of the non-volatile memory according to the second embodiment described with reference to FIG. Omit it.

Alternatively, in the nonvolatile memory whose circuit diagram is shown in FIG. 25, a pair of memory cells MC _Anm ,
MC _Bnm (n = 1, 2, ..., N, m = 1, 2 ...
.., M) is stored as complementary 1-bit data.
The method of reading data from the nonvolatile memory of the sixth embodiment and rewriting the data may be substantially the same as the operation of the nonvolatile memory of the second embodiment described with reference to FIG. Therefore, detailed description is omitted.

The bit line BL_A1And bit line BL_B2The
Sense amplifier SA₁Connected to the bit line BL_A2And bit line
BL_B1Sense amplifier SA₂Be configured to connect to
You can also In this case, the paired memory cell MC_A1m，
MC_B2m, Or a pair of memory cells MC_A2m, M
C_B1m1-bit complementary to (m = 1, 2, ..., M)
The data is stored. Such a nonvolatile memory according to the sixth embodiment
To read and rewrite data from non-volatile memory
Substantially corresponds to that of the second embodiment described with reference to FIG.
Since it can be similar to the operation of the non-volatile memory,
Detailed description is omitted. Alternatively, the memory cell MC
_AnmAnd memory cell MC_BnmIndependently controlled and paired
By applying a reference voltage to one of the bit lines,
Memory cell MC _Anm, MC_Bnm1 bit from each of
Read the data. Nonvolatile of Embodiment 6
How to read data from memory and rewrite
Substantially, the second embodiment described with reference to FIG.
Since it can be similar to the operation of volatile memory,
Detailed explanation is omitted.

The method of manufacturing the nonvolatile memory according to the sixth embodiment will be described below.

[Step-600] First, in the same manner as in [Step-100] of the first embodiment, N which functions as the selection transistors TR _A1 and TR _A2 in the nonvolatile memory is formed.
Individual MOS type transistors are formed on the semiconductor substrate 10.

[Step-610] Next, in the same manner as in [Step-210] of the second embodiment, a lower insulating layer is formed on the entire surface, and then the selecting transistor T is formed on the lower insulating layer.
A bit line BL _A1 electrically connected to one of the source / drain regions 15A of R _A1 and TR _A2 through a connection hole 16.
Form BL _A2 . Then, after forming an upper insulating layer on the entire surface, in the same manner as in [Step-220] of the second embodiment,
The opening 18 of the first layer is formed in the upper insulating layer and the lower insulating layer (insulating layer 17) above the other source / drain region 15B of the selecting transistors TR _A1 and TR _A2 .

[Step-620] Next, similarly to [Step-130] of the first embodiment, the n-th plug is formed in the other source / drain region 15B of the n-th selection transistor TR _An. Connected first layer plug 1
9 ₁ and 19 ₂ are formed on the opening 18 of the first layer by plating.
Form inside.

[Step-630] Then, in the same manner as [Step-230] and [Step-240] of the second embodiment,
On the upper insulating layer (insulating layer 17), a first electrode 21, a ferroelectric layer 22 and a second electrode 23 are formed, and the common first electrode 21 (common node CN _A1 ) is the first layer. The memory unit MU _A1 connected to the _first plug 19 ₁ of the above can be obtained.

[Step-640] After that, the n'th layer (where n '= 1, 2, ..., N-
1) The interlayer insulating layer is formed, and (N-n ') th (n' + 1) th opening is formed in the n'th interlayer insulating layer, and platinum, iridium, palladium, and rhodium are formed. And a metal selected from the group consisting of ruthenium or an alloy thereof, and the second to the (N−n ′ + 1) th n′th layer
Each of the first to (N-n ') th plugs of the (n' + 1) th layer electrically connected to each of the first to (n '+) th plugs is subjected to (n' +
1) After being formed in the opening of the 1st layer, the common first electrode is connected to the 1st plug of the (n '+ 1) th layer on the n'th interlayer insulating layer. The step of forming the memory unit of the (n ′ + 1) th layer is
n ′ is incremented by 1 from 1 to (N−1) and repeated.

In the fifth embodiment, since N = 2, n '= 1.

Therefore, the first interlayer insulating layer 27 is formed on the entire surface, and (N−n ′ = 1) second layer openings 28 are formed in the first interlayer insulating layer 27. Of the second layer, which is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium, and ruthenium or an alloy thereof, and is electrically connected to the second plug 19 ₂ of the first layer. After forming the _first plug 29 ₁ in the opening 28 of the second layer by the plating method, the common first electrode 3 is formed on the interlayer insulating layer 27 of the first layer.
1 is a memory unit MU _A2 of the second layer connected to the _first plug 29 ₁ of the second layer (composed of the first electrode 31, the ferroelectric layer 32, and the second electrode 33). The memory cell MC _A2m ) is formed. After that, the insulating film 37A is formed on the entire surface.
Are formed to complete the nonvolatile memory M _A.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these. The structure of the nonvolatile memory described in the embodiments of the invention, the materials used, various forming conditions, circuit configurations, driving methods, etc. are merely examples, and can be changed as appropriate. A so-called planar nonvolatile memory can be manufactured by the method for manufacturing a nonvolatile memory according to the first aspect of the present invention. That is, the structure of the non-volatile memory according to the first aspect of the present invention may be a planar type.

A non-volatile memory manufactured by the method for manufacturing a non-volatile memory according to any of the second to sixth aspects of the present invention, or a non-volatile memory according to any of the second to fifth aspects of the present invention. The memory may be of a so-called gain cell type. Second Embodiment of Gain Cell Type Nonvolatile Memory
FIG. 28 shows a circuit diagram when applied to the nonvolatile memory described in FIG. 28, and FIG. 29 shows a schematic layout of various transistors constituting this nonvolatile memory. Sectional views are shown in FIG. 30 and FIG.
Shown in 1. Further, FIG. 32 illustrates a circuit diagram when the gain cell type nonvolatile memory is applied to the nonvolatile memory described in the fifth embodiment. Note that in FIG. 29, regions of various transistors are surrounded by dotted lines, active regions and wiring layers are shown by solid lines, and gate electrodes or word lines are shown by dashed lines. A schematic partial cross-sectional view of the nonvolatile memory shown in FIG. 30 is a schematic partial cross-sectional view taken along the line AA of FIG. 29, and a schematic partial cross-sectional view of the nonvolatile memory shown in FIG. The partial cross-sectional view is a schematic partial cross-sectional view taken along the line BB of FIG.

This nonvolatile memory M _A is, for example, a bit line BL _A , a writing transistor (which is a selection transistor in the second embodiment) TR _AW , and M (however, M ≧ 2, For example, M = 8) memory cell MC
It is composed of a memory unit MU _A composed of _AM and M plate lines PL _M. Each memory cell MC _AM comprises a first electrode 21 and the ferroelectric layer 22 and a second electrode 23, first electrode 21 of the memory cells MC _AM constituting the memory unit MU _A includes a memory is common in the unit MU _a, the common first electrode (common node CN _a) via the transistor for writing TR _AW is connected to the bit line BL _a, the constituting each memory cell MC _{a m} The second electrode 23 is connected to the plate line PL _m . The illustration of the adhesion layer is omitted. Number of memory cells (M) that make up the memory unit MU _A of the nonvolatile memory
Is not limited to eight, and in general, M ≧ 2 may be satisfied, and a power of 2 (M = 2, 4, 8, 16 ...) Is preferable.

Furthermore, the potential change of the common first electrode is detected.
The detection result is output to the bit line BL. _AWith current or voltage
A signal detection circuit for transmitting the signal is provided. In other words
For example, the detection transistor TR_AS, And read transition
Star TR_ARIs equipped with. That is, the signal detection circuit detects
Transistor TR_ASAnd read transistor TR_AROr
It is composed of Then, the detection transistor TR_AS
One end has a predetermined potential V_ccA wiring layer having
Connected to the power supply line composed of the physical layer, and the other end is for reading
Transistor TR_ARVia the bit line BL_AConnected to
Each memory cell MC_AmThe data stored in the
When read transistor TR_ARIs turned on, and each
Morisell MC_AmCommon first based on data stored in
Electrode (common node CN_A) Is detected by the potential generated in
Transistor TR_ASIs controlled.

Specifically, various transistors are MOS
Type FET, and one source / drain region 15A of the writing transistor (selecting transistor) TR _AW is connected to the bit line BL _A through a connection hole (contact hole) 16 formed in the insulating layer 17. The other source / drain region 15B is connected to the common first electrode (common node CN _A ) via the plug 19 provided in the opening 18 formed in the insulating layer 17. There is. Further, one source / drain region of the detection transistor TR _AS is connected to a wiring layer having a predetermined potential V _cc , and the other source / drain region is connected to one source / drain region of the read transistor TR _AR. It is connected. More specifically, the detection transistor TR _AS
Of the other source / drain region and the read transistor T
One source / drain region of R _AR occupies one source / drain region. Further, the other source / drain region of the read transistor TR _AR is connected to the bit line BL _A via a connection hole (contact hole) 16, and further, a common first electrode (common node CN _A , or The other source / drain region of the write transistor TR _AW ) is connected to the gate electrode of the detection transistor TR _{A S} via the plug 19A provided in the opening and the word line WL _S. In addition, the writing transistor T
The word line WL _W connected to the gate electrode of R _AW and the word line WL _R connected to the gate electrode of the read transistor TR _AR are connected to the word line decoder / driver WD. On the other hand, each plate line PL _m is connected to the plate line decoder / driver PD. Furthermore, the bit line BL _A is connected to the sense amplifier SA.

Memory cell MC of this nonvolatile memory_A1Or
When reading data from the selected plate line PL₁To V_cc
Is applied. At this time, the selected memory cell MC_A1To the data
If "1" is stored, polarization inversion will occur in the ferroelectric layer.
Then, the amount of accumulated charge increases and the common node CN_APotential is higher
Rise. On the other hand, the selected memory cell MC_A1Data "0"
If it is remembered, no polarization reversal will occur in the ferroelectric layer, and
Communication node CN_AThe electric potential of is hardly increased. That is, common
CN_AThrough the ferroelectric layer of unselected memory cells
Multiple non-selected plate lines PL_jCoupling to (j ≠ 1)
Common node CN_APotential of 0 volt
Maintained at a level relatively close to. In this way, select
Memory cell MC_A1Depending on the data stored in
CN _AA change occurs in the potential of. Therefore, select memory
An electric field sufficient for polarization reversal is applied to the ferroelectric layer of the cell
be able to. And the bit line BL_AFloating
Read transistor TR_ARIs turned on. one
The selected memory cell MC_A1Based on the data stored in
Common first electrode (common node CN_A) To the potential
From the detection transistor TR_ASIs controlled.
Specifically, the selected memory cell MC_A1Data stored in
Based on the common first electrode (common node CN_AHigh)
If a potential is generated, the detection transistor TR_ASIs conductive
And the detection transistor TR_ASOne source / do
The rain region has a predetermined potential V_ccIs connected to the wiring layer having
Therefore, from the wiring layer, the detection transistor T
R_ASAnd read transistor TR_ARThrough bit line B
L_ACurrent flows to the bit line BL_AThe potential of rises. Immediately
Then, the signal detection circuit causes a common first electrode (common no
De CN_A) Potential change is detected.
Line BL_AIs transmitted as a voltage (potential) to. here,
Detection transistor TR_ASThe threshold of V_th, Detection tran
Dista TR_ASPotential of the gate electrode (that is, the common node C
N_APotential)_gIf so, the bit line BL_AThe potential of
Ne (V_g-V_th). The detection transistor TR
_ASIs a depletion type NMOSFET,
Value V_thTakes a negative value. As a result, the bit line BL_Aof
A stable sense signal amount can be secured regardless of the size of the load.
Wear. The detection transistor TR_ASPMOSFET
It can also consist of

Since such a gain cell type nonvolatile memory can be manufactured substantially by the manufacturing method described in the second embodiment, detailed description thereof will be omitted. Further, such a gain cell type non-volatile memory can be applied to the non-volatile memories described in the third to sixth embodiments.

The predetermined potential of the wiring layer to which one end of the detection transistor is connected is not limited to _Vcc and may be grounded, for example. That is, the predetermined potential of the wiring layer to which one end of the detection transistor is connected may be 0 volt. However, in this case, when the potential (V _cc ) appears on the bit line when reading the data in the selected memory cell, the potential of the bit line is set to 0 volt when rewriting, and 0 when reading the data in the selected memory cell. When the volt appears on the bit line, it is necessary to set the potential of the bit line to V _cc when rewriting. To that end, the transistors TR _IV-1 , TR shown in FIG.
A type of switch circuit (inversion circuit) composed of _IV-2 , TR _IV-3 , and TR _IV-4 is arranged between the bit lines, and when reading data, the transistors TR _IV-2 and TR _IV-4 are connected. The transistor T is turned on when data is rewritten.
R _IV-1 and TR _IV-3 may be turned on.

Further, for example, as shown in FIG. 34, as a modification of the nonvolatile memory of the fifth embodiment, the first electrodes 21 'and 31' are upper electrodes and the second electrodes 23 'and 3'
3'can also be used as the lower electrode. Such a structure can also be applied to the nonvolatile memory according to the other embodiments of the invention.

FIG. 20 and FIG. 23 show an example in which two memory cells are constituted by a laminated structure of first electrode / ferroelectric layer / second electrode / ferroelectric layer / first electrode. Alternatively, however, two memory cells can be formed by a laminated structure of the second electrode / ferroelectric layer / first electrode / ferroelectric layer / second electrode.

The semiconductor memory manufacturing method of the present invention can be applied not only to a ferroelectric non-volatile semiconductor memory using a ferroelectric thin film (so-called FERAM) but also to a DRAM. In this case, the polarization of the ferroelectric layer is used within the range of the additional voltage at which polarization reversal does not occur. That is, the difference (P _max -P _r ) between the maximum (saturation) polarization P _{max due} to the external electric field and the remanent polarization P _r when the external electric field is 0 has a constant relationship (a relationship that is substantially proportional) with the power supply voltage. Utilizing the property that has. The polarization state of the ferroelectric layer is always between the saturation polarization (P _max ) and the remanent polarization (P _r ) and does not reverse.
Data is retained by refresh. Alternatively,
Having a high dielectric constant and a perovskite structure or a pseudo-perovskite structure, such as BaTiO ₃ , SrTiO ₃ ,
It is also possible to form a ferroelectric layer by using a dielectric thin film made of (Ba, Sr) TiO ₃ to form a DRAM.

[0199]

According to the present invention, osmium (Os)
However, unlike the case where a plug made of tungsten is formed by a CVD method, a plug made of a platinum group metal or an alloy thereof is formed without using hydrogen gas, and a ferroelectric layer is formed. Oxides as the ferroelectric material that composes are reliably exposed to a hydrogen gas atmosphere and reduced, and the occurrence of problems such as deterioration of the ferroelectric characteristics and peeling of the ferroelectric layer from the electrodes can be reliably prevented. be able to. Further, it is possible to avoid the problem that the atoms of the material forming the first electrode and the atoms of the conductive material forming the plug mutually diffuse. As a result of the above,
It is possible to obtain a ferroelectric non-volatile semiconductor memory having high reliability.

[Brief description of drawings]

FIG. 1 is a schematic partial end view of a semiconductor substrate or the like for explaining a method of manufacturing a ferroelectric non-volatile semiconductor memory according to a first embodiment of the present invention.

2 is a schematic partial end view of a semiconductor substrate and the like for explaining the method for manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention, following FIG. 1;

FIG. 3 is a schematic partial end view of a semiconductor substrate and the like for explaining the method for manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a schematic partial end view of a semiconductor substrate or the like for explaining the method of manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a schematic partial end view of a semiconductor substrate or the like for explaining the method for manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a circuit diagram of the ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention.

FIG. 7 is a circuit diagram of a ferroelectric non-volatile semiconductor memory according to a second embodiment of the invention.

FIG. 8 is a diagram showing operation waveforms in the ferroelectric non-volatile semiconductor memory according to the second embodiment of the invention.

FIG. 9 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a second embodiment of the invention.

FIG. 10 is a circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the second embodiment of the invention.

11 is a diagram showing operation waveforms in a modification of the ferroelectric non-volatile semiconductor memory according to the second embodiment of the invention shown in FIG.

FIG. 12 is a circuit diagram of a ferroelectric non-volatile semiconductor memory according to a third embodiment of the invention.

FIG. 13 is a circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

FIG. 14 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a third embodiment of the invention.

FIG. 15 is a circuit diagram of a ferroelectric non-volatile semiconductor memory according to a fourth embodiment of the invention.

FIG. 16 is a circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the fourth embodiment of the invention.

FIG. 17 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a fourth embodiment of the invention.

FIG. 18 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a fifth embodiment of the invention.

FIG. 19 is a schematic partial cross-sectional view of a modification of the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the invention.

FIG. 20 is a schematic partial cross-sectional view of another modification of the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the invention.

FIG. 21 is a circuit diagram of still another modification of the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the invention.

FIG. 22 is a schematic partial cross-sectional view of still another modification of the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the invention.

FIG. 23 is a schematic partial cross-sectional view of still another modification of the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the invention.

FIG. 24 is a circuit diagram conceptual diagram of a ferroelectric non-volatile semiconductor memory according to a sixth embodiment of the invention.

FIG. 25 is a conceptual diagram of another circuit diagram of the ferroelectric non-volatile semiconductor memory according to the sixth embodiment of the invention.

FIG. 26 is a circuit diagram of a memory unit in a ferroelectric non-volatile semiconductor memory according to a sixth embodiment of the invention.

FIG. 27 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a sixth embodiment of the invention.

FIG. 28 is a circuit diagram when a gain cell type ferroelectric non-volatile semiconductor memory is applied to the ferroelectric type non-volatile semiconductor memory described in the second embodiment of the invention.

29 is a layout diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 28. FIG.

30 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG.

31 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG. 28 when seen in a cross section different from FIG. 30.

FIG. 32 is an example of a circuit diagram when a gain cell type ferroelectric non-volatile semiconductor memory is applied to the ferroelectric non-volatile semiconductor memory described in the fifth embodiment of the invention.

FIG. 33 is a circuit diagram showing a kind of switch circuit arranged between bit lines when a predetermined potential of a wiring layer to which one end of a detection transistor is connected is set to 0 volt.

FIG. 34 is a schematic partial cross-sectional view of another modification of the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the invention.

FIG. 35 is a PE hysteresis loop diagram of a ferroelectric substance.

[Explanation of symbols]

10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode,
14 ... Gate side wall, 15A, 15B ...
・ Source / drain regions, 16 ... Connection holes (contact holes), 17 ... Insulating layers, 18, 28, 38, 4
8 ... Opening part, 19, 29, 39, 49 ... Connection hole 21,21A, 21B, 21 ', 31, 31A, 3
1B, 31 '... 1st electrode, 22, 22A, 22
B, 32, 32A, 32B ... Ferroelectric layer, 23, 2
3 ', 33, 33' ... second electrode, 24, 27A,
37A, 57A ... Insulating film, 26, 36, 46 ...
Pad portion, 27, 37, 47 ... Interlayer insulating layer, M ...
・ Non-volatile memory, MU ... Memory unit, MC
..Memory cells, TR ... Selection transistors, WL
・ ・ ・ Word line, BL ・ ・ ・ Bit line, PL ・ ・ ・ Plate line, WD ・ ・ ・ Word line decoder / driver, SA
... Sense amplifier, PD ... Plate line decoder /
Driver, CN ... Common node

Continued front page    F term (reference) 5F083 AD21 FR01 FR02 FR03 FR10                       GA21 GA25 JA14 JA15 JA17                       JA19 JA38 JA39 JA40 JA43                       JA44 KA06 KA19 MA06 MA17                       MA19 MA20 PR21 PR22 PR23                       PR33

Claims (12)

[Claims] 1. A process of forming a selecting transistor on a semiconductor substrate, and (b) a part of the insulating layer above one source / drain region of the selecting transistor after forming an insulating layer on the entire surface. A step of forming an opening in the opening, and (c) forming a plug made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof in the opening by a plating method. (D) forming on the insulating layer a memory cell comprising a first electrode, a ferroelectric layer and a second electrode, the first electrode being connected to the plug. A method for manufacturing a ferroelectric non-volatile semiconductor memory, which is characterized. 2. (A) a bit line, (B) a selection transistor, (C) a memory unit composed of M memory cells (where M ≧ 2), and (D) M plates. Line, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in the memory unit, the first electrode of the memory cell is common and the common first The electrode is connected to the bit line through the plug, the selection transistor, and the connection hole, and in the memory unit, the m-th electrode (where m = 1, 2,
, M) is a method for manufacturing a ferroelectric non-volatile semiconductor memory in which the second electrode of the memory cell is connected to the m-th plate line. And (b) after forming the lower insulating layer on the entire surface, a bit line electrically connected to one of the source / drain regions of the selecting transistor on the lower insulating layer through a connection hole. And (c) forming an upper insulating layer on the entire surface and then forming an opening in the upper insulating layer and lower insulating layer above the other source / drain region of the selecting transistor. (D) a step of forming a plug made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof in the opening by a plating method; On the insulating layer, the ferroelectric-type nonvolatile method of manufacturing a semiconductor memory in which the common first electrode is characterized by comprising the steps of forming a memory unit connected to the plug. 3. A number of (A) bit lines, (B) selection transistors, and (C) M (where M ≧ 2) memory cells, each of which is N (where N ≧ 2). ) Memory unit and (D) M × N plate lines, N memory units are stacked with an interlayer insulating layer in between, and each memory cell has a first electrode and a ferroelectric layer. The memory cell includes a body layer and a second electrode, and in each memory unit, the first electrode of the memory cell is common, and the common first electrode is the bit through the plug, the selection transistor, and the connection hole. Connected to the line, in the n-th layer (where n = 1, 2, ..., N) memory unit, the m-th (where m = 1, 2 ...
The second electrode of the M) th memory cell is the [(n-1) M +
A method of manufacturing a ferroelectric non-volatile semiconductor memory connected to a [m] th plate line, comprising: (a) forming a selection transistor on a semiconductor substrate; and (b) forming a lower insulating layer on the entire surface. After that, a step of forming a bit line electrically connected to one source / drain region of the selection transistor through a connection hole on the lower insulating layer, and (c) forming an upper insulating layer on the entire surface. After that, a step of forming a first-layer opening in the upper insulating layer and the lower insulating layer above the other source / drain region of the selection transistor, and (d) platinum, iridium, palladium, rhodium And a step of forming a plug of a first layer made of a metal selected from the group consisting of ruthenium or an alloy thereof in the opening of the first layer by plating, (e) on the upper insulating layer A step of forming a memory unit of a first layer in which a common first electrode is connected to the plug of the first layer, and (f) an n'th layer (however, n '= 1, 2 ...
., N-1) an interlayer insulating layer is formed, an opening of the (n '+ 1) th layer is formed in the n'th interlayer insulating layer, and platinum, iridium, palladium, rhodium and ruthenium are used. A (n ′ + 1) th layer plug made of a metal selected from the group or an alloy thereof is electrically connected to the (n ′ + 1) th layer plug by the plating method. After being formed in the eye opening, the common first electrode is connected to the (n ′ + 1) th layer plug on the (n ′ + th) layer interlayer insulating layer.
1) In the step of forming the memory unit of the first layer, n ′ is set to 1
To (N-1) are incremented by one and repeated, and the method is for manufacturing a ferroelectric non-volatile semiconductor memory. 4. An (A) bit line, (B) N (where N ≧ 2) selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells. In addition, each memory cell includes N memory units and (D) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode of the cell is common, and the common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is the plug, the n-th selection transistor, and It is connected to the bit line through the connection hole, and in the nth memory unit, the mth memory unit (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A method of manufacturing a ferroelectric non-volatile semiconductor memory connected to a m-th plate line shared between memory units, comprising: (a) forming N selection transistors on a semiconductor substrate; (B) a step of forming a lower insulating layer on the entire surface, and then forming a bit line electrically connected to one source / drain region of each selection transistor through a connection hole on the lower insulating layer And (c) forming an upper insulating layer on the entire surface, and then forming an opening in the upper insulating layer and the lower insulating layer above the other source / drain region of each selection transistor, and (d) ) A metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, wherein the nth plug is the other source / drain of the nth selection transistor. Forming a plug connected to the rain region in the opening based on a plating method; and (e) forming an n-th plug in which a common first electrode is connected to the n-th plug on the upper insulating layer. A step of forming a th memory unit, and a method for manufacturing a ferroelectric non-volatile semiconductor memory. 5. An (A) bit line, (B) N (where N ≧ 2) selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells. In addition, the memory cell includes N memory units and (D) M plate lines. The N memory units are stacked with an interlayer insulating layer interposed therebetween, and each memory cell has a first electrode and a strong electrode. The memory unit of the nth layer (where n = 1, 2, ..., N) is composed of a dielectric layer and a second electrode, and the first electrode of the memory cell is common in each memory unit. Is connected to the bit line through the plug, the n-th selection transistor and the connection hole, and in the memory unit of the n-th layer, the m-th electrode (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A method of manufacturing a ferroelectric non-volatile semiconductor memory connected to a m-th plate line shared between memory units, comprising: (a) forming N selection transistors on a semiconductor substrate; (B) a step of forming a lower insulating layer on the entire surface and then forming a bit line electrically connected to one source / drain region of each selection transistor through a connection hole on the lower insulating layer (C) After forming an upper insulating layer on the entire surface, a first layer opening is formed in the upper insulating layer and the lower insulating layer above the other source / drain region of each selection transistor. And (d) a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium or an alloy thereof, wherein the nth plug is the other of the nth selection transistors. A step of forming a plug of a first layer connected to the source / drain region in the opening of the first layer by a plating method, and (e) a common first electrode on the upper insulating layer Forming the memory unit of the first layer connected to the first plug of the first layer, and (f) the n'th layer (where n '= 1, 2, ...
, N−1) interlayer insulating layer is formed, and (N−n ′) th (n ′ + 1) th layer openings are formed in the n′th interlayer insulating layer, and platinum and iridium are formed. , A metal selected from the group consisting of palladium, rhodium and ruthenium or an alloy thereof, and the second to the (N−n ′ + 1) th n′th layer.
Each of the first to (N-n ') th plugs of the (n' + 1) th layer electrically connected to each of the plugs up to the (n'th) th plug-
After being formed in the opening of the +1) th layer, the common first electrode is connected to the first plug of the (n ′ + 1) th layer on the n′th interlayer insulating layer. The step of forming the memory unit of the (n ′ + 1) th layer is
A method for manufacturing a ferroelectric non-volatile semiconductor memory, characterized in that n'is incremented from 1 to (N-1) one by one. 6. (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) each M (where M ≧ 2) memory cells. Composed of N memory units and (D) M plate lines, and the N memory units are stacked via an interlayer insulating layer, and each memory cell has a first It is composed of an electrode, a ferroelectric layer, and a second electrode, and in each memory unit, the first electrode of the memory cell is common, and the nth layer (however, n = 1, 2, ..., N) The common first electrode in the memory unit is connected to the nth bit line through the plug, the nth selection transistor, and the connection hole, and in the memory unit of the nth layer, mth (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A method of manufacturing a ferroelectric non-volatile semiconductor memory connected to a m-th plate line shared between memory units, comprising: (a) forming N selection transistors on a semiconductor substrate; (B) After the lower insulating layer is formed on the entire surface, the n-th insulating layer electrically connected to one of the source / drain regions of the n-th selecting transistor via a connection hole on the lower insulating layer. And (c) after forming the upper insulating layer on the entire surface, the first layer is formed on the upper insulating layer and the lower insulating layer above the other source / drain region of each selection transistor. And (d) a metal selected from the group consisting of platinum, iridium, palladium, rhodium, and ruthenium or an alloy thereof, wherein the n-th plug is the n-th selection gate. Forming a plug of the first layer connected to the other source / drain region of the transistor in the opening of the first layer by a plating method; and (e) forming a common plug on the upper insulating layer. Forming a first-layer memory unit in which the first electrode is connected to the first plug of the first layer, and (f) the n'th layer (however, , N '= 1, 2 ...
, N−1) interlayer insulating layer is formed, and (N−n ′) th (n ′ + 1) th layer openings are formed in the n′th interlayer insulating layer, and platinum and iridium are formed. , A metal selected from the group consisting of palladium, rhodium and ruthenium or an alloy thereof, and the second to the (N−n ′ + 1) th n′th layer.
Each of the first to (N-n ') th plugs of the (n' + 1) th layer electrically connected to each of the plugs up to the (n'th) th plug-
After being formed in the opening of the +1) th layer, the common first electrode is connected to the first plug of the (n ′ + 1) th layer on the n′th interlayer insulating layer. The step of forming the memory unit of the (n ′ + 1) th layer is
A method for manufacturing a ferroelectric non-volatile semiconductor memory, characterized in that n'is incremented from 1 to (N-1) one by one. 7. (A) a selection transistor formed on a semiconductor substrate; and (B) a first electrode, a ferroelectric layer and a second electrode formed on an insulating layer. A ferroelectric non-volatile semiconductor memory comprising a memory cell in which an electrode is connected to one source / drain region of a selection transistor via a plug, wherein the plug is platinum, iridium, palladium, rhodium and A ferroelectric non-volatile semiconductor memory comprising a metal selected from the group consisting of ruthenium or an alloy thereof, which is formed by a plating method. 8. (A) a bit line, (B) a selection transistor, (C) a memory unit composed of M (where M ≧ 2) memory cells, and (D) M plates. Line, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in the memory unit, the first electrode of the memory cell is common and the common first The electrode is connected to the bit line through the plug, the selection transistor, and the connection hole, and in the memory unit, the m-th electrode (where m = 1, 2,
, M) is a ferroelectric non-volatile semiconductor memory in which the second electrode of the memory cell is connected to the m-th plate line, and the plug includes platinum, iridium, palladium, rhodium and A ferroelectric non-volatile semiconductor memory comprising a metal selected from the group consisting of ruthenium or an alloy thereof, which is formed by a plating method. 9. (A) a bit line, (B) a selection transistor, and (C) each consisting of M (where M ≧ 2) memory cells, N (where N ≧ 2). ) And (D) M × N plate lines, N memory units are stacked with an interlayer insulating layer in between, and each memory cell has a first electrode and a ferroelectric layer. The memory cell includes a body layer and a second electrode, and in each memory unit, the first electrode of the memory cell is common, and the common first electrode is the bit through the plug, the selection transistor, and the connection hole. Connected to the line, and in the n-th layer (where n = 1, 2, ..., N) memory unit, the m-th (where m = 1, 2, ..., M)
The second electrode of the M) th memory cell is the [(n-1) M +
A ferroelectric non-volatile semiconductor memory connected to the [m] th plate line, wherein the plug is made of a metal selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium, or an alloy thereof, and is plated. A ferroelectric non-volatile semiconductor memory characterized by being formed according to a method. 10. An (A) bit line, (B) N (where N ≧ 2) selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells. In addition, each memory cell includes N memory units and (D) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode of the cell is common, and the common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is the plug, the n-th selection transistor, and It is connected to the bit line through the connection hole, and in the nth memory unit, the mth memory unit (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A ferroelectric non-volatile semiconductor memory connected to an m-th plate line common to memory units, wherein the plug is selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium. A ferroelectric non-volatile semiconductor memory comprising a metal or an alloy thereof and formed by a plating method. 11. The ferroelectric non-volatile semiconductor memory according to claim 10, wherein the N memory units are stacked via an interlayer insulating layer. 12. (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) M (where M ≧ 2) memory cells, respectively. Composed of N memory units and (D) M plate lines, the N memory units are stacked via an interlayer insulating layer, and each memory cell has a first It is composed of an electrode, a ferroelectric layer, and a second electrode, and in each memory unit, the first electrode of the memory cell is common, and the nth layer (however, n = 1, 2, ..., N). The common first electrode in the memory unit is connected to the n-th bit line through the plug, the n-th selection transistor, and the connection hole. mth (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A ferroelectric non-volatile semiconductor memory connected to an m-th plate line common to memory units, wherein the plug is selected from the group consisting of platinum, iridium, palladium, rhodium and ruthenium. A ferroelectric non-volatile semiconductor memory comprising a metal or an alloy thereof and formed by a plating method.