JP2002184170A - Ferroelectric nonvolatile semiconductor memory and applied voltage pulse width control circuit - Google Patents

Abstract

[PROBLEMS] To provide a ferroelectric non-volatile semiconductor memory which is provided with measures against manufacturing variations and temperature dependence of the inversion voltage of a ferroelectric material and which has excellent disturbance resistance. A ferroelectric nonvolatile semiconductor memory includes a memory cell including a capacitor having a ferroelectric layer.
C _1M , MC _2M include a plurality of memory units MU ₁ , MU ₂ arranged in a row, and further include an applied voltage pulse width control circuit 10. The applied voltage pulse width control circuit 10 includes first and second memory cells. The voltage pulse width can be set such that data can be written to and / or read from a capacitor portion in a selected memory cell, and polarization inversion can be performed in a ferroelectric layer constituting a capacitor portion of an unselected memory cell. Is variably controlled so that the pulse width does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric nonvolatile semiconductor memory (a so-called FERAM), and more particularly to a ferroelectric nonvolatile semiconductor memory excellent in disturbance resistance. The present invention relates to an applied voltage pulse width control circuit suitable for the use of the present invention.

[0002]

2. Description of the Related Art In recent years, research on a large-capacity ferroelectric nonvolatile semiconductor memory has been actively conducted. A ferroelectric nonvolatile semiconductor memory (hereinafter sometimes abbreviated as a nonvolatile memory) is capable of high-speed access, and
It is non-volatile, small in size and low in power consumption, and also resistant to shocks. Therefore, for example, various electronic devices having file storage and resume functions, for example,
It is expected to be used as a main storage device of a portable computer, a mobile phone, or a game machine, or as a recording medium for recording audio and video.

This non-volatile memory employs a method of detecting a change in the amount of charge stored in a capacitor portion having a ferroelectric layer by utilizing high-speed polarization inversion of a ferroelectric material and its remanent polarization.
This is a non-volatile memory that can be rewritten at high speed, and is basically composed of a capacitor section and a selection transistor (switching transistor). The capacitor unit includes, for example, a lower electrode, an upper electrode, and a ferroelectric layer having a high relative dielectric constant ε sandwiched between these electrodes. Writing and reading of data in this nonvolatile memory is performed by applying a ferroelectric PE hysteresis loop shown in FIG. That is, when an external electric field is applied to the ferroelectric layer and then the external electric field is removed, the ferroelectric layer exhibits spontaneous polarization. And the remanent polarization of the ferroelectric layer is
The -P _r when when positive direction of the external electric field is applied + P _r, the negative direction of the external electric field is applied. Here, the case where the remanent polarization is + P _r (see “D” in FIG. 25) is data “0”, and the case where the remanent polarization is −P _r (see “A” in FIG. 25) is data “ 1 ".

In order to determine the state of “1” or “0”, for example, an external electric field in the positive direction is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer is in the state of “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is “0”, no polarization inversion of the ferroelectric layer occurs. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the capacitor unit. By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current. If the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 25 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is temporarily destroyed. Therefore, when the data is “1”, an external electric field in the negative direction is applied,
The state of “A” is set via the paths “D” and “E”, and data “1” is written again.

[0005] The structure of nonvolatile memory, which is currently the mainstream, is
The construction and its operation are described in U.S. Pat. No. 4,873,664.
And S. Shefilled et al.
This nonvolatile memory has an equivalent circuit diagram shown in FIG.
And two memory cells. Incidentally, FIG.
, One nonvolatile memory was surrounded by a dotted line. Each method
The memory cell is, for example, a selection transistor TR₁₁, TR
₁₂, Capacitor part FC ₁₁, FC₁₂It is composed of

A two- or three-digit suffix, for example, a suffix “11”, is a suffix that should be displayed as a suffix “1,1”. For example, “111” is a suffix “11,1”. Is to be displayed, but for simplicity of display, it is displayed with a two-digit or three-digit subscript. The subscript “M” is used, for example, when displaying a plurality of memory cells and plate lines collectively, and the subscript “m” is used, for example, when displaying a plurality of memory cells and plate lines individually. .

Then, one bit is stored by writing complementary data to each memory cell. In FIG. 26, the symbol “WL” indicates a word line, the symbol “BL” indicates a bit line, and the symbol “PL” indicates a plate line. Focusing on one nonvolatile memory, the word line W ₁ is connected to a word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to a differential sense amplifier SA. Further, the plate line PL
₁ is connected to the plate line decoder / driver PD.

When reading stored data in a nonvolatile memory having such a structure, the word line W
When L ₁ is selected and the plate line PL ₁ is driven,
Complementary data is stored in a pair of capacitor units FC ₁₁ , F
A voltage (bit line potential) is applied to the paired bit lines BL ₁ and BL ₂ from C ₁₂ via the selection transistors TR ₁₁ and TR _12.
Appear as. The paired bit lines BL ₁ and BL ₂
(Bit line potential) is detected by the differential sense amplifier SA.

One nonvolatile memory has a word line W
L ₁ and a region surrounded by a pair of bit lines BL ₁ and BL ₂ . Therefore, if the word lines and the bit lines are arranged at the shortest pitch, the minimum area of one nonvolatile memory is 8F ² when the minimum processing dimension is F. Therefore, the minimum area of the nonvolatile memory having such a structure is 8F ² .

When an attempt is made to increase the capacity of a nonvolatile memory having such a structure, its realization depends only on miniaturization of processing dimensions. Further, two selection transistors and two capacitor units are required to constitute one nonvolatile memory. Further, it is necessary to arrange the plate lines at the same pitch as the word lines. Therefore, it is almost impossible to arrange nonvolatile memories at the minimum pitch,
In reality, the area occupied by one nonvolatile memory is 8F
It will increase significantly than ² .

Furthermore, it is necessary to arrange the word line decoder / driver WD and the plate line decoder / driver PD at the same pitch as that of the nonvolatile memory. In other words, two decoders / drivers are required to select one row address. Therefore, the layout of the peripheral circuit becomes difficult, and the area occupied by the peripheral circuit becomes large.

One of the means for reducing the area of the nonvolatile memory is
One is known from Japanese Patent Application Laid-Open No. 9-121032.
As shown in an equivalent circuit diagram in FIG.
The disclosed non-volatile memory includes one selection transistor.
TA TR₁Each of multiple capacitor parts in parallel with one end of
Cell MC having one end connected to_1M(For example, M =
4) and paired with such a nonvolatile memory
The non-volatile memory also has one selection transistor TR._Twoof
One end of each of the capacitor units is connected in parallel to one end.
Connected memory cells MC_2MIt is composed of For selection
Transistor TR ₁, TR_TwoThe other end of each is a bit
Line BL₁, BL_TwoIt is connected to the. Bit line pair
BL₁, BL_TwoIs connected to the differential sense amplifier SA.
You. Also, the memory cell MC_1m, MC_2m(M = 1,2 ...
・ The other end of M) is a plate line PL_mConnected to the
Rate line PL_mIs for plate line decoder / driver PD
It is connected. Further, the word line WL is a word line deco.
WD / driver WD.

The paired memory cells MC _1m , M ₁
Complementary data is stored in C _2m (m = 1, 2,..., M). For example, memory cells MC _1k , MC _2k (where k
When reading data stored in any one of 1, 2, 3, and 4), the word line WL is selected and the plate line PL _m is selected.
The (m ≠ k) while applying a voltage of (1/2) V _cc, driving the plate line PL _k. Here, V _cc is, for example, a power supply voltage. As a result, complementary data is transferred from the paired memory cells MC _1k and MC _2k to the paired bit line B via the selection transistors TR ₁ and TR _2.
It appears as a voltage (potential) on L ₁ and BL ₂ . Then, the voltages (potentials) of the paired bit lines BL ₁ and BL ₂ are
It is detected by the differential sense amplifier SA.

A pair of nonvolatile memories in a pair
Selection transistor TR₁And TR_TwoAre the word lines WL,
And the paired bit lines BL₁, BL_TwoSurrounded by
Occupies an area. Therefore, if the word lines and bit
If the conductors are arranged at the shortest pitch,
A pair of selection transistors TR in a volatile memory ₁
And TR_TwoArea is 8F^TwoIt is. However,
A pair of selection transistors TR₁, TR_TwoWith M pairs
Memory cell MC_1m, MC_2m(M = 1, 2 ...
M), the selection transformer per bit
Jista TR₁, TR_TwoFewer words and words
Since the arrangement of the lines WL is loose, the size of the nonvolatile memory can be reduced.
It is easy to plan. In addition, one word
Line decoder / driver WD and M plate line decoders
The M bit can be selected by the data / driver PD.
Therefore, by adopting such a configuration, the cell area is reduced.
8F^TwoLayout that is close to that of a DRAM.
Chip size can be realized.

[0015]

Problems to be Solved by the Invention Japanese Patent Application Laid-Open No. 9-12103
The technique for reducing the area of the nonvolatile memory disclosed in Japanese Patent Publication No. 2 is very effective, but has the following problems.

That is, for example, a pair of memory cells MC
₁₁ and MC ₂₁ , the data “1” is stored in the memory cell MC _11.
When writing, the plate line PL ₁ and ground level (0 volt), by the V _cc bit lines BL _1, but to polarize the ferroelectric layer, this time, in the memory cell MC ₂₁ data "0" to keep holding the, it is necessary to make the bit line BL ₂ and the ground level (0 volt). Note that these memory cells MC ₁₁ and MC ₂₁ are called selected memory cells.

On the other hand, unselected plate lines PL _m (m = 2,
Memory cells connected to (3, 4) (non-selected memory cells)
In order to prevent destruction of data stored in MC _1m and MC _2m (m = 2, 3, 4), unselected plate lines PL _m (m
= 2, 3, 4), is an intermediate voltage of the bit line BL _1, BL ₂ (1/2) fixed at V _cc, non-selected memory cells MC
_The electric field applied to the ferroelectric layer constituting the capacitor section of _{1 m} and MC _{2 m} is reduced. That is, the unselected memory cells MC _1m , M
A disturbance of (1/2) V _cc is added to C _2m .

Here, the disturb refers to the direction in which the polarization is inverted with respect to the ferroelectric layer constituting the capacitor portion of the non-selected memory cell, that is, the direction in which the stored data is deteriorated or destroyed. , An electric field is applied. When a strong disturbance is applied to the ferroelectric layers constituting the capacitor portions of the unselected memory cells MC _1m and MC _2m ,
Polarization inversion occurs, and the data held in the unselected memory cells MC _1m and MC _2m is destroyed.

[0019] In general, as the potential difference between the applied voltage and the bit line applied to the non-selected plate line PL _m increases, likely polarization inversion occurs in the ferroelectric layer constituting the capacitor portion of the non-selected memory cells Become. The pulse width of the voltage applied to the pulse width and the non-selected plate line PL _m of the voltage applied to the selected plate line PL ₁ (hereinafter,
As the applied voltage pulse width becomes longer, the polarization inversion is more likely to occur in the ferroelectric layer constituting the capacitor portion of the unselected memory cell. Therefore, if the pulse width of the applied voltage is reduced, polarization inversion hardly occurs in the ferroelectric layer constituting the capacitor portion of the non-selected memory cell, but data writing and reading in the selected memory cell cannot be performed reliably. On the other hand, if the applied voltage pulse width is made longer, data writing and / or reading in the selected memory cell can be performed reliably, but polarization inversion tends to occur in the ferroelectric layer constituting the capacitor portion of the non-selected memory cell.

Incidentally, in the conventional nonvolatile memory, the pulse width of the applied voltage is determined at the time of designing the nonvolatile memory, and is interlocked with the operation clock of the system. That is, the plate line PL _m (m = 1, 2,...)
The applied voltage pulse width applied to M) is controlled only statically, and there is no known method of dynamically optimizing the applied voltage pulse width, that is, variably controlling the applied voltage pulse width during the operation of the nonvolatile memory. Not been.

The degree of disturbance applied to the ferroelectric layers constituting the capacitor portions of the non-selected memory cells MC _1m and MC _2m causes polarization reversal, for example, depending on the thickness and composition of the ferroelectric layers. And the temperature of the ferroelectric layer. When manufacturing a non-volatile memory chip, the thickness and composition of the ferroelectric layer may vary. Therefore,
Even if the value of the applied voltage or the value of the applied voltage pulse width is determined at the time of design, data writing and / or reading in the selected memory cell cannot be performed reliably, or the capacitor portion of the unselected memory cell is not used. It is difficult to suppress the occurrence of a phenomenon that polarization inversion occurs in the constituent ferroelectric layer.

Further, a ferroelectric material constituting the ferroelectric layer
Has a negative temperature characteristic as the intrinsic physical property
I do. (A) and (B) of FIG.
PE hysteresis through ferroelectric material at 5 ° C
An example is shown below. In addition, in (A) and (B) of FIG.
Therefore, the PE hysteresis loop of the solid line is V_cc= 1.5 button
And the dotted line PE hysteresis loop is
V_cc= 1.0 volts. Data at 0 volts
The difference in polarization between data "1" state and data "0" state is 2P
_rThis 2P_rIs the signal amount (signal power
Load). In FIG. 28, when the operating temperature is 20 ° C.
The reversal voltage is about ± 0.9 volts. Therefore,
V_cc= 1.5 volts to operate the non-volatile memory,
Disturb voltage (1/2) V_ccNow, unselect
The data stored in the memory cell capacitor is destroyed.
7.9 μC / cm^TwoSignal charge
Wear. On the other hand, the inversion voltage at 105 ° C is ±
It is about 0.55 volt. Therefore, V_cc= 1.5 Vol
If the nonvolatile memory is operated at a speed of 11 μC / cm ^Two
Signal charge can be held, but with disturb voltage
Some (1/2) V_ccNow, the capacity of unselected memory cells
The data in the data section is inverted, and the stored data is destroyed.

On the contrary, in order to prevent the charge of the capacitor portion of the non-selected memory cell from being inverted at the operating temperature of 105 ° C., it is necessary to set V _cc = 1 volt. In this case, although it holds the signal charges of 6.9μC / cm ^2, at 20 ° C, the signal charges of 2.8μC / cm ² only will not be maintained, the signal amount becomes extremely small. As described above, the coercive voltage of the nonvolatile memory has a large negative temperature dependency. In other words, when the temperature rises, the coercive voltage of the non-volatile memory decreases, and the polarization of the capacitor portion of the non-selected memory cell tends to be reversed.

Therefore, unless some measure is taken for the characteristic that the reversal voltage of the ferroelectric material constituting such a ferroelectric layer has a negative temperature characteristic, the non-volatile characteristics in the temperature range required for the LSI are increased. There is a problem that the operation of the non-volatile memory cannot be guaranteed.

Accordingly, an object of the present invention is to provide a countermeasure against a variation at the time of manufacturing or a countermeasure against a temperature dependence of an inversion voltage of a ferroelectric material constituting a ferroelectric layer.
An object of the present invention is to provide a ferroelectric nonvolatile semiconductor memory that can reliably guarantee the operation and has excellent disturbance resistance. It is a further object of the present invention to provide an applied voltage pulse width control circuit suitable for use in such a ferroelectric nonvolatile semiconductor memory.

[0026]

According to a first aspect of the present invention, there is provided a ferroelectric nonvolatile semiconductor memory, comprising: a memory cell having a capacitor section having a ferroelectric layer; When a first voltage is applied to the capacitor portion of the selected memory cell at the time of writing data to the selected memory cell and / or reading data from the selected memory cell, A ferroelectric nonvolatile semiconductor memory having a structure in which a second voltage is applied to a capacitor portion of a non-selected memory cell, wherein a pulse width of the first and second voltages is applied to a capacitor portion in a selected memory cell. Data writing and / or data reading, and polarization inversion occurs in the ferroelectric layer constituting the capacitor portion of the non-selected memory cell. Characterized in that it is variably controlled in odd pulse width.

Here, "variably control" means variably controlling in order to optimize the pulse width of the first and second voltages during the operation of the ferroelectric nonvolatile semiconductor memory. "Writing data to the selected memory cell and / or reading data from the selected memory cell" means "writing data to the selected memory cell, reading data from the selected memory cell, and writing data to the selected memory cell." Means a combination of the data rewrite operations. Furthermore,
"In the selected memory cell, data can be written to and / or read from the capacitor section" means that the data "1" or the data "1" is applied to the ferroelectric layer constituting the capacitor section of the selected memory cell. This means that such a ferroelectric layer is provided with a polarization amount that can sufficiently and reliably determine “0”. Further, "the polarization inversion does not occur in the ferroelectric layer constituting the capacitor portion of the non-selected memory cell" means that the data held in the capacitor portion of the non-selected memory cell is not destroyed, and the data in this memory cell is not destroyed. In the read operation, this means that the amount of polarization that can reliably read such data is reliably maintained. The same applies to the following. The first voltage applied to the capacitor portion of the selected memory cell means a potential difference between a potential applied to the first electrode and a potential applied to the second electrode forming the capacitor portion, and The second voltage applied to the capacitor portion of the cell means a potential difference between a potential applied to the first electrode and a potential applied to the second electrode constituting the capacitor portion, and more specifically, for example, , The difference between the potential of the bit line to which the first electrode is connected and the potential of the plate line to which the second electrode is connected.

In the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention, the pulse widths of the first and second voltages are variably controlled depending on a temperature change of the ferroelectric layer. Is preferred.

The second object of the present invention for achieving the above object is as follows.
The ferroelectric nonvolatile semiconductor memory according to the aspect includes a memory unit in which a plurality of memory cells each including a capacitor unit having a ferroelectric layer are arranged, and writes and / or writes data to a selected memory cell. A ferroelectric type having a structure in which a first voltage is applied to a capacitor portion of a selected memory cell when data is read from a selected memory cell and a second voltage is simultaneously applied to a capacitor portion of an unselected memory cell A nonvolatile semiconductor memory, further comprising an applied voltage pulse width control circuit, wherein the applied voltage pulse width control circuit controls the pulse width of the first and second voltages to transfer data to a capacitor portion in a selected memory cell. Writing and / or
Alternatively, the pulse width can be variably controlled so that the data can be read and the ferroelectric layer constituting the capacitor portion of the non-selected memory cell does not cause polarization inversion.

An object of the present invention is to provide an applied voltage pulse width control circuit for variably controlling a pulse width of an applied voltage applied to a capacitor portion in a memory cell including a capacitor portion having a ferroelectric layer, The present invention can be achieved by an applied voltage pulse width control circuit according to the present invention, which includes a ferroelectric capacitor.

The ferroelectric nonvolatile semiconductor memory according to the first or second embodiment of the present invention (hereinafter, these may be collectively referred to as the nonvolatile memory of the present invention).
, The memory unit comprises: (A) a bit line;
(B) a selection transistor and (C) M (where M ≧
The capacitor section which comprises the memory cell of 2) and (D) M plate lines, and constitutes each memory cell, comprises a first electrode, a ferroelectric layer and a second electrode. The first electrode of the capacitor unit to be configured is common in the memory unit, the common first electrode is connected to a bit line via a selection transistor, and the second electrode is connected to a plate line. It can be configured.

In such a configuration, it suffices to satisfy M ≧ 2. As a practical value of M, for example, a power of 2 (M = 2, 4, 8, 16, 32,...) ).

In the nonvolatile memory according to the present invention having the above-described structure, the first and second voltages are applied to the capacitor section via the plate line, or the applied voltage pulse width control circuit is connected to the plate line. Can be connected. In the applied voltage pulse width control circuit according to the present invention, in the nonvolatile memory having the above configuration, the applied voltage pulse width control circuit may be configured to be connected to a plate line. In the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention,
It is preferable that the operation of the selection transistor is further controlled by the pulse widths of the first and second voltages. Also,
In the nonvolatile memory according to the second aspect having the above-described configuration of the present invention, or in the applied voltage pulse width control circuit of the present invention, the selection is further performed by the applied voltage pulse width control circuit. It is preferable to control the operation of the application transistor.

In the nonvolatile memory of the present invention, the first
When the value of the voltage V _SEL is V _SEL and the value of the second voltage V _NON-SEL , to prevent the occurrence of disturbance, | V
_NON-SEL | = α | V _SEL | (where 0 <α <1) is required to be satisfied. Α is preferably 0 <α ≦
0.6, and more preferably 0 <α ≦ 0.35.

In the nonvolatile memory according to the second aspect of the present invention, it is preferable that the applied voltage pulse width control circuit includes a ferroelectric capacitor. Here, in the nonvolatile memory according to the second embodiment having such a configuration, or alternatively, in the applied voltage pulse width control circuit of the present invention, the ferroelectric capacitor is the same as the memory cell. , A first electrode, a ferroelectric layer, and a second electrode.
In the nonvolatile memory according to the second aspect having such a configuration, or in the applied voltage pulse width control circuit of the present invention, the ferroelectric material constituting the applied voltage pulse width control circuit is used. A configuration in which the pulse widths of the first and second voltages are variably controlled based on the time during which the amount of polarization of the capacitor (more specifically, the amount of polarization of the ferroelectric layer constituting the ferroelectric capacitor) changes. Is preferred. The applied voltage pulse width control circuit further includes a capacitor (capacitor) connected to the ferroelectric capacitor, and the first and second voltages or applied voltages are set based on the amount of charge stored in the capacitor (capacitor). It is desirable that the pulse width of the voltage is variably controlled. Furthermore, in this case, a plurality of capacitors (capacitors) are provided, and the pulse width basic set value of the first and second voltages or the applied voltage is determined by use or non-use of each of the plurality of capacitors (capacitors). Alternatively, a plurality of capacitors (capacitors) are provided, and further, a temperature detection / control means is provided, and each of the plurality of capacitors (capacitors) operates based on the temperature detected by the temperature detection / control means. Is desirably controlled. Alternatively, a plurality of capacitors (capacitors) are provided, and further, a temperature detecting / controlling means is provided, and the use of each of the plurality of capacitors (capacitors) depends on whether the first voltage and the second voltage or the applied voltage is applied. The pulse width basic set value may be determined, and the operation of each of the plurality of capacitors (capacitors) may be controlled based on the temperature detected by the temperature detection / control means. The use or non-use of each of the plurality of capacitors can be achieved, for example, by cutting the wiring connected to each of the capacitors using a laser beam. In addition, the control of the operation of each of the plurality of capacitors includes, for example,
This can be achieved by connecting a switching element composed of a MOS FET and controlling the operation (on / off) of the switching element by a temperature detection / control unit. Here, the pulse width basic setting value is, for example,
Under certain conditions, an operation test of a prototyped nonvolatile memory is performed, and the predetermined applied voltage pulse width for the nonvolatile memory in actual production is determined in advance. This is the value of the applied voltage pulse width that is the basis for variably controlling the width.

In the nonvolatile memory according to the second aspect of the present invention or the memory cell in the applied voltage pulse width control circuit of the present invention, the capacitor part and the ferroelectric capacitor constituting the memory cell have substantially the same structure, It can be formed simultaneously. That is, the first electrode, the ferroelectric layer, and the second electrode forming the memory cell, and the first electrode, the ferroelectric layer, and the second electrode forming the ferroelectric capacitor are made of the same material. It is preferable to configure. The ferroelectric layer forming the memory cell and the ferroelectric layer forming the ferroelectric capacitor may be hereinafter collectively referred to as a ferroelectric layer or the like.

As a material constituting the ferroelectric layer or the like, a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material can be exemplified. Bi
The perovskite-type ferroelectric material having a system layered structure belongs to a so-called nonstoichiometric compound, and has tolerance to composition deviation at both sites of a metal element and an anion (O or the like) element. In addition, it is not unusual to exhibit optimum electrical characteristics at a position slightly deviating from the stoichiometric composition. The Bi-based layered structure perovskite-type ferroelectric material has, for example, the general formula (Bi ₂
O ₂ ) ²⁺ (A _m-1 B _m O _{3m + 1} ) ^2- . Here, “A” is Bi, Pb, Ba, Sr, Ca, N
represents one kind of metal selected from the group consisting of metals such as a, K, and Cd, and “B” represents Ti, Nb, Ta,
One type selected from the group consisting of W, Mo, Fe, Co, and Cr, or a combination of a plurality of types at an arbitrary ratio. M is an integer of 1 or more.

[0038] Alternatively, the material for constituting the ferroelectric layer or the _{like, (Bi X, Sr 1-} X) 2 (Sr Y, Bi 1-Y) (Ta Z, Nb 1-Z) 2 O d Formula ( 1) (However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0
≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3). Alternatively, the material for constituting the ferroelectric layer or the _{like, Bi X Sr Y Ta 2 O} d (2) (wherein, X + Y = 3,0.7 ≦ Y ≦ 1.3,8.7 ≦ d
≤ 9.3) as a main crystal phase. In these cases, the crystal phase represented by the formula (1) or (2) is used as a main crystal phase.
% Is more preferable. Equation (1)
Among the meanings of _{(Bi X, Sr 1-X} ) is the site occupied by the original in the crystal structure and Bi Sr occupies the proportion of Bi and Sr at this time X: means that it is (1-X) . Further, the meaning of (Sr _Y , Bi _1-Y ) means that Bi occupies a site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). . Materials constituting the ferroelectric layer or the like containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include oxides of Bi, oxides of Ta and Nb, and oxides of Bi, Ta and Nb. May be slightly contained.

Alternatively, the material forming the ferroelectric layer or the like is represented by the following formula: Bi _x (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d Formula (3) (where 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0). "(Sr, Ca, Ba)"
Means one element selected from the group consisting of Sr, Ca and Ba. If the composition of the material constituting the ferroelectric layer and the like represented by each of these formulas is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb
₂ O ₉ , Bi ₂ BaTa ₂ O ₉ , Bi ₂ SrTaNbO _{9 and the} like can be mentioned. Alternatively, as a material constituting the ferroelectric layer or the like, Bi ₄ SrTi ₄ O ₁₅ , Bi ₄ Ti
₃ O ₁₂ , Bi ₂ PbTa ₂ O _{9 and the} like can be exemplified, but also in these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change. That is, there may be a composition deviation at both sites of the metal element and the oxygen element.

Alternatively, PbTiO ₃ , lead zirconate titanate which is a solid solution of PbZrO ₃ and PbTiO ₃ having a perovskite structure [PZT, Pb (Zr _1-y , Ti _y ) O ₃ (where 0 <y <1)], and PZT-based compounds such as PLZT, which is a metal oxide obtained by adding La to PZT, and PNZT, which is a metal oxide obtained by adding Nb to PZT. .

In the nonvolatile memory of the present invention, the first electrode is formed below the ferroelectric layer, and the second electrode is formed on the ferroelectric layer (that is, the first electrode is The second electrode corresponds to the upper electrode), or the first electrode is formed on the ferroelectric layer,
A structure in which a second electrode is formed below the ferroelectric layer (that is, the first electrode corresponds to an upper electrode, and the second electrode corresponds to a lower electrode) may be employed. The plate line may be configured to extend from the second electrode,
The electrode may be formed separately from the second electrode and connected to the second electrode. In the latter case, for example, aluminum or an aluminum-based alloy can be exemplified as a wiring material forming the plate line. As a structure in which the first electrode is common, specifically, a structure in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. Can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer, and the second electrode corresponds to a capacitor portion. As a structure in which the first electrode is common, a structure in which a ferroelectric layer is formed in a predetermined region of the first electrode and a second electrode is formed on the ferroelectric layer, or Each of the first surface is provided on a predetermined surface area of the wiring layer.
Are formed, a ferroelectric layer is formed on each of the first electrodes, and a second electrode is formed on the ferroelectric layer. It does not do.

In order to obtain a ferroelectric layer or the like, the ferroelectric thin film may be patterned in a step after the formation of the ferroelectric thin film. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film can be formed by a method suitable for a material constituting the ferroelectric thin film, such as a MOCVD method, a pulse laser ablation method, a sputtering method, and a sol-gel method. Also,
The patterning of the ferroelectric thin film can be performed by, for example, an anisotropic ion etching (RIE) method.

In the present invention, the materials constituting the first electrode and the second electrode include, for example, Ir, IrO _2-x , S
rIrO ₃ , Ru, RuO _2-X , SrRuO ₃ , Pt, P
t / IrO _2-x , Pt / RuO _2-x , Pd, Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La _0.5 Sr _0.5 CoO ₃ (LSCO), Pt
/ LSCO laminated structure, YBa ₂ Cu ₃ O ₇ . Here, the value of X is 0 ≦ X <2. still,
In the laminated structure, the material described before "/" forms the upper layer, and the material described after "/" forms the lower layer. The first electrode and the second electrode may be made of the same material, may be made of the same material, or may be made of different materials. In order to form the first electrode or the second electrode, in the step after forming the first electrode material layer or the second electrode material layer, the first electrode material layer or the second electrode material layer is formed. May be patterned. The first electrode material layer or the second electrode material layer is formed by, for example, a first electrode material layer such as a sputtering method, a reactive sputtering method, an electron beam evaporation method, an MOCVD method, or a pulse laser ablation method. It can be carried out by a method suitable for the material constituting the electrode material layer. The patterning of the first electrode material layer and the second electrode material layer can be performed by, for example, an ion milling method or an RIE method.

In the present invention, as a material constituting an interlayer insulating layer described later, silicon oxide (SiO ₂ ), silicon nitride (SiN), SiON, SOG, NSG, BPS
G, PSG, BSG and LTO can be exemplified.

The selection transistor (switching transistor) is, for example, a well-known MIS type FET or MOS transistor.
It can be composed of a type FET. Examples of the material forming the bit line include polysilicon doped with impurities and a high melting point metal material. Electrical connection between the common first electrode and the selection transistor is established via a connection hole (contact hole) provided in an insulating layer formed between the common first electrode and the selection transistor. Alternatively, it can be performed through a connection hole (contact hole) provided in the insulating layer and a wiring layer formed on the insulating layer. In addition, as a material constituting the insulating layer, silicon oxide (SiO ₂ ), silicon nitride (Si
N), SiON, SOG, NSG, BPSG, PSG,
BSG and LTO can be exemplified.

In the nonvolatile memory according to the first aspect of the present invention, the pulse widths of the first and second voltages applied to the capacitor portion of the selected memory cell and the capacitor portion of the unselected memory cell are variably controlled. Since the nonvolatile memory according to the second aspect of the present invention includes the applied voltage pulse width control circuit, the nonvolatile memory according to the second aspect further includes the applied voltage pulse width control circuit according to the present invention, whereby the ferroelectric layer Even if the film thickness or composition fluctuates or the ferroelectric layer changes in temperature, data writing and / or reading in the selected memory cell can be reliably performed. It is possible to reliably prevent the polarization inversion from occurring in the ferroelectric layer constituting the capacitor portion of the cell.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the present invention (hereinafter, abbreviated as embodiments).

(Embodiment 1) In Embodiment 1, the relationship between the values of the first and second voltages and the pulse widths of the first and second voltages was examined.

A memory cell having a capacitor portion having a ferroelectric layer was experimentally manufactured. This memory cell has a lower electrode made of Ir or IrO ₂ formed on an insulating film, a ferroelectric layer made of Bi ₂ SrTa _1.5 Nb _0.5 O ₉ formed on the lower electrode, and a ferroelectric layer formed on the ferroelectric layer. And an upper electrode made of Ir.

In the test, first, V _cc (= 2.5 volts) was applied to the lower electrode for 5 milliseconds with the upper electrode grounded. As a result, the remanent polarization of the ferroelectric layer is about-
It was 10 μC / cm ² . Next, while the lower electrode is grounded, the voltages of _Vcc (= 2.5 volts), (1/2) _Vcc and (1/3) _Vcc are applied to the upper electrode by changing the pulse width. Applied. The pulse width is 1
It changed from 0 nanoseconds to 120 nanoseconds. Then, the remanent polarization of the ferroelectric layer was measured. FIG. 1 shows the measurement results.

As is clear from FIG. 1, when V _cc is applied (in FIG. 1, indicated by a white circle), complete polarization inversion occurs in the ferroelectric layer at a pulse width of 50 nanoseconds. . Further, when (1/2) V _cc is applied (indicated by a white triangle in FIG. 1), at a pulse width of 50 nanoseconds,
The remanent polarization value of the ferroelectric layer is approximately 0 μC / cm ² .
Furthermore, when (1/3) V _cc is applied (indicated by a white square in FIG. 1), at a pulse width of 120 nanoseconds,
The remanent polarization value of the ferroelectric layer is approximately 0 μC / cm ² .

Next, the first and second voltage values V _SEL , V
The relationship between _NON-SEL and the pulse width t of the first and second voltages was examined.

In the test, first, a value of the first voltage V _SEL (= V _cc =
2.5 volts) were applied with pulse widths of 10 ns, 50 ns, and 100 ns, respectively. As a result, the residual polarization of the ferroelectric layer, when the pulse width is 10 nanoseconds, about -5μC / cm ^2, when the pulse width is 50 nanoseconds, about -10 C / cm ^2, the pulse width is 100 nanoseconds In the case of the above, it was about −12 μC / cm ² .

[0054] Then, in a state of grounding the lower electrode, the upper electrode, respectively, the value of V _NON-SEL / V _{S EL} varied in increments 0.1, a pulse width of 10 nanoseconds, 50 nanoseconds, 100
In nanoseconds, each was applied as a second voltage.
Then, the remanent polarization of the ferroelectric layer was measured. FIG. 2 shows the measurement results. In FIG. 2, white circles indicate that the pulse width is 1
The measurement results at the time of 00 nanoseconds are shown, the white triangles show the measurement results when the pulse width is 50 nanoseconds, and the white diamonds show the measurement results when the pulse width is 10 nanoseconds.

As is clear from FIG. 2, when the pulse width is 1
For 00 ns, the value of V _NON-SEL / V _{S EL} is about 0.36
, The remanent polarization value of the ferroelectric layer becomes approximately 0 μC / cm ² . When the pulse width is 50 nanoseconds, V _NON-SEL
When the value of / V _SEL is about 0.62, the remanent polarization value of the ferroelectric layer is almost 0 μC / cm ² . Furthermore, when the pulse width is 1
In the case of 0 nanoseconds, when the value of V _NON-SEL / V _SEL is about 0.75, the remanent polarization value of the ferroelectric layer is almost 0 μC / cm ² .

For example, the case where the value of V _NON-SEL / V _SEL is 0.4 will be described. When the pulse width is 100 nanoseconds, data is stored in the memory cell at the first voltage V _SEL (= V _cc ). When written, the remanent polarization value of the ferroelectric layer is about-
It becomes 12 μC / cm ² . This state is referred to as data “0” for convenience. Then, the second voltage V _{NON-SE L}
When (= 0.4 V _SEL ) is applied to the memory cell with a pulse width of 100 nanoseconds, the remanent polarization value of the ferroelectric layer becomes about 2 μm.
C / cm ² . That is, at a pulse width of 100 nanoseconds,
The polarization of the ferroelectric layer in the memory cell after being disturbed is inverted, and stored data is destroyed.

On the other hand, when data is written in the memory cell at the first voltage V _SEL (= V _cc ) at a pulse width of 50 nanoseconds, the remanent polarization value of the ferroelectric layer becomes about -10 μC
/ Cm ² . Then, the second voltage V _NON-SEL (= 0.
4V _SEL ) is applied to the memory cell with a pulse width of 50 nanoseconds, the remanent polarization value of the ferroelectric layer becomes about -6.5 μC /
cm ² . That is, with a pulse width of 50 nanoseconds, the ferroelectric layer in the memory cell after being disturbed is:
The polarization is not inverted, and the stored data is reliably retained. When the direction of the electric field received by the ferroelectric layer is opposite, when data is written to the memory cell at the first voltage V _SEL (= V _cc ) with a pulse width of 50 nanoseconds, Of about 10 μC / cm
It becomes ² . This state is referred to as data “1” for convenience. Then, the second voltage V _{NON -SEL} (= 0.4
When V _SEL ) is applied to the memory cell with a pulse width of 50 nanoseconds, the remanent polarization value of the ferroelectric layer becomes about 6.5 μC / cm.
It becomes ² . Assuming the worst case where the difference between the signal amounts of data “0” and data “1” is minimized, both the memory cell holding data “0” and the memory cell holding data “1” suffered disturbance. In this case, a polarization difference of 13 μC / cm ² is obtained even in this case.

Further, when the pulse width is 10 nanoseconds,
When data is written to the memory cell at the first voltage V _SEL (= V _cc ), the remanent polarization value of the ferroelectric layer becomes about -5 μC
/ Cm ² . Then, the second voltage V _NON-SEL (= 0.
4V _SEL ) is applied to the memory cell with a pulse width of 10 nanoseconds, the remanent polarization value of the ferroelectric layer becomes about -4.5 μC /
cm ² . That is, with a pulse width of 10 nanoseconds, the ferroelectric layer in the memory cell after receiving the disturbance has
The polarization is not inverted, and the stored data is reliably retained. When the direction of the electric field received by the ferroelectric layer is opposite, when data is written to the memory cell at the first voltage V _SEL (= V _cc ) with a pulse width of 10 nanoseconds, the ferroelectric layer Has a remanent polarization value of about 5 μC / cm ²
Becomes Then, the second voltage V _NON-SEL (= 0.4
When V _SEL ) is applied to the memory cell with a pulse width of 10 nanoseconds, the remanent polarization value of the ferroelectric layer becomes about 4.5 μC / cm.
It becomes ² . Assuming the worst case where the difference between the signal amounts of data “0” and data “1” is minimized, both the memory cell holding data “0” and the memory cell holding data “1” suffered disturbance. In this case, a polarization difference of 9 μC / cm ² is obtained even in this case. However, this difference in the amount of polarization is due to the pulse width of 50
This is a small value compared to the case of nanosecond. In consideration of variation in the time of manufacturing the memory cell or the like, the residual polarization value 5 [mu] C / cm ² or -5μC / cm ² of the ferroelectric layer is somewhat smaller value.

From the above test results, in the memory cell manufactured as a trial, data can be written to and / or read from the capacitor section in the selected memory cell, and the capacitor section in the non-selected memory cell can be used. It can be seen that a pulse width of 50 nanoseconds should be selected so that the polarization inversion does not occur in the ferroelectric layer to be constituted. When the value of the first voltage is V _SEL (= V _cc = 2.5 volts), the value of the second voltage V _NON-SEL is
_It can be seen that the value of _NON-SEL / _VSEL should be set to a value that is about (1/3) _Vcc . Generally, (1) the value of the remanent polarization of the ferroelectric layer after writing data to the memory cell is as large as possible, and (2) the amount of change in the remanent polarization of the ferroelectric layer before and after receiving the disturbance. Is as small as possible,
Moreover, (3) when both the memory cell holding data “0” and the memory cell holding data “1” are disturbed, the difference between the values of the remanent polarization of the ferroelectric layer in these memory cells is The basic pulse width setting values of the first and second voltages may be determined so as to be as large as possible.

(Embodiment 2) In Embodiment 2, the nonvolatile memory and the applied voltage pulse width control circuit according to the first and second aspects of the present invention are disclosed in Japanese Patent Application Laid-Open No. 9-1210.
This is an example in which the invention is applied to a nonvolatile memory disclosed in Japanese Patent Publication No. 32. FIG. 3 shows an equivalent circuit diagram of the nonvolatile memory according to the second embodiment. FIG. 4 is a schematic partial cross-sectional view of the memory unit.

This nonvolatile memory has a memory cell MC _1M (m = 1, 2) having a capacitor section having a ferroelectric layer.
.. M) are arranged in a plurality of memory units M
Comprising a U _1, further memory cells MC _2M having a capacitor portion having a ferroelectric layer (m = 1,2 ··· M) is provided with a plurality, a memory unit MU ₂ composed are arranged. In FIG. 3, M = 8, but the value of M is not limited to such a value. For example, a power of 2 (2, 4, 8, 16, 32,...) Is preferred.

Then, the memory unit MU ₁ has (A)
Bit line BL ₁ , (B) selection transistor TR ₁ ,
(C) M (here, in the second embodiment, M = 8) memory cells MC _1M and (D) M plate lines PL _M , and the memory unit MU ₂ includes (A) bit lines BL ₂ and
(B) for selection transistors TR _2, consisting of (C) and M memory cells MC _2M, (D) M plate lines PL _M. Incidentally, the memory unit MU ₁ is referred to as a first memory unit MU _1, there is a case where the memory unit MU ₂ is referred to as a second memory unit MU _2.

Further, the capacitor part forming each of the memory cells MC _1M and MC _2M is composed of the first electrode 41 and the ferroelectric layer 4.
2 and a second electrode 43. Then, the memory cell M
The first electrode 41 (sometimes referred to as a _first common node CN ₁ ) of the capacitor section constituting C _1m (m = 1, 2,..., M) is common to the first memory unit MU ₁ . is there. Also, the memory cell MC _2m (m = 1, 2,... M)
A first electrode 41 of the capacitor portion constituting the (when the second is referred to as a common node CN ₂ is) is common in the second memory unit MU _2. A common first electrode (first common node CN ₁ ) constituting the first memory unit MU ₁ is connected to the bit line BL ₁ via the selection transistor TR ₁ , and the second memory unit MU ₂ common first electrode constituting the (second common node CN ₂₎ is connected to the bit line BL ₂ through the selection transistor TR _2. Also, the memory cell MC _1m and the memory cell MC
The second electrode 43 forming _2m is connected to a common plate line PL _m
(M = 1, 2,..., M).

In the schematic partial cross-sectional view of FIG. 4, the second bit line BL ₂ , the second selection transistor TR ₂ and the second memory cell MC _2m are connected to the first bit line BL ₁ a first selection transistor TR ₁ and the first memory cell MC _{1 m,} adjacent in the direction perpendicular to the paper surface. Also,
Fig In 4, a first selection transistor TR ₁ and the first memory cell MC _{1 m,} the first selection transistor TR adjacent to a direction of extension of the first bit line BL ₁ '
₁ and a part of the first memory cell MC ′ _1m are also shown. The first memory cells MC _1m , MC ′ _1m ... Adjacent in the direction in which the first bit line BL ₁ extends
Bit line BL ₁ is common.

Plate line PL in memory cell MC _2m
m is shared with the plate line PL _m in the memory cell MC _1m, and is connected to the plate line decoder / driver PD. Further, the first selection transistor TR
₁ gate electrode 33 and second selection transistor TR ₂
Are connected to a word line WL, and the word line WL is connected to a word line decoder / driver WD. Further, the first bit line BL ₁ and the second bit line BL ₂ are connected to a differential sense amplifier SA.

[0066] In the nonvolatile memory of the second embodiment, sharing the plate line PL _m (i.e., paired)
Complementary data is stored in the memory cells MC _1m and MC _2m (m = 1, 2,..., M). For example, when writing data stored in the selected memory cells MC _1k and MC _2k (where k is one of 1, 2,... M) or reading data, the word line WL is selected. the the bit lines BL ₁ and V _cc, the bit lines BL ₂ and 0 volts. Then, the first voltage V _SEL (= V _cc ) is applied to the selected plate line PL _k constituting the selected memory cells MC _1k and MC _2k . On the other hand, the voltage of the second voltage V _NON-SEL [for example, (１ ／) V _cc ] is applied to the unselected plate line PL _m (m ≠ k) constituting the unselected memory cell MC _m (m ≠ k). Is applied. Here, V _cc is, for example, a power supply voltage. As a result, complementary data is written to the paired memory cells MC _1k and MC _2k .

At this time, the first and second voltages V _SEL , V
The pulse width t of the _NON-SEL is such that in the selected memory cell, data can be written to and / or read from the capacitor portion, and in the ferroelectric layer forming the capacitor portion of the non-selected memory cell. Is variably controlled to a pulse width that does not cause polarization inversion.

This nonvolatile memory includes an applied voltage pulse width control circuit 10. The applied voltage pulse width control circuit can control the pulse width t of the first and second voltages V _SEL and V _NON-SEL to write and / or read data to and from the capacitor section in the selected memory cell. The pulse width is variably controlled so that the polarization inversion does not occur in the ferroelectric layer constituting the capacitor portion of the unselected memory cell.

FIG. 5 shows an example of a specific equivalent circuit of the applied voltage pulse width control circuit 10. Specifically, the applied voltage pulse width control circuit 10 is connected to or incorporated in the word line decoder / driver WD and the plate line decoder / driver PD. The applied voltage pulse width control circuit 10 includes a switch FET 11, a ferroelectric capacitor 12, a switch FET 13, an impedance conversion circuit 14, an integration circuit 15, and a switch FE.
T16, NAND circuit 17, AND circuit 18, switch FET 21, ferroelectric capacitor 22, switch F
ET23, impedance conversion circuit 24, integration circuit 2
5, switch FET 26, NAND circuit 27, AND
It is composed of circuits 28 and 29.

One end of the ferroelectric capacitor 12 is connected to a line L
₀ and connected to the power supply PS, and the switch FE
It is connected to one source / drain region of T11. The other source / drain region of the switching FET 11 is grounded. The other end of the ferroelectric capacitor 12 is connected to one of the source / drain regions of the switching FET 13 and to the input of the impedance conversion circuit 14. The other source / drain region of the switching FET 13 is connected to a power supply (voltage: _Vcc ). The output of the impedance conversion circuit 14 is connected to the input of the integration circuit 15, and the output of the integration circuit 15 is connected to the gate of the switching FET 16. One source / drain region of the switching FET16 power supply (voltage: V _cc) is connected to, the other of the source / drain regions is connected to one input of NAND circuit 17 through the line L _4. The other input of the NAND circuit 17 is connected to the power supply PS. NAND circuit 1
The output of 7 is connected to one input of the AND circuit 18. The other input of the AND circuit 18 is connected to a power supply PS through the wiring L _1. The AND circuit 18
"Output 1" is output from the output unit. AND circuit 18
Is output to a well-known plate line decoder / driver PD, and the plate line decoder / driver PD outputs a first voltage V _SEL .

Further, one end of the ferroelectric capacitor 22 is
The other source / drain region of the switching FET 16,
And one source / drain of the switching FET 21
Connected to the area. The other of the switching FET 21
The source / drain regions are grounded. Ferroelectric capacitor
The other end of the capacitor 22 is connected to one of the sources of the switching FET 23.
Source / drain region and impedance
It is connected to the input of the conversion circuit 24. F for switch
The other source / drain region of ET23 is
Pressure: V_cc)It is connected to the. Impedance conversion circuit
The output of 24 is connected to the input of an integration circuit 25,
The output of the circuit 25 is the gate of the switch FET 26
It is connected to the. One saw of the switching FET 26
Power / voltage (voltage: V_ccConnected to other)
The source / drain region is the wiring L _FiveThrough NAND
It is connected to one input of the circuit 27. NAND times
The other input of the path 27 is connected to the power supply PS.
The output of NAND circuit 27 is connected to one of AND circuits 28 and 29.
Connected to the other input section. AND circuits 28 and 29
The other input section is a line L_Two, L_ThreeConnect to power supply PS via
Have been. The AND circuit 28 outputs "output"
2 "is output. The AND circuit 29 has an output section
Outputs "output 3". "OUT" from the AND circuit 28
Force 2 ”is transmitted to the well-known plate line decoder / driver PD.
Input, such plate line decoder / driver PD
From the second voltage V_NON-SELIs output. Also, AND times
The "output 3" from the path 29 is connected to the well-known word line decoder /
The word line decoder / decoder is input to the driver WD.
A predetermined voltage is output from the driver WD and the selected transistor
The operation of the data is controlled.

Hereinafter, a data write operation in the nonvolatile memory of the second embodiment will be described with reference to FIG. 6 showing operation waveforms in the method of driving the nonvolatile memory of the second embodiment. Incidentally, as an example, the paired memory cells MC
₁₁ and MC ₂₁ are to be written.
The data "1" to C _11, it is assumed that data "0" is written in the memory cell MC _21. FIG. 6 shows operation waveforms.
In FIG. 6, the numbers in parentheses correspond to the numbers of the steps described below.

(1-A) In the standby state, the word lines and all the plate lines are at 0 volt. Also, the bit line BL
₁ and BL ₂ are equalized to 0 volt. It is assumed that data to be written is held in the differential sense amplifier SA.

[0074] (1-B) at the start of data write, the V _cc is applied to the bit line BL _1, bit line BL ₂ applying 0 volts. Here, V _cc is a power supply voltage. (1-C) Next, by setting the word line WL to a high level, the selection transistors TR ₁ and TR ₂ are turned on. At the same time, the first voltage V _SEL (= V _cc , 3.3 volts) is applied to the selected plate line PL _1, and the second voltage V _SEL is applied to the non-selected plate line PL _k (k = 2, 3,... 8). Voltage V
_{Apply NON-SEL} [= (1/2) _Vcc , 1.65 volts]. Thus, in the memory cell MC ₂₁ is the potential of the selected plate line PL ₁ is the first voltage V _SEL, the potential of the bit line BL ₂ is 0 volts, therefore, the data "0" is written. (1-D) Then, the selected plate line PL ₁ and 0 volts. Thus, in the memory cell MC ₁₁ is the potential is 0 volt selected plate line PL _1, the potential of the bit lines BL ₁ is thus is a V _cc, data "1" is written. (1-E) When the data writing is completed, the word line WL is set to the low level to turn off the selection transistors TR ₁ and TR ₂ , and then the bit line BL _{1 is set} to 0 volt. , And discharges the non-selected plate lines PL _k (k = 2, 3... 8) to 0 volt.

In the applied voltage pulse width control circuit 10, the switching FETs 11, 13, 21, and 23 are turned on in advance, and the ferroelectric layers constituting the ferroelectric capacitors 12 and 22 are polarized. FET11,
13, 21, and 23 are turned off. Then, in the step (1-A) and the step (1-B), the wiring L ₀ keep the 0 volt. As a result, the wirings L ₁ , L ₂ and L ₃ are also at 0 volt, and the outputs 1, 2 and 3 of the AND circuits 18, 28 and 29 are also at 0 volt.

At the same time as the start of the step (1-C), the wiring L _{0
Is Vcc} . At this time, the switching FET 16
Is in the off state. Therefore, the wiring L ₄ are remains 0 volt, the output from the NAND circuit 17 becomes V _cc. A
Since the two input portions of the ND circuit 18 are both at _Vcc , the output 1 of the AND circuit 18 is at _Vcc . As a result, the voltage of the selected plate line PL ₁ constituting the selected memory cell MC _11, MC ₂₁ is, V immediately after the start of the step (1-C)
It becomes _SEL .

The switching FET 26 is off. Therefore, the wiring and L ₅ remains 0 volt, NA
The output from the ND circuit 27 becomes _Vcc . AND circuit 2
8 and 29 are both at _Vcc , the outputs 2 and 3 of the AND circuits 28 and 29 are _Vcc.
Becomes As a result, unselected memory cells MC _1k and MC _2K
The voltage of the selection plate line PL _k constituting (k ≠ 1) is
Immediately after the start of the step (1-C), V _NON-SEL is set. The potential of the word line WL is also high (eg, 5 volts).
, And the selection transistors TR ₁ and TR ₂ are turned on. As a result, the first node CN ₁ potential V _cc, and the second potential of the node CN ₂ becomes 0 volts.

In the step (1-C), the polarization inversion in the ferroelectric layer constituting the ferroelectric capacitor 12 progresses as time elapses. Then, the charge transfer to the capacitor (capacitor) 15A through the impedance conversion circuit 14 and the integration circuit 15 proceeds. As the charge of the capacitor 15A constituting the integration circuit 15 is accumulated, the potential of the gate of the switching FET 16 increases. as a result,
After a certain time t ₁ has elapsed, switching FET16 is turned on, the potential of the wiring L ₄ is V _cc. Then
Since the potential of the two input portions of the NAND circuit 17 becomes _Vcc , the output of the NAND circuit 17 becomes 0 volt. Therefore, the output 1 of the AND circuit 18 becomes 0 volt. As a result, the voltage of the selected plate line PL ₁ constituting the selected memory cell MC _11, MC _21, after the certain time t ₁ has elapsed, 0
Become a bolt. When the certain time t ₁ has elapsed, corresponds at the end of step (1-C).

The time t ₁ from the start to the end of the process (1-C), that is, the pulse width of the first voltage V _SEL , ensures that data is written to the capacitor portion in the selected memory cell MC ₁₁ . It is necessary that the pulse width be such that it can be used. Such a pulse width can be determined in advance by performing the test described in the first embodiment.
In other words, such a pulse width is determined by the capacitance of the capacitor 15A constituting the integrating circuit 15, and is determined independently of an external operation clock. Therefore, when designing the nonvolatile memory, the optimum capacitance of the capacitor 15A may be determined in advance by performing the test described in the first embodiment. In the second embodiment, the basic pulse width setting value of the first voltage _VSEL is set to 25 nanoseconds.

[0080] Incidentally, when the completion of step (1-C), the wiring L ₄ is V _cc, begins to progress polarization inversion in the ferroelectric layer constituting the ferroelectric capacitor 22. Then, the charge transfer to the capacitor (capacitor) 25A through the impedance conversion circuit 24 and the integration circuit 25 proceeds. The electric potential of the gate portion of the switching FET 26 rises with the charge accumulation of the capacitor 25A constituting the integration circuit 25. As a result, after a certain time t ₂ has elapsed, switching FET26 is turned on, the potential of the wiring which L ₅ V
_cc . Then, since the potentials of the two input portions of the NAND circuit 27 become _Vcc , the output of the NAND circuit 27 becomes 0 volt. Therefore, the outputs 2 of the AND circuits 28 and 29,
Output 3 goes to 0 volts. As a result, the non-selected memory cells MC _1k, the voltage of the selected plate line PL _K constituting the MC _2K, after a certain time t ₂ has passed, becomes 0 volts. Further, the selection transistors TR ₁ and TR ₂ are turned off. When the certain time t ₂ has elapsed, the step (1-
This corresponds to the end of D).

The total time (t ₁ + t ₂ ) of the time t ₁ from the start to the end of the step (1-C) and the time t ₂ from the start to the end of the step (1-D), that is, the second voltage The pulse width of V _NON-SEL needs to be such that the polarization inversion does not occur in the ferroelectric layers constituting the capacitor portions of the non-selected memory cells MC _1K and MC _2k . Such a pulse width can be determined in advance by performing the test described in the first embodiment. In other words, the pulse width is determined by the capacitance of the capacitor 15A constituting the integrating circuit 15.
And a capacitor 25 constituting the integration circuit 25
A is determined by the capacity of A, and is determined independently of an external operation clock. Therefore, when designing the non-volatile memory, the tests described in the first embodiment may be performed in advance to determine the optimum capacities of the capacitors 15A and 25A.

When a temperature change occurs in the ferroelectric layer forming the memory cell, the ferroelectric capacitor 1
A similar temperature change occurs in the ferroelectric layers constituting the layers 2 and 22. First pulse width of the voltage V _SEL (t ₁₎ and a second pulse width of the voltage _{V NON-SEL (t 1 +} t 2) is the polarization in the ferroelectric layer constituting the ferroelectric capacitors 12 and 22 inverted Is variably controlled without depending on an external operation clock depending on the temperature change of the nonvolatile memory.

Next, an example of a method for reading data from the nonvolatile memory of the second embodiment and rewriting data will be described below. As an example, it is assumed that data is read from a pair of memory cells MC ₁₁ and MC ₂₁ .
The memory cell MC ₁₁ is data "1", the memory cell MC
It is assumed that data “0” is stored in ₂₁ . FIG. 7 shows operation waveforms. In FIG. 7, the numbers in parentheses correspond to the numbers of the steps described below.

(2-A) In the standby state, all bit lines, all word lines, and all plate lines are grounded. Then, the electrical connection between the ground line (not shown) and the bit lines BL ₁ and BL ₂ is released, and the bit lines BL ₁ and BL ₂ are brought into a floating state.

(2-B) At the start of data reading, the word
By setting the line WL to a high level, the selection transistor
Jista TR₁, TR_TwoIs turned on. In addition, select
Rate line PL₁To the first voltage V_SEL(= V_cc)
You. In addition, unselected plate lines PL _kIn a floating state.
As a result, the capacitor storing the data "1"
Memory cell MC composed of₁₁Releases the inverted charge
And as a result, the bit line BL₁, BL_TwoPotential difference between
Occurs. Next, the differential sense amplifier SA is activated,
Such a bit line BL₁, BL_TwoThe potential difference between
Read.

(2-C) After that, by setting the word line WL to low level, the selection transistors TR ₁ ,
And turn off the TR _2. In addition, select plate line PL ₁
To 0 volts. At the same time, the bit lines BL ₁ and BL ₂ are
The bit line B is charged and discharged by the differential sense amplifier SA.
The V _cc is applied to L _1, the bit line BL ₂ applying 0 volts.

(2-D) Then, the steps (1)
By executing -C), the memory cell MC _21, the data "0" is written again.

(2-E) Next, the above-described step (1)
By executing the -D), that is, by the selected plate line PL ₁ and 0 volt, the memory cell MC
Data “1” is written into ₁₁ again.

(2-F) When ending the data writing, the bit lines BL ₁ and BL ₂ are discharged to 0 volt, and the non-selected plate lines PL _m (m = 2, 3... 8) )
To 0 volts.

In the above-described reading of data from the memory cell and rewriting of data, the operation of the applied voltage pulse width control circuit 10 described with reference to FIG. 2-E) the pulse width (t ₁ ) of the first voltage V _SEL and the second voltage V _NON-SEL
The pulse width (t ₁ + t ₂ ) may be variably controlled.

Further, a modified example of the method of reading data from the nonvolatile memory of Embodiment 2 and rewriting the data will be described below. As an example, it is assumed that data is read from a pair of memory cells MC ₁₁ and MC ₂₁ .
The memory cell MC ₁₁ is data "1", the memory cell MC
It is assumed that data “0” is stored in ₂₁ . FIG. 8 shows operation waveforms. In FIG. 8, the numbers in parentheses correspond to the numbers of the steps described below.

(3-A) In the standby state, all bit lines, all word lines, and all plate lines are grounded. Then, the electrical connection between the ground line (not shown) and the bit lines BL ₁ and BL ₂ is released, and the bit lines BL ₁ and BL ₂ are brought into a floating state.

(3-B) At the start of data reading, word
By setting the line WL to a high level, the selection transistor
Jista TR₁, TR_TwoIs turned on. In addition, select
Rate line PL₁To the first voltage V_SEL(= V_cc)
Unselected plate line PL_m(M = 2,3 ... 8)
Voltage V_NON-SEL[= (1/2) V_cc] Is applied. This
As a result, the capacitor unit storing the data “1”
Memory cell MC composed of₁₁Releases reverse charge from
As a result, the bit line BL₁, BL_TwoPotential difference between
Occurs. Next, the differential sense amplifier SA is activated,
Bit line BL ₁, BL_TwoPotential difference between
read out.

(3-C) Thereafter, the bit lines BL ₁ , BL ₂
Were allowed to charge and discharge by the differential sense amplifier SA, the V _cc is applied to the bit line BL _1, the bit line BL ₂ applying 0 volts. As a result, data “0” is written into the memory cell MC ₂₁ again.

(3-D) Thereafter, the selected plate line PL ₁
By zero volts, the memory cell MC _11, data "1" is written again.

(3-E) When ending the data writing, the bit lines BL ₁ and BL ₂ are discharged to 0 volt and the unselected plate lines PL _m (m = 2, 3, 4) are discharged. 0
Discharge to volts.

According to the above sequence, the disturbance applied to the capacitor portion in the unselected memory cells MC _1m and MC _2m (m = 2, 3, 4) is always (１ ／) V _cc
It can be suppressed below.

In this example, when reading data from a memory cell and rewriting data, the data shown in FIG.
The pulse width (t ₁ ) of the first voltage V _SEL in the steps (3-B), (3-C) and (3-D) by the operation of the applied voltage pulse width control circuit 10 described with reference to FIG. )
The pulse width (t ₁ + t ₂ ) of the second voltage V _NON-SEL may be variably controlled.

Further, another modified example of the method of reading data from the nonvolatile memory of Embodiment 2 and rewriting data will be described below. As an example, data is read from a pair of memory cells MC ₁₁ and MC _21, and data “1” is stored in the memory cell MC ₁₁ and data “0” is stored in the memory cell MC ₂₁ . And FIG.
Shows operation waveforms. In FIG. 9, the numbers in parentheses correspond to the numbers of the steps described below.

(4-A) In the standby state, all bit lines, all word lines, and all plate lines are grounded. Then, the electrical connection between the ground line (not shown) and the bit lines BL ₁ and BL ₂ is released, and the bit lines BL ₁ and BL ₂ are brought into a floating state.

(4-B) At the start of data reading, word
By setting the line WL to a high level, the selection transistor
Jista TR₁, TR_TwoIs turned on. In addition, select
Rate line PL₁To the first voltage V_SEL(= V_cc)
Unselected plate line PL_m(M = 2,3 ... 8)
Voltage V_NON-SEL[= (1/2) V_cc] Is applied. This
As a result, the capacitor unit storing the data “1”
Memory cell MC composed of₁₁Releases reverse charge from
As a result, the bit line BL₁, BL_TwoPotential difference between
Occurs. Next, the differential sense amplifier SA is activated,
Bit line BL ₁, BL_TwoPotential difference between
read out.

(4-C) Thereafter, the word line WL is set to the low level, whereby the selection transistors TR ₁ ,
And turn off the TR _2. In addition, select plate line P
L ₁ , the unselected plate line PL _{m is set} to 0 volt. At the same time, the bit lines BL ₁ and BL ₂ are charged and discharged by the differential sense amplifier SA, and _Vcc is applied to the bit line BL ₁ ,
The bit line BL ₂ applying 0 volts.

(4-D) Thereafter, the steps (1)
By executing -C), the memory cell MC _21, the data "0" is written again.

(4-E) Next, the above-described step (1)
By executing the -D), that is, by the selected plate line PL ₁ and 0 volt, the memory cell MC
Data “1” is written into ₁₁ again.

(4-F) When ending the data writing, the bit lines BL ₁ and BL ₂ are discharged to 0 volt, and the non-selected plate lines PL _m (m = 2, 3... 8) )
To 0 volts.

In this example, when data is rewritten, the steps (4-D) and (4-D) are performed by the operation of the applied voltage pulse width control circuit 10 described with reference to FIG.
First pulse width of the voltage V _SEL at E) (t ₁₎ and a second pulse width of the voltage V _NON-SEL to (t ₁ + t ₂₎ may be variably controlled. In reading data, FIG.
As shown in the figure, the applied voltage pulse width control circuit 10A is composed of a switching FET 11, a ferroelectric capacitor 12, a switching FET 13, an impedance conversion circuit 14, an integrating circuit 15, a switching FET 16, a NAND circuit 17, and A
ND circuit 18A, AND circuit 18B, AND circuit 18C
The pulse width (t ′) of the first voltage V _SEL and the second voltage V _NON-SEL in step (4-B) may be variably controlled by the operation of the applied voltage pulse width control circuit. . The AND circuit 18A outputs "output 1" from its output section. “Output 1” from the AND circuit 18A is input to a well-known plate line decoder / driver PD, and the plate line decoder / driver PD outputs a first voltage V _SEL . The AND circuit 18
“Output 2” from B is input to a well-known plate line decoder / driver PD, and the plate line decoder / driver PD outputs a second voltage V _NON-SEL . The "output 3" from the AND circuit 18C is input to a known word line decoder / driver WD, and a predetermined voltage is output from the word line decoder / driver WD.
The operation of the selection transistor is controlled.

Also, similarly to a so-called flash memory, memory cells connected to a plate line can be rewritten collectively. In this case, the read operation is omitted and
Operation can be simplified and rewriting can be speeded up. That is, data "0" may be written once to all memory cells in the memory unit, and then data "1" may be written to predetermined memory cells. In this case, FIG.
The modified example of the applied voltage pulse width control circuit of the present invention having the configuration shown in FIG. However, the AND circuit 18A is unnecessary.

A method for collectively rewriting data in the nonvolatile memory according to the second embodiment will be described below. FIG. 11 shows operation waveforms. In FIG. 11, the numbers in parentheses correspond to the numbers of the steps described below.

(5-A) First, by setting the word line WL to a high level, the selection transistors TR ₁ , T
R ₂ is turned on. Note that bit lines BL ₁ and BL ₂ are set to 0
Leave as bolts. Then, the plate line PL _m (m =
1, 2, ... 7, 8), sequentially, the first voltage V _SEL (=
V _cc ). As a result, data “0” is written to all the memory cells MC _1m and MC _2m .
FIG. 11 shows a state in which data “0” is written to the memory cells MC ₁₁ and MC ₂₁ .

(5-B) Next, by setting the word line WL to low level, the selection transistors TR ₁ ,
And turn off the TR _2. In addition, the plate line PL _m (m
= 1,2,7,8) is set to 0 volt, and the bit line BL
Let ₁ be V _cc and bit line BL ₂ be (１ ／) V _cc .

(5-C) After that, by setting the word line WL to high level, the selection transistors TR ₁ ,
The TR ₂ is turned on, in addition, the selected memory cell M
The plate line PL ₁ forming C ₁₁ and MC ₂₁ is set to 0 volt, and the plate line PL _k forming non-selected memory cells MC _1k and MC _2k (k ≠ 1) is set to (2/3) _Vcc . Thereby, the selected memory cell M connected to the bit line BL ₁
In C _11, the potential of the first electrode is V _cc, second
Of the first voltage V _SE because the potential of the
_L becomes _Vcc , and data "1" is written. on the other hand,
In the selected memory cell MC ₂₁ connected to the bit line BL _2, the potential of the first electrode is (1/3) V _cc, the potential of the second electrode is at 0 volts, therefore, data "0 "
Remains. In the non-selected memory cell MC _1k connected to the bit line BL ₁ , the potential of the first electrode is V
_cc , and since the potential of the second electrode is (2/3) _Vcc , the second voltage _VNON-SEL becomes (1/3) _Vcc .
On the other hand, unselected memory cells M connected to bit line BL ₂
At C _2k , since the potential of the first electrode is (１ ／) V _cc and the potential of the second electrode is (２) V _cc , the second voltage V _NON-SEL is (１ ／) _Vcc .

(5-D) When ending the data writing, the bit lines BL ₁ and BL ₂ are discharged to 0 volt, and the non-selected plate lines PL _m (m = 2, 3... 8) )
To 0 volts.

In this way, data "1" can be written to a predetermined memory cell, and disturbance in non-selected memory cells can be reduced. Then, in the data writing, the pulse width of the first voltage V _SEL in step (5-C) (specifically, the selection transistors TR ₁ and TR ₂ are turned on by the operation of the applied voltage pulse width control circuit) ) And the pulse width of the second voltage V _NON-SEL may be variably controlled.

In the operation of the non-volatile memory according to the second embodiment described above, usually, in one memory unit, data reading from the first memory cell to the M-th memory cell and reading and resuming are successively performed. Write sequentially
Do. Therefore, the unselected memory cells receive (M-1) disturbances. Therefore, it is necessary to determine the pulse width of the second voltage so that the data stored in the memory cell is not destroyed even when such disturbs are received.

The method of manufacturing the nonvolatile memory according to the second embodiment will be described below. However, the nonvolatile memory according to the other embodiments or modifications thereof can be manufactured by substantially the same method.

First, a MOS transistor functioning as a selection transistor in a nonvolatile memory is formed on a semiconductor substrate 30. For this purpose, for example, an element isolation region 31 having a LOCOS structure is formed based on a known method. Note that the element isolation region may have a trench structure or a combination of a LOCOS structure and a trench structure. Thereafter, the surface of the semiconductor substrate 30 is oxidized by, for example, a pyrogenic method to form a gate insulating film 32. Next, after a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, the polysilicon layer is patterned to form a gate electrode 33. This gate electrode 33 also serves as a word line WL. Note that the gate electrode 33 may be formed of polycide or metal silicide instead of being formed of the polysilicon layer. Next, ions are implanted into the semiconductor substrate 30 to form an LDD structure. Thereafter, a SiO ₂ layer is formed on the entire surface by the CVD method, and the SiO ₂ layer is etched back to form a gate sidewall (not shown) on the side surface of the gate electrode 33. Next, after the semiconductor substrate 30 is subjected to ion implantation, the source / drain regions 34 are formed by performing an activation annealing treatment of the ion-implanted impurities.

Next, the lower insulating layer made of SiO ₂ is
After being formed by the VD method, one of the source / drain regions 3
An opening is formed in the lower insulating layer above 4 by RIE. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. Thereby, the connection hole (contact hole) 3
5 can be obtained. Next, by patterning the polysilicon layer on the lower insulating layer, the bit line BL
To form Then, the upper insulating layer made of BPSG is replaced with C
It is formed on the entire surface by the VD method. After the formation of the upper insulating layer made of BPSG, for example, at 900 ° C. in a nitrogen gas atmosphere.
It is preferable to reflow the upper insulating layer for × 20 minutes. Further, if necessary, it is desirable to planarize the upper insulating layer by chemically and mechanically polishing the top surface of the upper insulating layer by, for example, a chemical mechanical polishing method (CMP method).
The lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 36.

Next, after an opening 37 is formed in the insulating layer 36 above the other source / drain region 34 by RIE, the inside of the opening 37 is filled with impurity-doped polysilicon to form a connection hole. (Contact hole) 3
8 is completed. The bit line BL extends over the lower insulating layer in the left-right direction in the drawing so as not to contact the connection hole 38.

The connection holes 38 are formed in the openings 37 formed in the insulating layer 36 by, for example, tungsten, Ti, P
t, Pd, Cu, TiW, TiNW, WSi ₂ , MoS
It can also be formed by embedding a metal wiring material made of refractory metal or metal silicide of i ₂ and the like. The top surface of the connection hole 38 may exist on substantially the same plane as the surface of the insulating layer 36, or the top portion of the connection hole 38 may extend on the surface of the insulating layer 36. Opening 37 with tungsten
Table 1 below shows the conditions for forming the connection holes 38 by embedding the holes.
An example is shown below. It is preferable that a Ti layer and a TiN layer are sequentially formed on the insulating layer 36 including the inside of the opening 37 by, for example, a magnetron sputtering method before filling the opening 37 with tungsten. Here, the reason why the Ti layer and the TiN layer are formed is to obtain an ohmic low contact resistance, prevent the semiconductor substrate 30 from being damaged by the blanket tungsten CVD method, and improve tungsten adhesion.

[Table 1] Sputtering conditions of Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Heating of substrate: none Sputtering condition of TiN layer (thickness: 100 nm) Process Gas: N ₂ / Ar = 100/35 sccm Pressure: 1.0 Pa RF power: 6 kW Heating of substrate: None Tungsten CVD forming conditions Gas used: WF ₆ / H ₂ / Ar = 40/400/2250
Sccm pressure: 10.7 kPa Forming temperature: 450 ° C. Etching conditions for tungsten layer, TiN layer and Ti layer First stage etching: Etching of tungsten layer Gas used: SF ₆ / Ar / He = 110: 90: 5 scc
m Pressure: 46 Pa RF power: 275 W Second stage etching: TiN layer / Ti layer etching Gas used: Ar / Cl ₂ = 75/5 sccm Pressure: 6.5 Pa RF power: 250 W

Next, it is desirable to form an adhesion layer (not shown) made of TiN on the insulating layer 36. And
A first electrode material layer constituting a first electrode (lower electrode) 41 made of Ir is formed on the adhesion layer by, for example, a sputtering method. By patterning based on the etching technique, the first electrode 41 (common node CN)
Can be obtained. In a region where a peripheral circuit is to be formed, a lower electrode of a ferroelectric capacitor constituting an applied voltage pulse width control circuit is simultaneously formed.

Then, for example, by the MOCVD method,
A ferroelectric thin film made of a Bi-based layered structure perovskite ferroelectric material (specifically, for example, Bi ₂ SrTa ₂ O ₉ ) is formed on the entire surface. Thereafter, after performing a drying treatment in air at 250 ° C., a heat treatment is performed for 1 hour in an oxygen gas atmosphere at 750 ° C. to promote crystallization.

Next, an IrO _{2 -X} layer and a Pt layer are sequentially formed on the entire surface by a sputtering method, and then the Pt layer, the IrO 2
_2-X layer, are sequentially a ferroelectric thin film, is patterned, the second electrode 43 and a ferroelectric layer 4 serving also as a plate line PL _m
Form 2 In addition, the ferroelectric layer 4 is etched.
2 may be subjected to heat treatment at a temperature required for damage recovery. In a region where a peripheral circuit is to be formed, an upper electrode and a ferroelectric layer of a ferroelectric capacitor constituting an applied voltage pulse width control circuit are simultaneously formed. After that, the upper insulating layer 50A is formed on the insulating layer 36 and the capacitor section.

Each second electrode 43 is connected to a plate line PL _m
It is not necessary to double as. In this case, after the upper insulating layer is formed on the insulating layer 36 and the capacitor portion, the plate line PL _m is formed on the upper insulating layer, and the second electrode 43 and the plate line PL _m are connected together. The connection may be made by a connection hole (via hole) provided in the upper insulating layer. Further, the ferroelectric thin film need not be patterned.

For example, the conditions for forming a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ are shown in Table 2 below. In Table 2, "thd" is an abbreviation for tetramethylheptanedione. The source materials shown in Table 2 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.

[Table 2] Formation by MOCVD method Source material: Sr (thd) ₂ -tetraglyme Bi (C ₆ H ₅ ) ₃ Ta (O-iC ₃ H ₇ ) ₄ (thd) Formation temperature: 400 to 700 ° C. Process gas: Ar / O ₂ = 1000/1000 cm ³ Formation rate: 5 to 20 nm / min

Alternatively, a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ is formed by a pulse laser ablation method,
It can also be formed over the entire surface by a gel method or an RF sputtering method. The forming conditions in these cases are shown in Table 3 below.
Examples are shown in Tables 4 and 5. When a thick ferroelectric thin film is formed by the sol-gel method, spin coating and drying, or spin coating and baking (or annealing) may be repeated a desired number of times.

[Table 3] Formation by pulsed laser ablation method Target: Bi ₂ SrTa ₂ O ₉ Laser: KrF excimer laser (wavelength 248 nm,
(Pulse width 25 ns, 5 Hz) Forming temperature: 400 to 800 ° C. Oxygen concentration: 3 Pa

[Table 4] Formation by sol-gel method Raw material: Bi (CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₃ [Bismuth / 2-ethylhexanoic acid, Bi (OOc) ₃ ] Sr ( CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [Strontium / 2-ethylhexanoic acid, Sr (OOc) ₂ ] Ta (OEt) ₅ [Tantalum ethoxide] Spin coating conditions: 3000 rpm × 20 seconds Drying : 250 ° C × 7 minutes Firing: 400 to 800 ° C × 1 hour (RTA treatment is added if necessary)

[Table 5] Formation by RF sputtering Target: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Formation temperature: room temperature゜ 600 ° C. Process gas: Ar / O ₂ flow rate ratio = 2/1 to 9/1

When the ferroelectric layer is made of PZT or PLZT, the PZT by magnetron sputtering is used.
Table 6 below shows conditions for forming T or PLZT. Alternatively, PZT or PLZT is prepared by reactive sputtering, electron beam evaporation, sol-gel, or MOCVD.
It can also be formed by a method.

[Table 6] Target: PZT or PLZT Process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Forming temperature: 500 ° C.

Furthermore, PZT or PLZT can be formed by a pulse laser ablation method. The forming conditions in this case are shown in Table 7 below.

[Table 7] Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 ns, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Forming temperature: 550 to 600 ° C. Oxygen concentration: 40 to 120 Pa

In the nonvolatile memory according to the second embodiment,
The paired memory cells MC_1m, MC_2mComplement by
Data storage as an example, but for example, dummy cells
, The data for reading data “1” is applied to the reference side bit line.
And a reference potential in the middle of the read potential of data "0".
1 bit for each memory cell
It is also possible. FIG. 12 shows an equivalent circuit diagram in this case.
Show. Unlike the configuration shown in FIG. 3, this nonvolatile memory
In the modification of the above, the selection transistor TR ₁And election
Selection transistor TR_TwoOf the word lines WL₁Passing
And word line WL_TwoAnd these word lines WL₁,
WL_TwoIs connected to a word line decoder / driver WD.
ing.

Further, as shown in an equivalent circuit diagram of FIG. 13, one memory unit MU may constitute a nonvolatile memory.

(Embodiment 3) Embodiment 3 is a modification of the applied voltage pulse width control circuit described in Embodiment 2. In the third embodiment, the integrating circuit 15 included in the applied voltage pulse width control circuit 10 includes (A) in FIG.
, A plurality of capacitors (capacitors) 15B, 15C,... Connected in parallel are provided. After completion of the nonvolatile memory, a characteristic test is performed to determine whether each of the plurality of capacitors is used or not. Specifically, use or non-use can be achieved by cutting the wiring connected to each of the capacitors using an excess current or a laser beam.
The pulse width basic set value of the first and second voltages or the applied voltage can be determined by using or not using each of the plurality of capacitors (capacitors).

Alternatively, the applied voltage pulse width control circuit 1
As shown in FIG. 14B, a plurality of capacitors (capacitors) 15B, 15B
.., And a temperature detecting / controlling unit 19 having, for example, a thermocouple, and a plurality of capacitors 15 based on the temperature detected by the temperature detecting / controlling unit 19.
., 15C... May be controlled. A plurality of capacitors 15B, 15C
.. Are controlled by connecting the switching elements 15b, 15c... Made of, for example, MOS-type FETs to each of the capacitors, and operating the switching elements 15b, 15c. OFF) is controlled by the temperature detection / control means 19.

Incidentally, the integration circuit 25 constituting the applied voltage pulse width control circuit 10 may be configured as shown in FIG. 14 (A) or (B). Further, the integration circuits 15 and 25 constituting the applied voltage pulse width control circuit 10 may be a combination of the configurations shown in FIGS. 14A and 14B. 14A and 14B of FIG.
Can be applied to the applied voltage pulse width control circuit shown in FIG.

By configuring the applied voltage pulse width control circuit 10 in such a configuration, the ferroelectric capacitors 12 and
Even if the characteristics of the capacitor 22 constituting the memory cell vary, or if the characteristics of the switching FETs 16 and 26 vary, these variations should be compensated for. Can be. Further, in the configuration shown in FIG. 14B, it is possible to more reliably cope with a temperature change of the ferroelectric layer.

(Embodiment 4) In Embodiment 4,
Is a modification of the nonvolatile memory described in the second embodiment.
Is shown. The nonvolatile memory according to the fourth embodiment is a nonvolatile memory.
First memory unit MU constituting memory₁And this
Volatile memory and first bit line BL₁In the direction in which
A first memory unit constituting an adjacent nonvolatile memory
MU '₁Are laminated via an interlayer insulating layer 50,
Second memory unit MU constituting a volatile memory_TwoAnd this
Nonvolatile memory and second bit line BL_TwoWho extends
A second memory unit constituting a non-volatile memory adjacent to the second memory unit
Knit MU '_TwoAre laminated with an interlayer insulating layer 50 interposed therebetween.
Have A model of such a nonvolatile memory according to the fourth embodiment.
FIG. 15 shows a schematic partial cross-sectional view. However, in FIG.
The first memory unit MU ₁, MU '₁Only shown
did. Second memory unit MU_Two, MU '_TwoFigure 15
Are adjacent to each other in the direction perpendicular to the plane of the drawing. Note that the first memory unit
MU '₁The reference number for the component of
Attached.

More specifically, in the nonvolatile memory shown in FIG. 15, an element isolation formed of a LOCOS structure, a shallow trench structure, or a combination of a LOCOS structure and a shallow trench structure formed in a p-type silicon semiconductor substrate 30 is used. In the active region surrounded by the region 31, selection transistors TR ₁ and TR ′ _{1 each} composed of a MOS FET are formed. The selection transistors TR ₁ and TR ′ ₁ are:
A gate insulating film 32 made of, for example, a silicon oxide film formed on the surface of the silicon semiconductor substrate 30 and a gate electrode 33 (word line WL ₁ ,
WL 'also serves as a _1), and, a silicon semiconductor substrate 3
The source / drain region 34 is formed in the active region 0 and contains an n ⁺ -type impurity.

Then, a bit line BL ₁ is formed on a lower insulating layer formed on the entire surface, and the bit line BL ₁ is connected to a selection transistor via a contact hole (contact hole) 35 formed in the lower insulating layer. It is connected to one of the source / drain regions 34 of TR ₁ and TR ′ ₁ . Further, the upper insulating layer is formed on the lower insulating layer including the bit line BL _1. In the drawings, the lower insulating layer and the upper insulating layer are collectively represented as an insulating layer 36. Also, the bit line BL
₁ extends in the left-right direction of FIG. 15 so as not to contact a connection hole (contact hole) 38 described later.

On the insulating layer 36, a first electrode (lower electrode)
41, a ferroelectric layer 42 is formed on the first electrode 41, and a second electrode (upper electrode) is formed on the ferroelectric layer 42.
43 are formed, and these constitute a memory cell _MC1M . The first electrode 41 is common to the memory cells _MC1M and has a stripe-shaped planar shape. The first electrode 41 is connected to the other source / drain region 34 of the selection transistor TR ₁ through a connection hole 38 provided in the opening 37 formed in the insulating layer 36. Incidentally, the common first electrode 41 is connected to the common node C.
It is shown by the N _1. The ferroelectric layer 42 is formed in substantially the same pattern as the second electrode 43.

Further, an interlayer insulating layer 50 is formed on the memory cell MC _1M and the insulating layer 36. Then, a first electrode (lower electrode) 41 'is formed on the interlayer insulating layer 50, a ferroelectric layer 42' is formed on the first electrode 41 ', and a first electrode (lower electrode) 41' is formed on the ferroelectric layer 42 '. 2 electrodes (upper electrode) 4
3 'is formed, the memory cell MC by these' _1M is constructed. The first electrode 41 'is connected to the memory cell M
It is common to C ′ _1M and has a stripe-shaped planar shape. The first electrode 41 ′ is formed in the connection hole 46 provided in the opening 45 formed in the interlayer insulating layer 50, the pad portion 44 formed on the insulating layer 36, and the insulating layer 36. It is connected to the other source / drain region 34 of the selection transistor TR ′ ₁ via a connection hole 38 provided in the opening 37. Note that 'a common node CN' common first electrode 41 shown in _1. Ferroelectric layer 4
2 'is formed in substantially the same pattern as the second electrode 43'. Further, an upper insulating layer 60A is formed on the memory cell _MC'1M and the interlayer insulating layer 50.

The word lines WL ₁ and WL ′ ₁ extend in the direction perpendicular to the plane of FIG. Also, the second electrodes 43, 43 '
Are the memory cells M adjacent to each other in the direction perpendicular to the paper of FIG.
It is common to C _2m and MC ′ _2m and also serves as the plate line PL _m . The memory cell MC _1M and the memory cell MC ′ _1M
And are aligned in the vertical direction. With such a structure, the area occupied by the memory cells can be reduced, and the degree of integration can be improved.

(Embodiment 5) In Embodiment 5,
Also, a modification of the nonvolatile memory described in the second embodiment.
Is shown. 16 and 17 show the nonvolatile memory according to the fifth embodiment.
FIG. 18 shows an equivalent circuit diagram of a moly, and FIG.
Is shown. A nonvolatile memory whose equivalent circuit diagram is shown in FIG.
In the first memory unit MU₁Is a sub note
Reunit SMU_{1 1}, SMU₁₂The second menu
Moly unit MU_TwoIs the sub memory unit SMU_{twenty one},
SMU_{twenty two}It is composed of And the sub memory unit
SMU₁₁, SMU_{twenty one}Transistor for selection connected to
TA TR₁₁, TR_{twenty one}Each of the gate electrodes is a word line
WL₁And the sub memory unit SMU₁₂, SM
U_{twenty two}Selection transistor TR connected to₁₂, TR_{twenty two}of
Each of the gate electrodes is connected to a word line WL_TwoConnected to
I have. On the other hand, a nonvolatile memory whose equivalent circuit diagram is shown in FIG.
, The memory unit MU₁, MU_TwoThe components that make up
Memory unit SMU ₁₁, SMU₁₂, SMU_{twenty one}, SM
U_{twenty two}Selection transistor TR connected to₁₁, TR₁₂,
TR_{twenty one}, TR_{twenty two}Of the word lines W
L₁, WL_Two, WL _Three, WL_FourIt is connected to the. The following
In the various equivalent circuit diagrams described in
Illustration of the width control circuit is omitted.

The nonvolatile memory according to the fifth embodiment has the structure (A-
1) and the first bit line BL _1, (B-1) N pieces (however,
N ≧ 1, and in the fifth embodiment, specifically, N =
2) the first selection transistor TR _1N and (C-1)
Each of the M (where M ≧ 2, and in the fifth embodiment, M = 8) first memory cells MC _1nM (n = 8)
N, where N ≧ 2
In the fifth embodiment, N = 2) first sub memory units SMU _1N and (D-1) first memory cells MC _1nm forming each of _N sub memory units SMU _1N. A _first memory unit MU ₁ composed of M plate lines PL _m shared by (m = 1, 2,... M), and (A-2) a second bit line BL ₂ ;
(B-2) N second selection transistors TR _2N ,
(C-2) M second memory cells MC _{2nM each}
N second sub-memory units SM
U _2N and (D-2) N sub memory units SMU _2N
Is the common second memory cell MC _2nm constituting each, and consists of the first of the M constituting the memory unit MU ₁ and the plate line PL _m common M plate lines PL _m, and a second memory unit MU _2.

In the schematic partial sectional view of FIG. 18, these second bit line BL ₂ , second selection transistors TR ₂₁ and TR ₂₂ and second memory unit MU are shown.
₂ is adjacent to the first bit line BL ₁ , the first selection transistors TR ₁₁ , TR _12, and the first memory unit MU ₁ in the direction perpendicular to the paper.

Then, each memory cell MC_1nm(m = 1, 2
.. M and n = 1, 2,... N
In state 5, m = 1, 2,... 8, n = 1, 2)
Are first electrodes (lower electrodes) 41 and 51 and a ferroelectric layer
42, 52 and second electrodes (upper electrodes) 43, 53
Consisting of Then, the first memory unit MU₁smell
And the n-th (where n = 1, 2,... N) first
Memory unit SMU _1nFirst memory cell constituting
MC_1nmOf the first electrode 41, 51 are the n-th first electrode
Sub memory unit SMU_1nAre common in
Common first electrodes 41 and 51 (common node CN)_1nPlace to call
) Is the n-th first selection transistor T
R_1nVia the first bit line BL₁Connected to the second
The electrodes 43 and 53 share a common plate line PL._mConnected to
I have. On the other hand, the second memory unit MU_TwoIn the
n-th second sub-memory unit SMU_2nMake up
Second memory cell MC_2nmThe first electrodes 41 and 51 of
N-th second sub-memory unit SMU_2nAt
The first electrodes 41 and 51 (common node)
De CN_2n) Is the n-th second choice
Transistor TR_2nVia the second bit line BL_TwoTo
And the second electrodes 43 and 53 are connected to a common plate line P
L_mIt is connected to the.

Note that the number of memory cells constituting the memory unit of the nonvolatile memory is not limited to eight.
Is preferably a power number (2, 4, 8, 16, 32...).

The memory cells MC _11m , MC _12m , MC _21m ,
The plate line PL _m in the MC _22m is shared,
It is connected to a plate line decoder / driver PD.
Furthermore, the gate electrode of the first transistor for selection TR ₁₁ is the gate electrode of the second transistor for selection TR ₂₁ is connected to the word line WL _1, a first selection transistor TR
The gate electrode and the gate electrode of the second selection transistor TR ₂₂ of ₁₂ is connected to the word line WL _2, the word line WL _1,
WL ₂ is connected to a word line decoder / driver WD. Further, the first bit line BL ₁ and the second bit line BL ₂ are connected to a differential sense amplifier SA.

In the nonvolatile memory of the fifth embodiment, each of first sub memory units SMU ₁₁ and SMU ₁₂ constituting _first memory unit MU ₁ is stacked with interlayer insulating layer 50 interposed therebetween. Second sub memory unit SM forming _second memory unit MU ₂
Each of U ₂₁ and SMU ₂₂ is stacked via an interlayer insulating layer 50. That is, the first sub memory unit SMU ₁₁ and the second sub memory unit SMU ₁₂ constituting the _first memory unit MU ₁ are stacked via the interlayer insulating layer 50. Furthermore, the first sub memory unit SMU constituting the _second memory unit MU _2
21 and the second sub memory unit SMU ₂₂ are also stacked via the interlayer insulating layer 50. Thus, high integration of the nonvolatile memory can be achieved.

[0154] Then, in the nonvolatile memory shown in FIG. 16, the memory cells MC sharing the plate line PL _m
11m, stores one bit by writing complementary data in MC _21m, the memory cells sharing the plate line PL _m M
One bit is stored by writing complementary data to C _12m and MC _22m .

[0155] On the other hand, in the nonvolatile memory shown in FIG. 17, the memory cells M sharing the plate line PL _m
One bit is stored in each of C _11m , MC _12m , MC _21m , and MC _22m .

A method of driving a nonvolatile memory for reading data from the nonvolatile memory of the fifth embodiment and rewriting data, or a method of driving a nonvolatile memory for writing data to the nonvolatile memory of the fifth embodiment Since the driving method can be the same as that described in the second embodiment, the detailed description is omitted.

The details of the nonvolatile memory of the fifth embodiment will be described below. In the following description, a description will be given of a first memory unit MU _1, the second memory unit MU ₂ has the same structure.

More specifically, in the nonvolatile memory shown in FIG. 18, an element isolation formed of a LOCOS structure, a shallow trench structure, or a combination of a LOCOS structure and a shallow trench structure formed on a p-type silicon semiconductor substrate 30 In the active region surrounded by the region 31, the first selection transistors TR ₁₁ and TR
₁₂ are formed. First selection transistor T
R ₁₁ and TR ₁₂ are gate insulating films 3 formed on the surface of the silicon semiconductor substrate 30 and made of, for example, a silicon oxide film.
2. Gate electrode 33 formed on gate insulating film 32
(Also serving as word lines WL ₁ and WL ₂ ), and a source / drain region 34 formed in the active region of the silicon semiconductor substrate 30 and containing n ⁺ -type impurities.

Then, a bit line BL ₁ is formed on a lower insulating layer formed on the entire surface, and the bit line BL ₁ is connected to a selection transistor via a contact hole (contact hole) 35 formed in the lower insulating layer. It is connected to one of the source / drain regions 34 of TR ₁₁ and TR ₁₂ . Further, the upper insulating layer is formed on the lower insulating layer including the bit line BL _1. In the drawings, the lower insulating layer and the upper insulating layer are collectively represented as an insulating layer 36. Also, the bit line BL
₁ extends in the left-right direction of FIG. 18 so as not to contact a connection hole (contact hole) 38 described later.

On the insulating layer 36, a first electrode (lower electrode)
41, a ferroelectric layer 42 is formed on the first electrode 41, and a second electrode (upper electrode) is formed on the ferroelectric layer 42.
43 are formed, and these constitute a memory cell MC _11M . Further, the first sub memory unit SM
U ₁₁ is configured. The first electrode 41 is common to the memory cells _MC11M and has a stripe-shaped planar shape. The first electrode 41, the other source / drain region 34 of the selection transistor TR ₁₁ via the connecting hole 38 provided in the opening 37 formed in the insulating layer 36
It is connected to the. Incidentally, the first electrode 41 of the common, indicated by a common node CN _11. The ferroelectric layer 42 includes the second electrode 4
3 is formed in substantially the same pattern.

Further, on the memory cell MC _11M (sub-memory unit SMU ₁₁ ) and the insulating layer 36, the interlayer insulating layer 5
0 is formed. Then, a first electrode (lower electrode) 51 is formed on the interlayer insulating layer 50, and the first electrode 51 is formed.
A ferroelectric layer 52 is formed thereon, a second electrode (upper electrode) 53 is formed on the ferroelectric layer 52, and these constitute a memory cell _MC12M. A unit SMU ₁₂ is configured. The first electrode 51 is common to the memory cells _MC12M and has a stripe-shaped planar shape. And the first electrode 51 is
A connection hole 46 provided in an opening 45 formed in the interlayer insulating layer 50, a pad portion 44 formed on the insulating layer 36,
And, via the connecting hole 38 provided in the opening 37 formed in the insulating layer 36, and is connected to the other source / drain region 34 of the selection transistor TR _12. still,
The common first electrode 51, shown at a common node CN _12. The ferroelectric layer 52 is formed in substantially the same pattern as the second electrode 53. Further, an upper insulating layer 60A is formed on the memory cell MC _12M and the interlayer insulating layer 50.

The word lines WL ₁ and WL ₂ extend in the direction perpendicular to the plane of FIG. In addition, the second electrode 43 is provided as shown in FIG.
Of the second memory unit MU ₂ adjacent to the second memory unit
A common memory cell MC _21m of the first sub-memory unit SMU ₂₁ constituting the also serves as a plate line PL _m. Further, the second electrode 53 is also connected to the memory cell M of the second sub memory unit SMU ₂₂ constituting the _second memory unit MU ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.
C _22m and are common also serves as a plate line PL _m. These plate lines PL _m shared by the memory cells MC _11m , MC _12m , MC _21m , and MC _22m extend in the direction perpendicular to the plane of FIG. 18 and are connected via connection holes in a region (not shown). I have. The memory cells _MC11M and _MC12M are aligned in the vertical direction. With such a structure, the area occupied by the memory cells can be reduced, and the degree of integration can be improved.

(Sixth Embodiment) In the sixth embodiment,
Also, a modification of the nonvolatile memory described in the second embodiment.
Is shown. 20 and 21 show the nonvolatile memory according to the sixth embodiment.
FIG. 19 shows an equivalent circuit diagram of Moly, and FIG.
Is shown. The nonvolatile memory whose equivalent circuit diagram is shown in FIG.
In the first memory unit MU₁Is a sub note
Reunit SMU_{1 1}, SMU₁₂, SMU₁₃, SMU₁₄Or
And a second memory unit MU_TwoIs a sub note
Reunit SMU_{twenty one}, SMU_{twenty two}, SMU_{twenty three}, SMU_{twenty four}Or
It is composed of Then, the sub memory unit SMU
₁₁, SMU_{twenty one}Selection transistor TR connected to₁₁,
TR_{twenty one}Are connected to the word line WL₁Contact
Connected to the sub memory unit SMU₁₂, SMU_{twenty two}Connect to
Selection transistor TR ₁₂, TR_{twenty two}Gate electrode of
Of the word lines WL_TwoConnected to the sub memory
Unit SMU₁₃, SMU_{twenty three}Selection transformer connected to
Jista TR₁₃, TR_{twenty three}Each of the gate electrodes
Do line WL_ThreeAnd the sub memory unit SMU₁₄,
SMU_{twenty four}Selection transistor TR connected to₁₄, TR
_{twenty four}Are connected to the word line WL_FourConnected to
Have been. On the other hand, FIG.
In the memory, the sub memory unit SMU₁₁, SMU
₁₂, SMU ₁₃, SMU₁₄, SMU_{twenty one}, SMU_{twenty two}, SMU
_{twenty three}, SMU_{twenty four}Selection transistor TR connected to₁₁,
TR₁₂, TR₁₃, TR₁₄, TR_{twenty one}, TR_{twenty two}, TR_{twenty three}, T
R_{twenty four}Are connected to the word line WL₁, W
L_Two, WL_Three, WL_Four, WL_Five, WL₆, WL₇, WL₈Contact
Has been continued. In FIGS. 20 and 21, the first
Bit line BL₁And the second bit line BL_TwoWas connected
Illustration of the differential sense amplifier SA is omitted.

In the nonvolatile memory of the sixth embodiment, four sub memory units SMU ₁₁ , SMU ₁₂ , SMU ₁₃ and SMU ₁₄ constituting _first memory unit MU ₁
Stacked in tiers. Although not shown, the sub memory unit SMU constituting the _second memory unit MU _2
21 , SMU ₂₂ , SMU ₂₃ , and SMU ₂₄ are also stacked in four layers.

The nonvolatile memory according to the sixth embodiment has the structure (A-
1) First bit line BL₁And (B-1) N (however,
N ≧ 1, and in the sixth embodiment, specifically, N =
4) First selection transistor TR_1N(TR₁₁, TR
₁₂, TR₁₃, TR₁₄) And (C-1) each M
(However, M ≧ 2, and in the sixth embodiment, M =
8) First memory cell MC_1nM(MC_11M, MC_12M,
MC_13M, MC_14M) Consisting of N first sub-
Memory unit SMU_1N(SMU₁₁, SMU ₁₂, SMU
₁₃, SMU₁₄) And (D-1) N sub-memory units.
SMU_1nOf the first memory cell MC configuring each of
_1nm(MC_11m, MC_12m, MC_12m, MC_14m) And common
M plate lines PL_m, A first memory consisting of
Unit MU₁And (A-2) the second bit line B
L_TwoAnd (B-2) N second selection transistors T
R_2N(TR_{twenty one}, TR_{twenty two}, TR_{twenty three}, TR_{twenty four}) And (C-
2) Each of the M second memory cells MC_2nM(MC
_21M, MC_22M, MC_23M, MC_24MN)
Second sub-memory units SMU_2N(SMU_{twenty one}, S
MU_{twenty two}, SMU_{twenty three}, SMU_{twenty four}) And (D-2) N
Memory unit SMU_2nOf each of the second
Memory cell MC_2nm(MC_21m, MC_22m, MC_22m, MC
_24m) And the first memory unit
M plate lines common to the M plate lines constituting
PL_m, A second memory unit MU comprising_TwoComposed of
Have been.

That is, the nonvolatile memory according to the sixth embodiment
The sub memory unit constituting the memory unit has a four-layer configuration. The number of memory cells forming the sub memory unit is not limited to eight, and the number of memory cells forming the memory unit is not limited to 32.

Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, each of the memory cell MC _11M and the memory cell MC _21M
, A ferroelectric layer 42, and a second electrode 43. Further, the memory cell MC _12M and the memory cell MC
Each of _22M has a first electrode 51 and a ferroelectric layer 52.
And a second electrode 53. Further, the memory cell M
Each of the C _13M and the memory cell MC _23M includes a first electrode 61, a ferroelectric layer 62, and a second electrode 63. Each of the memory cells _MC14M and _MC24M includes a first electrode 71, a ferroelectric layer 72, and a second electrode 73.

In the first memory unit MU ₁ , the first electrode of the first memory cell MC _{1 nm} forming the n-th (n = 1, 2,..., N) first sub-memory unit SMU _1n 41, 51, 61, 71 are common to the n-th first sub-memory unit SMU _1n , and the common first electrodes 41, 51, 61, 71 are connected to the n-th first selection unit. the first is connected to the bit line BL ₁ via the use transistor TR _1n, the second electrode 43,53,63,7
3 are connected to a common plate line PL _m.

In the second memory unit MU ₂ , the first electrodes 41, 51, 6 of the second memory cells MC _2nm forming the n-th second sub memory unit SMU _2n
1, 71 are the n-th second sub memory unit SM
U _{2n and} the common first electrodes 41 and 5
1,61,71 is connected to the second bit line BL ₂ through the n-th second transistor for selection TR _2n, the second electrode 43,53,63,73 common plate line P
It is connected to L _m.

More specifically, in the nonvolatile memory shown in FIG. 19, an element isolation formed by a LOCOS structure, a shallow trench structure, or a combination of a LOCOS structure and a shallow trench structure formed on a p-type silicon semiconductor substrate 30 is used. In the active region surrounded by the region 31, the first selection transistors TR ₁₁ and TR
_12, TR _13, TR ₁₄ are formed. The first selection transistors TR ₁₁ , TR ₁₂ , TR ₁₃ , and TR ₁₄ are formed on the gate insulating film 32 made of, for example, a silicon oxide film, and formed on the surface of the silicon semiconductor substrate 30. The gate electrode 33 (word lines WL ₁ , WL ₂ ,
WL ₃ and WL ₄ ), and a source / drain region 34 formed in the active region of the silicon semiconductor substrate 30 and containing n ⁺ -type impurities.

Then, a bit line BL ₁ is formed on a lower insulating layer formed on the entire surface, and the bit line BL ₁ is connected to the first and second via a connection hole 35 formed in the lower insulating layer.
One source / drain region 34 of the first first selection transistor TR ₁₁ , TR ₁₂ , and one source / drain region 34 of the third and fourth first selection transistors TR ₁₃ , TR ₁₄ 34. Further, the upper insulating layer is formed on the lower insulating layer including the bit line BL _1. The bit lines BL ₁ so as not to contact the connection hole 38 to be described later, and extends in the lateral direction in FIG. 19.

On the insulating layer 36, a first electrode (lower electrode)
41, a ferroelectric layer 42 is formed on the first electrode 41, and a second electrode (upper electrode) is formed on the ferroelectric layer 42.
43 is formed, the memory cells MC _11M is formed by the sub-memory cell SMC ₁₁ is formed.
The first electrode 41 is common to the sub-memory cell SMC _11, having a stripe-shaped planar shape. The first electrode 41 is connected to the other of the source / drain region 34 of the first selection transistor TR ₁₁ via the connecting hole 38 provided in the opening 37 formed in the insulating layer 36 ing. Incidentally, the common first electrode 41 is connected to the common node C.
It is shown by the N _11. The ferroelectric layer 42 is formed in substantially the same pattern as the second electrode 43.

Further, on the sub memory cell SMC ₁₁ and the insulating layer 36, a first interlayer insulating layer 80 is formed.
Then, a first electrode (lower electrode) 51 is formed on the first interlayer insulating layer 80, a ferroelectric layer 52 is formed on the first electrode 51, and a second electrode is formed on the ferroelectric layer 52. (Upper electrode) 53 is formed.
_12M, the sub-memory unit SMU ₁₂ is formed.
The first electrode 51 is common to the memory cells _MC12M ,
It has a stripe planar shape. Then, the first electrode 51 is connected to the opening 45 formed in the first interlayer insulating layer 80.
The connection hole 46 provided therein, the pad portion 44 formed on the insulating layer 36, and the opening 3 formed in the insulating layer 36.
Through a connection hole 38 provided in the 7, the other source / drain region 3 of the second transistor for selection TR ₁₂
4 is connected. Incidentally, the common first electrode 51, shown at a common node CN _12. The ferroelectric layer 52 is formed in substantially the same pattern as the second electrode 53.

Further, a second interlayer insulating layer 81 is formed on the sub memory cell SMC ₁₂ and the first interlayer insulating layer 80. Then, a first electrode (lower electrode) 61 is formed on the second interlayer insulating layer 81, a ferroelectric layer 62 is formed on the first electrode 61, and a second electrode is formed on the ferroelectric layer 62. (Upper electrode) 63 are formed, and these constitute a memory cell MC _13M and a sub memory unit SMU ₁₃ . The first electrode 61 is common to the memory cells _MC13M and has a stripe-shaped planar shape. And
The first electrode 61 includes a connection hole 56 provided in an opening 55 formed in the second interlayer insulating layer 81, a pad portion 54 formed on the first interlayer insulating layer 80, Connection hole 4 provided in opening 45 formed in insulating layer 80
6, the pad portion 44 formed on the insulating layer 36, and, via the connecting hole 38 provided in the opening 37 formed in the insulating layer 36, the other of the third transistor for selection TR ₁₃ It is connected to the source / drain region 34.
Incidentally, the common first electrode 61, shown at a common node CN _13. The ferroelectric layer 62 is formed in substantially the same pattern as the second electrode 63.

Further, a third interlayer insulating layer 82 is formed on sub memory cell SMC ₁₃ and second interlayer insulating layer 81. Then, a first electrode (lower electrode) 71 is formed on the third interlayer insulating layer 82, a ferroelectric layer 72 is formed on the first electrode 71, and a second electrode is formed on the ferroelectric layer 72. (Upper electrode) 73 are formed, and these constitute memory cell MC _14M , and sub memory unit SMU
₁₄ are configured. The first electrode 71 is connected to the memory cell M
It is common to _C14M and has a striped planar shape. Then, the first electrode 71 is provided with a third interlayer insulating layer 82.
A connection hole 66 provided in an opening 65 formed on the second interlayer insulating layer 81; a pad portion 64 formed on the second interlayer insulating layer 81;
Connection holes 56 formed in openings 55 formed in the first interlayer insulating layer 81, pad portions 54 formed on the first interlayer insulating layer 80, openings formed in the first interlayer insulating layer 80. The fourth through a connection hole 46 provided in the hole 45, a pad portion 44 formed on the insulating layer 36, and a connection hole 38 provided in an opening 37 formed in the insulating layer 36. It is connected to the other of the source / drain region 34 of the selection transistor TR _14. The common first electrode 71
And it may be referred to as the common node CN _14. Ferroelectric layer 7
2 is formed in substantially the same pattern as the second electrode 73. Further, an upper insulating layer 83 is formed on the memory cell MC _14M and the third interlayer insulating layer 82.

Word line WL₁, WL_Two, WL_Three, WL_FourIs
It extends in the direction perpendicular to the paper surface of FIG. Also, the second electrode
43 is a memory cell M adjacent to the memory cell M in FIG.
C_{twenty one m}And the plate line PL_mAlso serves as. Change
19, the second electrodes 53, 63 and 73 are also perpendicular to the plane of FIG.
Memory cell MC immediately adjacent to_22m, MC_23m, MC
_24mAnd the plate line PL_mAlso serves as. Each method
Morisel MC_11m, MC_{1 2m}, MC_13m, MC_14m, MC
_21m, MC_22m, MC_23m, MC_24mThese shared by
Each plate line PL_mExtends in the direction perpendicular to the plane of FIG.
And are connected via connection holes in an area (not shown).
ing. Also, the memory cell MC_11MAnd memory cell MC_12M
And memory cell MC_13MAnd memory cell MC_14MIs vertical
It is aligned. With such a structure,
The area occupied by the molycell can be further reduced,
The degree of integration can be further improved.

In the nonvolatile memory whose equivalent circuit diagram is shown in FIG. 20, the first selection transistors TR ₁₁ , T
R ₂₁ is connected to the word line WL _1, the second selection transistor TR _12, TR ₂₂ is connected to the word line WL _2, the third selection transistor TR _13,
TR ₂₃ is connected to the word line WL _3, the fourth selection transistor TR _14, TR ₂₄ is connected to the word line WL _4.

The memory cells MC _11m and MC _21m sharing the plate line PL ₁ , the memory cells MC _12m and MC _22m sharing the plate line PL ₂ , the MC _13m and MC _23m sharing the plate line PL ₃ and the plate line By writing complementary data into the memory cells MC _14m and MC _24m sharing the PL ₄ , 1 bit is stored in each of the data. The structure of the second selection transistors TR ₂₁ , TR ₂₂ , TR ₂₃ , TR ₂₄ and the memory cells MC _{21 m} , MC _22m , MC _23m , MC _24m
Is the same as the structure shown in FIG. 19, and is adjacent in the direction perpendicular to the plane of FIG. Moreover, eight of the selection transistor _{TR 11 ~TR 14, TR 21 ~TR} 24, 64 memory cells MC _11m to MC _14m, the MC _21m to MC _24m, 1 single memory unit (access units) is configured , 32 bits.

The word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ are connected to a word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to a differential sense amplifier (not shown). Further, the plate line PL
_m is connected to a plate line decoder / driver PD.

In an actual nonvolatile memory, this 3
A set of nonvolatile memories storing two bits is arranged in an array as an access unit.

In the nonvolatile memory whose equivalent circuit is shown in FIG. 21, the first selection transistors TR ₁₁ , T
Each of R ₂₁ is connected to word lines WL ₁ and WL ₅ , and each of the second selection transistors TR ₁₂ and TR ₂₂ is connected to word lines WL ₂ and WL ₆ , and
Each of the fourth selection transistors TR ₁₃ and TR ₂₃ is connected to word lines WL ₃ and WL ₇ , and each of the fourth selection transistors TR ₁₄ and TR ₂₄ is connected to word lines WL ₄ and WL ₈ . Have been.

Then, the plate line PL_mNotes shared with
Recell MC_11m, MC_12m, MC_13m, MC_14m, M
C_21m, MC_22m, MC_23m, MC_24mData for each of
, Each stores one bit.
That is, eight selection transistors TR₁₁~ TR₁₄, TR
_{twenty one}~ TR_{twenty four}And 64 memory cells MC_11m~ MC_14m,
MC _21m~ MC_24mOne memory unit (A
Access unit), and stores 64 bits.
You.

The word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ , W
L ₅ , WL ₆ , WL ₇ , WL ₈ are connected to a word line decoder / driver WD. Further, the bit lines BL ₁ and BL ₂
Are connected to a differential sense amplifier (not shown).
Furthermore, the plate line PL _m is connected to a plate line decoder / driver PD.

In an actual nonvolatile memory, this 6
A set of nonvolatile memories storing 4 bits is arranged in an array as an access unit.

(Embodiment 7) The nonvolatile memory of Embodiment 7 is a modification of the nonvolatile memory of Embodiment 6. Nonvolatile memory of the seventh embodiment is different from the non-volatile memory of the sixth embodiment, the memory cells of the first sub-memory unit SMU ₁₁ MC _11m and second memory cell sub-memory unit SMU ₁₂ the second electrode (plate line) is shared by MC _12m, a second electrode in the third sub-memory unit SMU ₁₃ memory cells MC _13m and the memory cells MC _14m in the fourth sub-memory unit SMU ₁₄ (Plate line) is common.
Further, the memory cell MC _21m of the first sub-memory unit SMU ₂₁ and the second sub-memory unit SMU ₂₂
Of the second electrode in the memory cell MC _22m (plate line) is the common, third sub-memory unit memory cell MC _23m and fourth sub-memory unit SM of SMU ₂₃
Second electrode in the memory cell MC _24m of U ₂₄ (plate line)
Is common.

The nonvolatile memory according to the seventh embodiment, whose partial cross-sectional view is schematically shown in FIG. 22, includes a memory cell MC _11m (including a first electrode 41A, a ferroelectric layer 42A, and a second electrode 43). m = 1, 2, 3,
· A 7,8, _{specifically, MC 111, MC 11 2,} M
C ₁₁₃ ... MC ₁₁₇ and MC _118, which are sub memory units SMU ₁₁ ), and a memory cell MC _12m (m = 1) including a first electrode 41B, a ferroelectric layer 42B, and a second electrode 43. , 2,3 ・
· A 7,8, _{specifically, MC 121, MC 12 2,} M
C ₁₂₃ ... MC ₁₂₇ , MC ₁₂₈ and the sub memory unit SMU ₁₂ ), a memory cell MC _13m (m = 1) including the first electrode 51A, the ferroelectric layer 52A, and the second electrode 53 , 2,3 ・
· A 7,8, _{specifically, MC 131, MC 13 2,} M
C ₁₃₃ · · · MC _137, an MC _138, a sub-memory unit SMU _13), and a first electrode 51B and the ferroelectric layer 52B and the memory cell MC _14m consisting of the second electrode 53 (m = 1,2,3
... and 7, 8, _{specifically, MC 141, MC 14 2,} M
C ₁₄₃ ... MC ₁₄₇ , MC ₁₄₈ and the sub-memory unit SMU ₁₄ ).

That is, the nonvolatile memory of the seventh embodiment is
Each memory unit has a four-layer sub memory unit. Note that the number of memory cells constituting the memory unit is not limited to eight, and the number of memory cells constituting the nonvolatile memory is not limited to 32.

Selection transistor TR₁₁, TR₁₂, TR
₁₃, TR₁₄, TR_{twenty one}, TR_{twenty two}, TR _{twenty three}, TR_{twenty four}Structure of
Shows the structure of the nonvolatile memory described in the sixth embodiment.
Since it is the same as the structure, detailed description is omitted.

Then, the first electrode 41 is formed on the insulating layer 36.
A is formed, and a ferroelectric layer 42A is formed on the first electrode 41A.
Is formed, and a second electrode 43 is formed on the ferroelectric layer 42A, and these constitute the memory cell _MC11M . The first electrode 41A is common to the memory cells _MC11M and has a stripe-shaped planar shape. And
The first electrode 41 </ b> A is formed in the opening 3 formed in the insulating layer 36.
Through a connection hole 38 provided in the 7 and is connected to the other source / drain region 34 of the selection transistor TR _11. The ferroelectric layer 42A is formed in substantially the same pattern as the second electrode 43.

Further, the memory cell MC _11M and the insulating layer 36
A ferroelectric layer 42B is formed thereon, and a first
Electrode 41B is formed. Then, the first electrode 4
1B, the ferroelectric layer 42B and the second electrode 43 constitute a memory cell _MC12M . First electrode 41B
_Are common to the memory cells _MC12M and have a stripe-shaped planar shape. The first electrode 41B is connected to the connection hole 3 provided in the opening 37 formed in the insulating layer 36.
8 through, and is connected to the other source / drain region 34 of the selection transistor TR _12. Ferroelectric layer 42
B is formed in substantially the same pattern as the first electrode 41B.

Furthermore, the memory cell MC _12M and the insulating layer 36
An interlayer insulating layer 50 is formed thereon. Then, a first electrode 51A is formed on the interlayer insulating layer 50, and the first electrode 51A is formed.
A ferroelectric layer 52A is formed on the electrode 51A, and a second electrode 53 is formed on the ferroelectric layer 52A, and these constitute a memory cell _MC13M . The first electrode 51A is common to the memory cells _MC13M and has a stripe-shaped planar shape. Then, the first electrode 51A
Are the connection holes 46 provided in the openings 45 formed in the interlayer insulating layer 50, and the pad portions 4 formed on the insulating layer 36.
4 and a connection transistor 38 provided in an opening 37 formed in the insulating layer 36 through the selection transistor TR _21.
Is connected to the other source / drain region.
The ferroelectric layer 52A is formed in substantially the same pattern as the second electrode 53.

Furthermore, a ferroelectric layer 52B is formed on the memory cell _MC13M and the interlayer insulating layer 50, and a first electrode 51B is formed thereon. The first electrode 51B, the ferroelectric layer 52B, and the second electrode 53 form a memory cell _MC14M . First electrode 5
1B is common to the memory cells _MC14M and has a stripe-shaped planar shape. And the first electrode 51B is
A connection hole 46 provided in an opening 45 formed in the interlayer insulating layer 50, a pad portion 44 formed on the insulating layer 36,
And, via the connecting hole 38 provided in the opening 37 formed in the insulating layer 36, and is connected to the other source / drain region 34 of the selection transistor TR _22. The ferroelectric layer 52B is formed in substantially the same pattern as the first electrode 51B. Further, an upper insulating layer 60A is formed on the memory cell MC _14M and the interlayer insulating layer 50.

The memory cells MC _11M , MC _12M , MC _13M, and MC _14M are aligned in the vertical direction. With such a structure, the area occupied by the memory cells can be further reduced, and the degree of integration can be further improved.

Incidentally, the configuration of the memory unit MU ₂ can be made similar. The equivalent circuit diagram of the nonvolatile memory of the seventh embodiment is the same as that shown in FIG. 20 or FIG. Furthermore, the word lines WL ₁ to WL ₄ or, word lines WL ₁ to WL _8, the structure of the plate line PL _m, since it is possible to substantially similar to the sixth embodiment, the detailed description is omitted I do.

Although the present invention has been described based on the embodiments, the present invention is not limited to these embodiments. The structure and configuration of the nonvolatile memory, the structure and configuration of the applied voltage pulse width control circuit, the materials used, various forming conditions, the circuit configuration, the driving method, and the like described in the embodiments of the invention are examples, and may be changed as appropriate. can do. For example, FIG.
As shown in FIG. 3, as a modified example of the nonvolatile memory of the fourth embodiment, the first electrode 41 can be an upper electrode and the second electrode 43 can be a lower electrode. Such a structure can be applied to the non-volatile memory according to another embodiment of the present invention. 23, reference numeral 90,
Reference numeral 91 indicates a lower layer and an upper layer of the first interlayer insulating layer, respectively, and reference numerals 92 and 93 indicate a lower layer and an upper layer of the upper insulating layer, respectively.

A modification of the nonvolatile memory described in the fifth embodiment is shown in a schematic partial sectional view of FIG. In this nonvolatile memory, the first memory unit MU
₁ , the first sub memory unit SMU ₁₁ (memory cell MC _11M ), SMU ₁₂ (memory cell MC _12M ) and the second sub memory unit SMU ₂₁ (memory cell MC ₁₂ ) forming the _second memory unit MU _{2 21M} ), SMU ₂₂
(Memory cell MC _22M ) is formed of an interlayer insulating layer 8
0, 81 and 82 are stacked. Except for this point, the structure of this non-volatile memory can be the same as the structure of the non-volatile memory described in the fifth embodiment, and a detailed description thereof will be omitted. In addition, such a structure,
The present invention can be applied to the nonvolatile memory described in the other embodiments.

The ferroelectric layer may have substantially the same planar shape as the first electrode and may be formed so as to cover the first electrode, depending on the method of manufacturing the nonvolatile memory. Alternatively,
A configuration in which the ferroelectric layer is not patterned may be adopted.

In the embodiments of the present invention, a nonvolatile memory having a configuration in which a plurality of memory cells are connected to one selection transistor has been described. However, the configuration of the nonvolatile memory according to the present invention is non-volatile. The present invention can be applied to a nonvolatile memory of any type or configuration having a structure in which disturbance occurs in a selected memory cell. For example, a non-volatile memory having a configuration in which a selection transistor and a capacitor section are integrated, specifically, a memory cell having a structure in which a ferroelectric thin film is formed instead of a gate insulating film of a field-effect transistor is used. The nonvolatile memory of the present invention or the applied voltage pulse width control circuit of the present invention can also be applied to a nonvolatile memory composed of a plurality of memory units arranged in a row.

Alternatively, a voltage variable circuit for changing the value of the first voltage and / or the second voltage may be provided. Then, the value of the first voltage and the value of the second voltage enable data writing and / or data reading to and from the capacitor portion in the selected memory cell,
Further, the ferroelectric layer constituting the capacitor portion of the non-selected memory cell may be variably controlled to a value that does not cause polarization inversion. Such a voltage variable circuit is provided with a ferroelectric capacitor, and the first and second voltage values are variably controlled based on the time during which the amount of polarization in the ferroelectric capacitor constituting the voltage variable circuit changes. Configuration.

[0200]

According to the nonvolatile memory of the present invention, the pulse widths of the first and second voltages applied to the capacitor portion of the selected memory cell and the capacitor portion of the non-selected memory cell are automatically variably controlled. Therefore, even when the thickness or composition of the ferroelectric layer varies or the temperature of the ferroelectric layer changes, it is necessary to reliably perform data writing and / or reading in the selected memory cell. In addition, it is possible to reliably prevent the polarization inversion from occurring in the ferroelectric layer constituting the capacitor portion of the non-selected memory cell. Therefore, it is possible to reliably cope with the characteristic variation of the ferroelectric layer constituting the memory cell, and it is possible to manufacture a nonvolatile memory having excellent disturbance resistance at a high manufacturing yield.

[Brief description of the drawings]

FIG. 1 is a graph showing the results of measuring the remanent polarization of a ferroelectric layer after applying a voltage applied to a capacitor part constituting a memory cell while changing a pulse width.

FIG. 2 shows first and second voltage values V _SEL and V _NON-SEL ;
9 is a graph showing a result of measuring a relationship between pulse widths of first and second voltages.

FIG. 3 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory according to Embodiment 2 of the present invention;

FIG. 4 is a schematic partial sectional view of a ferroelectric nonvolatile semiconductor memory according to a second embodiment of the present invention;

FIG. 5 is an equivalent circuit diagram showing an example of an applied voltage pulse width control circuit according to the present invention.

FIG. 6 is a diagram showing operation waveforms at the time of data writing in the method of driving a ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 7 is a diagram showing operation waveforms at the time of data reading and rewriting in the method of driving a ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 8 is a diagram showing operation waveforms at the time of data reading and rewriting in a modification of the method of driving the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 9 is a diagram showing operation waveforms at the time of data reading and rewriting in another modification of the method of driving the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 10 is an equivalent circuit diagram showing a modification of the applied voltage pulse width control circuit of the present invention.

FIG. 11 is a diagram showing operation waveforms for explaining a method of collectively rewriting data in the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 12 is an equivalent circuit diagram of a modification of the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 13 is an equivalent circuit diagram of a modification of the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;

FIG. 14 is an equivalent circuit diagram showing an applied voltage pulse width control circuit according to a third embodiment of the present invention.

FIG. 15 is an equivalent circuit diagram of a modification of the ferroelectric nonvolatile semiconductor memory according to the fourth embodiment of the present invention;

FIG. 16 is an equivalent circuit diagram of the ferroelectric nonvolatile semiconductor memory according to the fifth embodiment of the present invention;

FIG. 17 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory of Embodiment 5 of the present invention;

FIG. 18 is a schematic partial sectional view of a ferroelectric nonvolatile semiconductor memory according to Embodiment 5 of the present invention;

FIG. 19 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to Embodiment 6 of the present invention;

FIG. 20 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory according to Embodiment 6 of the present invention;

FIG. 21 is an equivalent circuit diagram of a modification of the ferroelectric nonvolatile semiconductor memory according to Embodiment 6 of the present invention;

FIG. 22 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to Embodiment 7 of the present invention;

FIG. 23 is a schematic partial cross-sectional view of a modification of the ferroelectric nonvolatile semiconductor memory according to Embodiment 4 of the present invention;

FIG. 24 is a schematic partial cross-sectional view of a modification of the ferroelectric nonvolatile semiconductor memory according to the fifth embodiment;

FIG. 25 is a PE hysteresis loop diagram of a ferroelectric substance.

FIG. 26 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in US Pat. No. 4,873,664.

FIG. 27 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in Japanese Patent Application Laid-Open No. 9-121032.

FIG. 28 is a diagram exemplifying a PE hysteresis loop of a ferroelectric material at 20 ° C. and 105 ° C.

[Explanation of symbols]

MU: Memory unit, SMU: Sub memory unit, MC: Memory cell, TR: Transistor for selection, WL: Word line, BL: Bit line, P
L: plate line, WD: word line decoder / driver, SA: differential sense amplifier, PD: plate line decoder / driver, CN: common node, 1
0 ... applied voltage pulse width control circuit, 11, 13, 1
6, 21, 23, 26 ... switch FET, 12,
22: ferroelectric capacitor, 14, 24: impedance conversion circuit, 15, 25: integration circuit, 15
A, 15B, 15C, 15D: capacitors (capacitors), 15b, 15c, 15d: switching elements, 17, 27: NAND circuits, 18, 18A, 1
8B, 18C, 28, 29 ... AND circuit, 19 ...
.Temperature detection and control means, 30 ... semiconductor substrate, 31.
..Element isolation region, 32... Gate insulating film, 33.
.Gate electrode, 34... Source / drain region, 3
5, 38 ... connection hole (contact hole), 36
-Insulating layer, 37 ... Opening, 41, 51, 61, 71
... first electrode, 42, 52, 62, 72 ... ferroelectric layer, 43, 53, 63, 73 ... second electrode, 5
0, 80, 81, 82, 90, 91, 92, 93 ...
Interlayer insulating layer, 50A, 60A ... upper insulating layer

Continued on the front page F term (reference) 5B024 AA04 BA02 BA29 CA01 CA07 CA11 5F083 FR01 GA09 JA15 JA17 JA38 JA43 LA10 LA12 LA16 NA01 NA08

Claims (21)

[Claims] A memory cell including a capacitor unit having a ferroelectric layer includes a plurality of arranged memory units, and writes data to a selected memory cell and / or reads data from the selected memory cell. A ferroelectric nonvolatile semiconductor memory having a structure in which when a first voltage is applied to a capacitor portion of a selected memory cell, a second voltage is simultaneously applied to a capacitor portion of an unselected memory cell; The pulse widths of the first and second voltages are such that, in the selected memory cell, data can be written to and / or read from the capacitor portion, and the ferroelectric material constituting the capacitor portion of the unselected memory cell can be used. A ferroelectric nonvolatile semiconductor memory characterized in that a pulse width in a body layer is variably controlled so as not to cause polarization inversion. 2. The ferroelectric nonvolatile semiconductor memory according to claim 1, wherein the pulse widths of the first and second voltages are variably controlled depending on a temperature change of the ferroelectric layer. . 3. A memory unit comprising: (A) a bit line; (B) a selection transistor; (C) M memory cells (where M ≧ 2); (D) M plate lines; The capacitor portion forming each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode of the capacitor portion forming the memory cell is common to the memory units. The ferroelectric nonvolatile memory according to claim 1, wherein the common first electrode is connected to a bit line via a selection transistor, and the second electrode is connected to a plate line. Semiconductor memory. 4. The method according to claim 3, wherein the first and second voltages are applied to the capacitor section via a plate line.
3. The ferroelectric nonvolatile semiconductor memory according to 1. 5. The pulse width of the first and second voltages,
4. The ferroelectric nonvolatile semiconductor memory according to claim 3, further comprising controlling the operation of the selection transistor. 6. When the value of the first voltage is V _SEL and the value of the second voltage is V _NON-SEL , | V _NON-SEL | = α | V _SEL |
2. The ferroelectric nonvolatile semiconductor memory according to claim 1, wherein 0 <α <1 is satisfied. 7. A memory cell including a capacitor unit having a ferroelectric layer includes a plurality of memory units arranged in a row, and writes data to a selected memory cell and / or reads data from the selected memory cell. A ferroelectric nonvolatile semiconductor memory having a structure in which when a first voltage is applied to a capacitor portion of a selected memory cell, a second voltage is simultaneously applied to a capacitor portion of an unselected memory cell; An applied voltage pulse width control circuit further includes an applied voltage pulse width control circuit that controls the pulse widths of the first and second voltages, and writes and / or reads data to and from a capacitor unit in a selected memory cell. And the pulse width is variably controlled so that no polarization inversion occurs in the ferroelectric layer constituting the capacitor portion of the non-selected memory cell. Type nonvolatile semiconductor memory characterized by and. 8. The voltage pulse width control circuit according to claim 7, further comprising a ferroelectric capacitor.
3. The ferroelectric nonvolatile semiconductor memory according to 1. 9. The pulse width of the first and second voltages is variably controlled based on the time during which the amount of polarization in the ferroelectric capacitor constituting the applied voltage pulse width control circuit changes. 9. The ferroelectric nonvolatile semiconductor memory according to 8. 10. The applied voltage pulse width control circuit further includes a capacitor connected to the ferroelectric capacitor, and the first and second capacitors are connected based on the amount of charge stored in the capacitor.
10. The ferroelectric nonvolatile semiconductor memory according to claim 9, wherein the pulse width of the voltage is variably controlled. 11. The apparatus according to claim 10, wherein a plurality of capacitors are provided, and a basic setting value of the pulse width of the first and second voltages is determined by use or non-use of each of the plurality of capacitors. 3. The ferroelectric nonvolatile semiconductor memory according to 1. 12. A plurality of capacitors are provided, further comprising a temperature detecting / controlling means, wherein each operation of the plurality of capacitors is controlled based on the temperature detected by the temperature detecting / controlling means. The ferroelectric nonvolatile semiconductor memory according to claim 10, wherein: 13. A memory unit comprising: (A) a bit line; (B) a selection transistor; (C) M memory cells (where M ≧ 2); (D) M plate lines; The capacitor portion forming each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode of the capacitor portion forming the memory cell is common to the memory units. The ferroelectric nonvolatile memory according to claim 7, wherein the common first electrode is connected to a bit line via a selection transistor, and the second electrode is connected to a plate line. Semiconductor memory. 14. The ferroelectric nonvolatile semiconductor memory according to claim 13, wherein said applied voltage pulse width control circuit is connected to a plate line. 15. The ferroelectric nonvolatile semiconductor memory according to claim 14, wherein the operation of the selection transistor is further controlled by an applied voltage pulse width control circuit. 16. When the value of the first voltage is V _SEL and the value of the second voltage is V _NON-SEL , | V _NON-SEL | = α | V _SEL
The ferroelectric nonvolatile semiconductor memory according to claim 7, wherein | (where 0 <α <1) is satisfied. 17. An applied voltage pulse width control circuit for variably controlling a pulse width of an applied voltage applied to a capacitor portion in a memory cell including a capacitor portion having a ferroelectric layer, the ferroelectric material comprising: An applied voltage pulse width control circuit comprising a capacitor. 18. The application according to claim 17, wherein the pulse width of the applied voltage is variably controlled based on the time during which the amount of polarization in the ferroelectric capacitor constituting the applied voltage pulse width control circuit changes. Voltage pulse width control circuit. 19. The applied voltage pulse width control circuit further includes a capacitor connected to the ferroelectric capacitor, wherein the pulse width of the applied voltage is variably controlled based on the amount of charge stored in the capacitor. 19. The applied voltage pulse width control circuit according to claim 18, wherein: 20. The applied voltage according to claim 19, wherein a plurality of capacitors are provided, and a basic setting value of a pulse width of the applied voltage is determined by use / non-use of each of the plurality of capacitors. Pulse width control circuit. 21. A system comprising: a plurality of capacitors; and a temperature detection / control means, wherein the operation of each of the plurality of capacitors is controlled based on the temperature detected by the temperature detection / control means. 20. The applied voltage pulse width control circuit according to claim 19, wherein: