JP2003172950A - Electro-optical device, method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

(57) Abstract: In an electro-optical device in which a pixel switching transistor element is formed on a substrate, a light-shielding film is used to improve light resistance and to reduce the light-shielding performance due to oxidation of the light-shielding film. In addition, the contamination of the semiconductor layer and the like by the light shielding film is reduced. SOLUTION: A transistor element having a pixel electrode, a semiconductor layer connected thereto and including a channel region, and a wiring connected thereto, and a light-shielding film covering at least the channel region from the support substrate side are provided. And an insulating portion disposed between at least one of the light-shielding film and the semiconductor layer and between the support substrate and the light-shielding film and including a silicon nitride film or a silicon nitride oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device, such as an active matrix driving type liquid crystal device, in which a transistor element for pixel switching is formed on a supporting substrate, a manufacturing method thereof, and such electro-optical device. It belongs to the technical field of electronic equipment provided with a device.

[0002]

2. Description of the Related Art For example, in an electro-optical device of a TFT active matrix driving system, a pixel switching thin film transistor (hereinafter referred to as a TFT (Thi
When incident light is applied to a channel region (referred to as “n Film Transistor”), photo-leakage current is generated by excitation by light and the characteristics of the TFT are changed. Particularly in the case of an electro-optical device for a light valve in a projector, since the intensity of incident light is high, it is important to shield the incident light from the channel region of the TFT and its peripheral region.
Therefore, conventionally, a light-shielding film that defines an opening area of each pixel provided on the counter substrate or a data line that passes over the TFT on the TFT array substrate and is made of a metal film such as Al (aluminum) is used. It is configured to shield the channel region and its peripheral region from light.

In particular, a light shielding film made of, for example, a refractory metal may be provided below the TFT on the TFT array substrate. If a light-shielding film is also provided on the lower side of the TFT in this way, the back surface reflected light from the TFT array substrate side,
When a plurality of electro-optical devices are combined via a prism or the like to form one optical system, return light such as projection light penetrating the prism or the like from another electro-optical device is incident on the TFT of the electro-optical device. You can prevent it.

[0004]

However, according to the research by the inventor of the present application, a light-shielding film formed of a refractory metal or the like formed on the lower side of a TFT is Oxidation tends to progress over time. And
It has been found that in such a light-shielding film, when such oxidation progresses, the light transmittance increases depending on the degree of oxidation, and when the oxidation proceeds, the original function of the light-shielding film cannot be sufficiently exhibited. There is a problem. For example, a TFT of a type in which a light-shielding film made of such a high melting point metal is provided under the TFT
When the array substrate is subjected to atmospheric oxidation with 15% oxygen and 85% water, the light-shielding film with a thickness of about 200 nm is completely oxidized even if it is covered with a protective insulating film made of a silicon oxide film with a thickness of about 800 nm. There are also confirmed cases of accidents.

Further, according to the research conducted by the inventor of the present application, when a light-shielding film made of a refractory metal or the like is arranged below the channel region of the semiconductor layer constituting the TFT, the contamination by the light-shielding film in the semiconductor layer is observed. Nation (contamination due to diffusion of impurities) is also a problem. That is, it has been confirmed that impurities entering the semiconductor layer increase as compared with the case where such a light-shielding film is not provided, which causes a problem that the transistor characteristics of the TFT are deteriorated.

The present invention has been made in view of the above-mentioned problems, and by using a light-shielding film, it is possible to reduce light-shielding performance due to oxidation of the light-shielding film as well as excellent light resistance.
Further, it is possible to reduce the adverse effect of contamination of the semiconductor layer and the like by the light-shielding film, and an electro-optical device capable of displaying a bright and high-quality image, a manufacturing method thereof, and an electronic device including such an electro-optical device. The challenge is to provide equipment.

[0007]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention includes a pixel electrode on a supporting substrate,
A transistor element having a semiconductor layer that is connected to the pixel electrode and includes a channel region, a wiring connected to the transistor element, a light-shielding film that covers at least the channel region from the support substrate side, the light-shielding film, and the light-shielding film. An insulating portion is disposed between the semiconductor layer and at least one of the supporting substrate and the light shielding film, and includes a silicon nitride film or a silicon nitride oxide film.

According to the electro-optical device of the present invention, by supplying a scanning signal, an image signal or the like to the wiring, the pixel element can be switching-controlled by the transistor element, and active matrix driving can be performed. During such an operation, if the above-mentioned return light is incident on the channel region of the semiconductor layer forming the transistor element, the transistor characteristics will change due to the generation of a light leak current.
A light-shielding film is provided at least under the channel region of the semiconductor layer in at least the light incident region or the image display region (that is, the region on the supporting substrate, excluding the peripheral region and the like, where incident light involved in image display is reflected or transmitted). Is provided, it is possible to effectively prevent the generation of a light leak current due to such return light.

In the present invention, the insulating portion including the silicon nitride film or the silicon nitride oxide film is arranged between at least one of the light shielding film and the semiconductor layer and between the supporting substrate and the light shielding film. . The silicon nitride film or the silicon oxynitride film is a silicon oxide film that is a typical example of an interlayer insulating film formed in a laminated structure on a supporting substrate, or other various insulating films that form a laminated structure on the supporting substrate. Compared to various conductive films and various semiconductor films, it can be formed more densely, and the transmittance of oxidizing species such as oxygen and moisture can be significantly reduced. That is, since oxidizing species such as oxygen and water are difficult to penetrate through the dense silicon nitride film or silicon nitride oxide film forming the insulating portion,
Almost no light-shielding film can be reached. Therefore, oxidative species such as oxygen and water may infiltrate during operation or manufacturing of the electro-optical device from the surface side of the supporting substrate on which the transistor elements are formed or the interface in the laminated structure built on the supporting substrate. Alternatively, even if oxidizing species such as oxygen and water are incorporated into various conductive films, various edge films, various semiconductor films and the like formed on the supporting substrate during its manufacture, The amount of the oxidizing species such as oxygen and moisture reaching the light-shielding film during manufacturing or operation can be reduced by the insulating portion including the dense silicon nitride film or silicon nitride oxide film. Therefore, it is possible to effectively prevent the light shielding film from being oxidized during the operation or manufacturing of the electro-optical device. Therefore, it is possible to avoid the increase of the light transmittance due to the oxidation of the light shielding film, that is, the deterioration of the light shielding performance, and it is possible to maintain the high performance of the transistor element.

In particular, if an insulating portion including a dense silicon nitride film or silicon oxynitride film is arranged between the light-shielding film and the semiconductor layer, impurities from the light-shielding film made of, for example, a refractory metal film are used as semiconductors. It is also possible to effectively prevent contamination that diffuses into the layers. That is, the impurities from the light-shielding film hardly reach the semiconductor layer because it is difficult for the impurities to pass through the dense silicon nitride film or silicon nitride oxide film forming the insulating portion. Therefore, it becomes possible to prevent the characteristic deterioration of the transistor element due to the contamination from the light shielding film in the semiconductor layer.

As a result of the above, according to the electro-optical device of the present invention,
Finally, it becomes possible to display a high-quality image for a long time.

In addition, it is not necessary to form the light-shielding film thicker than necessary in anticipation of a reduction in the light-shielding performance of the light-shielding film due to oxidation.

When the electro-optical device is of a transmissive type, a light transmissive one may be used as the supporting substrate.

In one aspect of the electro-optical device of the present invention, the insulating portion has a multilayer structure.

According to this aspect, by forming the insulating portion including the silicon nitride film or the silicon oxynitride film into a multi-layer structure, it is possible to further enhance the ability to block oxidative species such as oxygen and moisture in the insulating portion. Becomes Therefore, it becomes possible to more effectively prevent oxidation of the light-shielding film and contamination by the light-shielding film.

In this aspect, the laminated structure includes the silicon nitride film or the silicon nitride oxide film and the silicon oxide film formed on the upper surface or the lower surface of the silicon nitride film or the silicon nitride oxide film. You may comprise.

According to this structure, a laminated body of the silicon nitride film or the silicon oxynitride film and the silicon oxide film formed thereon is used to block the oxidizing species such as oxygen and water in the insulating portion. It is possible to further enhance the ability. Further, for example, a stacked structure in which a silicon oxide film is sandwiched between two silicon nitride films or a silicon nitride oxide film, a stacked structure in which a silicon nitride film or a silicon nitride oxide film is sandwiched between two silicon oxide films, three or more, It is also possible to construct a laminated structure using membranes.

The insulating portion may have a single layer structure such as only a silicon nitride film or only a silicon nitride oxide film.

In one aspect of the electro-optical device of the present invention, the insulating portion is in close contact with the light shielding film.

According to this aspect, since the insulating portion including the dense silicon nitride film or the silicon nitride oxide film is in close contact with the upper surface, the lower surface or both surfaces of the light shielding film, or the edges or edges,
It is possible to reduce the possibility that oxidizing species such as oxygen and water contained in other interlayer insulating films and the like will reach the light shielding film.

Alternatively, in another aspect of the electro-optical device of the present invention, the insulating portion faces the light-shielding film via an interlayer insulating film.

According to this aspect, since the insulating portion including the dense silicon nitride film or the silicon nitride oxide film faces the light shielding film via the interlayer insulating film such as the silicon oxide film, oxygen, moisture, etc. Can be blocked to some extent at a position separated from the light-shielding film.

In another aspect of the electro-optical device of the present invention, the light shielding film has a plane pattern of a predetermined shape, and the insulating portion has a plane pattern of a shape that completely covers the light shielding film. The edge of the insulating portion is separated from the edge of the light shielding film when seen in a plan view.

According to this aspect, for example, at least the channel region of the semiconductor layer can be shielded from the lower side by the light shielding film having a plane pattern of a predetermined shape such as a lattice shape, a stripe shape, or an island shape. The insulating portion has a flat pattern that completely covers the light-shielding film and has a shape, such as a lattice shape, a stripe shape, or an island shape, which is slightly larger than the light-shielding film. Seen from the edge of the light shielding film. Therefore, the insulating portion can three-dimensionally cover the light shielding film from the upper side or the lower side or both sides on the supporting substrate, and further reduce the possibility that oxidizing species such as oxygen and water may reach the light shielding film.

The insulating portion may be formed on almost one surface of the supporting substrate regardless of the plane pattern of the light shielding film.
Further, some effects can be obtained without completely covering the light shielding film. Further, in this aspect, it is desirable that the distance between the edge of the insulating portion and the edge of the light shielding film is within 2 μm in plan view. As a result, it is possible to reduce the possibility that oxidizing species such as oxygen and moisture may reach the light-shielding film from the edge of the insulating portion, and at the same time, to significantly reduce the rate of light reduction in the insulating portion. Further, in this aspect, it is desirable that the edge of the insulating portion is formed in a self-aligned manner with the edge of the light shielding film when seen in a plan view. This makes it possible to reduce the light reduction rate in the insulating portion to the limit.

In another aspect of the electro-optical device of the present invention, the semiconductor layer has an SOI structure made of a single crystal silicon film.

According to this aspect, by the SOI technology, a high-performance driving MOSFET, a pixel switching TFT, etc. are formed by using a single crystal silicon thin film having excellent crystallinity.
A transistor element having excellent transistor characteristics such as high speed, low power consumption, and high integration can be built on a supporting substrate.

In another aspect of the electro-optical device of the present invention, the semiconductor layer is made of a polysilicon film or an amorphous silicon film.

According to this aspect, a transistor element can be constructed at a relatively low cost by using a semiconductor layer made of a polysilicon film or an amorphous silicon film on a supporting substrate such as a glass substrate or a quartz substrate.

In another aspect of the electro-optical device of the present invention, the light shielding film contains a refractory metal.

According to this aspect, the light shielding film is, for example, T
i (titanium), Cr (chrome), W (tungsten),
A refractory metal such as a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of these, which contains at least one refractory metal such as Ta (tantalum), Mo (molybdenum), or Pb (lead). Consisting of a film containing. Therefore, a high light blocking performance can be obtained by the light blocking film.

The light-shielding film may be made of a silicon film which shields light by partially absorbing light.

In another aspect of the electro-optical device of the present invention, the total layer thickness of the silicon nitride film or the silicon nitride oxide film of the insulating portion is 100 nm or less.

According to this aspect, since the total film thickness of the silicon nitride film or the silicon nitride oxide film having the light absorption characteristics having frequency dependence is 100 nm or less, the display light is transmitted through the insulating portion. Even when the above structure is adopted, coloring of display light due to light absorption in the insulating portion can be reduced. For example, it has been found that a yellowish tint is obtained when light for display is transmitted through a silicon nitride film or a silicon nitride oxide film having a thickness of 100 nm or more. Film thickness is 100 nm
By the following, it is possible to reduce the yellowish phenomenon. In particular, according to this aspect, it is possible to reduce the yellowish phenomenon by further reducing the total film thickness of the silicon nitride film or the silicon nitride oxide film.

In another aspect of the electro-optical device of the present invention, the electro-optical device further includes an opposite substrate arranged to face the supporting substrate, and an electro-optical material layer sandwiched between the supporting substrate and the opposite substrate. .

According to this aspect, an electro-optical device such as a liquid crystal device is constructed in which an electro-optical material layer such as liquid crystal is sandwiched between a pair of support substrates and a counter substrate. In particular, since the light shielding film and the insulating portion as described above are provided,
Excellent light shielding performance can be maintained, and high-quality image display can be performed for a long period of time.

In order to solve the above problems, the electronic equipment of the present invention includes the above-described electro-optical device of the present invention (however, including various aspects thereof).

According to the electronic apparatus of the present invention, since it is provided with the above-described electro-optical device of the present invention, it is possible to display a bright and high-quality image for a long period of time. Notebook, word processor, viewfinder type or monitor direct view type video tape recorder,
Various electronic devices such as workstations, videophones, POS terminals, and touch panels can be realized.

In order to solve the above-mentioned problems, the method for manufacturing an electro-optical device according to one aspect of the present invention includes a step of forming a light-shielding film in a predetermined region on a supporting substrate, and a direct or interlayer insulating film on the light-shielding film. A step of forming an insulating portion containing a silicon nitride film or a silicon nitride oxide film via the above step, a step of forming a semiconductor layer on the insulating portion directly or via an interlayer insulating film, and using the semiconductor layer as a constituent element The method includes a step of forming a transistor element in which a channel region is arranged at a position covered by a light-shielding film from below, and a step of forming a wiring and a pixel electrode connected to the transistor element.

According to this manufacturing method, first, a light-shielding film is formed in a predetermined region (for example, a lattice-shaped, stripe-shaped, island-shaped region or the like) on a supporting substrate such as a glass substrate, a silicon substrate, or a quartz substrate. . Here, a light-shielding film is formed by forming a light-shielding film on one surface by sputtering of a refractory metal, and then patterning by photolithography and etching. Subsequently, an insulating portion including a silicon nitride film or a silicon oxynitride film is formed directly on this or through an interlayer insulating film such as a silicon oxide film. Here, for example, a silicon oxide film may be first formed, and the surface thereof may be nitrided or oxynitrided with dinitrogen monoxide or nitric oxide, or a silicon nitride film or a silicon nitride oxide film may be formed by a CVD method. Further thereon, a semiconductor layer such as a polysilicon film, an amorphous silicon film, a single crystal silicon film or the like is formed directly or through an interlayer insulating film.
Then, at least in the light incident region or the image display region, the channel region is arranged at a position covered by the light shielding film from below with the semiconductor layer as a constituent element.
And other transistor elements are formed. Then, the wiring connected to the transistor element is formed from a conductive metal film, a polysilicon film, or the like, and the pixel electrode is made of ITO (Indium Titanium).
in Oxide) film or the like. Therefore, it is possible to relatively easily manufacture the electro-optical device of the present invention in which at least the insulating portion is provided above the light shielding film as described above.

In one mode of this manufacturing method, before the step of forming the light shielding film, the method further includes the step of forming another insulating portion including a silicon nitride film or a silicon nitride oxide film on the supporting substrate.

According to this aspect, on the supporting substrate,
Since another insulating portion including a silicon nitride film or a silicon nitride oxide film is formed before the formation of the light-shielding film, the light-shielding film is sandwiched between the two insulating portions as described above. The electro-optical device can be manufactured relatively easily.

In order to solve the above-mentioned problems, another method of manufacturing an electro-optical device according to the present invention comprises a step of forming an insulating portion containing a silicon nitride film or a silicon oxynitride film on a supporting substrate, and a step on the insulating portion. A step of forming a light-shielding film in a predetermined region directly or via an interlayer insulating film; a step of forming a semiconductor layer on the light-shielding film directly or via an interlayer insulating film; The method includes a step of forming a transistor element in which a channel region is arranged at a position covered with a film from below, and a step of forming a wiring and a pixel electrode connected to the transistor element.

According to this manufacturing method, first, an insulating portion including a silicon nitride film or a silicon nitride oxide film is formed on a supporting substrate such as a glass substrate, a silicon substrate or a quartz substrate. Here, for example, a silicon oxide film may be first formed, and the surface thereof may be nitrided or oxynitrided with dinitrogen monoxide or nitric oxide, or a silicon nitride film or a silicon nitride oxide film may be formed by a CVD method. Then, a light-shielding film is formed on a predetermined region (for example, a lattice-shaped, stripe-shaped, island-shaped region, etc.) on the insulating portion directly or through an interlayer insulating film such as a silicon oxide film. Here, a light-shielding film is formed by forming a light-shielding film on one surface by sputtering of a refractory metal, and then patterning by photolithography and etching. Further thereon, a semiconductor layer such as a polysilicon film, an amorphous silicon film, a single crystal silicon film or the like is formed directly or through an interlayer insulating film. Then, at least in the light incident area or the image display area, a transistor element such as a TFT is formed in which the semiconductor layer is used as a constituent element and a channel region is arranged at a position covered by the light shielding film from the lower side. Then, the wiring connected to this transistor element is formed from a conductive metal film, a polysilicon film, or the like, and the pixel electrode is I
It is formed from a TO (Indium Tin Oxide) film or the like. Therefore, the electro-optical device of the present invention in which at least the insulating portion is provided under the light shielding film as described above can be relatively easily manufactured.

In another aspect of the method of manufacturing an electro-optical device of the present invention, in the step of forming the semiconductor layer, the single crystal silicon substrate on which the semiconductor layer is formed, the light shielding film and the insulating portion are formed. The method includes a step of bonding the supporting substrate and a step of thinning the single crystal silicon substrate after bonding.

According to this aspect, first, the semiconductor layer is separately formed on the single crystal silicon substrate, and this single crystal silicon substrate is bonded to the support substrate on which the light shielding film and the insulating portion have already been formed. Here, for example, a silicon oxide film is formed on the bonding surface, the bonding surface is flattened, and then the two substrates are brought into close contact with each other by utilizing hydrogen bonding force, and further heat treatment is performed to increase the bonding strength. By. Then, the single crystal silicon substrate is thinned. Here, for example, leaving the semiconductor layer on the support substrate side,
The single crystal silicon substrate may be thinned by peeling the single crystal silicon substrate from the supporting substrate side. Alternatively, the single crystal silicon substrate may be thinned by etching, polishing, grinding, or the like with respect to the single crystal silicon substrate. Therefore, the electro-optical device of the present invention having an extremely high performance transistor element having a single crystal silicon film as a semiconductor layer on the SOI substrate as described above can be relatively easily manufactured.

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The following embodiments apply the electro-optical device of the present invention to a liquid crystal device of a TFT active matrix driving system.

(SOI Substrate) First, S constituting an example of an element substrate suitably used for the electro-optical device of this embodiment.
The OI substrate will be described.

First, FIG. 1 shows a sectional structure of an SOI substrate according to an embodiment of the present invention, and the structure of this SOI substrate 200 will be described.

As shown in FIG. 1, the SOI substrate 200 of the present embodiment comprises a support substrate 201 made of silicon, quartz, glass or the like and a single crystal silicon layer 202, and the support substrate 201 and the single crystal silicon layer 202. An insulating portion 205 having a laminated structure of a plurality of insulating films is formed between and. In this embodiment, the insulating portion 205 is the support substrate 20.
A first silicon oxide film 203B, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A are sequentially stacked from the first side.

Next, a method of manufacturing the SOI substrate 200 having the above structure will be described as a method of manufacturing the SOI substrate according to this embodiment with reference to FIGS. Figure 2
(A)-(e) and FIG. 3 (a)-(c) have shown sectional drawing in each process, respectively. The manufacturing method described below is an example, and the present invention is not limited to the method described below.

First, as shown in FIG. 2A, a single crystal silicon substrate 202A having a film thickness of, for example, about 300 to 900 μm is prepared, and as shown in FIG. 2B, the single crystal silicon substrate 202A is formed. A first silicon oxide film having a film thickness of, for example, about 5 to 400 nm is formed on one surface of the single crystal silicon substrate 202A by thermally oxidizing one surface at 700 to 1150 ° C. in an O ₂ or H ₂ O atmosphere. 203B is formed.

Next, as shown in FIG. 2C, the single crystal silicon substrate 2 on which the first silicon oxide film 203B is formed.
By nitriding or oxynitriding the surface of 02A at 800 to 1150 ° C. in an atmosphere of dinitrogen monoxide or nitric oxide, a silicon nitride film or a silicon nitride oxide film is formed on the single crystal silicon substrate 202A side of the first silicon oxide film 203B. The film 204 is formed.

When the supporting substrate 201 is made of a light-transmitting substrate such as a quartz substrate or a glass substrate, and the SOI substrate 200 is applied to a light-transmitting device such as a transmissive liquid crystal device, In order to prevent a decrease in light transmittance due to the presence of the silicon nitride film or the silicon nitride oxide film 204, the thickness of the silicon nitride film or the silicon nitride oxide film 204 is preferably 100 nm or less. Particularly, by reducing the total film thickness of the silicon nitride film or the silicon nitride oxide film, the yellowish phenomenon can be reduced. Particularly, it is desirable that the total film thickness of the silicon nitride film or the silicon nitride oxide film be 10 nm or less. This makes it possible to suppress the decrease in transmittance within a few percent.

Next, as shown in FIG. 2D, the surface of the single crystal silicon substrate 202A on which the silicon nitride film or the silicon nitride oxide film 204 is formed is heated at 700 to 1150 ° C. in an O ₂ or H ₂ O atmosphere. By thermal oxidation, a second silicon oxide film 203A having a film thickness of, for example, about 5 to 400 nm is formed on the silicon nitride film or the silicon nitride oxide film 204 on the single crystal silicon substrate 202A side.
As described above, the insulating portion 205 including the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A is formed on the surface of the single crystal silicon substrate 202A.

Next, as shown in FIG. 2E, hydrogen ions (H ⁺ ) are applied to the surface of the single crystal silicon substrate 202A having the insulating portion 205 formed on the insulating portion 205 side, for example, at an accelerating voltage of 100 keV and a dose. Inject at a dose of 10 × 10 ¹⁶ / cm ² . By this processing, the single crystal silicon substrate 20
A high concentration layer 206 of hydrogen ions is formed in 2A.

Next, as shown in FIG. 3A, the insulating portion 2
05 The surface (the surface of the first silicon oxide film 203B) is used as the bonding surface, and the single crystal silicon substrate 202A and the supporting substrate 201 made of silicon, quartz, glass, or the like are bonded to each other. The hydrogen bonding force of In the bonding step, for example, a method of directly bonding the two substrates by performing heat treatment at 300 ° C. for 2 hours can be adopted. Also,
To further increase the bonding strength, it is necessary to further raise the heat treatment temperature to about 450 ° C., but the support substrate 201 made of quartz or the like and the single crystal silicon substrate 202.
Since the coefficient of thermal expansion of A has a large difference, if heated as it is, defects such as cracks may occur in the single crystal silicon layer, and the quality of the manufactured SOI substrate 200 may deteriorate.

Therefore, in order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 202A, which has been once subjected to the heat treatment for bonding at 300 ° C., is subjected to wet etching or CMP (chemical mechanical polishing). It is desirable to perform a heat treatment at a higher temperature after the thickness is reduced to about 100 to 150 μm by the method). For example 80 ℃
After the single crystal silicon substrate 202A is etched to a thickness of 150 μm using the KOH aqueous solution, the substrate is bonded to the supporting substrate 201, and heat treatment is performed again at 450 ° C. to increase the bonding strength. desirable.

Next, as shown in FIG. 3B, the two bonded substrates are heat-treated to form the supporting substrate 20.
Most of the single crystal silicon substrate 202A is peeled off while leaving the thin film single crystal silicon layer 202 on the surface of No. 1. The peeling phenomenon of the substrate occurs because hydrogen ions introduced into the single crystal silicon substrate 202A break the silicon bond. That is, in the single crystal silicon substrate 202A, the high concentration layer 206 of hydrogen ions is
The single crystal silicon substrate 202A can be divided at a portion in the vicinity of the boundary between the ion implantation region and the portion not implanted with hydrogen ions.

The heat treatment for peeling the single crystal silicon substrate 202A is, for example, 2 times per minute for two bonded substrates.
It can be performed by heating to 600 ° C. at a temperature rising rate of 0 ° C. By this heat treatment, most of the bonded single crystal silicon substrate 202A is supported substrate 20.
1, the single crystal silicon layer 202 having a film thickness of, for example, about 200 nm ± 5 nm is formed on the surface of the supporting substrate 201. Note that the single crystal silicon layer 202
Can be formed with an arbitrary film thickness from 50 nm to 3000 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 202A described above.

As described above, the SOI substrate 200 is manufactured as shown in FIG.

After the single crystal silicon substrate 202A and the supporting substrate 201 are bonded together, the single crystal silicon substrate 2
The method for forming the single crystal silicon layer 202 by thinning 02A is not limited to the method using hydrogen ions described above, and the thin single crystal silicon layer 202 is formed by bonding a single crystal silicon substrate and a supporting substrate to each other. After that, the surface of the single crystal silicon substrate is polished to have a film thickness of 3 to 5 μm, and then PACE (Plasma Assist)
d Chemical Etching) is used to finish the film by etching to a thickness of about 0.05 to 0.8 μm, or an epitaxial silicon layer formed on the porous silicon is selectively etched to form a porous silicon layer on a supporting substrate. ELTRAN to transfer to
(Epitaxial Layer Transfer
It can also be obtained by method r).

According to the method of manufacturing the SOI substrate of this embodiment, the silicon nitride film or the silicon nitride oxide film 20 is formed on the surface.
4A formed with single crystal silicon substrate 202A and supporting substrate 2
By bonding 01 and 01, the silicon nitride film or the silicon nitride oxide film 204 can be positioned closer to the single crystal silicon layer 202 than the bonding surface of the supporting substrate 201 and the single crystal silicon substrate 202A. It is possible to completely prevent the impurities contained in 201 and the impurities adsorbed on the bonding surface of the supporting substrate 201 and the single crystal silicon substrate 202A from diffusing to the single crystal silicon layer 202 side.

In particular, according to the method for manufacturing an SOI substrate of the present embodiment, a light-shielding film that covers at least the channel region of the pixel switching TFT from the support substrate 201 side and shields the return light is provided on the support substrate 201 as described later. In the case of being formed as described above, the insulating portion 205 including the silicon nitride film or the silicon nitride oxide film 204, which is a dense film having a low transmittance with respect to oxidizing species or impurities such as oxygen and moisture, is shielded from a refractory metal or the like. It is possible to effectively prevent the oxidation species from diffusing into the film, and at the same time, from the light shielding film to the single crystal silicon layer 20.
Impurities can be effectively prevented from diffusing into 2.

Further, the second silicon oxide film 203A, the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 203B are formed by the CVD method or the like.
May be sequentially laminated on the surface of the single crystal silicon substrate 202A. However, in this case, the manufacturing process becomes complicated, and the second silicon oxide film 203A, the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 203A.
The film thickness of the silicon oxide film 203B may become uneven.

However, in this embodiment, after the first silicon oxide film 203B is formed by thermally oxidizing the surface of the single crystal silicon substrate 202A, the single crystal silicon substrate 202A on which the first silicon oxide film 203B is formed is formed.
By nitriding or oxynitriding the surface, a silicon nitride film or a silicon nitride oxide film 204 is formed on the single crystal silicon substrate 202A side of the first silicon oxide film 203B, and the silicon nitride film or the silicon nitride oxide film 20 is further formed.
Since the method of forming the second silicon oxide film 203A on the single crystal silicon substrate 202A side of the silicon nitride film or the silicon nitride oxide film 204 by adopting the method of thermally oxidizing the surface of the single crystal silicon substrate 202A on which No. 4 is formed, Flat first silicon oxide film 203 having a uniform film thickness
B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A can be formed. By forming these films having a uniform thickness in this way, it is possible to prevent the occurrence of voids on the bonding surface between the supporting substrate 201 and the single crystal silicon substrate 202A, and improve the bonding strength. In addition, when a transistor element or the like is formed using the SOI substrate 200, film peeling or the like can be prevented from occurring, so that the yield of products can be improved.

Further, according to this method, the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A can be formed integrally with the single crystal silicon substrate 202A. Therefore, the SOI substrate 200 in which the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, the second silicon oxide film 203A, and the single crystal silicon layer 202 have high mutual adhesion can be manufactured. it can.

Further, according to the present embodiment, the first silicon oxide film 203B is formed on the surface of the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 20 is formed.
Since the surface of 3B is used as the bonding surface, the first silicon oxide film 203B is not formed on the surface of the silicon nitride film or the silicon nitride oxide film 204, and the surface of the silicon nitride film or the silicon nitride oxide film 204 is bonded to the bonding surface. Adhesion between the support substrate 201 and the single crystal silicon substrate 202A can be improved more than in the case described above, and the bonding strength can be improved.

The first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A are formed on the single crystal silicon substrate 20.
In the case where a flat film can be formed by using a CVD method or the like instead of integrally forming with 2A, the first silicon oxide film 203B, the silicon nitride film or the silicon nitride film other than those described in the above manufacturing method or The method for forming the silicon nitride oxide film 204 and the second silicon oxide film 203A, and the bonding pattern of the single crystal silicon substrate 202A and the supporting substrate 201 can be given as examples.

Further, in the present embodiment, the second silicon oxide film 203A is formed after the silicon nitride film or the silicon nitride oxide film 204, which is formed on the single crystal silicon substrate 202A. This is only when lattice defects are formed when the silicon oxide film 204 is directly formed. In particular, since a lattice defect is less likely to be formed when the silicon nitride oxide film is formed, the second silicon oxide film 203A may not be formed.

Next, based on FIGS. 4A to 4D, a first silicon oxide film 203B other than the above, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A are formed. The method and the bonding pattern will be briefly described. 4 (a) to 4 (d) respectively,
FIG. 4 is a cross-sectional view showing a combination of a support substrate 201 and a single crystal silicon substrate 202A that are to be bonded together and taken out.

As shown in FIG. 4A, the second silicon oxide film 203A, the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 203A are formed on the surface of the single crystal silicon substrate 202A by the CVD method. After the films 203B are sequentially formed, the single crystal silicon substrate 202A and the supporting substrate 201 may be attached to each other.

Further, after the second silicon oxide film 203A is formed by thermally oxidizing the surface of the single crystal silicon substrate 202A, the silicon nitride film or the silicon nitride oxide film 204 and the first silicon oxide film are formed by the CVD method. Two
03B and the like, and the CV method described above.
It may be formed in combination with the D method.

When a silicon oxide film and a silicon nitride film or a silicon oxynitride film are formed on the surface of the single crystal silicon substrate 202A by the CVD method, FIG.
As shown in (b), the silicon nitride film or the silicon nitride oxide film 204 may be formed directly without providing the second silicon oxide film 203A on the surface of the single crystal silicon substrate 202A.

Even with such a structure, the silicon nitride film or the silicon oxynitride film 204 can be located closer to the single crystal silicon layer 202 than the bonding surface between the supporting substrate 201 and the single crystal silicon substrate 202A. Impurities contained in the supporting substrate 201 and the supporting substrate 201
It is also possible to completely prevent the impurities adsorbed on the bonding surface between the single crystal silicon substrate 202A and the single crystal silicon substrate 202A from diffusing to the single crystal silicon layer 202 side.

In FIGS. 4A and 4B, the case where the silicon oxide film and the silicon nitride film or the silicon oxynitride film are formed on the single crystal silicon substrate 202A side and then bonded is described. The invention is not limited to this. Below, FIG. 4 (c) and (d)
A case where a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is formed on the supporting substrate 201 side and then bonding is performed will be described with reference to FIG.

As shown in FIG. 4C, the first silicon oxide film 203 is formed on the surface of the supporting substrate 201 by the CVD method.
B, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A are sequentially formed,
The support substrate 201 and the single crystal silicon substrate 202A may be attached to each other.

In this case, it is desirable to previously form the silicon oxide film 203C on the surface of the single crystal silicon substrate 202A by the thermal oxidation or the CVD method. In this way, the supporting substrate 201 and the single crystal silicon substrate 202 are formed.
By forming the outermost surface on the bonding side of any of the substrates A as a silicon oxide film, the adhesion between the two substrates after bonding can be improved.

When the supporting substrate 201 is made of a quartz substrate or a glass substrate, since the main component of the supporting substrate 201 is silicon oxide, as shown in FIG. The first silicon oxide film 203B does not have to be formed, and the supporting substrate 201 is formed by a CVD method.
After sequentially forming a silicon nitride film or a silicon nitride oxide film 204 and a second silicon oxide film 203A on the side,
This support substrate 201 and the single crystal silicon substrate 202A having a silicon oxide film 203C formed on the surface may be bonded together.

In the bonding patterns shown in FIGS. 4C and 4D, since the silicon nitride film or the silicon oxynitride film 204 is formed on the supporting substrate 201 side with respect to the bonding surface, the supporting substrate The impurities contained in 201 can be prevented from diffusing to the single crystal silicon layer 202 side, but the impurities adsorbed on the bonding surface cannot be prevented from diffusing to the single crystal silicon layer 202 side. That is, the bonding patterns shown in FIGS. 4C and 4D are effective when a substrate containing impurities such as a quartz substrate or a glass substrate is used as the supporting substrate 201.

And, in particular, S shown in FIGS. 4C to 4D is used.
According to the manufacturing method of the OI substrate, as in the case of the manufacturing method shown in FIGS. 2 and 3, a light shielding film for covering the channel region of the pixel switching TFT from the supporting substrate 201 side is formed on the supporting substrate 201 as described later. When formed, the insulating portion including the silicon nitride film or the silicon oxynitride film 204 can effectively prevent the diffusion of the oxidizing species into the light shielding film, and at the same time,
Impurities can be effectively prevented from diffusing from the light shielding film to the single crystal silicon layer 202.

(Element Substrate) Next, an element substrate manufactured by using the SOI substrate 200 as described above and suitably used for the electro-optical device of this embodiment will be described with reference to FIG.

In FIG. 5, the element substrate 210 is an SOI.
After the single crystal silicon layer 202 of the substrate 200 is formed in a predetermined pattern, a TFT is formed using this single crystal silicon layer.
It is manufactured by forming (transistor element). 5, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 5, a TFT 220, which is an example of a transistor element, includes a single crystal silicon layer 202 manufactured on the SOI substrate 200 as described above, and a semiconductor layer 20.
Configured as eight. Further, in FIG. 5, a support substrate 201, an insulating portion 205 including a first silicon oxide film 203B and a silicon nitride film or a silicon nitride oxide film 204 and a second silicon oxide film 203A, and a single crystal silicon layer 202 are formed. Semiconductor layer 208 is SOI
It is a substrate.

As shown in FIG. 5, a TFT 220 including a semiconductor layer 208, a gate insulating film 209, a gate electrode 211, a source electrode 215, a drain electrode 216, and an interlayer insulating film 212 is formed on the surface of the insulating portion 205. ing.

More specifically, the gate insulating film 209 is formed on the surface of the supporting substrate 201 on which the semiconductor layer 208 is formed, and the gate electrode 211 is formed on the surface of the gate insulating film 209. Further, an interlayer insulating film 212 is provided on the surface of the support substrate 201 on which the gate electrode 211 is formed.

Interlayer insulating film 212 and gate insulating film 209
Are formed with contact holes 217 and 218 which communicate with a source region and a drain region (both not shown) formed in the semiconductor layer 208, and the source electrode 215 and the drain electrode 216 are respectively formed with contact holes 217 and 218. It is formed so as to be electrically connected to the source region and the drain region of the semiconductor layer 208 via.

The element substrate 210 of this embodiment is the same as the above S.
Since it is formed using the OI substrate 200, the impurities contained in the support substrate 201 and the support substrate 201
It is possible to completely prevent the impurities adsorbed on the bonding surface of the single crystal silicon substrate 202A and the single crystal silicon substrate 202A from diffusing to the semiconductor layer 208 (TFT 220) side.
It is possible to prevent the deterioration of the characteristics of No. 20.

In particular, according to the element substrate 210 of the present invention, the TFT 220 is connected to the pixel switching TF as described later.
In the case where T is provided in an image display region where incident light or return light is incident, a light-shielding film that covers at least the channel region of the semiconductor layer 208 forming the TFT 220 from the support substrate 201 side to shield the return light is supported. When formed on the substrate 201, the insulating portion 205 including the silicon nitride film or the silicon nitride oxide film 204 can effectively prevent the diffusion of the oxidizing species into the light shielding film. At the same time, the insulating film 205 can effectively prevent impurities from diffusing from the light shielding film to the semiconductor layer 208.

(Electro-Optical Device) Next, as an embodiment according to the electro-optical device of the present invention, an active matrix type using a TFT (transistor element) as a switching element, which is preferably used in a projection type display device such as a projector. This liquid crystal device will be described with reference to FIGS. 18 and 19 and FIGS. 6 to 8.

The liquid crystal device of this embodiment basically includes an element substrate (see FIG. 5) manufactured by using the SOI substrate (see FIGS. 1 to 4) described above. That is, the basic structure of the element substrate constituting the electro-optical device of the present embodiment, as described above, includes a silicon nitride film or a silicon nitride oxide film on the surface of the substrate body corresponding to the supporting substrate. A TFT provided with an insulating portion and a semiconductor layer formed from a single crystal silicon layer above the insulating portion.
Has been formed.

Further, in the projection type display device, light is normally incident from the substrate side (surface of the liquid crystal device) of the two substrates constituting the liquid crystal device, the side facing the element substrate. In order to prevent light leakage current from being generated by being incident on the channel region of the TFT formed on the surface of the element substrate, TF
It is common to have a structure in which a light shielding layer is provided on the side on which the T light is incident.

However, even if the light-shielding layer is provided on the side of the TFT where light is incident, the light incident on the liquid crystal device may be reflected by the interface on the back surface of the element substrate and incident on the channel portion of the TFT as return light. . This return light is a small proportion of the amount of light incident from the surface of the liquid crystal device,
In a device using a very strong light source such as a projector, a sufficient light leak current can occur. That is, the return light from the back surface of the element substrate affects the switching characteristics of the TFT and deteriorates the characteristics of the device.

Therefore, in the present embodiment, in order to prevent the deterioration of the characteristics of the TFT due to such return light,
A light-shielding film is provided immediately above the substrate body corresponding to the supporting substrate so as to correspond to each TFT (transistor element). Further, in order to electrically insulate the light-shielding film made of metal or the like from the semiconductor layer forming the TFT, The first silicon oxide film, the silicon nitride film, or the silicon nitride oxide film, and the second silicon oxide film are provided as an insulating portion.

First, various concrete examples of the structure in which the light shielding film is formed below the TFT in the electro-optical device of this embodiment will be described with reference to FIGS. 17 (a) to 17 (c) and 18 (a).
(C) and FIGS. 19 (a), (b), FIG. 20 (a),
This will be described with reference to (b). 17 (a) to (c)
18 (a) to 18 (c), the same components as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be appropriately omitted.

In the specific example shown in FIG. 17A, the first light shielding film 11a is provided immediately above the support substrate 201 so as to correspond to each TFT (transistor element) 220. Such a first light-shielding film 11a is made of, for example, Ti (titanium) or Cr.
(Chrome), W (tungsten), Ta (tantalum),
It is composed of a film containing a refractory metal, such as a simple metal, an alloy, a metal silicide, a polysilicide, or a laminated layer thereof, which contains at least one refractory metal such as Mo (molybdenum) or Pb (lead). Alternatively, the first light shielding film 11a is
It may be made of a light absorbing film such as a silicon film that shields light by partially absorbing light, or may have a high reflectance of Al.
It may be made of an (aluminum) film or the like. The plane pattern of the first light shielding film 11a may have a predetermined shape such as a lattice shape, a stripe shape, or an island shape, but at least the semiconductor layer 2
The channel region of 08 is on the supporting substrate 201 side (lower side in the figure)
It is formed so as to cover from. Then, between the first light-shielding film 11a and the TFT 220 configured as described above,
An insulating portion 205 including a first silicon oxide film 203B, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A is formed. As a result, the impurities contained in the supporting substrate 201 and the impurities adsorbed on the bonding surface between the supporting substrate 201 and the single crystal silicon substrate 202A are absorbed in the semiconductor layer 208 (TFT 220).
Since it can be prevented from diffusing to the side,
The deterioration of the characteristics of 220 can be prevented.

Furthermore, in this specific example, when the step of separating the semiconductor layer 208 by LOCOS or the like is included, or when the step of thinning the semiconductor layer 208 to thin the semiconductor layer 208 is included, or the gate oxidation is performed. Even when the step of forming the film 209 is performed, in the oxidation step, the silicon nitride film or the silicon nitride oxide film 204 above the first light-shielding film 11a is prevented from diffusing an oxidizing species, and for example, a refractory metal film or the like. It is possible to prevent the first light-shielding film 11a made of 1 from being oxidized. Thereby, the first light-shielding film 1
It can be effectively prevented that 1a is oxidized and the light transmittance of the first light-shielding film 11a is increased, that is, the light-shielding function of the first light-shielding film 11a is deteriorated. In addition, impurities are removed from the semiconductor layer 20 from the first light-shielding film 11a made of, for example, a refractory metal film.
8 can be effectively prevented by the silicon nitride film or the silicon oxynitride film 204, and the deterioration of the transistor characteristics of the TFT 220 due to such diffusion of impurities can be prevented.

Next, in the specific example shown in FIG. 17B, the first light shielding film 11a is provided immediately above the support substrate 201 so as to correspond to each TFT 220, and the first light shielding film 11a and the TF.
A silicon nitride film or a silicon nitride oxide film 204 and a silicon oxide film 203A are formed between T220 and T220. Thus, the impurities contained in the supporting substrate 201, the supporting substrate 201 and the single crystal silicon substrate 202A
Impurities adsorbed on the bonding surface of the semiconductor layer 208
Since it can be prevented from diffusing to the (TFT 220) side, deterioration of the characteristics of the TFT 220 can be prevented.

Furthermore, in this specific example, when the step of separating the semiconductor layer 208 by LOCOS or the like is included, or when the step of oxidizing the semiconductor layer 208 to thin the semiconductor layer 208 is included, or when the gate oxide film is formed. Even when the step of forming 209 is performed, in the oxidation step, the silicon nitride film or the silicon oxynitride film 204 immediately above the first light-shielding film 11a is used to prevent the oxidation species from diffusing, and, for example, from a refractory metal film or the like. It is possible to prevent the first light-shielding film 11a that is formed from being oxidized. Thereby, the first light-shielding film 1
It can be prevented that 1a is oxidized and the light transmittance of the first light shielding film 11a is increased, that is, the light shielding function of the first light shielding film 11a is deteriorated. In addition, impurities may diffuse into the semiconductor layer 208 from the first light-shielding film 11a made of, for example, a refractory metal film, and the silicon nitride film or the silicon nitride oxide film 2 may be diffused.
04, the deterioration of the transistor characteristics of the TFT 220 due to such diffusion of impurities can be prevented.

Next, in the specific example shown in FIG. 17C, the silicon nitride film or the silicon nitride oxide film 204 is not substantially on one surface of the supporting substrate 201 as compared with the specific example of FIG. 17B described above. It is formed to have a plane pattern that is slightly larger than the first light shielding film 11a having a plane pattern of a predetermined shape. Other configurations are shown in FIG.
This is similar to the case of the specific example of 7 (b). Therefore, it is possible to prevent the impurities contained in the support substrate 201 and the impurities adsorbed on the bonding surface of the support substrate 201 and the single crystal silicon substrate 202A from diffusing to the semiconductor layer 208 (TFT 220) side. Further, it is possible to prevent the diffusion of the oxidizing species in the silicon nitride film or the silicon nitride oxide film 204 immediately above the first light shielding film 11a. In addition, it is possible to prevent impurities from diffusing from the first light shielding film 11a into the semiconductor layer 208.

Especially, in this specific example, since the silicon nitride film or the silicon nitride oxide film 204 is provided almost or not in the opening region of each pixel which actually contributes to the display by transmitting the display light, This silicon nitride film or silicon oxynitride film 204 can prevent the situation where the light transmittance in the opening region is lowered. In particular, since the light transmittance of the silicon nitride film or the silicon nitride oxide film 204 has wavelength dependency, the presence of the silicon nitride film or the silicon nitride oxide film 204 causes the display light to be colored (for example, a screen image). This is advantageous because it avoids the situation where the whole becomes yellowish. Further, in this specific example, it is possible to increase the film thickness of the insulating portion as compared with the case of FIG. 17B by taking advantage of the above advantages, and it is possible to further prevent diffusion of oxidizing species. In this specific example, it is particularly desirable that the etching end of the insulating part is within 2 μm from the etching end of the light shielding film in the light transmitting part. This makes it possible to suppress the decrease in light transmittance due to the insulating portion in the opening region within several percent. Next, in the specific example shown in FIG. 19A, compared with the specific example shown in FIG. 17C, the etching end of the substantially insulating portion is formed in substantially self-alignment with the etching end of the light shielding film in the light transmitting portion. There is. As a result, the etching end of the insulating portion in the light transmitting portion of the opening region can be suppressed to 1 μm or less as compared with the etching end of the light shielding film, so that the reduction of the light transmittance of the insulating portion in the opening region is further suppressed. It will be possible. Further, particularly in the present specific example, as shown in FIG. 19B, it is possible to perform the exposure simply by exposing and removing the resist 221 by backside exposure or the like while leaving the shaded portion, and the specific example of FIG. It is possible to significantly reduce the cost compared to the example.

Next, in the specific example shown in FIG. 18A, the silicon nitride film or silicon oxynitride film 204A is provided above the first light-shielding film 11a as compared with the specific example of FIG. 17B described above. However, it is provided on the lower side, and other configurations are similar to those of the specific example of FIG. 17B described above. Therefore, it is possible to prevent the impurities contained in the support substrate 201 from diffusing to the semiconductor layer 208 (TFT 220) side. Furthermore, it is possible to prevent the diffusion of the oxidizing species in the silicon nitride film or the silicon nitride oxide film 204A immediately below the first light shielding film 11a.

Next, in the specific example shown in FIG. 18B, the silicon nitride films or the silicon nitride oxide films 204A and 204B are different from those in the specific example of FIG. 17B or FIG. It is provided not only on the upper side or the lower side of the first light-shielding film 11a, but also on the upper and lower sides. Other configurations are similar to those in the specific example of FIG. 17B or FIG. 18A described above. Therefore, the first light shielding film 11a
Silicon nitride film or silicon oxynitride film 204 immediately above
It is possible to prevent the oxidizing species from diffusing in the silicon nitride film or the silicon oxynitride film 204A immediately below B and the first light shielding film 11a. In addition, diffusion of impurities from the first light-shielding film 11a into the semiconductor layer 208 can also be effectively prevented by the silicon nitride film or the silicon nitride oxide film 204B.

Next, in the specific example shown in FIG. 18C, the silicon nitride film or the silicon nitride oxide films 204A and 204B are formed on almost one surface of the support substrate 201 as compared with the specific example of FIG. 18B described above. Instead, it is formed to have a plane pattern that is slightly larger than the first light-shielding film 11a having a plane pattern of a predetermined shape. Other configurations are similar to those of the specific example of FIG. 18 (b) described above.
Therefore, the impurities contained in the supporting substrate 201 and the impurities adsorbed on the bonding surface between the supporting substrate 201 and the single crystal silicon substrate 202A are absorbed in the semiconductor layer 208 (TFT22).
It is possible to prevent the diffusion to the 0) side. Further, it is possible to prevent the diffusion of the oxidizing species in the silicon nitride film or silicon nitride oxide film 204B immediately above the first light shielding film 11a and the silicon nitride film or silicon nitride oxide film 204A immediately below the first light shielding film 11a. In addition, diffusion of impurities from the first light-shielding film 11a into the semiconductor layer 208 can also be effectively prevented by the silicon nitride film or the silicon nitride oxide film 204B.

Then, particularly in this specific example, FIG.
As in the case of the specific example shown in FIG.
Since the silicon nitride film or the silicon nitride oxide film 204A or 204B may be hardly or not provided at all, the silicon nitride film or the silicon nitride oxide film 204A or 204B is not provided.
By B, it is possible to avoid the situation where the light transmittance in the opening region is lowered. In particular, since the light transmittances of the silicon nitride films or the silicon nitride oxide films 204A and 204B have frequency dependence, the presence of the silicon nitride films or the silicon nitride oxide films 204A and 204B causes the display light to be colored ( This is advantageous because it is possible to avoid a situation where the entire screen becomes yellowish.

In this specific example, the silicon nitride film or the silicon nitride oxide film 204A is simultaneously etched at the time of etching the silicon nitride film or the silicon nitride oxide film 204B. There is no big difference even if you leave.

Particularly in this embodiment, as in the specific examples shown in FIGS. 17A and 17B and FIGS. 18A and 18B, the silicon nitride film or the nitride film is also formed in the opening region of each pixel. When adopting the structure in which the silicon oxide film 204, 204A, or 204B is provided, it is desirable that the total film thickness of the silicon nitride film or the silicon nitride oxide film be 100 nm or less. According to this structure, it is possible to reduce the light transmittance in the opening region of each pixel due to the presence of the silicon nitride film or the silicon oxynitride film, and to reduce the coloring of the display light to the extent that it cannot be visually recognized on the display image. Particularly, by reducing the total film thickness of the silicon nitride film or the silicon nitride oxide film, the yellowish phenomenon can be reduced. Further, it is desirable that the total film thickness of the silicon nitride film or the silicon nitride oxide film be 10 nm or less. This makes it possible to suppress the decrease in transmittance within a few percent.

In particular, FIGS. 17 (c) and 18 (c)
The silicon nitride film or the silicon oxynitride film forming the insulating portion is one size larger than the first light-shielding film 11a in plan view, and the former edge is more appropriate than the latter edge. It is preferable that they are separated by a distance. According to this structure, for example, a light-shielding film having a planar pattern of a predetermined shape such as a lattice shape, a stripe shape, or an island shape is formed on the supporting substrate 201 by the silicon nitride film or the silicon nitride oxide film forming the insulating portion. It is possible to cover three-dimensionally from the top, bottom, left, and right, and it is possible to reduce the possibility that oxidizing species may reach the first light-shielding film 11a and reduce the diffusion of impurities from the first light-shielding film 11a.

Particularly in this specific example, it is desirable that the etching end of the insulating portion in the light transmitting portion is within 2 μm from the etching end of the light shielding film. This makes it possible to suppress the decrease in light transmittance due to the insulating portion in the opening region within several percent.

Next, in the concrete example shown in FIG.
Compared with the specific example shown in FIG. 8 (c), the etching end of the insulating portion is formed in the light transmitting portion substantially in self alignment with the etching end of the light shielding film. As a result, the etching end of the insulating portion in the light transmitting portion of the opening region can be suppressed to 1 μm or less compared to the etching end of the light-shielding film. It is possible to hold within. Particularly, in this specific example, as shown in FIG. 20B, the resist 222 can be simply exposed by backside exposure or the like by leaving and removing the shaded portion, and thus the specific example of FIG. 18C. It is possible to significantly reduce the cost compared to.

In the embodiments described above, the semiconductor layer 208 is made of a single crystal silicon film using the SOI technique, but the semiconductor layer 208 may be made of, for example, a polysilicon film or an amorphous silicon film. Good. That is,
Even if the semiconductor layer 208 is made of a polysilicon film, an amorphous silicon film, or the like, the function and effect of preventing the light-shielding film from being oxidized by the insulating portion including the silicon nitride film or the silicon nitride oxide film as described above, or the silicon nitride film or The effect of preventing the diffusion of impurities from the light-shielding film into the semiconductor layer by the silicon oxynitride film is exhibited in substantially the same manner. If the semiconductor layer 208 is composed of a polysilicon film, an amorphous silicon film, or the like, the transistor characteristics are relatively inferior, but the TFT can be constructed at a relatively low cost. Therefore, in view of the device specifications, if the semiconductor layer 208 is made of a polysilicon film, an amorphous silicon film, or the like and sufficient transistor characteristics can be obtained, such a structure is less wasteful and advantageous.

Next, the light-shielding film and TF having the above structure
The structure in the image display region of the electro-optical device of the present invention including T and the insulating portion will be described with reference to FIGS. 6 to 8.

FIG. 6 is an equivalent circuit of various elements, wirings and the like in a plurality of pixels formed in a matrix which form a pixel portion (display area) of a liquid crystal device. FIG. 7 is an enlarged plan view showing a plurality of pixel groups adjacent to each other on an element substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, etc. are formed. Further, FIG. 8 is a cross-sectional view taken along the line AA ′ of FIG. 7.

In FIGS. 6 to 8, the TFT 30 (transistor element) is provided with a semiconductor layer 1a made of, for example, a single crystal silicon layer. 6 to 8, the same components as those in FIG. 1 or 5 are designated by the same reference numerals, and the description thereof will be omitted. 6 to 8, the scales of the layers and members are made different so that the layers and members are recognizable in the drawings.

In FIG. 6, a plurality of pixels formed in a matrix form the pixel portion of the liquid crystal device is composed of a plurality of pixel electrodes 9a formed in a matrix and TFTs 30 for controlling the pixel electrodes 9a. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signal S1 to be written in the data line 6a,
S2, ..., Sn may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. In addition, the TFT 30
The scanning line 3a is electrically connected to the gate of the scanning line 3a, and the scanning signal G is pulsed to the scanning line 3a at a predetermined timing.
1, G2, ..., Gm are line-sequentially applied in this order.

The pixel electrode 9a is electrically connected to the drain of the TFT 30 and is a switching element TF.
By closing the switch of T30 for a certain period, the image signals S1 and S supplied from the data line 6a are
2, ..., Sn are written at a predetermined timing. The image signals S1, S2, ..., Sn of a predetermined level written in the liquid crystal via the pixel electrode 9a are held for a certain period of time with the counter electrode described later formed on the counter substrate.

The liquid crystal modulates light by changing the orientation and order of the molecular assembly depending on the applied voltage level,
Enables gradation display. In the normally white mode, the light transmittance for the incident light is reduced according to the applied voltage, and in the normally black mode, the light transmittance for the incident light is increased according to the applied voltage, Light having a contrast corresponding to the image signal is emitted from the liquid crystal device as a whole.

Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is 70 times longer than the time when the voltage is applied to the data line.
Held by. As a result, the holding characteristic is further improved, and a liquid crystal device having a high contrast ratio can be realized. In the present embodiment, in particular, in order to form such a storage capacitor 70, the capacitance line 3b having a low resistance is provided by using the same layer as the scanning line or a conductive light shielding film as described later.

Next, the planar structure in the pixel portion (display region) of the element substrate will be described in detail with reference to FIG. As shown in FIG. 7, a plurality of transparent pixel electrodes 9a (outlined by a dotted line portion 9a ′) are provided in a matrix in a pixel portion on an element substrate of the liquid crystal device,
Data lines 6a are provided along the vertical and horizontal boundaries of the pixel electrode 9a,
A scanning line 3a and a capacitance line 3b are provided. The data line 6a is electrically connected to the later-described source region of the semiconductor layer 1a of the single crystal silicon layer via the contact hole 5, and the pixel electrode 9a is connected to the source region of the semiconductor layer 1a via the contact hole 8. It is electrically connected to a drain region described later. Further, the scanning line 3a is arranged so as to face the channel region (hatched region in the upper right of the drawing) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode.

The capacitance line 3b is a main line portion extending in a substantially straight line along the scanning line 3a (that is, the scanning line 3a in plan view).
Along the data line 6a from the intersection of the first region formed along with the data line 6a to the preceding stage side (upward in the drawing) (that is, the data line when viewed in plan). 6a and the 2nd area | region extended along).

A plurality of first light-shielding films 11a are provided in the area shown by the diagonal lines rising to the right in the figure. More specifically, each of the first light-shielding films 11a is provided at a position that covers the TFT including the channel region of the semiconductor layer 1a in the pixel portion when viewed from the substrate body side of the element substrate.
The main line portion that extends linearly along the scanning line 3a so as to face the main line portion of the capacitance line 3b, and the step side (that is, the downward direction in the figure) that is adjacent to the main line portion along the data line 6a from the point where the data line 6a intersects. And a protruding portion. The tip of the downward projecting portion in each step (pixel row) of the first light-shielding film 11a is overlapped with the tip of the upward projecting section of the capacitance line 3b in the next step below the data line 6a. A contact hole 13 that electrically connects the first light-shielding film 11a and the capacitance line 3b to each other is provided in the overlapping portion. That is, in the present embodiment, the first light-shielding film 11a is electrically connected to the capacitance line 3b at the front stage or the rear stage through the contact hole 13. Next, based on FIG. 8, a cross-sectional structure in the pixel portion of the liquid crystal device will be described. As shown in FIG. 8, in a liquid crystal device, a liquid crystal layer (electro-optical material layer) 50 is sandwiched between an element substrate 10 and a counter substrate 20 arranged to face the element substrate 10.

The element substrate 10 is a substrate body (supporting substrate) 10 made of a light-transmitting substrate such as silicon, quartz, or glass.
A and the pixel electrode 9 formed on the liquid crystal layer 50 side surface thereof
a, pixel switching TFT (transistor element) 3
0, an alignment film 16 as a main component, and the counter substrate 20 is a substrate body 20A made of a transparent substrate such as transparent glass or quartz and a counter electrode (common electrode) formed on the liquid crystal layer 50 side surface thereof. ) 21 and the alignment film 22 as main components. The pixel electrode 9a is provided on the surface of the element body 10 on the liquid crystal layer 50 side of the substrate body 10A,
An alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided on the liquid crystal layer 50 side, and a pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to each pixel electrode 9a. It is provided. The pixel electrode 9a is made of a transparent conductive thin film such as ITO (Indium Tin Oxide), and the alignment film 16a is formed.
Is an organic thin film such as polyimide.

Immediately above the substrate body 10A of the element substrate 10 (on the liquid crystal layer 50 side surface), each pixel switching TFT is provided.
The first light shielding film 11 a is provided at a position corresponding to 30.

In the present embodiment, since the first light-shielding film 11a is formed on the element substrate 10 in this way, the return light from the element substrate 10 side is reflected by the pixel switching TFT.
It is possible to prevent the light from entering the channel region 1a ′ and the LDD regions 1b and 1c of 30 and to prevent the characteristics of the pixel switching TFT 30 as a transistor element from being deteriorated due to the generation of photocurrent.

On the surface of the first light-shielding film 11a, the semiconductor layer 1a forming the pixel switching TFT 30 is formed on the entire surface of the substrate body 10A.
In order to electrically insulate from a and to flatten the surface of the substrate body 10A on which the first light shielding film 11a is formed,
A first interlayer insulating film made of a silicate glass film such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphosilicate glass), a silicon nitride film, a silicon oxide film, or the like. 12, the first silicon oxide film 203B, the silicon nitride film, or the silicon nitride oxide film 20 is further provided on the surface of the first interlayer insulating film 12.
4, the insulating portion 20 made of the second silicon oxide film 203A
5 is provided, and the pixel switching TFT 30 is provided on the surface of the insulating portion 205. The TFT 30 is provided on the surface of the insulating portion 205 and includes the semiconductor layer 1a formed of a single crystal silicon layer.

The structure of the insulating part 205 is the same as the structure of the insulating part 205 of the SOI substrate 200 and the element substrate 210, except that the contact hole 13 is opened. Omit it.

On the other hand, a counter electrode (common electrode) 21 is provided over the entire surface of the counter substrate 20 on the liquid crystal layer 50 side of the substrate body 20A, and the liquid crystal layer 50 side is rubbed. An alignment film 22 that has been subjected to a predetermined alignment treatment such as is provided. The counter electrode 21 is, for example, ITO.
The alignment film 22 is made of an organic thin film such as polyimide.

Further, on the surface of the substrate body 20A on the liquid crystal layer 50 side, as shown in FIG. 8, a second light-shielding film 23 is provided in a region other than the opening region of each pixel portion. By thus providing the second light-shielding film 23 on the side of the counter substrate 20, incident light from the side of the counter substrate 20 is used for pixel switching.
The channel region 1a ′ of the semiconductor layer 1a of the FT 30 and the LDD
It is possible to prevent entry into the (Lightly Doped Drain) regions 1b and 1c and improve the contrast.

Between the element substrate 10 and the counter substrate 20 which are configured as described above and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, a sealing material formed between the peripheral portions of the both substrates. A liquid crystal (electro-optical material) is enclosed in a space surrounded by (not shown), and a liquid crystal layer (electro-optical material layer) 50 is formed.
Are formed.

The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed, and the alignment film 16 is formed in a state where the electric field from the pixel electrode 9a is not applied.
A predetermined orientation state is adopted by the elements 22 and 22.

The sealing material is made of an adhesive such as a photo-curable adhesive or a thermosetting adhesive for adhering the element substrate 10 and the counter substrate 20 at their peripheral portions. Spacers such as glass fibers and glass beads are mixed to keep the distance between both substrates to a predetermined value.

Further, in this embodiment, the gate insulating film 2 is extended from the position facing the scanning line 3a to be used as a dielectric film, and the semiconductor film 1a is extended to be the first storage capacitor electrode 1f. The storage capacitor 70 is configured by using a part of the capacitance line 3b facing these as the second storage capacitor electrode.

More specifically, the high-concentration drain region 1e of the semiconductor layer 1a is extended below the data line 6a and the scanning line 3a, and the portion of the capacitance line 3b that also extends along the data line 6a and the scanning line 3a. Are opposed to each other via the insulating film 2 and serve as a first storage capacitor electrode (semiconductor layer) 1f.
Particularly, since the insulating film 2 as the dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the single crystal silicon layer by high temperature oxidation, it can be a thin and high breakdown voltage insulating film. The storage capacitor 70 can be configured as a large storage capacitor having a relatively small area.

Further, in the storage capacitor 70, as can be seen from FIGS. 7 and 8, the first light-shielding film 11a is formed on the first storage capacitor electrode 1f on the side opposite to the capacitance line 3b serving as the second storage capacitor electrode. By arranging the third storage capacitor electrodes so as to face each other through the first interlayer insulating film 12 (see the storage capacitor 70 on the right side of FIG. 8), the storage capacitor is further provided. That is, in the present embodiment, the double storage capacitor structure in which the storage capacitors are provided on both sides of the first storage capacitor electrode 1f is constructed, and the storage capacitance is further increased. With such a structure, it is possible to improve the function of the liquid crystal device according to the present embodiment to prevent flicker and burn-in in a display image.

As a result, the space outside the opening region, that is, the region under the data line 6a and the region where liquid crystal disclination occurs along the scanning line 3a (that is, the region where the capacitance line 3b is formed) is effective. Can be used to increase the storage capacity of the pixel electrode 9a.

Further, in this embodiment, the first light shielding film 11a is used.
(And the capacitance line 3b electrically connected to this) is electrically connected to the constant potential source, and the first light-shielding film 11a and the capacitance line 3b have a constant potential. Therefore, the pixel switching TFT 30 arranged so as to face the first light-shielding film 11a.
On the other hand, the potential fluctuation of the first light-shielding film 11a does not adversely affect. Further, the capacitance line 3b can function well as the second storage capacitance electrode of the storage capacitance 70.

Further, as shown in FIGS. 7 and 8, in the present embodiment, in addition to providing the first light-shielding film 11a on the element substrate 10, the first light-shielding film 11a is formed through the contact hole 13. It is configured to be electrically connected to the capacitance line 3b in the front stage or the rear stage. In the case of such a configuration, as compared with the case where each first light-shielding film 11a is electrically connected to the capacitance line of its own stage, the data line 6a is formed along the edge of the opening region of the pixel portion. The step difference between the region where the capacitance line 3b and the first light-shielding film 11a are formed is overlapped with other regions can be reduced. When the number of steps along the edge of the opening area of the pixel portion is small as described above, the disclination (orientation failure) of the liquid crystal caused by the step can be reduced, so that the opening area of the pixel portion can be expanded. Become.

Further, the first light-shielding film 11a has the contact hole 13 formed in the protruding portion protruding from the linearly extending main line portion as described above. Here, as the opening of the contact hole 13 is closer to the edge, cracks are less likely to occur because stress is more easily released from the edge. Therefore, the stress applied to the first light-shielding film 11a during the manufacturing process depends on how close to the tip of the protruding portion the contact hole 13 is formed (preferably, at the tip of the margin). Is alleviated, cracks can be prevented more effectively, and the yield can be improved.

The capacitance line 3b and the scanning line 3a are made of the same polysilicon film, and the dielectric film of the storage capacitor 70 and the gate insulating film 2 of the TFT 30 are made of the same high temperature oxide film. Storage capacitor electrode 1f, channel forming region 1a and source region 1d of TFT 30, drain region 1
e and the like are made of the same semiconductor layer 1a. Therefore, the laminated structure formed on the surface of the substrate body 10A of the element substrate 10 can be simplified, and in the method of manufacturing a liquid crystal device described later, the capacitance line 3b and the scanning line 3a are simultaneously formed in the same thin film forming step. It is possible to form the dielectric film of the storage capacitor 70 and the gate insulating film 2 at the same time.

The capacitance line 3b and the first light-shielding film 11a are the first
The two are electrically connected to each other reliably and with high reliability through the contact hole 13 formed in the interlayer insulating film 12, but such a contact hole 13 is
A hole may be formed for each pixel, or a pixel group including a plurality of pixels may be formed.

The contact hole 13 provided for each pixel or each pixel group is opened below the data line 6a when viewed from the counter substrate 20 side. For this reason,
The contact hole 13 is provided in the portion of the first interlayer insulating film 12 where the TFT 30 and the first storage capacitor electrode 1f are not formed, which is out of the opening region of the pixel portion, so that the pixel portion can be effectively used. At the same time, it is possible to prevent the TFT 30 and other wirings from becoming defective due to the formation of the contact hole 13.

In FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and the scanning line 3a and the channel region of the semiconductor layer 1a in which a channel is formed by the electric field from the scanning line 3a. 1
a ′, the gate insulating film 2 for insulating the scanning line 3a and the semiconductor layer 1a, the data line 6a, the low-concentration source region (source-side LDD region) 1b and the low-concentration drain region (drain-side LDD region) 1c of the semiconductor layer 1a. , A high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a.

A corresponding one of the plurality of pixel electrodes 9a is connected to the high concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e have a predetermined concentration for N type or P depending on whether an N type or P type channel is formed in the semiconductor layer 1a.
It is formed by doping a mold dopant. The N-type channel TFT has an advantage of high operating speed and is often used as the pixel switching TFT 30 which is a pixel switching element.

The data line 6a is composed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. Also, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e are formed on the scanning line 3a, the gate insulating film 2, and the first interlayer insulating film 12, respectively. Interlayer insulation film 4
Are formed. Through the contact hole 5 to the source region 1b, the data line 6a is connected to the high concentration source region 1
It is electrically connected to d.

Further, the data line 6a and the second interlayer insulating film 4 are formed.
A third interlayer insulating film 7 in which a contact hole 8 to the high-concentration drain region 1e is formed is formed thereover.
The pixel electrode 9a is electrically connected to the high concentration drain region 1e through the contact hole 8 to the high concentration drain region 1e. The above-mentioned pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured. The pixel electrode 9a and the high-concentration drain region 1e are
The same Al film as the data line 6a or the same polysilicon film as the scanning line 3b may be relayed and electrically connected.

The pixel switching TFT 30 preferably has the LDD structure as described above, but may have the offset structure in which the impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c. Alternatively, a self-aligned TFT may be used in which high-concentration source and drain regions are formed in a self-aligned manner by implanting high-concentration impurity ions using the gate electrode (scanning line 3a) as a mask.

Further, the single gate structure in which only one gate electrode (scanning line 3a) of the pixel switching TFT 30 is arranged between the source-drain regions 1b and 1e has two or more gate electrodes between them. You may arrange. At this time, the same signal is applied to each gate electrode. If the TFT is configured with a double gate or a triple gate or more as described above, it is possible to prevent a leak current at the junction between the channel and the source-drain region, and to reduce the off-state current. If at least one of these gate electrodes has an LDD structure or an offset structure, the off current can be further reduced, and a stable switching element can be obtained.

Here, in general, the single crystal silicon layer forming the channel region 1a ′, the low concentration source region 1b, the low concentration drain region 1c, etc. of the semiconductor layer 1a is affected by the photoelectric conversion effect of silicon when light is incident. Although a photocurrent is generated to deteriorate the transistor characteristics of the pixel switching TFT 30, in the present embodiment, the data line 6a is formed of a light-shielding metal thin film such as Al so as to cover the scanning line 3a from above. Therefore, at least the semiconductor layer 1
It is possible to prevent incident light from entering the channel region 1a ′ and the LDD regions 1b and 1c of a.

Further, as described above, since the first light-shielding film 11a is provided below the pixel switching TFT 30 (on the side of the substrate body 10A), at least the semiconductor layer 1 is provided.
It is possible to prevent the returning light from entering the channel region 1a ′ and the LDD regions 1b and 1c of a.

In the present embodiment, since the capacitance line 3b provided in the pixel in the preceding stage or the pixel in the subsequent stage adjacent to each other is connected to the first light shielding film 11a, the pixel in the uppermost stage or the lowermost stage is connected. The capacitance line 3b for supplying a constant potential to the first light shielding film 11a is required. Therefore, it is advisable to provide one extra capacity line 3b with respect to the number of vertical pixels.

(Method for Manufacturing Electro-Optical Device) Next, a method for manufacturing the liquid crystal device having the above structure will be described.

First, a method of manufacturing the element substrate 10 will be described as a method of manufacturing the element substrate according to the embodiment of the present invention with reference to FIGS. 9 to 1
4 is a process diagram showing a part of the element substrate in each process corresponding to the AA ′ cross section of FIG. 7 as in FIG. 8. In addition, in FIGS. 10 to 14, the insulating portion 205 is not shown in order to simplify the drawings. First, a substrate body (support substrate) 10A such as a silicon substrate, a quartz substrate, or a glass substrate is prepared. Here, it is preferably about 850 to 13 under an atmosphere of an inert gas such as N ₂ (nitrogen).
The substrate body 1 is annealed at a high temperature of 00 ° C., more preferably 1000 ° C., and is subjected to a high temperature process to be performed later.
Pretreatment is performed so that the distortion generated in 0A is reduced.
That is, the substrate body 10A is preliminarily heat-treated at the same temperature or higher in accordance with the maximum temperature processed in the manufacturing process.

As shown in FIG. 9A, Ti, Cr, W, and T are formed on the entire surface of the substrate body 10A thus treated.
A metal such as a, Mo, or Pd or a metal alloy film such as metal silicide is formed by a sputtering method or the like at 100 to 500.
The light shielding layer 11 having a film thickness of about nm, preferably about 200 nm is formed.

Next, as shown in FIG. 9B, a photoresist 207 corresponding to the pattern of the first light-shielding film 11a (see FIG. 7) is formed by photolithography.

Next, as shown in FIG. 9C, the light shielding layer 11 is etched through the photoresist 207 to form the first light shielding film 11a having the pattern shown in FIG. .

Next, as shown in FIG. 9D, TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl) is formed on the first light-shielding film 11a by, for example, a normal pressure or low pressure CVD method.・ Ethyl boat rate) gas, T
A first interlayer insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by using MOP (tetra-methyl-oxy-phosphorate) gas or the like. The thickness of the first interlayer insulating film 12 is, for example, about 400 to 1000 n.
m, more preferably about 800 nm.

Next, as shown in FIG. 9E, the entire surface of the first interlayer insulating film 12 is polished and flattened by the CMP (chemical mechanical polishing) method or the like.

Next, as shown in FIG. 9 (f), the substrate body 10A shown in FIG. 9 (e) on which the first interlayer insulating film 12 having a flattened surface is formed, and the first silicon oxide on the surface are formed. Membrane 2
03B, silicon nitride film or silicon nitride oxide film 20
4, the insulating portion 20 made of the second silicon oxide film 203A
Bonding is performed with the single crystal silicon substrate 202A on which No. 5 is formed. Next, as shown in FIG. 9G, most of the single crystal silicon substrate 202A is peeled off, leaving the thin film single crystal silicon layer 202 on the surface of the substrate body 10A.

The method of forming the insulating portion 205 on the surface of the single crystal silicon substrate 202A, the single crystal silicon substrate 202A having the insulating portion 205 formed on the surface, and the substrate body 10A.
And a single crystal silicon substrate 202A
Since the peeling method of 1 is described in detail in the manufacturing method of the SOI substrate 200, the description thereof will be omitted.

Next, as shown in FIG. 9H, the single crystal silicon layer 202 is formed into a predetermined pattern through a photolithography process, an etching process, etc., so that the semiconductor having the predetermined pattern as shown in FIG. 7 is formed. Form layer 1a. That is, particularly in the region where the capacitance line 3b is formed under the data line 6a and the region where the capacitance line 3b is formed along the scanning line 3a, the first layer extending from the semiconductor layer 1a forming the pixel switching TFT 30 is formed. One storage capacitor electrode 1f is formed.

Next, as shown in FIG. 9I, the first storage capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 is heated to a temperature of about 850 to 1300 ° C., preferably about 1000 ° C. By thermal oxidation for about 72 minutes, a thermal oxide silicon film having a relatively thin thickness of about 60 nm is formed, and the gate insulating film 2 of the pixel switching TFT 30 is formed together with the gate insulating film 2 for forming a capacitance. As a result, the semiconductor layer 1a and the first storage capacitor electrode 1f
The thickness of the gate insulating film 2 is about 30 to 170 nm.
Has a thickness of about 60 nm.

Next, as shown in FIG. 10A, a resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a.
Is formed, and the P-channel semiconductor layer 1a is doped with a dopant 302 of a group V element such as P at a low concentration (for example, P ions at an acceleration voltage of 70 keV and a dose amount of 2 × 10 ¹¹ / cm ² ). .

Next, as shown in FIG. 10B, a resist film is formed at a position corresponding to the P-channel semiconductor layer 1a (not shown), and a group III element such as B is added to the N-channel semiconductor layer 1a. Dopant 303 in a low concentration (eg,
Accelerating voltage of 35 keV for B ions, 1 × 10 ¹² / cm ²
Dope).

Next, as shown in FIG. 10C, the channel region 1 of each semiconductor layer 1a is formed for each P channel and N channel.
A resist film 305 is formed on the surface of the substrate 10 excluding the end portion of a ′, and a dopant of a group V element such as P having a dose amount about 1 to 10 times that of the process shown in FIG. Dopant 306 of the group III element such as B, which is about 1 to 10 times the dose shown in FIG. 10B for the N channel and 306, is doped.

Next, as shown in FIG. 10D, in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, the scanning line 3a (gate electrode) on the surface of the substrate body 10A is reduced. ) On the portion corresponding to the resist film 307 (scanning line 3a
Wider than the above), and using this as a mask, a dopant of a group V element such as P is added at a low concentration (for example, P ions are accelerated at an acceleration voltage of 70 keV, 3 × 10 5
Dope (with a dose of ¹⁴ / cm ² ).

Next, as shown in FIG. 11A, the contact holes 13 reaching the first light-shielding film 11a in the first interlayer insulating film 12 and the insulating portion 205 (not shown) are subjected to reactive etching and reactive ion beam. It is formed by dry etching such as etching or by wet etching. At this time, the anisotropic etching such as the reactive etching and the reactive ion beam etching has an advantage that the opening shape of the contact hole 13 can be made substantially the same as the mask shape. However, by combining dry etching and wet etching to open the holes, these contact holes 13 and the like can be tapered, so that there is an advantage that disconnection at the time of wiring connection can be prevented.

Next, as shown in FIG. 11B, the reduced pressure C
After depositing the polysilicon layer 3 to a thickness of about 350 nm by the VD method or the like, phosphorus (P) is thermally diffused to render the polysilicon film 3 conductive. Alternatively, P ions are added to the polysilicon film 3
A doped silicon film introduced at the same time as the film formation may be used. As a result, the conductivity of the polysilicon layer 3 can be increased.

Next, as shown in FIG. 11C, a capacitance line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 7 by a photolithography process using a resist mask, an etching process and the like. After this, the polysilicon remaining on the back surface of the substrate body 10A is removed.
The surface of A is covered with a resist film and removed by etching.

Next, as shown in FIG. 11D, N is formed in order to form a P-channel LDD region in the semiconductor layer 1a.
The resist film 3 is formed at a position corresponding to the semiconductor layer 1a of the channel.
09, and using the scanning line 3a (gate electrode) as a diffusion mask, first, a dopant 310 of a group III element such as B is used at a low concentration (for example, BF ₂ ions are accelerated at an acceleration voltage of 90 keV, 3 × 10 ¹³ / cm ² Dope, P
A low concentration source region 1b and a low concentration drain region 1c of the channel are formed.

Subsequently, as shown in FIG. 11E, in order to form a P-channel high-concentration source region 1d and a high-concentration drain region 1e in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is formed. Is covered with a resist film 309, and a resist layer is formed on the scanning line 3a corresponding to the P channel with a mask (not shown) having a width wider than that of the scanning line 3a. Dopant 311 of a group element is doped at a high concentration (for example, BF ₂ ions are accelerated at an accelerating voltage of 90 keV and a dose amount of 2 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 12A, in order to form an N-channel LDD region in the semiconductor layer 1a, P
A position corresponding to the semiconductor layer 1a of the channel is covered with a resist film (not shown), the scan line 3a (gate electrode) is used as a diffusion mask, and the dopant 60 of the group V element such as P is used at a low concentration (for example, P ion). Acceleration voltage of 70 keV, 6
(Dose amount of × 10 ¹² / cm ² ), doping, N-channel low-concentration source region 1b and low-concentration drain region 1c
To form.

Subsequently, as shown in FIG. 12B, in order to form the N-channel high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a, a mask wider than the scanning line 3a is used. After the resist 62 is formed on the scanning line 3a corresponding to the N channel, the dopant 61 of the V group element such as P is also highly concentrated (for example, P ion is 70
dope (accelerating voltage of keV, dose of 4 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 12C, for example, a normal pressure or low pressure CVD method or TEOS gas is used so as to cover the scanning line 3a and the capacitance line 3b and the scanning line 3a in the pixel switching TFT 30. Using NSG, PS
A second interlayer insulating film 4 made of a silicate glass film such as G, BSG, BPSG, a silicon nitride film, a silicon oxide film or the like is formed. The thickness of the second interlayer insulating film 4 is about 500 to
It is preferably 1500 nm, and more preferably 800 nm.

Thereafter, an annealing treatment at about 850 ° C. is performed for about 20 minutes to activate the high concentration source region 1d and the high concentration drain region 1e.

Next, as shown in FIG. 12D, the contact hole 5 for the data line 31 is formed by dry etching such as reactive etching or reactive ion beam etching, or by wet etching. Further, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings not shown are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.

Next, as shown in FIG. 13A, a light-shielding A film is formed on the second interlayer insulating film 4 by sputtering or the like.
The metal film 6 is made of a low resistance metal such as 1 or metal silicide, and has a thickness of about 100 to 700 nm, preferably about 350.
Then, as shown in FIG. 13B, the data line 6a is formed by a photolithography process, an etching process, and the like.

Next, as shown in FIG. 13C, NSG, PSG, BSG, etc. are formed so as to cover the data lines 6a by using, for example, a normal pressure or low pressure CVD method or TEOS gas.
Silicate glass film such as BPSG, silicon nitride film,
A third interlayer insulating film 7 made of a silicon oxide film or the like is formed. The thickness of the third interlayer insulating film 7 is about 500 to 1500 n.
m is preferable, and 800 nm is more preferable.

Next, as shown in FIG. 14A, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high concentration drain region 1e is subjected to reactive etching and reaction. It is formed by dry etching such as reactive ion beam etching.

Next, as shown in FIG. 14B, a transparent conductive thin film 9 of ITO or the like is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in FIG. 14C, the pixel electrode 9a is formed by a photolithography process, an etching process, and the like. When the liquid crystal device of this embodiment is a reflective liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid of a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 8) is formed.

The element substrate 10 is manufactured as described above.

According to the method of manufacturing the element substrate of this embodiment, the silicon nitride film or the silicon nitride oxide film 20 is formed on the surface.
4A formed single crystal silicon substrate 202A and substrate body 1
0A to bond the silicon nitride film or silicon oxynitride film 204 to the semiconductor layer 1 from the bonding surface between the substrate body 10A and the single crystal silicon substrate 202A.
Since it can be located on the a (TFT 30) side, impurities contained in the substrate body 10A and the substrate body 10A
It is possible to completely prevent the impurities adsorbed on the bonding surface between the single crystal silicon substrate 202A and the single crystal silicon substrate 202A from diffusing to the semiconductor layer 1a (TFT 30) side.

The element substrate 10 manufactured by the element substrate manufacturing method of the present embodiment is adsorbed on the impurities contained in the substrate body 10A and the bonding surface between the substrate body 10A and the single crystal silicon substrate 202A. Since it is possible to completely prevent the impurities from diffusing to the semiconductor layer 1a (TFT 30) side, deterioration of the characteristics of the TFT 30 can be prevented.

In particular, the element substrate 10 manufactured by the method of manufacturing the element substrate of the present embodiment is a silicon nitride film or a nitriding oxide film which is a dense film having a low transmittance with respect to oxidizing species or impurities such as oxygen and water. The silicon film 204 can effectively prevent the diffusion of the oxidizing species into the first light-shielding film 11a made of a refractory metal or the like, and at the same time, the effect that the impurities diffuse from the first light-shielding film 11a into the semiconductor layer 1a. Can be blocked.

Next, a method of manufacturing the counter substrate 20 and a method of manufacturing a liquid crystal device from the element substrate 10 and the counter substrate 20 will be described.

With respect to the counter substrate 20 shown in FIG. 8, a light-transmissive substrate such as a glass substrate is prepared as the substrate body 20A, and the second light-shielding film 23 and a peripheral parting portion described later are provided on the surface of the substrate body 20A. A second light shielding film is formed. Second
The light-shielding film 23 and a second light-shielding film as a peripheral partition described later are formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, or Al. Note that these second light-shielding films may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist, in addition to the above metal materials.

After that, a transparent conductive thin film such as ITO is deposited on the entire surface of the substrate body 20A by a sputtering method or the like to a thickness of about 50 to 200 nm to form the counter electrode 21. Further, after applying a coating solution of an alignment film such as polyimide on the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 8)). As described above, the counter substrate 20
Is manufactured.

Finally, the element substrate 10 and the counter substrate 20 manufactured as described above are pasted together with a sealing material so that the alignment films 16 and 22 face each other, and both are bonded by a vacuum suction method or the like. A liquid crystal device having the above-described structure is manufactured by sucking a liquid crystal obtained by mixing a plurality of types of nematic liquid crystals into the space between the substrates to form a liquid crystal layer 50 having a predetermined thickness.

(Overall Configuration of Liquid Crystal Device) The overall configuration of the liquid crystal device (electro-optical device) of this embodiment having the above-described configuration will be described with reference to FIGS. 15 and 16. Note that FIG.
FIG. 16 is a plan view of the element substrate 10 viewed from the counter substrate 20 side, and FIG. 16 shows H- of FIG. 15 including the counter substrate 20.
It is a H'sectional view.

In FIG. 15, a sealing material 52 is provided on the surface of the element substrate 10 along the edge thereof, and as shown in FIG. 16, it has substantially the same contour as the sealing material 52 shown in FIG. The counter substrate 20 that it has is fixed to the element substrate 10 by the sealing material 52.

As shown in FIG. 15, on the surface of the counter substrate 20, in parallel with the inside of the sealing material 52, for example, a second light shield as a peripheral parting or a frame made of the same material as or a material different from that of the second light shielding film 23. A membrane 53 is provided.

In addition, in the element substrate 10, the sealing material 5
In the region outside 2, the data line driving circuit 101 and the mounting terminals 102 are provided along one side of the element substrate 10, and the scanning line driving circuit 104 is provided along two sides adjacent to this one side. ing. When the delay of the scanning signal supplied to the scanning line 3a does not matter, the scanning line driving circuit 1
Needless to say, 04 may be provided on only one side.

Further, the data line driving circuits 101 may be arranged on both sides along the sides of the display area (pixel portion). For example, the odd-numbered data lines 6a supply an image signal from the data-line driving circuit arranged along one side of the display area, and the even-numbered data lines 6a are arranged along the opposite side of the display area. The image signal may be supplied from the provided data line driving circuit. By thus driving the data lines 6a in a comb shape, the occupied area of the data line driving circuit can be expanded, and a complicated circuit can be configured.

Further, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the display area are provided on the remaining one side of the element substrate 10, and further, a second light shield as a peripheral partition is provided. A precharge circuit may be provided hidden under the film 53. In addition, at least at one corner of the corner between the element substrate 10 and the counter substrate 20, a conductive material 106 for electrically connecting the element substrate 10 and the counter substrate 20 is provided.

Further, on the surface of the element substrate 10, an inspection circuit or the like for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or shipping may be further formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the surface of the element substrate 10, for example, a driving L mounted on a TAB (tape automated bonding substrate).
The SI may be electrically and mechanically connected via an anisotropic conductive film provided in the peripheral region of the element substrate 10.

On the light-incident side of the counter substrate 20 and the light-exiting side of the element substrate 10, respectively, for example, TN
(Twisted Nematic) mode, STN (Super Twisted N)
ematic) mode, VA (Vertically Aligned) mode,
A polarizing film, a retardation film, a polarizing means, etc. are arranged in a predetermined direction depending on an operation mode such as a PDLC (Polymer Dispersed Liquid Crystal) mode or a normally white mode / a normally black mode.

When the liquid crystal device of this embodiment is applied to a color liquid crystal projector (projection type display device), three liquid crystal devices are used as light valves for RGB, and each panel has RGB colors. The light of each color separated via the dichroic mirror for separation is incident as projection light. Therefore, in that case, as shown in the above-described embodiment, the counter substrate 20 is not provided with a color filter.

However, the substrate body 2 of the counter substrate 20
On the surface of the liquid crystal layer 50 side of 0A, R is provided in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed.
A GB color filter may be formed together with its protective film. With such a configuration, the liquid crystal device of the above embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflection type color liquid crystal television other than the liquid crystal projector.

Further, one pixel is formed on the surface of the counter substrate 20.
You may form a micro lens so that it may correspond individually. In this way, by improving the efficiency of collecting incident light,
A bright liquid crystal device can be realized. Furthermore, the counter substrate 20
A dichroic filter that produces RGB colors may be formed by using interference of light by depositing interference layers having different refractive indexes on the surface of. This counter substrate with a dichroic filter can realize a brighter color liquid crystal device.

In the liquid crystal device of this embodiment,
Although the incident light is made to enter from the counter substrate 20 side,
Since the first light-shielding film 11a is provided on the element substrate 10, incident light may be incident from the element substrate 10 side and may be emitted from the counter substrate 20 side. That is, even when the liquid crystal device is mounted on the liquid crystal projector in this way, the channel region 1a ′ and the LDD regions 1b, 1b of the semiconductor layer 1a are formed.
It is possible to prevent light from entering c and display a high-quality image.

In addition, the liquid crystal device of this embodiment has the element substrate 10 manufactured by the method of manufacturing the element substrate of this embodiment.
Therefore, the impurities contained in the substrate body 10A, and the substrate body 10A and the single crystal silicon substrate 20 are included.
Impurities adsorbed on the bonding surface of the semiconductor layer 1a
Since it is possible to completely prevent the diffusion to the (TFT 30) side, it is possible to prevent the deterioration of the characteristics of the TFT (transistor element) 30, and the performance becomes excellent.

In particular, in the liquid crystal device of this embodiment, the silicon nitride film or the silicon oxynitride film 204 can effectively prevent the diffusion of the oxidizing species into the first light shielding film 11a,
At the same time, it is possible to effectively prevent the diffusion of impurities from the first light-shielding film 11a to the semiconductor layer 1a, so that the light-shielding performance for returning light can be maintained at a high level for a long period of time, and the TFT 3
The characteristic of 0 can be maintained.

(Electrical Configuration of Liquid Crystal Device) Next, the electrical configuration of the liquid crystal device (electro-optical device) will be described. The liquid crystal device has a structure in which an element substrate and a counter substrate are attached with their electrode formation surfaces facing each other. Of these, in the element substrate, a plurality of scanning lines 3a are arranged in parallel along the X direction in FIG. 21, and a plurality of data lines are arranged in parallel along the Y direction orthogonal thereto. The line 6a is formed. At each intersection of these scanning line 3a and data line 6a, the gate electrode of the TFT 30 is connected to the scanning line 3a.
On the other hand, the source electrode of the TFT 30 is connected to the data line 6a, and the drain electrode of the TFT 30 is connected to the pixel electrode 9a. And each pixel is
As a result of being composed of the pixel electrode 9a, the common electrode formed on the counter substrate, and the liquid crystal sandwiched between these electrodes, as a result, corresponding to each intersection of the scanning line 3a and the data line 6a,
They will be arranged in a matrix. In addition to this, a storage capacitor (not shown) is formed in parallel for each pixel with respect to the liquid crystal sandwiched between the pixel electrode 9a and the common electrode electrically.

Now, the drive circuit 110 includes the dummy circuit 12
0, data line drive circuit 101, sampling circuit 140
And the scanning line driving circuit 104, and is formed in the peripheral portion of the display area on the opposing surface of the element substrate. The active elements of these circuits are all formed by a combination of p-channel TFTs and n-channel TFTs. The drive circuit 110 is formed in the same manufacturing process as the TFT 30 that switches pixels. This is advantageous in terms of integration, manufacturing cost, device uniformity, and the like.

Here, in the drive circuit 110, the dummy circuit 120 is constructed by simulating a part of the data line drive circuit 101 and the sampling circuit 140. The dummy circuit 120 is provided to detect the phase difference between the image signals VID1 to VID6 and the sampling signals S1 to Sm.

The data line driving circuit 101 has a shift register, and has an X clock signal CLX from the timing generator 150 and its inverted X clock signal CLXINV.
The sampling signals S1 to Sm are sequentially output based on

The sampling circuit 140 groups the six data lines 6a into one group (hereinafter referred to as a block), and for the data lines 6a belonging to these blocks, the image signals VID1 to VID according to the sampling signals S1 to Sm.
6 are sampled and supplied. Specifically, the sampling circuit 140 is provided with a switch 141 composed of an n-channel TFT at one end of each data line 114, and the source electrode of each switch 141 is supplied with any of the image signals VID1 to VID6. Signal line, and the drain electrode of each switch 141 is connected to one data line 6a. Further, the gate electrode of each switch 141 connected to the data line 6a belonging to each group is connected to any of the image signal lines to which the sampling signals S1 to Sm are supplied corresponding to the group. In this example, the image signals VID1 to VI
D6 is supplied at the same time and simultaneously sampled by the sampling signal S1.

By the way, the response speed of the TFT changes depending on the temperature and the cumulative use time. Therefore, the image signal V
Sampling signals S1 to S1 based on ID1 to VID6
The phase of Sm leads or lags. If the phase shift is significant, the sampling signals S1 to Sm may become active over the timing when the levels of the image signals VID1 to VID6 change. Then, the image signals VID1 to VID6 originally to be supplied to a certain block are mixed in the image signals to be supplied to the adjacent blocks, which causes image quality deterioration. In order to prevent such an inconvenience, the phase relationship between the image signals VID1 to VID6 and the sampling signals S1 to Sm is detected by using the dummy circuit 120 described above,
The phases of the sampling signals S1 to Sm with respect to the image signals VID1 to VID6 are adjusted based on the detection result.

The scanning line driving circuit 104 has a shift register, and includes the Y clock signal CLY from the timing generator 150 and its inverted Y clock signal CLYINV.
Based on the Y transfer X transfer start pulse DX and the like, the scanning signal is sequentially output to each scanning line 3a. In addition,
The Y transfer X transfer start pulse DX becomes active for a predetermined time at the start of each field period.

Furthermore, a monitor signal line is formed in the liquid crystal device. The monitor signal lines are image signals VID1 to VID.
It is wired in parallel with the six image signal lines for supplying ID6, and the line width thereof is equal to that of the image signal line. By the way, since the image signal line has a distributed resistance and a capacitance component, it equivalently forms a ladder-type low-pass filter. Therefore, there is a delay time from when the image signals VID1 to VID6 are supplied to the input terminal at the left end of the liquid crystal device and before reaching the right end. Since the monitor signal line is configured similarly to the image signal line, the time from the input monitor signal M1 being supplied to the monitor signal line to the dummy circuit 120 is substantially equal to the delay time described above.

(Data Line Driving Circuit) Next, the data line driving circuit 101 will be described as an example of the peripheral circuit. FIG. 22 is a circuit diagram showing the configuration of the data line driving circuit 101. The shift register 1350 includes unit circuits R1 to Rm +.
2 are cascaded in m + 2 (m is a natural number) stages,
The start pulse DX supplied at the beginning of the horizontal scanning period is set to X
Clock signal CLX and inverted X clock signal CLXIN
According to V, the output is sequentially shifted from the unit circuit at the front stage (left side) to the unit circuit at the rear stage (right side). The start pulse DX is active for a predetermined time at the start of each horizontal scanning period.

Of these unit circuits R1 to Rm + 2,
The unit circuits R1, R3 ,. ． ． ． ． ． , Rm + 2
Is a clocked inverter 1352 that inverts the input signal when the X clock signal CLX is at the H level (the inverted X clock signal CLXINV is at the L level), and an inverter 1354 that reinverts the inverted signal by the clocked inverter 1352. When the X clock signal CLX is at L level (when the inverted Y clock signal CLYINV is at H level)
And a clocked inverter 1356 that inverts the input signal.

On the other hand, of the unit circuits R1 to Rm + 2,
The unit circuits R2, R4 ,. ． ． ． ． ． , Rm + 1
Is basically an odd-numbered unit circuit R1, R
3 ,. ． ． ． ． ． , Rm + 2, but the clocked inverter 1352 has the X clock signal CLX.
Is an L level, and the clocked inverter 1356 inverts an input signal when the X clock signal CLX is H level.

Next, referring to FIG. 23, the NAND circuit 13
The inverter 76, the inverter 1378, and the AND circuit 1379 are provided corresponding to the third stage to the (m + 2) th stage of the shift register 1350, respectively, and are configured in a complementary type by combining a p-channel TFT and an n-channel TFT. Has been done.

Among them, in FIG. 22, the i-th NAND circuit 1376 from the left outputs the output signal of the unit circuit located at the i-1th stage and the output signal of the unit circuit located at the i-th stage in the shift register 1350. And the logical product of and. The inverter 1378 at each stage inverts the output signal of the corresponding NAND circuit 1378. Further, the AND circuit 1379 is connected to the corresponding inverter 13
78 and the enable signal EN, the logical product of the sampling signals S1, S2 ,. ． ． , Sm are output.

(Semiconductor Device Constituting Peripheral Circuit) Next, an embodiment of the semiconductor device constituting the peripheral circuit according to the present invention will be described with reference to FIGS. 23 to 28. 23 and 25 to 28 are plan views showing various specific examples of the semiconductor device, respectively. In addition, FIG.
4 is a cross-sectional view showing a double gate structure which sandwiches a channel region from above and below in the inverter circuit shown in FIG.

The semiconductor device of this embodiment has a transistor element formed on an SOI substrate. Then, as in the case of the SOI substrate shown in FIG. 1, an insulating portion having a supporting substrate and a single crystal silicon layer and having a single layer or a multilayer structure is formed between the supporting substrate and the single crystal silicon layer. Has been done. In particular, in addition to such a structure, in the present embodiment, the support substrate side of the insulating portion (that is, the side opposite to the single crystal silicon layer)
And a conductive member functioning as a gate electrode or a gate line. And this insulating part is comprised so that it may function as a gate insulating film.

In FIG. 23, an inverter circuit 400
Has a three-dimensional double gate structure. The inverter circuits 400 have the same conductive layer (for example, aluminum layer).
Input line 401, output line 402, V formed by
A DD potential line (high potential line) 403 and a VSS potential line (low potential line) 404 are provided. Furthermore, as a semiconductor layer, SOI
It has a P channel region 411 and an N channel region 412 formed of a single crystal silicon layer having a structure. Then, the upper gate electrode 421 is provided above the P-channel region 411 and the N-channel region 412 via a gate insulating film.
And a lower gate electrode 422 is formed below the P channel region 411 and the N channel region 412 via a gate insulating film.

That is, as shown in FIG. 24, the supporting substrate 20
1. The lower gate electrode 422 is formed on the first layer 1 by a film containing a refractory metal, such as a single substance of polysilicon or tungsten silicide, or a laminate of these, and P on the lower gate electrode 422 via an insulating portion 205. The channel region 411 or the N channel region 412 is stacked, and part of the insulating portion 205 functions as a gate insulating film. On the other hand, the upper gate electrode 42 is formed on the P-channel region 411 or the N-channel region 412 via the gate insulating film 431.
1 is formed of, for example, tungsten silicide. The upper gate electrode 421 and the lower gate electrode 422 share the common input line 40 via the contact hole 441.
Connected to 1. The VDD potential line 403 is connected to the source of the P-channel TFT 451 through the contact hole 442, and the VSS potential line 404 is connected to the source of the N-channel TFT 452 through the contact hole 443. And the P channel type T
The drains of the FT 451 and the N-channel TFT 452 are connected to the common output line 4 via the contact hole 444, respectively.
02 is connected.

As described above, the inverter circuit 400 in which the P-channel TFT 451 and the N-channel TFT 452 are combined is constructed. According to the inverter circuit 400 of this embodiment, the insulating portion 205 can prevent the impurities contained in the supporting substrate 201 and the impurities adsorbed on the bonding surface of the supporting substrate 201 from diffusing to the TFT side. Therefore, the deterioration of the characteristics of the TFT can be prevented. In addition, the lower gate electrode 42, which is an example of a conductive member,
The diffusion of impurities from 2 to the semiconductor layer side can be effectively prevented by the insulating portion 205. In addition, the lower gate electrode 4
22 also functions as a light-shielding film, and can effectively prevent the occurrence of a light leak current in the TFT.

In FIG. 25, the NAND circuit 500 is
For example, the input line 50 formed of the same Al layer
1a and 501b, output line 502, VDD potential line 503
And a VSS potential line 504. NAND circuit 500
The laminated structure in FIG.
Similar to 00, a semiconductor layer is laminated on a supporting substrate via an insulating portion, and upper gate electrodes 521a and 521b are formed on the supporting substrate via a gate insulating film, for example, from tungsten silicide. . NA of this embodiment
According to the ND circuit 500, the impurities contained in the supporting substrate and the impurities adsorbed on the bonding surface of the supporting substrate are T
Since diffusion to the FT side can be prevented by the insulating portion, deterioration of TFT characteristics can be prevented.

In FIG. 26, the NOR circuit 600 includes input lines 601a and 601b, an output line 602, a VDD potential line 603 and a VSS potential line 604, which are formed of the same aluminum layer, for example. NOR circuit 6
In the laminated structure of No. 00, as in the inverter circuit 400 shown in FIG. 24, the semiconductor layer is laminated on the supporting substrate via the insulating portion, and the upper gate electrode is formed on the semiconductor layer via the gate insulating film. 621a and 621b are formed of, for example, tungsten silicide. According to the NOR circuit 600 of this embodiment, the impurities contained in the supporting substrate and the impurities adsorbed on the bonding surface of the supporting substrate are T
Since diffusion to the FT side can be prevented by the insulating portion, deterioration of TFT characteristics can be prevented.

In FIG. 27, the NAND circuit 700 is
It has a three-dimensional double gate structure. NAND circuit 70
0 is, for example, the input lines 701a and 701b, the output line 702, and the VD formed of the same aluminum layer.
A D potential line 703 and a VSS potential line 704 are provided. NA
Similar to the inverter circuit 400 shown in FIG. 24, the laminated structure of the ND circuit 700 is such that a lower gate electrode 721a is formed on a supporting substrate and a semiconductor layer is laminated on the lower gate electrode 721a via an insulating portion. And a part of this insulating portion functions as a gate insulating film. On the other hand, the upper gate electrode 721b is formed on the semiconductor layer via the gate insulating film.

NA having the double gate structure of this embodiment
According to the ND circuit 700, the impurities contained in the supporting substrate and the impurities adsorbed on the bonding surface of the supporting substrate are T
Since diffusion to the FT side can be prevented by the insulating portion, deterioration of TFT characteristics can be prevented. Further, the insulating portion can effectively prevent diffusion of impurities from the lower gate electrode 721a, which is an example of a conductive member, to the semiconductor layer side. In addition, the lower gate electrode 721a also functions as a light-shielding film, and can effectively prevent the occurrence of a light leak current in the TFT. And especially the NAND circuit 700
Has an advantage that the occupied area is reduced as compared with the NAND circuit 500 of FIG.

In FIG. 28, NOR circuit 800 has a three-dimensional double gate structure. NOR circuit 800
Are input lines 801a and 801b, output lines 802, VD formed of the same aluminum layer.
A D potential line 803 and a VSS potential line 804 are provided. NO
Similar to the inverter circuit 400 shown in FIG. 24, the laminated structure of the R circuit 800 is such that a lower gate electrode 821a is formed on a supporting substrate and a semiconductor layer is laminated thereon via an insulating portion. And a part of this insulating portion functions as a gate insulating film. On the other hand, an upper gate electrode 821b is formed on the semiconductor layer via a gate insulating film.

NO having the double gate structure of this embodiment
According to the R circuit 800, the impurities contained in the supporting substrate,
And impurities adsorbed on the bonding surface of the supporting substrate are TFTs.
The diffusion to the side can be prevented by the insulating portion, so that deterioration of the characteristics of the TFT can be prevented. Further, diffusion of impurities from the lower gate electrode 821a, which is an example of a conductive member, to the semiconductor layer side can be effectively prevented by the insulating portion. In addition, the lower gate electrode 821a also functions as a light-shielding film, and can effectively prevent the occurrence of a light leak current in the TFT. In particular, the NOR circuit 800 is shown in FIG.
6 has the advantage that the occupied area is reduced as compared with the NOR circuit 600 of FIG.

(Electronic Device) As an example of an electronic device using the liquid crystal device (electro-optical device) of the above embodiment, the configuration of a projection type display device will be described with reference to FIG.

In FIG. 29, the projection type display device 1100 is used.
Prepared three liquid crystal devices of the above embodiment,
The schematic block diagram of the optical system of the projection type liquid crystal device used as B liquid crystal devices 962R, 962G, and 962B is shown.

A light source device 920 and a uniform illumination optical system 923 are employed in the optical system of the projection display apparatus of this example. Then, the projection display device uses the uniform illumination optical system 9
The color separation optical system 92 as a color separation unit that separates the light flux W emitted from the light source 23 into red (R), green (G), and blue (B).
4 and three light valves 925R, 925G, 925B as modulation means for modulating each color light flux R, G, B,
A color synthesizing prism 910 as a color synthesizing unit that re-synthesizes the modulated color light fluxes, and the synthesized light fluxes on the projection surface 10
The projection lens unit 906 is provided as a projection means for enlarging and projecting on the surface of 0. Further, a light guide system 927 for guiding the blue light flux B to the corresponding light valve 925B is also provided.

The uniform illumination optical system 923 is provided with two lens plates 921 and 922 and a reflection mirror 931 and the two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. Uniform illumination optical system 923
The two lens plates 921 and 922 each include a plurality of rectangular lenses arranged in a matrix. The light flux emitted from the light source device 920 is emitted from the first lens plate 92.
It is divided into a plurality of partial light beams by one rectangular lens.
Then, these partial light fluxes are converted into three light valves 925R and 92R by the rectangular lens of the second lens plate 922.
Superimposed around 5G and 925B. Therefore, by using the uniform illumination optical system 923, even if the light source device 920 has an uneven illuminance distribution in the cross section of the emitted light flux, the three light valves 925R, 925G, and 925B are used.
Can be illuminated with uniform illumination light.

Each color separation optical system 924 comprises a blue-green reflection dichroic mirror 941, a green reflection dichroic mirror 942, and a reflection mirror 943. First, in the blue-green reflective dichroic mirror 941, the blue luminous flux B and the green luminous flux G included in the luminous flux W are reflected at a right angle and head toward the green reflective dichroic mirror 942. The red light flux R passes through this mirror 941, is reflected at a right angle by the rear reflection mirror 943, and is emitted from the emitting portion 944 of the red light flux R to the prism unit 910 side.

Next, the green reflection dichroic mirror 942
, The green light flux G among the blue and green light fluxes B and G reflected by the blue-green reflection dichroic mirror 941
Only the light is reflected at a right angle and is emitted from the emitting portion 945 of the green light flux G to the color combining optical system side.

The blue light flux B which has passed through the green reflection dichroic mirror 942 is emitted from the emitting portion 946 of the blue light flux B to the light guide system 927 side. In the present example, the distances from the emission part of the light flux W of the uniform illumination optical element to the emission parts 944, 945, 946 of the respective color light fluxes in the color separation optical system 924 are set to be substantially equal.

Red and green luminous fluxes R of the color separation optical system 924,
Condensing lenses 951 and 952 are arranged on the emission sides of the G emission sections 944 and 945, respectively. Therefore,
The red and green luminous fluxes R and G emitted from the respective emission portions are incident on these condenser lenses 951 and 952 and are collimated.

The red and green luminous fluxes R and G thus collimated are incident on the light valves 925R and 925G and modulated, and image information corresponding to each color light is added. That is, these liquid crystal devices are switching-controlled according to image information by a driving unit (not shown), whereby the respective color lights passing therethrough are modulated. On the other hand, the blue light flux B is guided to the corresponding light valve 925B via the light guide system 927, and is similarly modulated here according to the image information. The light valves 925R, 925G, and 925B of this example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R and 962G arranged therebetween. , 962
A liquid crystal light valve composed of B and B.

The light guide system 927 is used for the emitting portion 94 of the blue luminous flux B.
6, a condenser lens 954 disposed on the emission side, an incident side reflection mirror 971, an emission side reflection mirror 972, an intermediate lens 973 disposed between these reflection mirrors, and a front side of the light valve 925B. It is composed of a condenser lens 953. The blue light flux B emitted from the condenser lens 946 passes through the light guide system 927 and the liquid crystal device 962B.
To be modulated. The optical path length of each color luminous flux, that is,
The liquid crystal devices 962R, 962G, 9
As for the distance to 62B, the blue light flux B has the longest distance, and thus the light quantity loss of the blue light flux becomes the largest. However, the light amount loss can be suppressed by interposing the light guide system 927.

Each light valve 925R, 925G, 92
The respective colored light fluxes R, G, and B that have passed through 5B are incident on the color combining prism 910 and are combined here. Then, the light combined by the color combining prism 910 is enlarged and projected on the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

Projection type display device 1100 having the above structure
Includes the liquid crystal device according to the above-described embodiment, it is possible to prevent the deterioration of the characteristics of the TFT (transistor element), and the performance becomes excellent.

The present invention is not limited to the above-mentioned embodiments, but can be appropriately modified within the scope of the gist or concept of the invention which can be read from the claims and the entire specification, and such modifications are accompanied. The electro-optical device, the method thereof, and the electronic device are also included in the technical scope of the present invention.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of an SOI substrate according to an embodiment of the present invention.

FIG. 2 is a process drawing showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.

FIG. 3 is a process drawing showing the method of manufacturing the SOI substrate according to the embodiment of the present invention.

FIG. 4 is a diagram showing a bonding pattern of a support substrate and a single crystal silicon substrate in a method for manufacturing an SOI substrate according to an embodiment of the present invention.

FIG. 5 is a sectional view showing a structure of an element substrate according to an embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of various elements, wirings, and the like that form a pixel portion in the electro-optical device according to the embodiment of the present invention.

FIG. 7 is a plan view of a plurality of pixel groups adjacent to each other on the element substrate in the electro-optical device according to the embodiment of the invention.

8 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 9 is a process drawing showing the method of manufacturing the element substrate according to the embodiment of the invention.

FIG. 10 is a process drawing showing the method of manufacturing the element substrate according to the embodiment of the invention.

FIG. 11 is a process drawing showing the method of manufacturing the element substrate according to the embodiment of the invention.

FIG. 12 is a process drawing showing the method of manufacturing the element substrate according to the embodiment of the invention.

FIG. 13 is a process drawing showing the method of manufacturing the element substrate according to the embodiment of the invention.

FIG. 14 is a process drawing showing the method of manufacturing the element substrate according to the embodiment of the invention.

FIG. 15 is a plan view of the element substrate of the electro-optical device according to the exemplary embodiment of the present invention, together with the respective components formed thereon, as viewed from the counter substrate side.

16 is a cross-sectional view taken along line HH 'of FIG.

FIG. 17 is a cross-sectional view showing various specific examples of a structure in which a light shielding film is formed below the TFT in the electro-optical device according to the embodiment.

FIG. 18 is a cross-sectional view showing various specific examples of a structure in which a light shielding film is formed below the TFT in the electro-optical device according to the embodiment.

FIG. 19 is a cross-sectional view showing various specific examples of a structure in which a light shielding film is formed below the TFT in the electro-optical device according to the embodiment.

FIG. 20 is a cross-sectional view showing various specific examples of a structure in which a light shielding film is formed below the TFT in the electro-optical device according to the embodiment.

FIG. 21 is a block diagram showing an overall configuration of a liquid crystal display device.

FIG. 22 is a circuit diagram showing a configuration of a data line driving circuit in a liquid crystal display device.

FIG. 23 is a plan view of an inverter circuit having a double gate structure, which is an example of a semiconductor device.

24 is a cross-sectional view showing a double gate structure which sandwiches a channel region of a semiconductor layer in the inverter circuit of FIG. 23 from above and below.

FIG. 25 is a plan view of a NAND circuit which is another example of the semiconductor device.

FIG. 26 is a plan view of a NOR circuit which is another example of the semiconductor device.

FIG. 27 is a plan view of a NAND circuit having a double gate structure, which is another example of the semiconductor device.

FIG. 28 is a plan view of a NOR circuit having a double gate structure, which is another example of the semiconductor device.

FIG. 29 is a configuration diagram of a projection type display device which is an example of an electronic apparatus using the electro-optical device according to the embodiment of the invention.

[Explanation of symbols]

200 ... SOI substrate 201 ... Support substrate 202 ... Single crystal silicon layer 202A ... Single crystal silicon substrate 203B ... First silicon oxide film 203A ... Second silicon oxide film 204. .. Silicon nitride film or silicon oxynitride film 204A ... First silicon nitride film or silicon oxynitride film 204B ... First silicon nitride film or silicon oxynitride film 205 ... Insulating portion 210 ... Element substrate 220. .. TFT (transistor element) 208 ... Semiconductor layer 222 ... Resist 1a ... Semiconductor layer 1a '... Channel region 1b ... Low concentration source region (source side LDD region) 1c ... Low Concentration drain region (drain side LDD region) 1d ... High concentration source region 1e ... High concentration drain region 10 ... Element substrate 10A ... Substrate body (supporting substrate) 20 ... Counter substrate 20A .. Substrate body 11a ... first light-shielding film 12 ... first layer Insulating film 30 ... pixel switching TFT (transistor element) 50 ... liquid crystal layer (electro-optical material layer)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09F 9/30 349 G09F 9/30 349C 5F110 H01L 21/8238 H01L 27/08 331E 27/08 331 27/12 B 27/092 29/78 619B 27/12 27/08 321B 29/786 29/78 626C F term (reference) 2H042 AA15 AA26 2H091 FA34X FA34Z FA35X FA35Z FA41Z FB08 FD02 GA13 LA03 MA07 2H092 GA11 GA17 GA24 GA25 GA43 HA03 HA05 HA43 HA03 HA05 HA05 JA24 JA28 JA31 JA32. AB07 AC04 BA09 BA16 BB05 BC06 BC16 5F110 AA21 BB02 BB04 CC02 DD02 DD03 DD05 DD12 DD13 DD14 DD15 DD17 DD22 EE05 EE09 EE14 EE30 GG02 GG12 GG13 GG15 GG25 GG32 GG51 HJ01 HJ12 HJ23 HL03 HL05 HL07 HL23 HM14 HM15 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN43 NN44 NN46 NN72 NN73 QQ03 QQ11 QQ03 QQ19

Claims (18)

[Claims] 1. A pixel electrode, a transistor element having a semiconductor layer connected to the pixel electrode and including a channel region, a wiring connected to the transistor element, and at least the channel region on a supporting substrate. A light-shielding film covering from the support substrate side, and a silicon nitride film or a silicon nitride oxide film, which is disposed between at least one of the light-shielding film and the semiconductor layer and between the support substrate and the light-shielding film. An electro-optical device, comprising: an insulating portion including. 2. The electro-optical device according to claim 1, wherein the insulating portion has a multilayer structure. 3. The laminated structure includes the silicon nitride film or silicon oxynitride film, and a silicon oxide film formed on an upper surface or a lower surface of the silicon nitride film or the silicon nitride oxide film. The electro-optical device according to claim 2. 4. The electro-optical device according to claim 1, wherein the insulating portion is in close contact with the light shielding film. 5. The insulating portion faces the light shielding film with an interlayer insulating film interposed therebetween.
The electro-optical device according to claim 1. 6. The light-shielding film has a flat pattern of a predetermined shape, the insulating portion has a flat pattern of a shape that completely covers the light-shielding film, and an edge of the insulating portion is seen in a plan view. 6. The electro-optical device according to claim 1, wherein the electro-optical device is separated from an edge of the light shielding film. 7. The edge of the insulating portion is 2 μm from the edge of the light shielding film.
The electro-optical device according to claim 1, further comprising a region that is within m. 8. The edge of the insulating portion is formed in a self-aligned manner with the edge of the light shielding film.
The electro-optical device according to claim 1. 9. The electro-optical device according to claim 1, wherein the semiconductor layer has an SOI (Silicon On Insulator) structure formed of a single crystal silicon film. 10. The electro-optical device according to claim 1, wherein the semiconductor layer is made of a polysilicon film or an amorphous silicon film. 11. The electro-optical device according to claim 1, wherein the light-shielding film contains a refractory metal. 12. The electro-optical device according to claim 1, wherein a total layer thickness of the silicon nitride or silicon oxynitride film of the insulating portion is 100 nm or less. 13. The method according to claim 1, further comprising: a counter substrate arranged to face the support substrate, and an electro-optical material layer sandwiched between the support substrate and the counter substrate. 13. The electro-optical device according to any one of 12. 14. An electronic apparatus comprising the electro-optical device according to claim 1. Description: 15. A step of forming a light-shielding film in a predetermined region on a supporting substrate, and a step of forming an insulating portion including a silicon nitride film or a silicon nitride oxide film on the light-shielding film directly or through an interlayer insulating film. And a step of forming a semiconductor layer on the insulating portion directly or via an interlayer insulating film, and a transistor in which a channel region is arranged at a position covered by the light shielding film from below with the semiconductor layer as a constituent element. A method for manufacturing an electro-optical device, comprising: a step of forming an element; and a step of forming a wiring and a pixel electrode connected to the transistor element. 16. The method according to claim 16, further comprising a step of forming another insulating portion including a silicon nitride film or a silicon nitride oxide film on the supporting substrate before the step of forming the light shielding film. 15. The method for manufacturing the electro-optical device according to 15. 17. A step of forming an insulating portion including a silicon nitride film or a silicon oxynitride film on a supporting substrate, and a step of forming a light shielding film in a predetermined region on the insulating portion directly or via an interlayer insulating film. A transistor element in which a semiconductor layer is formed on the light-shielding film directly or via an interlayer insulating film, and a channel region is arranged at a position covered by the light-shielding film from below from the light-shielding film as a constituent element. And a step of forming a wiring and a pixel electrode connected to the transistor element, and a method of manufacturing an electro-optical device. 18. The step of forming the semiconductor layer, the step of bonding the single crystal silicon substrate having the semiconductor layer formed thereon and the support substrate having the light-shielding film and the insulating portion formed thereon, and the step of adhering after the bonding. 18. A step of thinning a single crystal silicon substrate.
The method for manufacturing an electro-optical device according to any one of 1.