JP2003031799A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To prevent an increase in manufacturing cost without using an SOI substrate and to perform MISF similarly to the case using an SOI substrate.
The ET parasitic capacitance can be reduced and the current driving force can be improved due to the substrate floating effect.
A reduction in the current driving force of the ET can be suppressed, and the substrate potential of the MISFET can be easily secured as necessary. A silicon substrate and a silicon substrate are provided.
1. An oxide film 1 which is embedded in a part of
A channel region and a drain / source diffusion layer are formed in a region of the polysilicon 110 covered with the silicon substrate 09 and a surface layer of the silicon substrate, and the channel region and a part of the drain / source diffusion layer adjacent thereto are in contact with the oxide film 109. And a substrate region of the MISFET is electrically separated from the silicon substrate by a PN junction with a drain / source diffusion layer and an oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a substrate structure of a MIS field effect transistor and a method of forming the same, and is applied to, for example, a MIS integrated circuit.

[0002]

2. Description of the Related Art For MIS type integrated circuits having MIS type field effect transistors (FETs) formed on a silicon substrate, the demand for higher speed has become stronger in recent years. As a means, a technique for forming a MISFET on an SOI substrate is being developed.

By using the SOI substrate, MISFE
Although the speed of the MIS type integrated circuit can be increased by reducing the parasitic capacitance of T and improving the current driving force due to the substrate floating effect, on the other hand, a special transistor is formed to increase the cost, self-heating, and secure the substrate potential. There were some disadvantages such as having to do it.

Hereinafter, FIGS. 13A to 13D and FIG.
A method of manufacturing a MIS type integrated circuit formed on an SOI substrate by using a conventional technique will be described with reference to 4 (a) to 4 (d).

First, as shown in FIG. 13A, a P-type silicon substrate 1, a buried oxide film 2, and a silicon single crystal layer 3 are formed.
An oxide film 4 with a thickness of about 10 nm is formed on the SOI substrate made of SiO 2 by thermal oxidation, and further LPCVD (Low-Pressure
A silicon nitride film 5 and an oxide film 6 are sequentially deposited by the -Chemical-Vapor-Deposition method.

Next, as shown in FIG. 13B, a resist pattern 20 is formed on a region to be the element region 7 by using lithography, and the RIE (Reactive-Ion) using the resist pattern 20 as a mask. -Etching) or the like is used to process the surface oxide film 6 into a predetermined shape.

Subsequently, as shown in FIG. 13C, after the resist pattern 20 is peeled off, the nitride film 5, the oxide film 4, and the silicon single crystal are formed by RIE using the oxide film 6 as a mask material. The layer 3 is processed into a predetermined shape.

Next, as shown in FIG. 13D, CVD
After the oxide film 8 is embedded by using the chemical method, CMP (Chemical
-Mechanical-Polishing) is used to polish the oxide film 8 until the silicon nitride film 5 on the element region 7 is exposed.

Next, the silicon nitride film 5 exposed by the polishing is removed by hot phosphoric acid, and a P-type impurity region 9 is formed in the silicon single crystal layer 3 by ion implantation, as shown in FIG. Form.

Subsequently, the oxide film 4 on the surface is stripped with an HF-based solution, and then the gate insulating film 10 is formed by thermal oxidation, as shown in FIG. Further, after depositing polysilicon using LPCVD, resist patterning by lithography and MISFE using RIE are performed.
The gate electrode 11 of T is formed. And the gate electrode 1
By performing ion implantation using 1 as a mask, MIS
A low-concentration diffusion layer 12 to be the drain / source region of the LDD structure of the FET is formed.

Next, as shown in FIG.
A side wall 13 is formed on the outer periphery of the gate electrode 11 by depositing a nitride film by the VD method and etching back by the RIE method. Further, by performing ion implantation using the gate electrode 11 and the side wall 13 as a mask material, a high concentration diffusion layer 14 to be the drain / source region of the MISFET is formed.

Thereafter, as shown in FIG. 14 (d), a refractory metal such as Ti, Co, or Ni is deposited on the surface and subjected to a heat step, whereby the silicon single crystal layer 3 and the gate electrode 1
A metal silicide layer 15 is selectively formed on the metal layer 1. Further, the interlayer insulating film 16, the contact plug 17, and the metal wiring 18 are formed by using a wiring forming technique which is usually used.

However, the above conventional manufacturing method uses a high-priced SOI substrate at present, so that the manufacturing cost is significantly increased. Further, since the buried oxide film 2 exists below the MISFET, the generated heat is difficult to escape, the temperature of the element rises, the mobility deteriorates, and the current driving force of the MISFET decreases.

Further, the threshold voltage of the MISFET fluctuates when the substrate potential directly below the gate electrode of the MISFET fluctuates. However, when it is desired to avoid the fluctuation of the threshold voltage of the MISFET due to circuit operation, the substrate directly below the gate electrode of the MISFET. When a body contact is formed to secure (fix) the potential and a fixed potential is supplied to the channel region of the MISFET, it is necessary to form a special pattern to form the body contact.

[0015]

As described above, the semiconductor device in which the MISFET is formed on the conventional SOI substrate is as follows.
MI due to self-heating, which increases manufacturing costs
There are problems that the current driving force of the SFET decreases and that a special pattern has to be formed when the substrate potential immediately below the gate electrode of the MISFET is fixed.

The present invention has been made to solve the above-mentioned problems, and while suppressing an increase in manufacturing cost, the parasitic capacitance of the MISFET is reduced and the current is driven by the substrate floating effect as in the case of using the SOI substrate. To provide a semiconductor device and a method of manufacturing the same that can improve the power, can suppress the decrease in the current driving force of the MISFET due to self-heating, and can easily secure the substrate potential of the MISFET as necessary. With the goal.

[0017]

The semiconductor device of the present invention comprises:
A semiconductor substrate, a buried region which is embedded in a part of the semiconductor substrate and has an insulating film formed on the outer periphery thereof, and a channel region and a drain region formed on the surface layer of the semiconductor substrate.
A source diffusion layer is formed, and the channel region and at least a part of the drain / source diffusion layer adjacent to the channel region are in contact with the insulating film, and a MIS field effect transistor is provided.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming holes in a silicon substrate and a step of forming a buried element isolation region in the silicon substrate so as to be continuous with the outer periphery of the holes in the silicon substrate. A step of forming a groove and exposing the outer peripheral portion of the hole to the groove, and a step of thermally oxidizing the exposed hole and then filling the area with polysilicon to form a polysilicon region covered with an oxide film. A step of embedding in a part of the silicon substrate, and a MIS electric field having at least one of a channel region and a source / drain diffusion layer on a polysilicon region covered with the oxide film in a surface layer portion of the silicon substrate. And a step of forming an effect transistor.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIGS. 1 to 12 show steps of manufacturing a MISFET in a MIS type integrated circuit according to a first embodiment of the present invention.

First, as shown in FIG. 1, a thermal oxide film (SiO 2) of about 100 nm is formed on a P-type silicon substrate 101.
₂ film) 102 is formed, and a resist pattern 13 is formed thereon.
Form 0.

Next, as shown in FIG. 2, the thermal oxide film 10 is formed by RIE using the resist pattern 130 as a mask.
2 is processed into a predetermined pattern shape, the resist pattern 130 is removed, and then the P-type silicon substrate 101 is formed by RIE using the pattern of the oxide film 102 as a mask.
A groove 103 is formed in the groove.

Next, after removing the oxide film 102 on the surface using an HF-based solution, annealing is performed in a hydrogen atmosphere, so that a P-type silicon substrate 101 is formed as shown in FIG.
A hole 104 is formed therein. Here, the technique of forming vacancies in a silicon substrate by annealing in a hydrogen atmosphere is described in, for example, T. Sato et al., "A New Substrate.
Engineering for the Formation of Empty Space in Si
licon (ESS) Induced by Silicon Surface Migration ",
It is disclosed in IEDM 1999-517.

Next, as shown in FIG. 4, a silicon oxide film 105 is formed by thermal oxidation, and then a silicon nitride film 106 and a silicon oxide film 107 are sequentially deposited by the LPCVD method. Further, lithography is used to form a resist pattern 131 on a region to be the element region 108, and the resist pattern 131 is used as a mask to form an R pattern.
The silicon oxide film 107 is left only on the element region 108 by performing dry etching such as IE.

Next, as shown in FIGS. 5 (a) and 5 (b),
After removing the resist pattern 131, RIE is performed using the silicon oxide film 107 on the surface as a mask, whereby the silicon nitride film 106 and the silicon oxide film 1 are formed.
05 is removed so as to remain only on the element region 108, and the silicon substrate 101 is further etched to a predetermined depth to form a groove 132.

In this case, FIGS. 5A and 5B show the MISF to be formed in the element region 108 at this stage.
The cross section along the gate length direction of ET and the gate width direction orthogonal thereto is also shown correspondingly. Here, in the cross section along the gate width direction, the holes 104 penetrate the element region 108, and both ends thereof are the grooves 13 of the silicon substrate 101.
Please note that the numbers are two.

Next, as shown in the cross section along the gate width direction shown in FIG. 6, thermal oxidation is performed to thin silicon oxide in the silicon exposed region of the silicon substrate 101 (including the inner wall of the hole 104). After forming the film 109, LP
The polysilicon 110 is deposited by using the CVD method, and the inside of the hole 104 is filled with the polysilicon 110.

Next, as shown in the cross section along the gate width direction shown in FIG. 7A and the cross section along the gate length direction shown in FIG. 7B, the polysilicon 110 is etched back by RIE and By performing the isotropic dry etching, the polysilicon 110 is formed only inside the holes 104.
Is left in place. In this state, the inside of the hole 104 is filled with (non-doped) polysilicon 110 whose upper and lower sides are covered with a thin silicon oxide film 109.

Next, as shown in the cross section along the gate width direction shown in FIG. 8A and the cross section along the gate length direction shown in FIG. , CMP is performed to polish the oxide film 111 until the silicon nitride film 106 on the element region 108 is exposed.

Next, the silicon nitride film 106 exposed by the polishing is removed by hot phosphoric acid, and a P-type impurity region is formed in the silicon substrate 101 by ion implantation as shown in the cross section along the gate length direction shown in FIG. 112 is formed.

Thereafter, the silicon oxide film 105 on the surface is replaced with H
After peeling with an F-based solution, the gate insulating film 113 is formed by thermal oxidation as in the cross section along the gate length direction shown in FIG. Further, after depositing polysilicon using LPCVD, resist patterning by lithography and RIE are used to form the gate electrode 11 of the MISFET.
4 is formed. Then, by performing ion implantation using the gate electrode 114 as a mask, the LDD of the MISFET is
Low-concentration diffusion layer 115 serving as the drain / source region of the structure
To form.

Next, as shown in the cross section along the gate length direction shown in FIG. 11, a nitride film is deposited by LPCVD to form R.
By etching back by the IE method, the gate electrode 11
The side wall 116 is formed on the outer circumference. Furthermore, the gate electrode 1
Ion implantation is performed using 14 and the side wall 116 as a mask material to form a high-concentration diffusion layer 117 to be the drain / source region of the MISFET.

After that, a refractory metal such as Ti, Co, or Ni is deposited on the surface as in the cross section along the gate length direction shown in FIG. 12A and the cross section along the gate width direction shown in FIG. 12B. By performing the heat treatment, the metal silicide 118 is selectively formed on the high-concentration diffusion layer 117 and the gate electrode 114. Further, the interlayer insulating film 119, the contact plug 120, and the metal wiring 121 are formed by using a wiring forming technique which is usually used.

In the method of manufacturing the MISFET described above, a hole is formed in the silicon substrate 101, polysilicon 110 is buried in the hole through a thin oxide film 109, and a polysilicon region covered with this thin oxide film is formed. It is characterized in that the MISFET is formed so that at least a part of the source / drain / channel region (in this example, the channel region and part of the source / drain region) exist.

According to the MISFET thus formed, the MISFET is formed on the embedded region (polysilicon 110 region covered with the oxide film 109 in this example) covered with the thin insulating film formed in the silicon substrate 101. The channel region and a part of the source / drain region exist.

As a result, similar to the MISFET formed on the SOI substrate of the conventional example, advantages such as reduction in diffusion layer capacitance and improvement in current driving force due to the substrate floating effect in the channel region can be obtained. Moreover, since an expensive SOI substrate is not used at present, an increase in manufacturing cost can be suppressed.

Moreover, since the polysilicon 110 region covered with the thin oxide film 109 has good thermal conductivity, MISFE
It is possible to prevent self-heating of the T substrate region. Further, since the polysilicon 110 covered with the thin oxide film 109 has a small difference in coefficient of thermal expansion from the silicon substrate 101, the influence of thermal stress can be small.

Further, a part of MIS in the MIS type integrated circuit
The FET is formed so as to have the above-mentioned structure, and other MISFETs are formed so as to have the normal structure without forming the polysilicon 110 region covered with the holes and the thin oxide film 109 below the MISFET. It is also possible to secure the channel potential by forming it. Therefore, the MISFET in which the substrate floating effect is desired to be generated and the MISFET in which the substrate floating effect is not desired to be generated can easily coexist in the MIS type integrated circuit.

<Second Embodiment> In the first embodiment, the polysilicon 110 region covered with the thin oxide film 109 in the silicon substrate 101 is defined as a channel region of the MISFET and a part of the source / drain regions in the vicinity thereof. An example is shown in which the area corresponding to the area immediately below is formed.

In the second embodiment, the polysilicon 110 region covered with the thin oxide film 109 is further added to the source / source region.
By forming a wide region (not shown) right under most of the drain region, the same effect as the first embodiment can be basically obtained, but the diffusion layer capacitance can be further reduced. .

Further, the polysilicon 110 region covered with the thin oxide film 109 in the silicon substrate 101 is not formed directly under the channel region, but is formed only in the region corresponding directly under the source / drain regions. However, the effect of reducing the diffusion layer capacitance can be obtained. In this case, the structure in which the silicon substrate exists in the region corresponding to the region directly below the source / drain region only through the oxide film (for example, Japanese Patent Publication No. 6-2422).
9), the polysilicon 110 region covered with the thin oxide film 109 has better thermal conductivity, so that the effect of suppressing self-heating can be expected.

[0042]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the parasitic capacitance of the MISFET and the substrate floating effect are reduced as in the case of using the SOI substrate while suppressing the increase of the manufacturing cost. It is possible to improve the current driving force due to, and to suppress the decrease in the current driving force of the MISFET due to self-heating.
The substrate potential of the SFET can be secured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a part of a manufacturing process of a MISFET in a MIS type integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 3 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 4 is a cross-sectional view showing a step that follows the step of FIG.

5 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 6 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 7 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 8 is a cross-sectional view showing a step that follows the step of FIG.

9 is a cross-sectional view showing a step that follows the step of FIG.

10 is a cross-sectional view showing a step that follows the step of FIG.

11 is a cross-sectional view showing a step that follows the step of FIG.

12 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 13 is a cross-sectional view showing a part of the manufacturing process of the MISFET in the MIS type integrated circuit using the conventional SOI substrate.

FIG. 14 is a cross-sectional view showing a step that follows the step of FIG.

[Explanation of symbols]

101 ... P-type silicon substrate, 102 ... oxide film, 103 ... groove, 104 ... hole, 105 ... Silicon oxide film, 106 ... Silicon nitride film, 107 ... Silicon oxide film, 108 ... Element area, 109 ... Silicon oxide film, 110 ... polysilicon, 111 ... Silicon oxide film, 112 ... P-type impurity region, 113 ... Gate insulating film, 114 ... Gate electrode, 115 ... Low-concentration diffusion layer, 116 ... Side wall, 117 ... High-concentration diffusion layer, 118 ... Metal silicide, 119 ... Interlayer insulating film, 120 ... contact hole, 121 ... Metal wiring.

Front page continued (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/786 F-term (reference) 5F048 AC01 AC04 BA09 BA16 BB05 BB08 BC01 BC06 BC11 BC12 BC16 BD01 BF06 BG05 5F110 AA02 AA15 CC02 DD05 DD13 DD25 EE05 EE09 EE14 EE32 EE45 FF02 FF23 GG02 GG12 GG39 HJ13 HK05 HK32.

Claims (5)

[Claims] 1. A semiconductor substrate, a buried region that is embedded in a part of the semiconductor substrate and has an insulating film formed on an outer periphery thereof, and a channel region and a drain / source diffusion layer in a surface layer of the semiconductor substrate. A semiconductor device comprising: a MIS field effect transistor which is formed and has at least a part of the drain / source diffusion layer adjacent to the channel region in contact with the insulating film. 2. The semiconductor device according to claim 1, wherein the buried region in which the insulating film is formed on the outer peripheral portion is a polysilicon region whose outer peripheral portion is covered with an oxide film. 3. The semiconductor device further comprises another MIS field effect transistor formed in a region of the surface layer portion of the semiconductor substrate other than an insulator region in which an insulating film is formed on the outer peripheral portion. The semiconductor device according to claim 1. 4. A step of forming a hole in a silicon substrate, wherein a groove for forming a buried element isolation region is formed in the silicon substrate so as to be continuous with an outer peripheral portion of the hole in the silicon substrate, and the hole is formed. A step of exposing the outer peripheral portion of the groove to the groove, and filling polysilicon with polysilicon after thermally oxidizing the inside of the exposed hole, so that the polysilicon region covered with an oxide film is partially formed in the silicon substrate. And a step of forming a MIS field effect transistor having at least one of a channel region and a source / drain diffusion layer on the polysilicon region covered with the oxide film in the surface layer portion of the silicon substrate. A method for manufacturing a semiconductor device, comprising: 5. The step of forming a hole in the silicon substrate comprises forming a groove in the silicon substrate, and then heating the silicon substrate in a hydrogen atmosphere to form a hole in the silicon substrate from the groove. The method for manufacturing a semiconductor device according to claim 4, wherein a hole is formed.