JP2003031687A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor integrated circuit device capable of setting different substrate potentials in each element region without requiring well separation. SOLUTION: A trench capacitor C is arranged and formed on a first silicon substrate 1. The surface of the silicon substrate 1 is covered with insulating films 14 and 15, and the second silicon substrate 2
Are adhered. The second silicon substrate 2 has a MISFET which constitutes a DRAM cell together with the trench capacitor C.
-QM and MISFET-QS constituting a logic circuit
Is formed. The trench capacitors C are arranged and formed beyond the area of the DRAM cell array. MISFE
The T-QM source diffusion layer 24 is connected to the storage electrode 13 of the capacitor C by a storage electrode plug 26 penetrating the T-QM and further penetrating the insulating film 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an integrated circuit device suitable for mounting a DRAM and a logic circuit together and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, system LSIs have been manufactured in which DRAMs are mixedly mounted on logic LSI chips such as MPUs. Such mixed mounting saves space by reducing the number of chips compared to the case where a DRAM chip and a logic LSI chip are manufactured separately to configure a system, and data transfer between the DRAM and the logic circuit is achieved. The effect that it can be performed at high speed and with low power consumption is obtained.

However, in the DRAM-embedded LSI, since the manufacturing process of the DRAM is added to the manufacturing process of the logic circuit, there are problems such as an increase in cost due to an increase in the manufacturing process and a longer manufacturing period. Also required DRA
Since the specifications are diversified for each type such as the scale of M, various masks are required, and the manufacturing process needs to be adjusted for each mask. This also leads to an increase in cost and a longer manufacturing period.

On the other hand, as an integrated circuit structure suitable for DRAM mixed mounting, a trench capacitor is formed in an array on a semiconductor substrate, a semiconductor layer is grown thereon, and a MOS transistor which constitutes a DRAM cell together with the trench capacitor is formed on this semiconductor layer. Then, a device in which a MOS transistor forming a peripheral circuit is formed has been previously proposed (Japanese Patent Laid-Open No. 11-354739). Here, for example, by making the array region of the trench capacitors in the LSI chip a certain scale and making it possible to configure the DRAM by using an appropriate range of the trench capacitor region, manufacturing of various types of DRAM mixed LSI Is possible.

[0005]

However, if the semiconductor substrate on which the trench capacitors are arranged and the semiconductor layer grown on the trench substrate are not electrically isolated from each other, the DR is not achieved.
The substrate potential of the AM cell array and the substrate potential of the logic circuit cannot be set to different potentials. That is, if the trench capacitor exists just below the substrate region of the logic region, it is not easy to form a well for applying a substrate potential different from that of the DRAM cell array in the logic circuit region. Further, since the semiconductor layer grown on the region where the element is formed has many crystal defects, it becomes difficult to manufacture an LSI with high yield.

An object of the present invention is to provide a semiconductor integrated circuit device capable of setting different substrate potentials in respective element regions without requiring well separation. The present invention also embeds a DRAM as a logic circuit area and a DRAM.
An object of the present invention is to provide a semiconductor integrated circuit device in which another substrate potential can be easily set in a cell array region and a manufacturing method thereof.

[0007]

A semiconductor integrated circuit device according to the present invention includes a first semiconductor substrate, a plurality of first semiconductor elements formed on the first semiconductor substrate, and the first semiconductor substrate.
Second semiconductor substrates adhered on the semiconductor substrate via an insulating layer covering the first semiconductor element, and a plurality of second semiconductor substrates are formed on the second semiconductor substrate, each penetrating the insulating layer. And a second semiconductor element connected to the corresponding first semiconductor element in one semiconductor substrate.

According to the present invention, the two semiconductor substrates are
Some of the semiconductor elements bonded to each other through the insulating layer and formed on the respective substrates are connected to each other through the insulating layer. In this case, since the two semiconductor substrates are basically separated by the insulating layer, different substrate potentials are applied to the substrate regions of the upper semiconductor element and the lower semiconductor element without performing well separation. Can be given. Further, in order to apply a substrate potential to the first semiconductor substrate, for example, a wiring is formed on an interlayer insulating film covering the second semiconductor element, and this is penetrated through the element isolation region of the second semiconductor substrate to form It may be connected to one semiconductor substrate.

In particular, the present invention is preferably applied to a DRAM embedded LSI. In this case, the first semiconductor element formed on the first semiconductor substrate is a trench capacitor, and the second semiconductor element formed on the second semiconductor substrate is connected to the terminal electrode of the corresponding trench capacitor. M forming a DRAM cell with a trench capacitor
ISFET. A logic circuit is formed on the second semiconductor substrate around the cell array in which the DRAM cells are arranged.

With such a DRAM-embedded LSI structure, the substrate potential of the DRAM cell array and the substrate potential of the logic circuit can be easily set to different potentials. That is, since the first semiconductor substrate on which the first semiconductor element is formed and the second semiconductor substrate on which the second semiconductor element is formed are separated by the insulating film, different substrate potentials are applied to them. Is possible without the need for complicated well formation. Further, the MISFET of the cell array and the MISFET of the logic circuit can be manufactured by sharing the main process, and the cost of the DRAM embedded LSI and the manufacturing period can be shortened.

In the case of a mixed DRAM, preferably the first
In this semiconductor substrate, trench capacitors not used for the DRAM cell are arranged outside the entire circumference of the array region where the DRAM cell is formed. As a result, the pattern regularity at the time of forming the trench capacitor is ensured beyond the DRAM cell array region, and a high yield can be obtained. In addition, a trench capacitor not used in the cell array may be buried under the logic circuit region of the first semiconductor substrate, and it is not necessary to take an extra space to maintain regularity in the pattern when forming the capacitor.
High integration becomes possible. Furthermore, by using the same semiconductor substrate on which trench capacitors are arranged and formed, a mixed D
It is possible to make multi-product products with different RAM scales.

When specifically constructing a DRAM cell array, the trench capacitors are arranged in a matrix on the first semiconductor substrate. In the second semiconductor substrate, an element formation region is partitioned by the element isolation insulating film so as to extend over two trench capacitor regions, and a gate electrode connected to a word line and a bit line are formed in each element formation region. Two MISFETs are formed that have a common drain connected to them and a source that penetrates the insulating layer and is connected to the corresponding terminal electrode of the trench capacitor.

The MISFET of the DRAM cell array is a planar MI having the upper surface of the second semiconductor substrate as a channel region.
It may be an SFET, or may be a vertical MISFET having a side wall of a trench formed in the second semiconductor substrate as a channel region and having a gate electrode embedded in the trench.
May be The planar MISFET has a source and a drain formed by impurity diffusion from the upper surface of the second semiconductor substrate. Then, the terminal electrode of the trench capacitor corresponding to the source is connected by the storage electrode plug buried penetrating the source and the insulating layer thereunder. The vertical MISFET is a source formed by diffusion of impurities to the bottom of the second semiconductor substrate from a storage electrode plug that is embedded in an insulating layer and connected to a terminal electrode of a trench capacitor before bonding the second semiconductor substrate. And a drain formed by impurity diffusion from the upper surface of the second semiconductor substrate.

A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of forming a plurality of trench capacitors on a first semiconductor substrate and an insulating layer on the first semiconductor substrate having the trench capacitors formed thereon. Adhesion of the second semiconductor substrate, MISFET forming a DRAM cell array on the second semiconductor substrate, and MISFET for logic circuit arranged around the DRAM cell array region
And a step of forming each M of the DRAM cell array region.
A step of burying and forming a storage electrode plug through the diffusion layer and the insulating layer immediately thereunder in order to connect the diffusion layer of the ISFET to the terminal electrode of the corresponding trench capacitor.

By such a manufacturing method, the DRAM cell array and the MISFET of the logic circuit are formed into a planar type MISFE.
As T, the manufacturing process can be shared to obtain mixed LSIs having different DRAM macro scales.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a plurality of trench capacitors on a first semiconductor substrate and an insulating layer on the first semiconductor substrate having the trench capacitors formed therein. A step of embedding a storage electrode plug connected to a terminal electrode of each trench capacitor in the insulating layer; a step of bonding a second semiconductor substrate on the insulation layer in which the storage electrode plug is embedded; In the DRAM cell array region of the second semiconductor substrate, a source formed at the bottom of the second semiconductor substrate by impurity diffusion from the storage electrode plug, and a buried embedded in a trench formed in the second semiconductor substrate. Forming a plurality of vertical MISFETs having a gate electrode and a drain formed on the upper surface of the second semiconductor substrate; Characterized in that it has.

With such a manufacturing method, the DRA composed of the trench capacitor formed on the first semiconductor substrate and the vertical MISFET formed on the second semiconductor substrate.
An M cell array can be obtained. In this case, DRAM
The MISFET of the logic circuit around the cell array may be formed as a planar MISFET by sharing the step of forming the drain diffusion layer with the planar gate electrode which is connected to the embedded gate electrode of the vertical MISFET and serves as a word line. it can.

Further, in the method of the present invention, preferably, the step of forming the plurality of trench capacitors includes the step of forming the plurality of trenches in the first semiconductor substrate and the step of forming a capacitor insulating film on the inner wall of each trench. A step of depositing a terminal electrode layer on the first semiconductor substrate, and a step of applying a voltage between the terminal electrode layer and the back surface of the first semiconductor substrate to perform a pass / fail judgment test of the capacitor insulating film. And a step of etching back the terminal electrode layer to embed the terminal electrodes separated for each trench. With such a process, if the quality of the trench capacitor is judged during the manufacturing process of the DRAM embedded LSI, the yield can be improved.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1A is a layout of a region extending from a DRAM cell array region of a DRAM embedded LSI chip according to an embodiment of the present invention to a logic circuit region, and FIG. 1B is a sectional view taken along the line II ′ of FIG. 1A. Is. In this embodiment, a bonded substrate formed by bonding two silicon substrates 1 and 2 is used as the element substrate. On the first silicon substrate 1, a plurality of trench capacitors C used for a DRAM cell as first semiconductor elements are arranged in a matrix form beyond the DRAM cell array region to the logic circuit region.

Regarding the relationship between the range in which the trench capacitor C is actually formed and the range of the DRAM cell array, it is preferable that the unused trench capacitors are arranged outside the DRAM cell array region over the entire circumference of the DRAM cell array region. To do so. In this way, the regularity of the pattern is ensured over the range of the DRAM cell array when processing the trench capacitor, which is preferable for improving the yield.

The region of the first silicon substrate 1 where the trench capacitors C are formed is n-type, and this n-type region serves as a common plate electrode for the plurality of trench capacitors C. The capacitor insulating film 1 is formed on the bottom surface and the side surface of the trench 11.
2 is formed, and a terminal electrode (storage electrode) 13 made of polycrystalline silicon is embedded in each trench 11. In this structure, since the pn junction is not formed on the first silicon substrate 1 on which the capacitor is formed, there is no fear of a parasitic transistor. Therefore, it is not necessary to embed a thick insulating film in the upper sidewall of the capacitor, which is usually required to prevent parasitic transistor leakage. As a result, the plug resistance of the storage electrode 13 above the capacitor can be reduced, and the access speed can be improved as compared with the conventional case. Further, since the upper portion of the trench can be used as a capacitor, the capacitance of the capacitor can be increased even if the trench depth is the same as the conventional one.

The trench capacitor C thus formed
The surface of the storage electrode 13 is formed of an insulating film 1 such as a silicon oxide film.
4, and the space between the trench capacitors C is also covered with the insulating film 15. Then, the second silicon substrate 2 is adhered to the first silicon substrate 1 while being insulated and separated by the insulating films 14 and 15. The second silicon substrate 2 is thick at the time of bonding, but after bonding, it is an SOI substrate having a silicon layer adjusted to have an appropriate thickness.

An element isolation insulating film 22 is formed on the second silicon substrate 2 so as to divide the p-type element forming region 21.
TI (Shallow Trench Isolati
on) and the like. Then, in each element formation region 21, as a second semiconductor element, MISFET-Q
M and QS are formed. That is, in the DRAM cell array region, the MISFET-QM that is a memory transistor that configures the DRAM cell together with the trench capacitor C on the silicon substrate 1 side is formed, and in the logic circuit region, the MISFET-QS for logic circuit is formed. .

The MISFET-QM is a device forming region 21.
The gate electrode 2 formed on the gate insulating film 28
3 is a planar MISFET having n-type diffusion layers 24 and 25 serving as a source and a drain. Gate electrode 23
Is continuously patterned in one direction in the DRAM cell array to form a word line WL, as shown in FIG. 1A. In the DRAM cell array region, two MISFET-QMs are formed in one element formation region 21 by sharing the n-type diffusion layer 25 serving as a drain. The MISFET-QS in the logic circuit region is formed, for example, at the same time as the MISFET-QM in the DRAM cell array.
Planar MISFE having 3 and n-type diffusion layers 24 and 25
T. Alternatively, these MISFET-QS and QM may be formed in separate steps.

The surface on which the MISFET is formed is flatly covered with the interlayer insulating film 30. In the DRAM cell array area,
A storage electrode plug 26 made of polycrystalline silicon is buried in the source region of the MISFET so as to penetrate the interlayer insulating film 30. At this time, the through hole is provided so as to penetrate through the source diffusion layer 24 of the second silicon substrate 2 and further through the insulating film 14 that covers the trench capacitor C. As a result, in the DRAM cell array region, MISFET-QM
The n-type diffusion layer 24 serving as the source of the
Via the storage electrode 1 of the corresponding trench capacitor C
3 is connected.

In this structure, the n-type diffusion layer 24 is not formed in advance, and the diffusion of the n-type impurity of the storage electrode plug 26 is performed to obtain a diffusion layer having a small extension to the channel side of the MISFET-QM. It will be possible. Thereby, the gate length (channel length) of the MISFET-QM can be made fine. The trench capacitor C in the logic circuit area is not used in this embodiment,
It remains embedded.

The interlayer insulating film 30 is further covered with an interlayer insulating film 31. Wiring contact plugs 27 are embedded in the interlayer insulating film 31, bit lines 32 are formed in the DRAM cell array, and wirings 33 such as source, drain, and gate are formed in the logic circuit region.

The manufacturing process of this embodiment will be specifically described below. In the following manufacturing process drawings, FIG.
A plan view corresponding to A and a cross-sectional view corresponding to FIG. 1B are used. 2A and 2B are a plan view and a cross-sectional view showing a state in which the trench 11 is formed in the first silicon substrate 1. A mask pattern made of an insulating film 15 is formed on the n-type silicon substrate 1 by lithography and RIE, and the silicon substrate 1 is etched by anisotropic dry etching using this mask pattern, and substantially the same as the entire substrate. The trenches 11 are formed in line with the dimensions and the rules. Here, as shown in FIG. 2A, the trench 11 has a long and narrow rectangular opening, but it can be arbitrarily changed depending on the cell design.

Next, as shown in FIG. 3, after forming the capacitor insulating film 12 on the inner wall of the trench 11, the storage electrode 13 is buried in the trench 11 by depositing a polycrystal silicon film or the like and etching back. Thereby, the trench capacitor C is obtained. As the capacitor insulating film 12,
A silicon nitride film, a silicon oxide film, a tantalum oxide film or other insulating film or a composite film of these is used, and a silicon nitride film, a silicon oxide film or a composite film of these is particularly resistant to a high temperature process performed later. preferable.
The storage electrode 13 is preferably polycrystalline silicon or amorphous silicon resistant to heat, or silicon-germanium, and a low resistance film doped with phosphorus, arsenic or boron is suitable for use as a terminal electrode.

Since the silicon substrate 1 serves as a plate electrode common to a plurality of capacitors, it is preferable that a low resistance n-type layer or p-type layer is formed at least in a region along the trench 11. Therefore, the capacitor insulating film 12
Prior to the formation of, the low resistance layer is formed by utilizing ion implantation of phosphorus, arsenic or boron, or solid phase diffusion or epitaxial growth. Alternatively, the substrate 1 which originally has a low resistance may be used.

In the case of this embodiment, the storage electrode 13 is
It is embedded so that its surface position is lower than the surface position of the insulating film 15. After this, as shown in FIG.
An insulating film 14 that covers the storage electrode 13 is deposited and the entire surface is planarized by CMP processing. As the insulating film 14, a silicon oxide film, a silicon nitride film, or the like is used.
If the same material as 5 is used, the flatness can be improved,
It is effective to prevent defective adhesion due to the generation of voids during bonding.

Although the case where the insulating film 15 as the mask pattern used for forming the trench is left as it is is described here, the insulating film 15 may be removed once after the step of FIG. In that case, the insulating film 14 that covers the storage electrode 13 is formed flat as a single insulating film so as to also cover the surface of the silicon substrate 1 around the trench.

Thereafter, as shown in FIG. 5, the insulating film 14,
The p-type second silicon substrate 2 is adhered to the surface flattened by 15. When the thickness required for forming the element as the silicon substrate 2 is, for example, several tens nm to several μm, several 100 μm
After bonding thick ones, this will be thinned.
In this case, in order to facilitate the thinning after bonding, it is effective to perform hydrogen ion implantation in the vicinity of a required thickness position in advance and peel off at the hydrogen ion implantation position after bonding. Alternatively, SO is used as the second silicon substrate.
It is also possible to use an I substrate and bond it together, then etch the support substrate using the embedded insulating layer of the SOI substrate as a stopper, and further etch the embedded insulating layer to leave the silicon layer.

Next, the second silicon substrate 21 bonded and adjusted in thickness in this manner is then attached to FIGS. 6A and 6B.
As shown in B, the element isolation insulating film 22 is formed by the STI technique.
Are formed by embedding to define the element forming region 21. Figure 6
A is a plan view corresponding to FIG. 1A, and FIG. 6B is its II ′.
6B is a cross-sectional view, and the hatched portion in FIG. 6A indicates the element isolation insulating film 22. The element isolation insulating film 22 is the underlying insulating film 1
It is formed to a depth reaching 4,15. In the DRAM cell array region, the element formation region 21 is formed so as to extend over almost two trench capacitors C. In the logic circuit area, an appropriate element forming area 21 is formed regardless of the trench capacitor C embedded therein.

Thereafter, as shown in FIGS. 7A and 7B,
An n-channel MISFET-QM that is a cell transistor is provided in the DRAM cell array region, and an n-channel MISFET-QS that constitutes a logic circuit is provided in the logic circuit region.
Are formed simultaneously, for example. When the logic circuit is a CMOS circuit, a step of forming a p-channel MISFET on the first silicon substrate 2 is performed.

Specifically, in the MISFET formation step, after forming the gate insulating film 28, the gate electrode 23 made of a polycrystalline silicon film is formed, and then impurities are ion-implanted,
The n-type diffusion layers 24 and 25 which will be the source and the drain are formed. As a result, in the DRAM cell array region, two MISFETs having the n-type diffusion layer 25 as a common drain are formed.
The QM is formed in one element forming region 21. Although not shown in the figure, a process of reducing the resistance of the gate electrode, the source and drain diffusion layers by a salicide technique can be appropriately introduced.

In the DRAM cell array region, the gate electrode 23 is patterned as word lines WL continuous in one direction. In addition, here, the gate electrode 23 is formed by patterning in a state in which the silicon nitride film 41 is laminated on the polycrystalline silicon film, and then the silicon nitride film 42 is also formed on the side wall of the gate electrode 23. Shows an example in which is protected by a silicon nitride film.

Thereafter, as shown in FIG. 8, the interlayer insulating film 3 is formed.
0 is deposited and planarized. Then, in the DRAM cell array region, as shown in FIG. 9, the region of the n-type diffusion layer 24 serving as the source penetrates the n-type diffusion layer 24 from the interlayer insulating film 30 and further penetrates the underlying insulating film 14. A contact hole is formed in this manner, and the storage electrode plug 26 made of a polycrystalline silicon film doped with an n-type impurity is embedded therein.
As a result, the source of the MISFET-QM is connected to the storage electrode 13 of the corresponding trench capacitor C.

Then, as shown in FIGS. 1A and 1B,
An interlayer insulating film 31 is deposited, a contact plug 27 doped with an n-type impurity is buried, and a bit line 32 is formed in the DRAM cell array region and a circuit wiring 33 is simultaneously formed in the logic circuit region.

According to this embodiment, the two silicon substrates 1 and 2 are separated by the insulating films 14 and 15, and the substrate region of the MISFET in the logic circuit region is the base silicon in which the trench capacitor C is embedded. It is independent of the substrate 1. The plate potential of the capacitor C of the cell array can be set independently of the logic circuit region by applying a substrate bias from the bottom surface of the silicon substrate 1, for example. Particularly when the logic circuit has a CMOS circuit configuration, a complicated well isolation structure is usually required. Therefore, if the substrate region of the logic circuit is continuous with the substrate region in which the trench capacitors are buried without isolation, the well isolation itself becomes difficult, but in the case of this embodiment, the logic circuit region is SOI
The structure does not require complicated well separation and D
The substrate potentials of the RAM cell array region and the logic circuit region can be made different.

Further, by using the bonded substrate, the MISFET-QM of the DRAM cell array can be formed in the silicon layer having good crystallinity, and excellent characteristics can be obtained. Furthermore, M of the DRAM cell array
ISFET-QM and MISFET-QS of logic circuit
Can be manufactured by sharing the main process, DR
It is possible to reduce the cost and manufacturing period of the AM-embedded LSI. Alternatively, since the two silicon substrates 1 and 2 are bonded to each other with an insulating film interposed therebetween, they do not have to be of the same quality, and for example, the first silicon substrate 1 or the second silicon substrate 2 side may be made of silicon-germanium. It can also be a substrate.

Further, the second silicon substrate 2 is attached to the first silicon substrate 1 in which the trench capacitors C are formed over a chip area wider than the DRAM cell array area, and only the trench capacitors C actually required for the DRAM cell array are attached. By utilizing the above, it becomes possible to use a common capacitor-formed wafer for a plurality of products having different DRAM macro scales. As a result, it is possible to reduce the number of masks for forming capacitors, reduce the manufacturing cost by improving the yield due to the effect of mass production, and shorten the manufacturing period by reducing the tuning period of the process for forming the capacitor wafer. Further, as described above, since the trench capacitor portion and the transistor portion are separated by the insulating film, the collar insulating film for preventing the parasitic transistor is not required unlike the conventional trench capacitor, which simplifies the process. .

Further, in the case of this embodiment, a trench capacitor which is not actually used in the DRAM cell is formed beyond the region of the DRAM cell array, which contributes to the improvement of the yield. That is, in the case of repeating a regular pattern such as a DRAM cell array, the processing condition may deviate from the central part at the end where the regularity is broken. On the other hand, if a dummy trench capacitor is formed outside the DRAM cell array, the processing conditions of the trench capacitor in the DRAM cell array region are constant, so that the yield is improved. In particular, the DRA covers the entire circumference of the DRAM cell array area.
If a trench capacitor is formed outside the M cell array, it has a great significance in improving the yield.

Furthermore, it is also effective in the case where an analog circuit including an inductance element is mixed in the logic circuit section. When the trench capacitor is densely embedded immediately below the inductance element, eddy current is suppressed by this, unnecessary loss is suppressed, and excellent high frequency characteristics can be obtained. Alternatively, it can be used as a capacitor as a circuit element. At this time, the storage electrode plugs can be connected in parallel to appropriately adjust the capacitance of the capacitor.

[Second Embodiment] FIG. 10 shows a sectional view of a DRAM-embedded LSI according to another embodiment corresponding to FIG. 1B of the previous embodiment. The parts corresponding to those in the previous embodiment are designated by the same reference numerals, and detailed description will be omitted. In the case of this embodiment, a void 45 is formed above the storage electrode 13 of the trench capacitor C in the logic circuit region.
There is a feature. Other than that, it is the same as the previous embodiment.

Such a structure can be obtained by bonding the second silicon substrate 2 without forming the insulating film 14 covering the storage electrode 13 in the step of FIG. 4 of the previous embodiment. However, by forming an insulating film on the adhesive surface side of the second silicon substrate 2, the storage electrode plug 26 and the back surface of the second silicon substrate 2 are prevented from being short-circuited. DR
In the AM cell array region, since the storage electrode plug 26 is embedded on the storage electrode 13, the storage electrode plug 26 fills the gap. Although FIG. 10 shows a state in which the storage electrode plug 26 completely fills the void, it does not matter if the void is partially left.

With such a structure, the parasitic capacitance of the logic circuit region can be reduced as compared with the previous embodiments. That is, in consideration of the burying margin of the storage electrode plug 26 and the reduction of resistance, it is preferable that the insulating film 14 is thin, but if the insulating film 14 is thin, the parasitic capacitance under the substrate region of the logic circuit becomes large. By forming this portion as the void 45, the parasitic capacitance is reduced and the circuit performance is improved. Further, since the step of depositing the insulating film 14 and flattening it is eliminated, the number of steps is reduced accordingly.

[Third Embodiment] In the embodiments so far, the planar MISFET is used.
An embodiment of the DRAM embedded LSI of the embodiment using the ET will be described. FIG. 11A shows a D according to this embodiment.
FIG. 11B is a cross-sectional view taken along the line II ′ of FIG. 11B, which shows a layout extending from the DRAM cell array region of the RAM embedded LSI chip to the logic circuit region. A bonded substrate formed by adhering two silicon substrates 1 and 2 is used as an element substrate, and a plurality of trench capacitors used in a DRAM cell as a first semiconductor element are used for the first silicon substrate 1. Similar to the previous embodiment, the Cs are arranged in a matrix form beyond the DRAM cell array region to the logic circuit region.

The first silicon substrate 1 on which the trench capacitor C is formed is covered with the insulating films 14 and 15, and the second silicon substrate 2 is adhered thereto, but the second silicon substrate 2 is different from the previous embodiment. The silicon substrate 2 is left thick. Then, in the DRAM cell array region, the element isolation insulating film 22
The vertical MISFET-QM is configured by utilizing the side surface of the element forming region 21 partitioned by. That is, the gate insulating film 28 is formed on both side surfaces of the element forming region 21 and the gate electrode 23a is embedded therein.

Insulating films 14, 1 on the first silicon substrate 1 side
5, a storage capacitor plug 26 doped with an n-type impurity is embedded in the trench capacitor C used in the DRAM cell array in advance. After the substrates are bonded together, the n-type diffusion layer 24 serving as the source is formed at the bottom of the element forming region 21 by impurity diffusion from the storage electrode plug 26 to the second silicon substrate 2 side. The n-type diffusion layer 25 serving as a drain is formed on the upper surface of the element formation region 21.

The first-layer gate electrode 23a embedded in each cell region is continuously connected in one direction to the second-layer gate electrode 23b which becomes the word line WL. In addition, an element formation region 21 in which two MISFET-QMs are formed
In addition to the bit line contact plug 27, a buried wiring 29 for giving a substrate potential is formed in the central portion of the word line WL.
Are continuously formed in the direction of.

The manufacturing process of this embodiment will be described below. In the following manufacturing process drawings, a plan view corresponding to FIG. 11A and a sectional view corresponding to FIG. 11B are used as necessary.
FIG. 12 shows a state in which trench capacitors C are formed on the first silicon substrate 1 in the same manner as in the previous embodiment. The substrate on which the capacitor C is formed is the insulating film 1
It is covered with 4, 15 evenly. The difference from the previous embodiment is that the portion of the trench capacitor C that is actually used as a DRAM cell array at this stage is
Contact holes are formed in the insulating films 14 and 15 to form the storage electrode 1.
3 is to embed the storage electrode plug 26 connected to No. 3. The storage electrode plug 26 is a polycrystalline silicon film doped with an n-type impurity and is embedded so that the surface is flat.

After this, as shown in FIG. 13, the p-type second
The silicon substrate 2 is bonded. Second silicon substrate 2
The thickness is adjusted after the bonding in the same manner as in the previous embodiment, but is left thicker than in the previous embodiment.

Thereafter, as shown in FIGS. 14A and 14B, a mask of an insulating film 50 is patterned on the surface of the silicon substrate 2 and etching is performed to form a gate electrode burying trench 51 at the position of the storage electrode plug 26. Form. A cap insulating film 52 is formed on the surface of the storage electrode plug 26 exposed on the bottom surface of the trench 51 in order to ensure separation between the storage electrode plug 26 and a gate electrode to be formed later. Then, on the silicon substrate 2, by solid phase diffusion from the storage electrode plug 26 in contact with the bottom surface,
An n-type diffusion layer 24 which will be a source is formed. However, the storage electrode plug 26 may be embedded after the bonding instead of being embedded before the substrate is bonded. That is, after bonding the substrate,
The trench 51 for embedding the gate electrode may be formed to a depth reaching the storage electrode 13, and then the storage electrode plug 26 may be embedded.

Next, the insulating film 50 is removed, and as shown in FIG. 15, after the gate insulating film 28 is formed from the surface of the silicon substrate 2 to the inner wall of the gate electrode burying hole 51, polycrystalline silicon to be the gate electrode 23a is formed. The film is deposited so as to fill the trench 51 and become flat.

Next, as shown in FIGS. 16A and 16B, the element isolation insulating film 22 is buried by STI so as to partition the element formation region 21 in the second silicon substrate 2. By this element isolation process, the gate electrode 23a becomes D
In the area of the RAM cell array, two MISFET areas are patterned so as to be continuous, and in the logic circuit area, the pattern is formed so as to cover the entire element area.

After that, as shown in FIG. 17, an insulating film 22b is buried so as to separate the gate electrode 23a between the two MISFETs at both ends of each element forming region 21 in the DRAM cell array region. This gives D
In the RAM cell array region, the gate electrode 23a is
Each SFET is separated and embedded.

Next, as shown in FIGS. 18A and 18B, a second-layer gate electrode 23b made of a polycrystalline silicon film overlapping the first-layer gate electrode 23a is formed. In the area of the DRAM cell array, the gate electrode 23b is connected to the word line W
A pattern is formed at the same time as the gate electrode 23a so as to be continuous as L. In the logic circuit area, the gate electrode 23
A and the gate electrode 23b overlapping with this are patterned at the same time. Specifically, the polycrystalline silicon film to be the gate electrode 23b is patterned in the state where the silicon nitride film 41 is laminated, and the silicon nitride film 42 is also formed on the side wall thereof.

In this gate electrode patterning process, DR
At both ends of each element formation region 21 in the AM cell array region, the gate electrode 23a is also etched to expose the silicon surface of the element formation region 21. The etching is stopped by the insulating film 22b between the gate electrodes 23b that are two passing word lines that cross the element formation region 21, and the surface of the element formation region 21 is not exposed. In the logic circuit area,
The surface of the element formation region 21 is exposed by etching the gate electrodes 23a and 23b.

By performing ion implantation of n-type impurities in this state, n-type diffusion layers 25 serving as drains are formed in the DRAM cell array region, and n-type diffusion layers 24 and 25 serving as sources and drains in the logic circuit region. Are formed at the same time. As a result, the vertical MISFET-QM using both end faces of the element formation region 21 is completed in the DRAM cell array region, and the normal planar MISFET-QS is completed in the logic circuit region.

After that, as shown in FIG. 19, an interlayer insulating film 30 is deposited, and the silicon nitride film 41 is used as a stopper for etching back to planarize. Next, as shown in FIG. 20, a bit line contact plug 27 made of a polycrystalline silicon film doped with an n-type impurity is buried and formed in the drain region in the DRAM cell array region and in the source and drain regions in the logic circuit region. . The logic circuit may have a configuration in which no plug is formed. Separately from this step, the element formation region 2 of the DRAM cell array
A buried bias wiring 29 for substrate bias, which is doped with a p-type impurity, is formed between the two passing word lines crossing the line 1. The plug 27 and the embedded wiring 29 may be formed at the same time, and the doping may be performed in different ion implantation steps.

The contact plug 27 is locally buried in each electrode region, but the buried bias wiring 29 for substrate bias is sandwiched between the word lines WL and in the same direction as the word lines WL as shown in FIG. 11A. Embedded as continuous wiring. Thereafter, as shown in FIG. 11B, an interlayer insulating film 31 is deposited, and the bit line 3 in the DRAM cell array region is deposited.
2 and the terminal wiring 33 in the logic circuit area are simultaneously patterned.

Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, in the case of this embodiment, a vertical MISFET is used as the MISFET-QM of the DRAM cell array, and its channel length is the second.
It can be adjusted by the thickness of the silicon substrate 2. Therefore, DR
The channel length of the MISFET-QM can be optimally set without limiting the channel length due to the miniaturization of the AM cell array, and excellent operating characteristics without a short channel effect can be obtained. The same vertical MISFET may be used in a logic circuit. Further, the vertical MISFET-QM is formed at both ends of one element formation region, and the substrate bias wiring is embedded and formed in the central portion, whereby the MISF is formed.
The channel body of the ET-QM can be set to the optimum potential instead of the floating state, and the operation stability can be secured. Furthermore, the trench of the capacitor C and the MISF
The capacitor is formed separately from the ET-QM trench, and by setting the former sufficiently larger than the latter, it is possible to secure a large capacitor capacitance.

[Fourth Embodiment] FIGS. 21A and 21B.
1A shows a plan view and a cross-sectional view of a DRAM mixed LSI that is a modification of the first embodiment, corresponding to FIGS. 1A and 1B. In this embodiment, the interlayer insulating films 31 and 30, the element isolation insulating film 22 and the substrate isolation insulating film 15 are penetrated so that the substrate potential (plate potential) on the capacitor C side is applied from the second silicon substrate 2 side. Contact plug 27
b is embedded, and the substrate bias wiring 33b is connected to the other wiring 3
It is formed at the same time as 3. The contact plug 27b can be formed, for example, simultaneously with the bit line contact plug 27 on the DRAM cell array side or via the storage electrode plug 26.

Further, this embodiment shows an example in which the source which is one end of the MISFET-QS of the logic circuit is connected to the capacitor C formed on the first silicon substrate 1. In this case, the storage electrode plug 26 that penetrates the n-type diffusion layer 24 and is connected to the storage electrode 13 of the capacitor C is, for example, the storage electrode plug 26 in the region of the DRAM cell array and the plug 26 a that is embedded in the interlayer insulating film 30 at the same time. Then, it may be formed by two-step embedding of the plug 26b to be embedded thereover. Of course, other contact plug embedding methods can also be used.

According to this embodiment, the plate potential of the DRAM cell array can be applied from the second silicon substrate side at an appropriate position. Further, when a capacitor is required in the logic circuit area, the trench capacitor redundantly arranged on the first silicon substrate 1 can be effectively used.

[Embodiment 5] Next, a preferred method of performing a wafer test of a trench capacitor in each of the above embodiments will be described. FIG. 22 shows, for example, the first embodiment.
As shown in FIG. 3, immediately before embedding the terminal electrode (storage electrode) 13 in each trench 11 of the first silicon substrate 1,
The state where the storage electrode layer 13 is continuously deposited is shown. In this state, by applying a voltage between the storage electrode layer 13 and the back surface of the silicon substrate 1, the leak characteristic of the capacitor can be checked. As a result, it is possible to limit the types of products to which each wafer can be applied before the substrates are bonded together, and the yield can be improved.

Alternatively, the storage electrode 13 can be divided and patterned once for each capacitor group, and the check can be performed for each capacitor group. As a result, even if there is a capacitor having a large leak, a high yield can be obtained by preventing the capacitor from being actually used in the DRAM cell array.

[Embodiment 6] In the embodiments so far, the chip-level structure of the DRAM embedded LSI has been described, but there are several ways of arranging the trench capacitors when viewed at the wafer level. Embodiments are possible. The two modes are shown in FIGS. 23 and 24.

FIG. 23 shows a preferred mode for multiple products having the same chip size. In this case, the capacitor area is set as shown by the diagonal lines only within each chip area of the wafer. As described in the above embodiments, the area of the capacitor region in which the trench capacitors are arranged has a size that covers the range of the DRAM cell array actually mounted. Since alignment is required when forming a transistor on a substrate bonded to this wafer, alignment marks are formed, for example, so as to surround a capacitor region in each chip region.

FIG. 24 shows another mode. In this case, regardless of the chip size, a trench capacitor is formed with a hatched area covering the entire chip area as the capacitor area. Preferably, the alignment mark is not particularly formed, and the regular trench pattern in the capacitor region is used as it is as the alignment mark. As a result, the trench capacitor is formed over the entire surface of the chip to be cut out, regardless of the chip size. That is, it is possible to use a common trench capacitor embedded wafer for all kinds of products. In this aspect, in particular, the regularity of the trench capacitor is maintained in a wide range exceeding the chip size. Therefore, when viewed at the chip level, the processing conditions of the capacitor are constant regardless of the size of the DRAM cell array region. A high yield can be obtained.

[0072]

As described above, according to the present invention, the second semiconductor substrate is bonded to the first semiconductor substrate having the trench capacitor embedded therein with the insulating film interposed therebetween, and the second semiconductor substrate is bonded.
By forming the MISFETs that form the DRAM cells and the MISFETs that form the logic circuits together with the trench capacitors on the semiconductor substrate of 1), it is possible to form different types of DRAM macro scales using a common capacitor formation wafer.

[Brief description of drawings]

FIG. 1A is a plan view of a principal portion of an LSI according to a first embodiment of the present invention.

1B is a cross-sectional view taken along the line I-I ′ of FIG. 1A.

FIG. 2A is a plan view showing a step of forming a trench in the first silicon substrate of the first embodiment.

2B is a cross-sectional view taken along the line I-I ′ of FIG. 2A.

FIG. 3 is a cross-sectional view showing a step of filling the storage electrode according to the first embodiment.

FIG. 4 is a cross-sectional view showing a step of covering the storage electrode of the first embodiment with an insulating film.

FIG. 5 is a cross-sectional view showing the step of adhering the second silicon substrate according to the first embodiment.

FIG. 6A is a plan view showing an element isolation process of the second silicon substrate according to the first embodiment.

6B is a cross-sectional view taken along the line I-I ′ of FIG. 6A.

FIG. 7A is a plan view showing a transistor forming step according to the first embodiment.

7B is a cross-sectional view taken along the line I-I ′ of FIG. 7A.

FIG. 8 is a cross-sectional view showing the interlayer insulating film forming step of the first embodiment.

FIG. 9 is a cross-sectional view showing a step of filling the storage electrode plug according to the first embodiment.

FIG. 10 is a cross-sectional view of essential parts of an LSI according to a second embodiment of the present invention.

FIG. 11A is a plan view of a principal portion of an LSI according to a third embodiment of the present invention.

11B is a cross-sectional view taken along the line I-I ′ of FIG. 11A.

FIG. 12 is a cross-sectional view showing a step of forming a trench capacitor in the first silicon substrate of the third embodiment.

FIG. 13 is a sectional view showing a step of adhering a second silicon substrate according to the third embodiment.

FIG. 14A is a plan view showing a step of forming a gate electrode burying trench in the second silicon substrate according to the third embodiment.

14B is a cross-sectional view taken along the line I-I ′ of FIG. 14A.

FIG. 15 is a cross-sectional view showing a step of forming a first-layer gate electrode according to the third embodiment.

FIG. 16A is a plan view showing the element isolation process of the third embodiment.

16B is a cross-sectional view taken along the line I-I ′ of FIG. 16A.

FIG. 17 is a cross-sectional view showing a step of separating the gate electrode according to the third embodiment.

FIG. 18A is a plan view showing a step of forming a second-layer gate electrode according to the third embodiment.

18B is a cross-sectional view taken along the line I-I ′ of FIG. 18A.

FIG. 19 is a cross-sectional view showing the interlayer insulating film forming step of the third embodiment.

FIG. 20 is a cross-sectional view showing a step of filling a contact plug according to the third embodiment.

FIG. 21A is a plan view of a principal portion of an LSI according to a fourth embodiment of the present invention.

21B is a cross-sectional view taken along the line I-I ′ of FIG. 21A.

FIG. 22 is a diagram for explaining a test method for a wafer on which a trench capacitor is formed.

FIG. 23 is a diagram showing one mode of a relationship between a chip size on a wafer and a capacitor region according to the present invention.

FIG. 24 is a diagram showing another mode of the relationship between the chip size on the wafer and the capacitor region according to the present invention.

[Explanation of symbols]

1 ... 1st silicon substrate, 2 ... 2nd silicon substrate, 1
DESCRIPTION OF SYMBOLS 1 ... Trench, 12 ... Capacitor insulating film, 13 ... Terminal electrode (storage electrode), 14, 15 ... Insulating film, 21 ... Element formation region, 22 ... Element isolation insulating film, 23 ... Gate electrode, 2
4, 25 ... N-type diffusion layer, 26 ... Storage electrode plug, 27 ...
Contact plug, 28 ... Gate insulating film, 29 ... Embedded wiring for substrate bias, 30, 31 ... Interlayer insulating film, 32
… Bit lines, 33… Wiring, C… Trench capacitors, Q
M, QS ... MISFET.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hidemi Ishiuchi             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Ichiro Mizushima             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Yoshitaka Tsunashima             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office F term (reference) 5F083 AD02 AD03 AD17 GA03 JA04                       JA06 JA19 JA53 MA03 MA06                       MA17 MA20 NA01 PR36 PR39                       PR40 PR43 PR44 PR45 PR53                       PR54 PR55 ZA12 ZA28

Claims (15)

[Claims] 1. A first semiconductor substrate, a plurality of first semiconductor elements formed on the first semiconductor substrate, and an insulating layer covering the first semiconductor element on the first semiconductor substrate. A plurality of second semiconductor substrates adhered to each other, and a plurality of second semiconductor substrates are formed on the second semiconductor substrate, each of which penetrates the insulating layer and is connected to a corresponding first semiconductor element in the first semiconductor substrate. And a second semiconductor element, and a semiconductor integrated circuit device. 2. The first semiconductor element is a trench capacitor, and the second semiconductor element is a MISFET connected to a terminal electrode of a corresponding trench capacitor to form a DRAM cell together with the trench capacitor. The semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 2, wherein a logic circuit is formed on the second semiconductor substrate around the cell array in which the DRAM cells are arranged. 4. The semiconductor integrated circuit device according to claim 3, wherein a trench capacitor not used for a DRAM cell is arranged outside the entire circumference of the cell array on the first semiconductor substrate. 5. The semiconductor integrated circuit according to claim 3, wherein a gap is provided between the trench capacitor not used for the cell array in the first semiconductor substrate and the second semiconductor substrate. apparatus. 6. The trench capacitors are arranged in a matrix on the first semiconductor substrate, and the second semiconductor substrate has an element formation region defined by an element isolation insulating film so as to extend over two trench capacitor regions. In each element formation region, two gate electrodes connected to a word line, a common drain connected to a bit line, and a source connected to a terminal electrode of a corresponding trench capacitor penetrating the insulating layer are provided. MIS
The semiconductor integrated circuit device according to claim 2, wherein a FET is formed. 7. The semiconductor integrated circuit device according to claim 2, wherein the MISFET is a planar MISFET having an upper surface of the second semiconductor substrate as a channel region. 8. The planar MISFET is characterized in that a source and a terminal electrode of a trench capacitor corresponding to the source are connected by a storage electrode plug buried penetrating the source and the insulating layer thereunder. The semiconductor integrated circuit device according to claim 7. 9. The MISFET has a sidewall of a trench formed in the second semiconductor substrate as a channel region,
Vertical M having a gate electrode embedded in the trench
The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is an ISFET. 10. The vertical MISFET is embedded in the insulating layer before bonding the second semiconductor substrate and is connected to a terminal electrode of the trench capacitor from a storage electrode plug of the second semiconductor substrate. 10. The semiconductor integrated circuit device according to claim 9, further comprising a source formed by impurity diffusion to the bottom and a drain formed by impurity diffusion from the upper surface of the second semiconductor substrate. 11. An interlayer isolation film, which covers the second semiconductor element of the second semiconductor substrate, is connected to the first semiconductor substrate through an element isolation region of the second semiconductor substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein a substrate bias wiring is formed. 12. A step of forming a plurality of trench capacitors on a first semiconductor substrate, and a step of adhering a second semiconductor substrate to the first semiconductor substrate having the trench capacitors formed thereon via an insulating layer, Forming a MISFET forming a DRAM cell array on the second semiconductor substrate and a MISFET for a logic circuit arranged around the DRAM cell array region; and forming a diffusion layer of each MISFET in the DRAM cell array region with a corresponding trench capacitor. A step of penetrating the diffusion layer and the insulating layer immediately thereunder so as to be connected to a terminal electrode, and burying a storage electrode plug to form the storage electrode plug. 13. A step of forming a plurality of trench capacitors on a first semiconductor substrate, a step of forming an insulating layer on the first semiconductor substrate having a trench capacitor formed thereon, and each trench capacitor on the insulating layer. A step of embedding a storage electrode plug connected to the terminal electrode of, a step of adhering a second semiconductor substrate on the insulating layer in which the storage electrode plug is embedded, a DRAM cell array region of the second semiconductor substrate, A source formed at the bottom of the second semiconductor substrate by impurity diffusion from the storage electrode plug, a buried gate electrode embedded in a trench formed in the second semiconductor substrate, and a second semiconductor substrate And a step of forming a plurality of vertical MISFETs having drains formed on an upper surface thereof. The method of production. 14. A MISFET of a logic circuit in the periphery of a DRAM cell array shares a plane gate electrode connected to an embedded gate electrode of a vertical MISFET and becomes a word line and a diffusion process of a drain to share a plane MISFE.
14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the semiconductor integrated circuit device is formed as T. 15. The step of forming a plurality of trench capacitors comprises: forming a plurality of trenches in the first semiconductor substrate; and forming a capacitor insulating film on an inner wall of each trench, and then forming the first semiconductor. Depositing a terminal electrode layer on a substrate, applying a voltage between the terminal electrode layer and the back surface of the first semiconductor substrate to perform a pass / fail test of the capacitor insulating film, and the terminal electrode layer 14. The method for manufacturing a semiconductor integrated circuit device according to claim 12, further comprising the step of etching back to embed the terminal electrodes separated for each trench.