JP2003018190A - Atm communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of connections of UTOPIA buses for connecting an ATM layer device to a PHY layer device. SOLUTION: Each control signal of a UTOPIA bus 2, for connecting an ATM layer device 1 to a PHY layer device 3, is shared by reception side processing and transmission side processing, and the transmission side processing and the reception side processing are switched alternately through time-division. In this case, the switching timing of PHY output enable to disable and the switching timing of ATM output disable to enable are executed respectively, at the rising and falling of a clock with a fixed time interval, far avoiding collision of the mutual output signals at switching.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ATM (Asynchronous).
nous Transfer Mode: A method to connect a plurality of physical (PHY) layer functions with an asynchronous transfer mode layer function, UTOPIA specified by the ATM Forum.
(Universal Test & Operations Physical Interface f
or ATM) level 2 interface (hereinafter referred to as UTOPIA bus).

[0002]

2. Description of the Related Art UTOPIA interface means AT
It is an interface inside the ATM communication control device proposed in the M Forum, and connects the ATM layer device and the PHY layer device.

According to the regulations of the ATM Forum, an address is defined for each port (transmission line) of the PHY layer, and the ATM layer performs a handshake on the transfer availability of cells using the address to a plurality of PHY layers. The cell transfer processing is performed based on

AT using such a UTOPIA bus
FIG. 4 shows an example of a conventional ATM communication control device that establishes a connection between an M layer device and a PHY layer device.

In the conventional ATM communication control device shown in FIG. 4, a PHY layer device 43 and an ATM layer device 41 are internally connected by a UTOPIA bus 42.

As signals for the UTOPIA bus 42,
The reference clock signal (Clk) is 1 bit, the Addr signal indicating the port of the PHY layer device 43 is 5 bits as a signal for handshake, and Clav which responds the cell transfer enable / disable state of the port specified by the Addr signal.
The signal is 1 bit, and the Enb signal for instructing cell transfer from the ATM layer device 41 is 1 bit. As a signal for actually transferring the main signal, the Data signal for transferring the main signal is 8 bits, the Pty signal indicating the parity of the main signal is 1 bit, and the SO indicating the first byte of the main signal is SO.
The C signal has 1 bit, and a total of 18 bits form a set of UTOPIA buses. Then, transmission side processing (hereinafter, Tx processing), reception side processing (hereinafter, Rx processing)
Since one set of buses is required for each processing), 36 bits are required for the UTOPIA bus 42.

Here, the Tx processing means a transmission processing from the in-device interface to the transmission path, and the Rx processing means a reception processing from the transmission path to the in-device interface.

The processing performed via the UTOPIA bus 42 is roughly classified into two processings, a polling processing and a cell transfer processing. What is polling process?
ATM layer device 41 is PHY layer device 43
Is a process for inquiring about the cell transfer availability. In addition, the cell transfer processing means the PHY layer device 4
3 transfers data received from the transmission path to the ATM layer device 41, and the ATM layer device 41
Is a process of transferring data received from the device interface to the PHY layer device 43.

Next, the polling process and the cell transfer process in this conventional ATM communication control device will be described with reference to the sequence chart shown in FIG.

First, from the ATM layer device 41 to PH
The Y layer device 43 is inquired by the Addr signal as to whether or not cell transfer is possible (step 101). The PHY layer device, which has received the inquiry of the cell transfer availability, responds to the inquiry of the cell transfer availability by the clav signal (step 102). The above-described polling processing is configured by the processing of steps 101 and 102.

Next, the ATM layer device 41 is
The PHY layer device 4 sends a cell transfer instruction using the b signal.
3 (step 103). Then, after the cell transfer instruction is issued, the cell transfer is executed by the Data / Pty signal and the SOC signal (step 104). Here, in the case of Tx processing, cell transfer is performed from the ATM layer device 41 to the PHY layer device 43, and in the case of Rx processing, cell transfer is performed from the PHY layer device 43 to the ATM layer device 41. . The above-described cell transfer processing is configured by the processing of steps 103 and 104.

As described above, in the conventional ATM communication control device, the polling process and the cell transfer process are sequentially performed in each of the Tx process and the Rx process. That is, in the Tx process, Tx polling process → Tx cell transfer process → Tx polling process → Tx cell transfer process → ... are performed in order, and in the Rx process, Rx polling process → R.
The x cell transfer process-> Rx polling process-> Rx cell transfer process-> ...

However, such a UTOPIA level 2
In the conventional ATM communication control device having an interface using, at least two sets of buses, that is, 36 bits are required as the UTOPIA bus 42 for connecting the PHY layer device 43 and the ATM layer device 41,
In such an ATM communication control device, when the PHY layer device 43 and the ATM layer device 41 are each configured as an integrated circuit, there is a problem in that the number of terminals increases and the outer shape does not become smaller. In addition, the number of wires on the printed wiring board on which this integrated circuit is mounted increases, and
It was also a factor that hinders the downsizing of the M communication control device.

In particular, when connecting an ATM layer function and a plurality of PHY layer functions, the number of UTOPIA buses connected becomes enormous, which is a major factor preventing the miniaturization of the device.

[0015]

SUMMARY OF THE INVENTION The conventional ATM described above.
In the communication control device, there is a problem in that downsizing of the device is hindered because the number of UTOPIA buses for connecting the ATM layer device and the PHY layer device is large.

An object of the present invention is to provide an ATM communication control device capable of reducing the number of UTOPIA buses for connecting an ATM layer device and a PHY layer device.

[0017]

In order to achieve the above object, the ATM communication control apparatus of the present invention comprises a UTOPIA bus for transmitting ATM cells, and an input signal from a transmission line in the receiving side processing. Perform PHY layer termination and
The AT that outputs the TM cell to the UTOPIA bus and receives it through the UTOPIA bus in the transmission side processing.
In the PHY layer device that transfers the M cell to the transmission path frame and outputs it to the transmission path,
The ATM cell from the PHY layer device is transferred to the UT
The process of receiving via the OPIA bus, multiplexing the PHY layer, and transferring to the in-device interface is performed. In the transmitting side process, the in-device interface is transferred to the UTOPIA bus and A is transferred to each PHY layer.
A having an ATM layer device for separating TM cells
In the TM communication control device, the UT connecting between the ATM layer device and the PHY layer device
Each control signal of the OPIA bus is shared by the reception process and the transmission process, and the transmission side process and the reception side process are alternately performed in a time division manner.

According to the present invention, by switching the processing on the receiving side and the transmitting side in a time division manner, the signals on the receiving bus and the transmitting bus of the UTOPIA are made common, and bidirectional cell transfer is performed, whereby the device It is possible to reduce the number of terminals and the number of wires on the printed wiring board.

Another ATM communication controller of the present invention is an AT.
A UTOPIA bus for transmitting M cells, and a PHY layer termination of an input signal from the transmission line in the receiving side processing, and an ATM cell is output to the UTOPIA bus, and in the transmitting side processing, the UTOPIA bus is used. And a plurality of PHY layer devices that transfer the received ATM cells to a transmission path frame and output them to the transmission path, and in the receiving side processing, receive the ATM cells from the PHY layer device via the UTOPIA bus. P
The HY layer is multiplexed, and the process of transferring to the in-device interface is performed. In the transmission side process, the in-device interface is transferred to the UTOPIA bus and the ATM layer device for separating the ATM cell into each of the PHY layers. In the ATM communication control device having, each control signal other than the address signal of the UTOPIA bus connecting the ATM layer device and the PHY layer device is shared by the reception process and the transmission process, and It is characterized in that the processing on the receiving side is alternately performed in a time division manner.

According to the present invention, even when the ATM layer device and the PHY layer device are connected in a one-to-many manner, the reception bus and the transmission bus of the UTOPIA can be switched by switching the processing on the reception side and the transmission side by time division. By making signals other than the address signal common and performing bidirectional cell transfer, it is possible to reduce the number of terminals of the device and the number of wirings of the printed wiring board.

Further, in another ATM communication control apparatus of the present invention, the processing of alternately performing the transmission side processing and the reception side processing in time division is performed by the ATM layer device in the transmission side processing.
Polling processing for inquiring whether or not cell transfer is possible to the HY device, cell transfer processing for transferring ATM cells between the ATM layer device and PHY device in receiving side processing, cell transfer in transmitting side processing This is a process in which the process and the polling process in the receiving process are alternately switched in synchronization with each other.

Further, in another ATM communication control device of the present invention, when switching between the transmitting side processing and the receiving side processing,
A certain time interval is provided.

According to the present invention, even if the timing of switching between the transmission side processing and the reception side processing is deviated due to the influence of the delay inside each of the ATM layer device and the PHY layer device, the collisions of the control signals are prevented. It can be avoided without fail.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the arrangement of an ATM communication control apparatus according to the first embodiment of the present invention. In the ATM communication control device of this embodiment, the PHY
Layer device 3 and ATM layer device 1 are UTOP
It is connected by the IA bus 2. In this embodiment, the PH
This is a case where there is one Y layer device 3 and two transmission / reception ports.

In the ATM communication control apparatus of this embodiment, as shown in FIG. 1, the AT which is the master of UTOPIA.
M layer device 1, P that is a slave of UTOPIA
The HY layer device 3 has only one set of UTOPIA terminals, and respective signals are connected as shown in FIG.

Specifically, the PHY layer device 3 and A
Clk signal, Addr signal of TM layer device 1,
Clav signal, Enb signal, Data / Pty signal, S
Connect OC signals respectively. These signals in the present embodiment are common without any distinction between Tx and Rx.

The receiving side processing (Rx processing) performs PHY layer termination for two ports of the input signal from the transmission line, and
A PHY layer device 3 that outputs cells to the UTOPIA bus 2 having a bidirectional communication configuration, and an ATM cell from the PHY layer device 3 are received via the UTOPIA bus 2.
This is performed by the ATM layer device 1 that multiplexes the PHY layer and transfers it to the in-device interface.

In the transmission side processing (Tx processing), the device internal interface is transferred to the UTOPIA bus 2, and each P
A PHY that receives an ATM cell by the ATM layer device 1 that separates an ATM cell into the HY layer and the UTOPIA bus 2, transfers the ATM cell to the transmission path frame, and outputs it to the transmission path
It is performed by the layer device 3.

The UTOPIA bus 2 has a bidirectional bus structure which can be used by both the transmitting side and the receiving side. In this embodiment, the address of the receiving side of the transmission path port 1 is set to Addr.
= 1, the address of the transmitting side is Addr = 3, the address of the receiving side of the transmission line port 2 is Addr = 2, and the address of the transmitting side is Addr = 4. In the UTOPIA bus 2 shown in the timing chart of FIG. The polling process and the cell transfer process are performed.

Next, the operation of the ATM communication control apparatus of this embodiment will be described in detail with reference to the drawings.

In the ATM communication control device of the present embodiment, one phase (1
Cell processing time), the polling process and the cell transfer process via the UTOPIA bus 2 alternately perform the Tx phase, which is the transmission side process, and the Rx phase, which is the reception side process.

As shown in FIG. 5, the Addr signal and the Clav signal are used in the polling process, and the Enb signal, the Data / Pty signal, and the SOC signal are used in the cell transfer process.
The cell transfer process in the Rx process is simultaneously performed in one phase, and in the next phase, the cell transfer process in the Tx process and the polling process in the Rx process are simultaneously performed. That is, in the Tx process and the Rx process, the polling process and the cell transfer process are alternately performed in a time division manner.

The ATM layer device 1 inquires of the PHY layer device 3 whether or not cell transfer is possible at the timing of Addr of the Addr signal. The PHY layer device 3 sets the transfer enable / disable state ('1' = transfer possible) of the port number designated at the timing of 1F of the Addr signal,
It responds to the ATM layer device 1 with a Clav signal. A
At the end of the phase of the polling process, the TM layer device 1 determines the transfer availability status of each port, and adds the addresses 30, 31, 32 for cell transfer to Add for cell transfer.
It is output at the timing designated by r, and the Enb signal is enabled at the next Clk timing.

In the case of the Rx phase of the cell transfer process, the cell of the port corresponding to the address 30 output at the timing specified by Addr for cell transfer is set to Data / Pty.
PHY layer device 3 for outputting signals and SOC signals
And is received by the ATM layer device 1.

In the case of the Tx phase of the cell transfer process, the cell of the port corresponding to the address 31 output at the timing of Addr for cell transfer is set to Data / Pt.
The y signal and the SOC signal are output from the ATM layer device 1 and received by the PHY layer device 3.

When various control signals are shared by Tx processing and Rx processing as in the present embodiment, the directions of the signals output to one signal line are bidirectional. Therefore, the signal in the direction from the PHY layer device 3 to the ATM layer device 1 and A
A process for switching signals in the direction from the TM layer device 1 to the PHY layer device 3 without collision is required. When processing is performed such that the PHY output enable is disabled and the ATM output disable is enabled at the same change point of the Clk signal, the switching timing is deviated due to the influence of the delay inside each device, PHY disable state and AT
There is a possibility that the M-disabled states will overlap and the outputs will collide. Therefore, it is necessary to provide a certain distance between the PHY disable and the ATM enable to reliably avoid the collision.

Specifically, in the cell transfer processing, in order to avoid a bus collision at the transition point from the Rx phase to the Tx phase or at the transition point from the Tx phase to the Rx phase, T
Data / Pty signal and S during x cell transfer phase
Bus collision avoidance processing is performed by outputting the OC signal at the falling edge of the Clk signal (time t ₁ ).
As a result, PHY disable processing and ATM
A gap will be provided between the enabling process and the collision of the output signals with each other with certainty.

As described above, in the present embodiment, by switching the processing on the receiving side and the transmitting side in a time division manner, the signals of the reception bus and the transmission bus of UTOPIA are made common, and bidirectional cell transfer is performed. By doing so, it is possible to reduce the number of terminals of the device and the number of wirings of the printed wiring board.

(Second Embodiment) Next, an ATM communication control apparatus according to a second embodiment of the present invention will be described.

ATM of the first embodiment shown in FIG.
In the communication control device, both the ATM layer device 1 and the PHY layer device 2 that are different from the conventional ones are used, and the ATM layer device 1 and the PHY layer device are connected one-to-one. A of this embodiment
As shown in FIG. 3, the TM communication control device uses the conventional PHY layer devices 23 to 28 which are generally used.
An embodiment in the case of using one and one PHY device = 1 transmission line is shown. In this case, in the PHY layer devices 23 to 28 that are generally used, the UTOPIA terminals are separated on the transmission side (Tx) and the reception side (Rx), and the transmission path addresses on the transmission side and the reception side are the same. You are using an address. Therefore, if the Addr signals are multi-connected on both the transmitting side and the receiving side as in the first embodiment shown in FIG. 1, it is not possible to distinguish the transmission paths of the transmitting side and the receiving side.

In FIG. 3, Add of the ATM layer device is added.
r output is RxAddr × 5 bits, TxAddr × 5
It has bits and R of PHY layer devices 23 to 28 respectively.
Multi-connect to the xAddr [4: 0] and TxAddr [4: 0] terminals. Other UTOPIA terminal connections are multi-connections for all PHY devices 23 to 28 as in FIG.

Switching between the polling process and the cell transfer process in the ATM communication control device of this embodiment is performed by the same process as the timing chart shown in FIG.

According to the ATM communication control apparatus of this embodiment, TxAddr and Rx on the ATM layer device 21 side are provided.
Separating the Addr distinguishes the sender from the receiver,
By sharing the signal lines other than Addr, it is possible to reduce the number of terminals of the device and the number of wirings of the printed wiring board.

[0045]

As described above, according to the present invention,
By switching the processing on the receiving side and the transmitting side in a time-sharing manner, the signals on the reception bus and the transmission bus of UTOPIA are made common, and bidirectional cell transfer is performed to reduce the number of device terminals and wiring of the printed wiring board. The effect is that the number can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an ATM communication control device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the ATM communication control device of FIG.

FIG. 3 is a block diagram showing a configuration of an ATM communication control device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional ATM communication control device.

5 is a sequence chart for explaining a polling process and a cell transfer process in the conventional ATM communication control device shown in FIG.

[Explanation of symbols]

1 ATM layer device 2 UTOPIA buses 3 PHY layer device 21 ATM layer device 22 UTOPIA Bus 23-28 PHY layer device 30 to 32 addresses 41 ATM layer device 42 UTOPIA Bus 43 PHY layer device 101-104 steps

Claims (4)

[Claims] 1. UTOP for transmitting ATM cells
The IA bus and the PHY layer termination of the input signal from the transmission line in the receiving side processing are performed, the ATM cells are output to the UTOPIA bus, and the ATM cells received via the UTOPIA bus are transmitted in the transmitting side processing. A PHY layer device that transfers the frame to a frame and outputs it to the transmission path, and in the receiving side processing, an ATM cell from the PHY layer device is received via the UTOPIA bus to multiplex the PHY layer, and an in-device interface is provided. In the ATM communication control device having an ATM layer device for separating the ATM cell into each PHY layer by transferring the in-device interface to the UTOPIA bus in the transmission side process, the ATM layer Between the device and the PHY layer device Have been shared control signals of the UTOPIA bus connection is by the transmission processing and the reception processing, ATM communication control device which comprises carrying out alternately receiving process and time division transmission side processing. 2. UTOP for transmitting ATM cells
The IA bus and the PHY layer termination of the input signal from the transmission line in the receiving side processing are performed, the ATM cells are output to the UTOPIA bus, and the ATM cells received via the UTOPIA bus are transmitted in the transmitting side processing. A plurality of PHY layer devices that transfer the frames and output to the transmission path, and in the receiving side processing, receive ATM cells from the PHY layer devices via the UTOPIA bus to perform PHY layer multiplexing, and In an ATM communication control device having a process of transferring to an internal interface, and in the transmitting side process, an ATM layer device for transferring the internal device interface to the UTOPIA bus and separating an ATM cell into each of the PHY layers, ATM layer device and the PHY layer device Each of the control signals other than the address signal of the UTOPIA bus connecting between them is shared by the reception process and the transmission process, and the transmission side process and the reception side process are alternately performed in a time division manner. Communication control device. 3. A process for alternately performing a transmission side process and a reception side process in a time division manner, a polling process for inquiring whether or not a cell transfer is possible from an ATM layer device to a PHY device in the transmission side process, and a reception process. The cell transfer processing for transferring ATM cells between the ATM layer device and the PHY device in the side processing, the cell transfer processing in the transmission side processing, and the polling processing in the reception side processing are switched alternately in synchronization with each other. The ATM communication control device according to claim 1, which is a process to be performed. 4. The method according to claim 1, wherein a fixed time interval is provided when switching between the transmitting side processing and the receiving side processing.
5. The ATM communication control device according to any one of 1 to 3.