JP2003008015A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a power semiconductor device in which the capacitance and feedback capacitance of a gate electrode are small, the switching speed is relatively fast, and the ON resistance is relatively low. A semiconductor surface layer having a higher resistance than a semiconductor substrate of a first conductivity type and formed on a surface of the semiconductor substrate.
A diffusion layer 150 of the first conductivity type selectively formed on the semiconductor surface layer, a source electrode 114 connected to the diffusion layer,
A drain electrode 190 formed on the back surface of the semiconductor substrate;
A trench 182 formed between the diffusion layers adjacent to each other with a channel portion 160 therebetween; a first offset layer 186 of a first conductivity type formed around the trench in the semiconductor surface layer having a lower resistance than the semiconductor surface layer; Formed from over the first offset layer to over the diffusion layer via the gate insulating film formed on the surface of the semiconductor surface layer, and around the opening of the trench so as not to overlap the trench. Gate electrode 180.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a power semiconductor device and a method for manufacturing the power semiconductor device.

[0002]

2. Description of the Related Art Conventionally, electronic devices such as personal computers and information communication devices may be equipped with a power supply incorporating a DC-DC converter or the like.
In recent years, electronic devices have become smaller and smaller, their drive voltage has decreased, and their drive current has increased. with this,
A power supply capable of efficiently flowing a large current and capable of supporting a high frequency is desired.

In order to allow a large current to flow at a low voltage, the lower the ON resistance of the power semiconductor element used for the power source, the better.
Further, in order to cope with high frequencies, it is necessary for the power semiconductor elements used for the power supply to switch at higher speed.

Further, conventionally, a Schottky diode is generally used for rectification in a power supply.
In recent years, power semiconductor devices have been used for rectification instead of Schottky diodes in order to be able to carry large currents at low voltages. Therefore, in addition to the switching power semiconductor element for switching between the input and output of the power supply, a rectifying power semiconductor element for rectifying current is required. Such a power source is called a synchronous rectifier circuit type power source because the rectifying power semiconductor element switches in synchronization with the switching of the switching power semiconductor element.

[0005]

FIG. 15 is a circuit diagram of a DC-DC converter 2000 used in a typical synchronous rectification circuit type power supply. Rectifying power semiconductor element 2
Since 010 and the switching power semiconductor element 2020 are operated in synchronization, it is preferable that both can be switched at high speed. Further, the rectifying power semiconductor element 2010 and the switching power semiconductor element 202
0 is preferable as the ON resistance is low, because a large current flows in both cases. Therefore, in the DC-DC converter 2000 of the synchronous rectification circuit system, the switching power semiconductor element 2020
Further, it is more desired to improve the ON resistance of the rectifying power semiconductor element 2010 such as a lower resistance and a faster switching speed.

Also, for example, the switching power semiconductor element 2
An inductance 2050 may be connected between the source electrode 2030 of 020 and the output 2040 of the DC-DC converter. Switching the power supply to which the inductance is connected from ON to OFF or from OFF to ON is generally called L load switching.

When the switching power semiconductor element 2020 is on, the potential difference between the drain electrode 2060 and the source electrode 2030 is close to zero. In addition, electric energy is stored in the inductance 2050.

On the other hand, the switching power semiconductor element 2020
When is switched from ON to OFF, the connection between the drain electrode 2060 and the source electrode 2030 is broken. Further, since the inductance 2050 tries to maintain the current when the switching power semiconductor element 2020 is ON, the potential of the source electrode 2030 decreases. At this time, the rectifying power semiconductor element 2010 is turned on,
Current is supplied to output 2040 through rectifying power semiconductor element 2010 and inductance 2050.

FIG. 16 is an enlarged sectional view of a conventional power semiconductor device 1000 used for a synchronous rectification circuit type power supply. The power semiconductor element 1000 can be used as both a rectifying power semiconductor element and a switching power semiconductor element. The conventional power semiconductor device 1000 has, for example, a semiconductor substrate 1 on the surface of an n ⁺ type semiconductor substrate 1010.
The semiconductor surface layer 1020 has a lower resistance than 010.
The semiconductor surface layer 1020 has p-type base layers 1030, 1
031 is selectively formed. Further, in the base layers 1030 and 1031 of the semiconductor surface layer 1020, the contact layers 1040 and 1041 and the contact layers 1040 and 1010 connected to the base layers 1030 and 1031, respectively.
Source layers 1050 and 1051 respectively adjacent to 41 are selectively formed. In the vicinity of the surface of the semiconductor surface layer 1020, channel portions 1060 and 1061 are formed in the base layers 1030 and 1031 and between the source layers 1050 and 1051 and the semiconductor surface layer 1020, respectively. Further, a drain electrode 1090 is formed on the back surface of the semiconductor substrate 1010 so as to be connected to the semiconductor substrate 1010.

A gate electrode 1080 is formed on the surface of the semiconductor surface layer 1020 via a gate insulating film 1070. The gate electrode 1080 extends from the source layer 1050, the channel portion 1060, the semiconductor surface layer 1020, and the channel portion 1061 to the source layer 1051. The gate electrode 1080 is covered with a silicon oxide film 1012, and the silicon oxide film 1012 is covered with a source electrode 1014.

In general, when the length Lg of the gate electrode 1080 is longer, the area of the gate electrode 1080 facing the semiconductor surface layer 1020 through the gate insulating film 1070 becomes larger accordingly, so that the gate electrode 1080 remains static. The electric capacity becomes larger. In particular, the semiconductor surface layer 10 in which the gate electrode 1080 faces the gate insulating film 1070
The capacitance (hereinafter, referred to as "feedback capacitance") between the facing region 1025 of 20 (the region shown by the arrow in FIG. 16) and the gate electrode 1080 becomes larger. When the electrostatic capacitance and the feedback capacitance of the gate electrode 1080 become large, the time for raising or lowering the voltage of the gate electrode 1080 for switching becomes long and the switching loss becomes large. Therefore, the switching speed of the power semiconductor device 1000 slows down and the switching loss increases, so that the conversion efficiency decreases.

However, in the power supply of the synchronous rectification circuit system, not only the power semiconductor element for switching but also the power required for driving the gate of the power semiconductor element for rectification must be reduced. Therefore, it is desirable that the capacitance and the feedback capacitance of the gate electrode 1080 are smaller. In general, the feedback capacitance of the capacitance of the gate electrode 1080 has a great influence on the switching speed and the switching loss.
Therefore, in order to reduce the feedback capacitance of the gate electrode 1080, it is conceivable to further reduce the area where the gate electrode 1080 and the facing region 1025 face each other (hereinafter, referred to as “facing area”).

In order to reduce the facing area, it is conceivable to shorten the distance between the base layer 1030 and the base layer 1031 which are adjacent to each other. When the distance between the base layer 1030 and the base layer 1031 is shortened, the channel portion 1
The channel length of 060 expands and the facing region 1025 narrows.

The increase in the channel length causes a problem that the ON resistance of the power semiconductor device 1000 increases. When the facing region 1025 becomes narrow, the current flowing from the semiconductor substrate 1010 to the channel portion 1060 becomes difficult to pass through the facing region 1025. This causes a problem that the ON resistance of the power semiconductor device 1000 becomes high.

As the distance between the base layer 1030 and the base layer 1031 is shortened, the distance between the source layer 1050 and the source layer 1051 adjacent to each other is shortened, whereby the spread of the channel length can be avoided. . Also,
Since the element pitch Lp becomes short, the power semiconductor device 100
0 becomes smaller. Therefore, it is preferable to shorten the distance between the source layer 1050 and the source layer 1051 which are adjacent to each other as the distance between the base layer 1030 and the base layer 1031 is shortened.

However, the problem that the ON resistance becomes high due to the narrowing of the facing region 1025 still remains.

On the other hand, if the facing region 1025 is kept wide in order to reduce the ON resistance of the power semiconductor device 1000, the facing area becomes large.

Therefore, conventionally, by reducing the facing area, the capacitance and the feedback capacitance of the gate electrode 1080 are reduced, the switching speed of the power semiconductor device 1000 is increased, the switching loss is reduced, and the facing region is reduced. There is a trade-off relationship with decreasing the ON resistance of the power semiconductor device 1000 by increasing 1025.

Therefore, an object of the present invention is to reduce the electrostatic capacitance of the gate electrode and the feedback capacitance between the facing region and the gate electrode, that is, the switching speed is relatively fast and ON.
An object is to provide a power semiconductor device having a relatively low resistance.

[0020]

A semiconductor device according to an embodiment of the present invention is a semiconductor substrate, a semiconductor surface layer formed on the surface of the semiconductor substrate, and a cross section of the semiconductor surface layer. A plurality of diffusion layers of the first conductivity type formed on, one of a source electrode or a drain electrode connected to the plurality of diffusion layers, and one of a source electrode or a drain electrode formed on the back surface of the semiconductor substrate. On the other hand, a channel portion in which a channel is formed between adjacent diffusion layers so as to connect to the diffusion layer, and a trench formed between adjacent diffusion layers with at least the channel portion separated from the diffusion layer. , Which has a resistance lower than that of the semiconductor surface layer and is formed on the semiconductor surface layer around the trench.
The first offset layer of conductivity type and the gate insulating film formed on the surface of the semiconductor surface layer reach from the first offset layer to the diffusion layer and do not overlap the trench. And a gate electrode formed around the opening of the trench.

The semiconductor substrate is the first conductivity type, the semiconductor surface layer is the second conductivity type or the first conductivity type having a higher resistance than the semiconductor substrate, the diffusion layer is the source layer, and the source layer has the source electrode. It is preferable that a drain electrode is formed on the back surface of the semiconductor substrate, which is connected.

The depth of the trench may be such that it penetrates the semiconductor surface layer and reaches the semiconductor substrate. In this case, the first offset layer is formed from the surface of the semiconductor surface layer to the semiconductor substrate through the semiconductor surface layer.

The semiconductor surface layer may be of the first conductivity type, and the trench may be formed to a depth up to an arbitrary position in the semiconductor surface layer without penetrating the semiconductor surface layer.
In this case, the offset layer is formed from the surface of the semiconductor surface layer to the bottom of the trench.

Further, the semiconductor device further comprises a second offset layer of the second conductivity type which is formed around the first offset layer from the surface of the semiconductor surface layer to the semiconductor substrate through the semiconductor surface layer to a semiconductor substrate and has a lower resistance than the semiconductor surface layer. May be. In this case, the depth of the trench is a depth that penetrates the semiconductor surface layer and reaches the semiconductor substrate, and the first offset layer is formed from the surface of the semiconductor surface layer to the semiconductor substrate through the semiconductor surface layer.

The drain electrode, the source layer, the first offset layer, the second offset layer and the gate electrode are provided at substantially symmetrical positions with respect to the center of the trench in the cross section of the semiconductor device and have substantially symmetrical shapes. It is preferable to be molded.

In the method for manufacturing a semiconductor device according to the embodiment of the present invention, a semiconductor surface layer of the first conductivity type or the second conductivity type having a higher resistance than that of the semiconductor substrate of the first conductivity type is formed on the surface of the semiconductor substrate. Step, an insulating film forming step of forming an insulating film on the semiconductor surface layer, a gate material forming step of forming a conductive gate material on the insulating film, and a gate material, an insulating film and a semiconductor surface layer according to a predetermined pattern. A step of forming a trench in the semiconductor surface layer by continuously anisotropically etching, and a first implantation step of implanting an impurity of the first conductivity type into a sidewall of the trench in an oblique direction with respect to the sidewall. And a diffusion step of forming a first offset layer by diffusing a first conductivity type impurity.

After the step of forming the gate material, the step of etching the gate material according to a predetermined pattern to form the source layer in a self-aligned manner using the etched gate material, and the etching in the step of forming the trench, Forming a gate electrode, forming a source electrode connected to the source layer after the diffusion step, and forming a drain electrode on the back surface of the semiconductor substrate;
May be further included.

After the first implanting step, the method further includes a second implanting step of implanting a second conductive type impurity having a diffusion length different from that of the first conductive type impurity into the sidewall of the trench. Then, in a diffusion step, a first conductivity type impurity and a second conductivity type impurity are diffused to form a first conductivity type first offset layer on a sidewall of the trench. A second conductivity type second offset layer may be formed around the periphery.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The present embodiment does not limit the present invention. Further, in the semiconductor device according to the following embodiment of the present invention, the conductivity type of each element is changed even if the p-type element is changed to the n-type and the n-type element is changed to the p-type. The effect of is not lost.

FIG. 1 is an enlarged sectional view of a power semiconductor device 100 according to the first embodiment of the present invention. According to the present embodiment, the power semiconductor device 100 has n ⁺
Type semiconductor substrate 110, an n-type semiconductor surface layer 120 having a higher resistance than the semiconductor substrate 110 and formed on the surface of the semiconductor substrate 110, a p-type source layer 150 and a source selectively formed on the semiconductor surface layer 120. The source layer between the layer 151, the source layer 150 and the source electrode 114 connected to the source layer 151, the drain electrode 190 formed on the back surface of the semiconductor substrate 110, and the source layer 150 and the source layer 151 adjacent to each other. Between the channel portion 160 and the channel portion 161 in which a channel is formed so as to be connected to the 150 and the source layer 151, respectively, and between the source layer 150 and the source layer 151 which are adjacent to each other,
A trench 182 formed by separating the source layer 150 and the source layer 151 from each other with at least the channel portion 160 and the channel portion 161 respectively, and an n-type formed around the trench 182 in the semiconductor surface layer 120 and having a resistance lower than that of the semiconductor surface layer 120. Of the offset layer 186 and the offset layer 189, and the gate insulating film 170 formed on the surface of the semiconductor surface layer 120, reaching the source layer 150 and the source layer 151 from the offset layer 186, respectively, and the trench 182. The gate electrode 180 and the gate electrode 181 are formed around the opening 188 of the trench 182 so as not to overlap each other.

In this embodiment, the base layer 130 and the base layer 131 are selectively formed on the semiconductor surface layer 120. The source layer 150 and the source layer 151 are
Each of the base layer 130 and the base layer 131 is selectively formed on the inner side thereof as a tab. Further provided are a contact layer 140 and a contact layer 141, which are connected to the source layer 150 and the source layer 151, respectively. Further, the source electrode 114 connected to the source layers 150 and 151 and the contact layers 140 and 141 is formed. The source electrode 114 is the gate insulating film 112 that covers the gate electrodes 180 and 181.
Is formed so as to cover the top.

For comparison with the conventional example, for convenience, the sizes, positions and concentrations of the base layers 130 and 131, the contact layers 140 and 141 and the source layers 150 and 151 are as follows.
Conventional base layers 1030, 1031 and contact layer 1
040, 1041 and source layers 1050, 1051 have the same size, position, and concentration.

The depth of the trench 182 according to the present embodiment is a depth that penetrates the semiconductor surface layer 120 and reaches the semiconductor substrate 110. Further, the offset layer 186 reaches the semiconductor substrate 110 from the surface of the semiconductor surface layer 120 through the semiconductor surface layer 120.

The impurity concentration of the offset layers 186 and 189 is higher than that of the semiconductor surface layer 120 and lower than that of the semiconductor substrate 110 and the source layers 150 and 151.

Inside the trench 182, the plug material 18
4 is filled. SiO ₂ as the plug material 184
Or epitaxially grown n ⁻ type or p ⁻ type silicon or the like is used.

The gate electrodes 180 and 181 are provided around the opening 188. Therefore, in the cross-sectional view of FIG. 1, the gap W appears between the gate electrodes 180 and 181.

FIGS. 2A and 2B are enlarged plan views of power semiconductor device 100 according to the first embodiment of the present invention. In this embodiment, the opening 188
(See FIG. 2A) is simply used as a groove, and the gate electrode 180,
Alternatively, the groove 188 may be divided into two by a groove 188 (see FIG. 2B). That is, as shown in FIG. 2A, when the gate electrode is provided with the opening 188, the gate electrodes 180 and 181 are not separated into two,
It is shaped like a ladder. On the other hand, when the groove 188 is provided in the gate electrode, the gate electrode is divided into two parts, each of which is independent and each of which is formed into a strip shape. Either the opening 188 or the groove 188 may be formed in the gate electrode. The sectional view taken along the line XX ′ in FIG. 2 (A) or FIG. 2 (B) corresponds to the sectional view in FIG. 1.

Next, the operation of the power semiconductor device 100 according to this embodiment will be described. Power semiconductor device 100
When the drain electrode 190 is turned off and the voltage is applied, the depletion layer is the semiconductor surface layer 120 and the base layer 1.
30 and 131 and the offset layers 186 and 189.

When the power semiconductor device 100 is turned on, a predetermined gate voltage is applied to the gate electrodes 180 and 181, so that the channel portions 160 and 161 are inverted. Thereby, a channel is formed and the source layer 15
0, 151 and the semiconductor surface layer 120 and the offset layer 18
A current flows between 6 and 189. Offset layer 18
Since the impurity concentration of 6, 189 is higher than that of the semiconductor surface layer 120, the current from the drain electrode 190 flows through the semiconductor substrate 110 through the offset layers 186, 189 toward the gate electrodes 180, 181. The current flows through the facing regions 125 and 126 below the gate electrodes 180 and 181, respectively, and flows to the source layers 150 and 151 and the source electrode 114 through the channels formed in the channel portions 160 and 161.

According to this embodiment, the base layer 130,
131, contact layers 140 and 141, and source layer 15
The sizes and positions of 0 and 151 are the same as those of the conventional base layers 1030 and 1031 and the contact layers 1040 and 1041.
And the source layers 1050 and 1051 have the same size and position. Therefore, the source layer 15 of the gate electrode 180
From the end on the 0 side, the source layer 151 of the gate electrode 181
The width Lg to the end on the side is almost the same as the width Lg of the gate electrode 1080 in the conventional example of FIG. Therefore, since the gap W is provided between the gate electrode 180 and the gate electrode 181, the area of the entire gate electrode facing the semiconductor surface layer 120 becomes smaller. Therefore, the capacitance of the gate electrode is smaller than that of the conventional example.

In this embodiment, the gap W '
Trench 182 is formed. Therefore, the facing region is formed from both side walls of the trench 182 to the base layers 130 and 131.
There will be two opposing regions 125, 126 between each up to. The sum of the areas of these two facing regions 125 and 126 is the facing area. Therefore, the feedback capacitance of the present embodiment is smaller than that of the conventional example by the amount of the trench 182 formed.

On the other hand, offset layers 186 and 189 having a lower resistance value than the semiconductor surface layer 120 are formed around the inner wall of the trench 182 in the semiconductor surface layer 120.
Therefore, current flows from the drain electrode 190 to the semiconductor substrate 1
Offset layer 186, 1 having a relatively low resistance
After passing through 89, it flows to the channel parts 160 and 161.
As a result, as the facing area decreases, the semiconductor device 100
It is possible to avoid an increase in the ON resistance of. Furthermore, the ON resistance of the semiconductor device 100 may be lowered as compared with the conventional example by increasing the impurity concentration of the offset layers 186 and 189 and lowering the resistance thereof. However, if the impurity concentration of the offset layers 186 and 189 is excessively increased, it becomes difficult for the depletion layer to spread in the offset layers 186 and 189. Therefore, the power semiconductor device 100 is OF
The breakdown voltage between the source and drain when set to F decreases. Therefore, the n-type impurity concentration of the offset layers 186 and 189 is preferably about 1 × 10 ¹² cm ⁻² to about 5 × 10 ¹² cm ⁻² .

In this embodiment, the gap W is almost equal to the gap W '. Thereby, as will be described later, according to the method of manufacturing the semiconductor device according to the present embodiment of the present invention, the power semiconductor device 100 can be easily manufactured. Further, in the sectional view of FIG. 1, the power semiconductor device 100 is formed substantially symmetrically with the center of the trench 182 as a boundary. Therefore, the respective constituent elements of the power semiconductor device 100 are provided at substantially symmetrical positions with the trench 182 as a boundary and are molded in a substantially symmetrical shape. As a result, the flow of current flowing through the power semiconductor device 100 becomes symmetrical. Therefore, since the electric field is not concentrated on a part of the power semiconductor device 100, the power semiconductor device 100 is not destroyed. In addition, the life of the power semiconductor device 100 is extended. Further, substantially the power semiconductor device 100
ON resistance decreases.

FIG. 3 is an enlarged sectional view of a power semiconductor device 200 according to the second embodiment of the present invention.

In the second to fifth embodiments,
Since the configuration on the left side of the trenches 282, 382, 482, 582 is symmetrical to the configuration on the right side of the trenches 282, 382, 482, 582, the trenches 282, 382,
Reference numerals of components on the left side of 482 and 582 are omitted.

Compared with the power semiconductor device 100 according to the first embodiment, the depth of the trench 282 of the power semiconductor device 200 according to the present embodiment is shallower than that of the trench 182, and the length of the offset layer 286 is equal to that of the offset layer 186.
Shorter. Therefore, the trench 282 and the offset layer 286 do not penetrate the semiconductor surface layer 220 and reach the semiconductor substrate 210. Therefore, in the power semiconductor device 200, the O
N resistance (JFET resistance) can be reduced.

On the other hand, below the trench 282 and the offset layer 286, there is a semiconductor surface layer 220 having a relatively low impurity concentration. Therefore, the depletion layer easily extends below the trench 282 and the offset layer 286. As a result, the breakdown voltage between the source and drain when the power semiconductor device 200 is OFF is higher than the breakdown voltage between the source and drain when the power semiconductor device 100 is OFF.

The power semiconductor device 100 and the power semiconductor device 200 may be selected according to the purpose of their use. For example, when importance is attached to the high breakdown voltage between the source and the drain, the power semiconductor device 200 may be selected.

FIG. 4 is an enlarged cross-sectional view of power semiconductor device 300 according to the third embodiment of the present invention.

Compared with the power semiconductor device 100 according to the first embodiment, the power semiconductor device 300 according to the present embodiment is different in using a p-type semiconductor surface layer 320. Therefore, due to the potential difference between the drain electrode 390 and the source electrode 314, the semiconductor surface layer 320
The depletion layer easily spreads from the offset layer 386 to the offset layer 386. As a result, the feedback capacitance between the gate electrode 380 and the facing region 325 becomes small. Therefore, the power semiconductor device 3
00 has a higher switching speed and smaller switching loss than the power semiconductor devices 100 and 200.

If the switching speeds comparable to those of power semiconductor device 100 and power semiconductor device 200 are sufficient, the impurity concentration of offset layer 386 can be increased. Thereby, the power semiconductor device 300 can further reduce the ON resistance as compared with the power semiconductor device 100 and the power semiconductor device 200.

FIG. 5 is an enlarged cross-sectional view of power semiconductor device 400 according to the fourth embodiment of the present invention.

The semiconductor surface layer 420 is p-type. further,
A p-type offset layer 487, which is formed around the offset layer 486 from the surface of the semiconductor surface layer 420 through the semiconductor surface layer 420 to the semiconductor substrate 410 and has a lower resistance than the semiconductor surface layer 420, is further provided.

The offset layer 487 has a higher impurity concentration than the semiconductor surface layer 420. Therefore, as compared with the power semiconductor device 300 according to the third embodiment, in the power semiconductor device 400 according to the present embodiment, the potential difference between the drain electrode 490 and the source electrode 414 causes the semiconductor surface layer 420 to be offset by the offset layer. The depletion layer is more easily spread to 486. As a result, the feedback capacitance between the gate electrode 480 and the facing region 425 is further reduced.
Therefore, the power semiconductor device 400 has a higher switching speed than the power semiconductor device 100, the power semiconductor device 200, and the power semiconductor device 300.

If a switching speed similar to that of power semiconductor device 100, power semiconductor device 200 or power semiconductor device 300 is sufficient, the impurity concentration of offset layer 486 can be increased. Therefore, the power semiconductor device 400 can further reduce the ON resistance as compared with the power semiconductor device 100, the power semiconductor device 200, and the power semiconductor device 300.

FIG. 6 is an enlarged sectional view of power semiconductor device 500 according to the fifth embodiment of the present invention. The power semiconductor device 500 is different from the power semiconductor device 400 according to the fourth embodiment of FIG. 5 in that an n-type semiconductor surface layer 520 is used. Therefore,
The depletion layer easily spreads from the semiconductor surface layer 520 to the offset layer 587 due to the potential difference between the drain electrode 590 and the source electrode 514. Thereby, the offset layer 5
The impurity concentration of 87 can be increased. Therefore, since the impurity concentration of the offset layer 586 can be increased, the power semiconductor device 500 can be used in the power semiconductor device 40.
Compared with 0, ON resistance can be further reduced.

FIG. 7 is an enlarged sectional view of power semiconductor device 700 according to the sixth embodiment of the present invention. It differs from the power semiconductor device 500 according to the fifth embodiment of FIG. 6 in that the source electrode 714 is formed on the back surface of the semiconductor substrate 710 and the drain electrode 790 is formed on the front surface of the semiconductor substrate 710.

Therefore, in power semiconductor device 700 according to the present embodiment, p ⁺ type semiconductor substrate 710, n type or p type semiconductor surface layer 720 formed on the surface of semiconductor substrate 710, and a cross section of semiconductor surface layer 720. , Two n-type drain layers 7 selectively formed apart from each other
11, 712, the drain electrode 790 connected to the drain layers 711 and 712, the source electrode 714 formed on the back surface of the semiconductor substrate 710, and the drain layers 711 and 712 adjacent to each other. A channel portion 713 in which a channel is formed so as to connect to
And between the drain layers 711 and 712 which are adjacent to each other, at least the channel portion 71 from the drain layers 711 and 712.
3 and the trench 782 formed with the semiconductor surface layer 7 formed therebetween.
N ⁺ -type offset layer 786 having a resistance lower than that of the semiconductor surface layer 720 and formed around the trench 782 in the semiconductor surface layer 720.
Through the gate insulating film 770 formed on the surface of the semiconductor surface layer 720, reaching from above the offset layer 786 to above the drain layers 711 and 712, and forming the trench 78.
2 and a gate electrode 780 formed around the opening of the trench 782 so as not to overlap.

Each of the drain layers 711 and 712 has a joint portion 711 joined to the drain electrode 790 and an electric field relaxation portion 712 extending from the joint portion 711 to the channel portion 713. The electric field relaxation portion 712 is formed in a self-aligned manner by using the gate electrode 780. The electric field relaxation portion 712 is provided to improve the breakdown voltage between the source and the drain by making it easier to extend the depletion layer extending between the channel portion 713 or the p-type semiconductor surface layer 720. Therefore, the electric field relaxation portion 712 may not always be necessary when the semiconductor surface layer 720 is n-type.

Further, a metal material 781 is deposited in the trench 782 so as to connect at least the semiconductor substrate 710 and the offset layer 786. Metal material 7
Reference numeral 81 electrically connects the semiconductor substrate 710 and the offset layer 786.

The power semiconductor device 700 further includes a p-type offset layer 787 around the offset layer 786. The offset layer 787 is a drain electrode 790.
When a positive potential is applied to the drain layers 711 and 712
When the depletion layer extending from the drain reaches the offset layer 786, the drain layer 711, 712 and the offset layer 786
Prevent pinch off between and. When the semiconductor surface layer 720 is n-type, the offset layer 787 is absolutely necessary to prevent a short circuit between the source and the drain. On the other hand, when the semiconductor surface layer 720 is p-type,
The offset layer 787 may not be necessary depending on the concentration of the semiconductor surface layer 720. For example, the drain layer 7
If the concentration of the semiconductor surface layer 720 is set to such an extent that the depletion layer extending from 11, 712 does not reach the offset layer 786, the offset layer 787 is not necessary.

In the semiconductor device 700 according to the present embodiment, the electric field relaxation portion 712 is formed in a self-aligned manner by utilizing the gate electrode 780, so that the drain layer 71 is formed.
The facing area between the gate electrode 780 and the gate electrodes 712 is determined by the diffusion of the electric field relaxation portion 712 toward the channel portion 713. Therefore, the facing region 725 in the semiconductor device 700 is compared with the facing regions 125, 126, 325, 425, 525 in the first to fifth embodiments,
Can be made smaller. Therefore, the semiconductor device 70
0 can reduce the feedback capacitance depending on the degree of diffusion of the electric field relaxation portion 712 as compared with the other embodiments.

Next, a method of manufacturing the semiconductor device according to the present invention will be described.

In the present embodiment, the cross-sectional view has a substantially symmetrical structure, and therefore the reference numerals of the components on the left side from the substantial center of the cross-sectional view are appropriately omitted.

8 to 14 are enlarged cross-sectional views of the power semiconductor device 100 according to the steps of the method for manufacturing the power semiconductor device 100 according to the first embodiment of the present invention in the order of processes.

Referring to FIG. 8, an n ⁺ type semiconductor substrate 1
10 is prepared, and the semiconductor substrate 11 is formed on the semiconductor substrate 110.
An n-type semiconductor surface layer 120 having a resistance higher than 0 is formed. A p-type base layer is selectively formed on the surface of the semiconductor surface layer 120. An insulating film 170 such as a silicon oxide film is formed on the semiconductor surface layer 120. Further, the insulating film 17
A gate material 178, such as metal or doped polysilicon, is deposited over the 0 and shaped into a predetermined shape.

Next, referring to FIG. 9, a mask material 1 such as a photoresist, a silicon oxide film, a silicon nitride film, etc.
The gate material 178 is covered by 76. Gate material 178 is patterned to have a gap W approximately in its middle portion. Nearly the middle of the gate material 178 is also approximately the middle of the adjacent base layers 130. The gap W is preferably smaller than the distance between the base layers 130 adjacent to each other. As a result, the offset layer 186 (see FIG. 12) does not affect the channel portion 160 (see FIG. 14).

Next, referring to FIG. 10, mask material 1
The gate material 178, the insulating film 170 and the semiconductor surface layer 120 are continuously and anisotropically etched from above 76 to form a trench 182 in the semiconductor surface layer 120.

In this embodiment, part of the semiconductor substrate 110 is also etched. Therefore, the trench 182 reaches the semiconductor substrate 110.

Referring now to FIG. 11, trench 18
The n-type impurity 185 is implanted into the side wall of the trench 182 in an oblique direction with respect to the side wall of the trench 182. The direction of implantation of the impurities 185 depends on the gap W of the trench 182 and the mask material 176.
From the surface of the trench 182 to the bottom of the trench 182.

That is, the implantation of the impurities 185 is performed with an angle | θ | ≧ tan from the direction perpendicular to the surface of the semiconductor substrate 110.
It is performed in an oblique direction with an inclination of ^-1 (W / D). In the present embodiment, the impurities 185 are implanted in the direction of arrow Y in FIG. Further, when the impurities are injected into the opposite sidewalls of the trench 182, the impurities 185 are not shown in the arrow Y of FIG.
It is injected in the direction of ´. Thereby, the trench 182
Impurities 185 are implanted into the entire sidewall of the. Impurity 1
85 is an n-type impurity such as arsenic or phosphorus.

Next, referring to FIG. 12, the trenches 182 are formed by heat treating the power semiconductor device 100.
Impurities 185 injected into are diffused. Impurity 185
Are diffused to form an offset layer 186.

Next, referring to FIG. 13, the mask material 1
76 removed and plug material 1 inside trench 182
84 is filled. Further, the contact layer 140 and the source layer 150 are selectively formed on the base layer 130.

Next, referring to FIG. 14, the interlayer insulating film 1
12 is formed so as to cover the gate electrodes 180 and 181. Further, a source electrode 114 is deposited on the interlayer insulating film 112, and the source electrode 114 is used as the contact layer 1.
40 and the source layer 150 are formed in ohmic contact. In addition, the drain electrode 190 is the semiconductor substrate 1
It is formed so as to make ohmic contact with the back surface of 10.

The interlayer insulating film 112 may be deposited by using a method such as CVD. The source electrode 114 and the gate electrode 180 are made of, for example, gold, silver,
A metal such as copper or aluminum can be formed by sputtering.

Further, the power semiconductor device 20 shown in FIG.
The 0 trench 282 is shallower than the trench 182 of the power semiconductor device 100. Therefore, the implantation of impurities is
An angle | θ | <tan ⁻¹ (W / D ′) with respect to the sidewall of the trench 282 from a direction perpendicular to the surface of the semiconductor substrate 210 (hereinafter, simply referred to as “direction V”) (see FIG. 3 for D ′ ), The high-concentration impurities are implanted at the bottom. If a high-concentration impurity is injected into the bottom, the breakdown voltage of the power semiconductor device 200 will fall.

Therefore, in the power semiconductor device 200, the impurity implantation is performed in the oblique direction inclined from the direction V by the angle | θ | ≧ tan ⁻¹ (W / D ′) with respect to the sidewall of the trench 282. . As a result, impurities are implanted into the side surface of the trench 282 and not into the bottom portion thereof.

Further, generally, the implantation of impurities is performed while rotating the semiconductor substrate. However, in the present embodiment, the impurities form an angle | with respect to the sidewall of trench 282 from direction V while stopping semiconductor substrate 210.
It is injected in two directions inclined by θ | ≧ tan ⁻¹ (W / D ′).

The reason is that, in the present embodiment, when the impurity is implanted while rotating the semiconductor substrate 210, the longitudinal direction of the trench 282 and the impurity implantation are performed in the direction V.
It may happen that the direction of inclining from is coincident with. This is because impurities are injected into the bottom of the trench 282.

When impurities are implanted into the bottom of the trench 282, extension of the depletion layer from the base layer 230 is limited, and the breakdown voltage between the source and train of the power semiconductor device 200 is reduced.

8 to 14 show the power semiconductor device 10.
The manufacturing method of 0 was shown. However, the power semiconductor device 20
It can also be applied to 0, 300, 400, 500.

For example, the power semiconductor device 400 further has a p-type offset layer 487 having a lower resistance than the semiconductor surface layer 420 around the offset layer 486. The offset layer 486 is formed by the following process. That is, FIG.
Referring to No. 1, after the impurity is injected, a p-type impurity (not shown) having a diffusion length different from that of the impurity 185 is injected into the sidewall of the trench. The p-type impurity is injected in substantially the same direction as the direction in which the impurity 185 is injected. The p-type impurity is boron or the like.

Further, by heat treating power semiconductor device 400, impurities 185 and p-type impurities are diffused. In the power semiconductor device 400, the diffusion length of the p-type impurity is longer than the diffusion length of the impurity 185. Therefore, the offset layer 48 is formed on the sidewall of the trench 182.
6 is formed, and a p offset layer 487 is formed around the offset layer 486 in a self-aligned manner.

It is extremely easy for those skilled in the art to apply the manufacturing method of FIGS. 8 to 14 to the power semiconductor devices 200, 300 and 500.

By the method for manufacturing a semiconductor device according to this embodiment, the semiconductor device according to the present invention can be manufactured by an existing device. Further, since the gate material 178, the insulating film 170, and the semiconductor surface layer 120 are continuously etched when the trench 182 is formed, the process steps do not become so long. Therefore, an increase in manufacturing cost can be suppressed low.

The embodiment according to the present invention may be used for either the switching power semiconductor element or the rectifying power semiconductor element of the synchronous rectification circuit. It may be used for a switching power semiconductor element and a rectifying power semiconductor element.

[0087]

According to the semiconductor device of the present invention, the capacitance of the gate electrode and the feedback capacitance between the facing region and the gate electrode can be reduced. That is, the semiconductor device according to the present invention can have a faster switching speed, a smaller switching loss, and a lower ON resistance than the conventional one.

Further, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device according to the present invention can be manufactured by the existing device, and the process steps do not become so long. Therefore, the increase of the manufacturing cost can be suppressed low. .

[Brief description of drawings]

FIG. 1 is an enlarged sectional view of a power semiconductor device 100 according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view of the power semiconductor device 100 according to the first embodiment of the present invention.

FIG. 3 is an enlarged cross-sectional view of a power semiconductor device 200 according to a second embodiment of the present invention.

FIG. 4 is an enlarged sectional view of a power semiconductor device 300 according to a third embodiment of the present invention.

FIG. 5 is an enlarged sectional view of a power semiconductor device 400 according to a fourth embodiment of the present invention.

FIG. 6 is an enlarged sectional view of a power semiconductor device 500 according to a fifth embodiment of the present invention.

FIG. 7 is an enlarged sectional view of a power semiconductor device 700 according to a sixth embodiment of the present invention.

FIG. 8 is an enlarged cross-sectional view of the semiconductor device showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 9 is an enlarged cross-sectional view of the semiconductor device showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 10 is an enlarged cross-sectional view of the semiconductor device showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 11 is an enlarged cross-sectional view of the semiconductor device showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 12 is an enlarged cross-sectional view of the semiconductor device showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 13 is an enlarged cross-sectional view of the semiconductor device showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 14 is an enlarged cross-sectional view of the semiconductor device showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of processes.

FIG. 15 is a circuit diagram of a DC-DC converter 2000 used in a conventional typical synchronous rectification circuit type power supply.

FIG. 16 is an enlarged cross-sectional view of a conventional power semiconductor device 1000 used for a conventional synchronous rectification circuit type power supply.

[Explanation of symbols]

100, 200, 300, 400, 500, 700 Power semiconductor device 110, 210, 310, 410, 510, 710 Semiconductor substrate 114, 214, 314, 414, 514, 714 Source electrode 120, 220, 320, 420, 520, 720 Semiconductor surface layer 125, 126, 325, 425, 525, 725 Opposing region 130, 131, 230, 330, 430, 530 Base layer 140, 141, 240, 340, 440 Contact layer 150, 151, 250, 350, 450 Source Layers 178, 180, 181, 280, 281, 380, 4
80, 580, 780 Gate electrodes 182, 282, 382, 482, 582, 782 Trench 186, 189, 286, 386, 486, 487, 5
86, 786, 787 Offset layer 190, 290, 390, 490, 590, 790 Drain electrode 170, 270, 370, 470, 570, 770 Gate oxide film 112 Inter-layer insulation film 184 Plug material 781 Metal material 176 Mask material

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Norio Yasuhara             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Yusuke Kawaguchi             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 4M104 AA01 BB01 BB02 BB04 BB08                       BB09 BB40 CC01 CC05 DD02                       DD37 DD66 DD91 EE03 EE05                       EE09 EE16 EE17 FF02 FF32                       GG18 HH14

Claims (9)

[Claims] 1. A semiconductor substrate, a semiconductor surface layer formed on a surface of the semiconductor substrate, and a plurality of diffusion layers of a first conductivity type which are selectively formed apart from each other in a cross section of the semiconductor surface layer, Between one of the source electrode or the drain electrode connected to the plurality of diffusion layers, the other of the source electrode or the drain electrode formed on the back surface of the semiconductor substrate, and between the diffusion layers adjacent to each other. A channel portion in which a channel is formed so as to be connected to a diffusion layer, a trench formed by separating at least the channel portion from the diffusion layer between adjacent diffusion layers, and a resistance lower than the semiconductor surface layer, Of the semiconductor surface layer, a first offset layer of a first conductivity type formed around the trench, and a gate insulating film formed on the surface of the semiconductor surface layer. And a gate electrode formed around the opening of the trench so as to reach from above the first offset layer to above the diffusion layer and not overlap above the trench. . 2. The semiconductor substrate is of a first conductivity type, the semiconductor surface layer is a second conductivity type or a first conductivity type having a higher resistance than the semiconductor substrate, and the diffusion layer is a source layer, The semiconductor device according to claim 1, wherein a source electrode is connected to the source layer, and a drain electrode is formed on the back surface of the semiconductor substrate. 3. The depth of the trench is a depth that penetrates the semiconductor surface layer to reach the semiconductor substrate, and the first offset layer penetrates the semiconductor surface layer from the surface of the semiconductor surface layer and The semiconductor device according to claim 2, further comprising a semiconductor substrate. 4. The semiconductor surface layer is of a first conductivity type, the depth of the trench is a depth to an arbitrary position in the semiconductor surface layer without penetrating the semiconductor surface layer, and the offset layer is 3. The semiconductor device according to claim 2, which is formed from the surface of the semiconductor surface layer to the bottom of the trench. 5. The depth of the trench is a depth that penetrates the semiconductor surface layer to reach the semiconductor substrate, and the first offset layer penetrates the semiconductor surface layer from a surface of the semiconductor surface layer and The semiconductor substrate is formed, the periphery of the first offset layer is formed from the surface of the semiconductor surface layer to the semiconductor substrate through the semiconductor surface layer, and the second conductivity type having a lower resistance than the semiconductor surface layer. The semiconductor device according to claim 2, further comprising a second offset layer. 6. The drain electrode, the source layer, the first
In the cross section of the semiconductor device, the first offset layer, the second offset layer, and the gate electrode are provided at substantially symmetrical positions with respect to the center of the trench and are formed into substantially symmetrical shapes. Claim 2 characterized by the above-mentioned.
The semiconductor device according to. 7. A semiconductor substrate having a resistance higher than that of a semiconductor substrate of the first conductivity type.
Forming a semiconductor surface layer of one conductivity type or a second conductivity type on the surface of the semiconductor substrate, an insulating film forming step of forming an insulating film on the semiconductor surface layer, a conductive gate material on the insulating film. A gate material forming step to be formed; a trench forming step of forming a trench in the semiconductor surface layer by anisotropically etching the gate material, the insulating film and the semiconductor surface layer continuously according to a predetermined pattern; Forming a first offset layer by first implanting a first conductivity type impurity into a sidewall of the trench in a direction oblique to the sidewall; and diffusing the first conductivity type impurity. A method of manufacturing a semiconductor device, comprising: a diffusion step. 8. After the step of forming the gate material, the gate material is etched according to a predetermined pattern,
Forming a source layer in a self-aligned manner using the gate material after the etching; forming a gate electrode by etching in the trench forming step; and a source electrode connected to the source layer after the diffusion step. The method of manufacturing a semiconductor device according to claim 7, further comprising: forming a drain electrode on the back surface of the semiconductor substrate. 9. After the first implantation step, a second conductivity type impurity having a diffusion length different from that of the first conductivity type impurity is formed on the sidewall of the trench.
The method further includes a second implanting step of implanting a conductive type impurity, wherein the diffusing step diffuses the first conductive type impurity and the second conductive type impurity to form a first conductive layer on a sidewall of the trench. 9. The semiconductor according to claim 7, wherein a first offset layer of a second conductivity type is formed, and a second offset layer of a second conductivity type is formed around the first offset layer. Device manufacturing method.