JP2003007815A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

[PROBLEMS] To form a highly reliable contact. Also,
Measure the inspection mark with high accuracy. SOLUTION: An element isolation groove 10 is formed in a mark portion of a substrate 101.
1a was formed. An element isolation insulating film 102 was formed in the element isolation groove 101a. An etching stopper film 110 made of a silicon nitride film was formed so as to cover at least a part of the surface of the element isolation insulating film 102 formed in the mark portion. Using the etching stopper film 110 at the mark part as an inspection mark, a circuit element was formed in the circuit part of the substrate 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to an element isolation technique.

[0002]

2. Description of the Related Art In recent years, miniaturization, high integration and high speed of semiconductor devices have been advanced. Further, it has become very important to reduce the resistance of the contact hole formed with a high aspect ratio and reduce the leak current in the element isolation insulating film.

A conventional semiconductor device will be described below. FIG. 43 is a sectional view for explaining a circuit portion of a conventional semiconductor device. Further, FIG. 44 is a diagram for explaining the mark portion of the conventional semiconductor device. FIG. 43 shows the circuit portion of the semiconductor device when the contact hole is opened outside the active region. In FIG. 43, 10
1 is a silicon substrate, 102 is an element isolation insulating film, 103 is a gate insulating film, 104 is a first wiring layer (gate electrode), 1
04a is a polysilicon film, 104b is a tungsten film,
105 is an insulating film, 106 is a low concentration diffusion layer (n-low concentration layer), 107 is a sidewall, 108 is a high concentration diffusion layer (n + high concentration layer), 109 is an interlayer insulating film, 120 is a contact hole, 121 is 121 A contact (contact plug), 121a is a barrier metal, 121b is a tungsten plug, 122 is a second wiring layer, 122a is a barrier metal, and 122b is a tungsten film.

Further, FIG. 44 shows a polysilicon film 104a.
The mark part of the semiconductor device after forming the resist pattern 123 which is a mask for implanting the N-type dopant therein is shown. Here, the mark portion is an area in which an alignment inspection mark for aligning a photomask is formed immediately before exposing a pattern, or an overlay of an exposure pattern (resist pattern) and a base layer is inspected. Is a region in which an overlay inspection mark is formed. In FIG. 44, the same reference numerals as those in FIG. 43 indicate the same parts, and therefore the description thereof will be simplified or omitted. Further, reference numeral 123 in FIG. 44 indicates a resist pattern. Conventionally, the element isolation insulating film 102 formed in the mark portion has been used as an overlay inspection mark of the resist pattern 123.

[0005]

However, the above-mentioned conventional semiconductor device has the following problems. As a first problem, as shown in FIG. 43, when the contact hole 120 is opened outside of the active region, the contact hole 120 reaches the element isolation insulating film 102. Here, the interlayer insulating film 109 and the element isolation insulating film 1
Reference numeral 02 is a silicon oxide film. Therefore, when the interlayer insulating film 109 is dry-etched to open the contact hole 120, a sufficient etching selection ratio with respect to the element isolation insulating film 102 cannot be secured. Therefore, there is a problem that the element isolation insulating film 102 is etched into a slit shape at the boundary between the element isolation region and the active region, that is, the boundary between the element isolation insulating film 102 and the high-concentration diffusion layer 108 (see FIG. 43). . In this case, the element isolation insulating film 1
02 and the high-concentration diffusion layer 108 have a problem that plasma damage at the time of dry etching remains at the boundary and the leak current increases. Further, when the element isolation insulating film 102 is etched into a slit shape deeper than the high-concentration diffusion layer 108, there is a problem that the leak current further increases. Further, even if the barrier metal 121a was formed in the contact hole 120 formed as described above by the sputtering method, the barrier metal 121a could not be formed uniformly. Further, there is a problem that the tungsten plug 121b cannot be formed with good coverage on the barrier metal 121a and the seam A is formed at the boundary between the element isolation insulating film 102 and the high concentration diffusion layer 108. In this case, there is a problem that the contact resistance increases and the reliability of the plug decreases.

A second problem is that the element isolation insulating film 102 used as the overlay inspection mark is a semitransparent silicon oxide film, and a sufficient contrast cannot be obtained. The position of the insulating film 102) could not be measured accurately. That is, there is a problem that the position of the overlay inspection mark is erroneously measured. Therefore, the overlay inspection cannot be performed accurately. As described above, if the position of the element isolation insulating film 102 is erroneously measured, there is a problem that the circuit element cannot be formed accurately.
For example, in the case shown in FIG. 44, the polysilicon film 104
There is a problem in that the N-type dopant cannot be accurately injected into a. The same applies when a P-type dopant is implanted into the polysilicon film 104a. Therefore, there is a problem that both the N-type dopant and the P-type dopant are implanted into the predetermined portion of the polysilicon film 104a, or no dopant is implanted. As a result, the resistance of the gate electrode 104 increases, which may cause device failure.

The present invention has been made in order to solve the above conventional problems, and an object thereof is to form a highly reliable contact. Moreover, it aims at measuring an inspection mark accurately.

[0008]

A method of manufacturing a semiconductor device according to a first aspect of the present invention is a method of manufacturing a semiconductor device having a circuit portion including an element isolation region for isolating an active region and a mark portion on a substrate. And forming an element isolation groove in the element isolation region and the mark portion, forming an element isolation insulating film in the element isolation groove, and covering at least an edge portion of the element isolation insulating film. And a step of forming a circuit element in the circuit portion by using the etching stopper film formed in the mark portion as an inspection mark. .

A method of manufacturing a semiconductor device according to a second aspect of the present invention is the method of manufacturing according to the first aspect, wherein the step of forming the circuit element includes the step of forming a gate insulating film on the substrate, A step of forming a conductive film on the gate insulating film; a step of forming a first resist pattern on the conductive film; and a step of implanting impurities into the conductive film using the first resist pattern as a mask. In addition, in the step of forming the first resist pattern, the etching stopper film formed in the mark portion is used as an inspection mark.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein the step of forming the circuit element includes the step of forming a silicide protection film on the substrate. Forming a second resist pattern on the silicide protection film, patterning the silicide protection film using the second resist pattern as a mask, and forming a second resist pattern on the upper layer of the substrate using the patterned silicide protection film as a mask. And a step of forming a silicide layer, wherein the etching stopper film formed on the mark portion is used as an inspection mark in the step of forming the second resist pattern.

A method of manufacturing a semiconductor device according to a fourth aspect of the present invention is a method of manufacturing a semiconductor device having a circuit portion including an element isolation region for isolating an active region and a mark portion on a substrate. Forming an element isolation groove in the region and the mark portion, forming an element isolation insulating film in the element isolation groove, forming a gate electrode in the active region, and adjoining the gate electrode A step of forming an impurity diffusion layer in the substrate; a step of forming an insulating film on the entire surface of the substrate after the impurity diffusion layer is formed; and a step of etching back the insulating film to remove the element isolation insulating film. A step of forming an etching stopper film covering the edge portion, and a step of forming a circuit element in the circuit portion by using the etching stopper film formed in the mark portion as an inspection mark And it is characterized in that it comprises a.

A method of manufacturing a semiconductor device according to a fifth aspect of the present invention is the method of manufacturing a semiconductor device according to the fourth aspect, wherein the etching stopper film is formed and a sidewall is formed on a side surface of the gate electrode. It is what

A method of manufacturing a semiconductor device according to a sixth aspect of the present invention is the method of manufacturing a semiconductor device according to the fourth or fifth aspect, wherein the step of forming the circuit element includes the step of forming a silicide protection film on the substrate. Forming a first resist pattern on the silicide protection film, patterning the silicide protection film using the first resist pattern as a mask,
A step of forming a silicide layer on the upper layer of the substrate using the patterned silicide protection film as a mask, and forming the first resist pattern, the etching stopper film formed on the mark portion is removed. It is characterized by being used as an inspection mark.

A method of manufacturing a semiconductor device according to a seventh aspect of the present invention is the method of manufacturing according to any of the fourth to sixth aspects, characterized in that the etching stopper film is formed in a self-aligned manner. Is.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the first to seventh aspects, wherein the inspection marks are alignment inspection marks and overlay inspection marks. It is a feature.

A method of manufacturing a semiconductor device according to a ninth aspect of the present invention is the method of manufacturing according to any one of the first to eighth aspects, wherein the etching stopper film includes a silicon nitride film. is there.

A method of manufacturing a semiconductor device according to a tenth aspect of the present invention is the method of manufacturing a semiconductor device according to the ninth aspect, wherein the etching stopper film further includes a silicon oxide film below the silicon nitride film. To do.

A method of manufacturing a semiconductor device according to an eleventh aspect of the present invention is the method of manufacturing a semiconductor device according to any one of the first to tenth steps, in which an interlayer insulating film is formed on the entire surface of the substrate so as to cover the circuit elements. And a step of forming a contact hole reaching from the surface of the interlayer insulating film to the surface of the substrate, and a step of forming a contact plug in the contact hole.

A semiconductor device manufacturing method according to a twelfth aspect of the present invention is the manufacturing method according to any one of the first to eleventh aspects, wherein the surface of the element isolation insulating film is lower than the surface of the substrate. It is characterized in that it is formed in the element isolation groove.

A semiconductor device manufacturing method according to a thirteenth aspect of the present invention is the method of manufacturing a semiconductor device according to any one of the first to eleventh aspects, wherein the surface of the element isolation insulating film is higher than the surface of the substrate. It is characterized in that it is formed in the element isolation groove.

A semiconductor device according to a fourteenth aspect of the present invention is characterized by being manufactured by using the manufacturing method according to any one of the first to thirteenth aspects.

A semiconductor device according to a fifteenth aspect of the present invention includes a circuit portion including an element isolation region for isolating an active region,
A semiconductor device having a mark portion on a substrate, wherein at least one of an element isolation groove formed in the mark portion, an element isolation insulating film formed in the element isolation groove, and a surface of the element isolation insulating film. An etching stopper film that covers the part,
An interlayer insulating film formed on the entire surface of the substrate, and a contact hole reaching from the surface of the interlayer insulating film to the surface of the substrate are provided.

A semiconductor device according to a sixteenth aspect of the present invention is the semiconductor device according to the fifteenth aspect, wherein the element isolation groove, the element isolation insulating film and the etching stopper film are formed in the element isolation region of the circuit section. Further, the contact hole is further formed, and the contact hole is further formed in the active region of the circuit portion.

According to a seventeenth aspect of the present invention, in the semiconductor device according to the sixteenth aspect, the etching stopper film formed in the element isolation region covers an edge portion of the element isolation insulating film. It is what

A semiconductor device according to an eighteenth aspect of the invention is the semiconductor device according to any one of the fifteenth to seventeenth aspects, wherein the etching stopper film includes a silicon nitride film.

A semiconductor device according to a nineteenth aspect of the present invention is the semiconductor device according to any one of the fifteenth to eighteenth aspects, wherein the element isolation insulating film has a surface lower than that of the substrate. It is characterized in that it is formed in the separation groove.

A semiconductor device according to a twentieth aspect of the present invention is the semiconductor device according to any one of the fifteenth to eighteenth aspects, wherein the element isolation insulating film has a surface higher than a surface of the substrate. It is characterized in that it is formed in the separation groove.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof may be simplified or omitted.

Embodiment 1. 1 is a sectional view for explaining a circuit portion of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a sectional view for explaining the mark portion of the semiconductor device according to the first embodiment.

In FIG. 1, reference numeral 101 is a substrate, for example, a P-type silicon wafer (semiconductor substrate) having a specific resistance of 10 Ω · cm. The substrate 101 includes a circuit portion including an active region and an element isolation region for isolating the active region,
And a mark portion on which an inspection mark described later is formed. Reference numeral 101a is an element isolation groove formed in the substrate 101. Reference numeral 102 denotes an element isolation insulating film formed in the element isolation trench 101a, which is, for example, a plasma silicon oxide film having a film thickness of 300 nm. The plasma silicon oxide film is, for example, HDPCVD (High Density Plasma Chemical Vap).
A silicon oxide film (hereinafter referred to as “HDP oxide film”) formed by the or deposition method. 1
A gate insulating film 03 is, for example, a silicon oxynitride film (SiON) or a silicon oxide film having a thickness of 3 nm.

Reference numeral 104 denotes a gate electrode as a first wiring layer, which is formed by stacking, for example, a polysilicon film 104a and a tungsten film 104b. Here, the polysilicon film 104a is formed, for example, in a non-doped polysilicon film by implanting, for example, phosphorus (P ⁺ ) as an N-type dopant in the N-type region at 10 keV and 5E15 cm ⁻² , and in the P-type region as a P-type region.
Boron (BF ₂ ⁺ ) is 3keV, 5E1 as a type dopant
It was injected at 5 cm ^-2 . Reference numeral 105 denotes an insulating film as a hard mask, which is, for example, a silicon nitride film having a film thickness of 100 nm. Reference numeral 106 denotes an extension low-concentration diffusion layer (n-low-concentration layer), for example, arsenic 30 keV, 1E14 cm
It was injected into the substrate 101 at ^-2 and 45 degrees. 10
Reference numeral 7 is a sidewall, which is, for example, a silicon nitride film having a film thickness of 50 nm. Reference numeral 108 denotes a high-concentration diffusion layer (n + high-concentration layer) in which, for example, arsenic is injected into the substrate 101 at 50 keV, 5E15 cm ^-2 , and 7 degrees. An interlayer insulating film 109 is, for example, an HDP oxide film having a film thickness of 700 nm.

Reference numeral 110 is an etching stopper film formed so as to cover at least a part of the surface of the element isolation insulating film 102, and is, for example, a silicon nitride film having a film thickness of 30 nm. Further, the etching stopper film 110 is oversized not only on the element isolation insulating film 102 but also on the high concentration diffusion layer 108 so as to cover the boundary between the high concentration diffusion layer 108 in the active region and the element isolation insulating film 102. Is formed. Reference numeral 120 is a contact hole having a bottom diameter of 0.1 μm, for example, and 121 is a contact (contact plug) formed in the contact hole 120. The contact 121 has a barrier metal 121a made of TiN / Ti = 20 nm / 20 nm and a tungsten plug 121b. 122 is a second wiring layer. The second wiring layer 122 is
A barrier metal 122a composed of TiN / Ti = 20/20 nm and a tungsten film 122b having a film thickness of 100 nm are laminated.

In FIG. 2, the same reference numerals as those in FIG. 1 denote the same parts. Further, reference numeral 123 indicates a resist pattern. FIG. 2 shows the polysilicon film 104a.
The mark part of the semiconductor device after forming the resist pattern 123 which is a mask for implanting the N-type dopant therein is shown. Here, the mark portion is an area in which an alignment inspection mark for aligning a photomask is formed immediately before exposing a pattern, or an overlay of an exposure pattern (resist pattern) and a base layer is inspected. Is a region in which an overlay inspection mark is formed. The etching stopper film 110 formed in the mark portion shown in FIG. 2 is used as an overlay inspection mark for inspecting the overlay of the resist pattern 123 and the underlying layer. Further, in the mark portion, the etching stopper film 1 as an outer mark
10 is, for example, 20 to 30 μm square and 0.2 to 0.4 μm wide, and the resist pattern 123 as an inner mark is, for example, 10 to 15 μm square.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 3 to 8 are views for explaining the method of manufacturing the semiconductor device according to the first embodiment.
First, as shown in FIG. 3, a thermal oxide film 131 is formed on the substrate 101.
Is formed with a film thickness of 30 nm, for example. Next, a silicon nitride film 132 is formed on the thermal oxide film 131 to have a film thickness of 150 nm, for example. Then, a resist pattern (not shown) covering the active region is formed on the silicon nitride film 132, and the formed silicon nitride film 1 is used as a mask.
32 and the thermal oxide film 131 are dry-etched. Further, the substrate 101 is dry-etched using the etched silicon nitride film 132 and thermal oxide film 131 as a mask. This allows, for example, depth within the substrate 101.
A device isolation trench 101a of 300 nm is formed. Next, an HDP oxide film, for example, with a film thickness of 500 nm is deposited as the element isolation insulating film 102 in the element isolation trench 101a, and CMP polishing is performed. Then, in order to reduce the trench isolation step, the element isolation insulating film 102 is wet-etched by a thickness of 150 nm, for example.

Next, as shown in FIG. 4, the silicon nitride film 132 and the silicon oxide film 131 are wet-etched. As a result, the surface of the substrate 101 and the surface of the element isolation insulating film 102 have the same height. Next, a silicon nitride film as the etching stopper film 110 is formed with a film thickness of 30 nm on the entire surface of the substrate. Then, the etching stopper film 11
0 to form a resist pattern 133. Here, the resist pattern 133 is at least the element isolation insulating film 1
It is formed so as to cover the edge portion of 02.

Next, as shown in FIG. 5, the etching stopper film 11 is formed using the resist pattern 133 as a mask.
0 is wet-etched. At the same time, the etching stopper film 110 in the mark portion is also patterned (see FIG. 6). Next, the resist pattern 133 is removed. Then, as the gate insulating film 103, for example, a silicon oxynitride film (SiON) is formed with a film thickness of 3 nm. Further, a non-doped polysilicon film 104a having a film thickness of 100 nm is formed on the gate insulating film 103. Next, a resist film is formed on the polysilicon film 104a, and pattern exposure is performed on this resist film. As a result, a resist pattern 123, which is a mask for injecting an N-type dopant into the polysilicon film 104a, is formed on the polysilicon film 104a. Further, as shown in FIG. 6, the resist pattern 123 is also formed on the mark portion at the same time.

After the resist pattern 123 is formed, the resist pattern 12 in the circuit portion is used as an overlay inspection mark using the etching stopper film 110 in the mark portion.
3 and the overlay layer are inspected. In this overlay inspection, the position of the inspection mark (etching stopper film 110) can be accurately measured. Therefore, the overlay inspection of the resist pattern 123 can be performed accurately. The resist pattern 123 in the mark portion is the resist pattern 12 formed in the circuit portion.
Pattern with a dimension close to the minimum rule of 3. Thereby, the influence of the aberration of the lens in the exposure apparatus (not shown) can be suppressed, and the accuracy of overlay inspection can be improved.

Next, although not shown, the resist pattern 1
23 as a mask, the polysilicon film 104 in the N-type region
For example, phosphorus (P ⁺ ) 10 k
Inject with eV, 5E15cm ^-2 . Similarly, boron (BF ₂ ⁺ ) as a P-type dopant is implanted into the polysilicon film 104a in the P-type region at 3 keV and 5E15 cm ^-2 .

Next, as shown in FIG. 7, a tungsten film 104b is formed to a thickness of 100 nm on the polysilicon film 104a. Then, the insulating film 105 is formed with a thickness of 100 nm on the tungsten film 104b. Next, the insulating film 105
The patterned insulating film 105
Using the as a mask, the tungsten film 104b and the polysilicon film 104a are dry-etched. As a result, the gate electrode 104 is formed. Then, a low-concentration diffusion layer (n-low-concentration layer) 106, for example, arsenic (As ⁺ ) 3
It is formed by implanting into the substrate 101 at 0 keV, 1E14 cm ^-2 and 45 degrees. Then, for example, a silicon nitride film with a film thickness of 50
It is formed on the entire surface of the substrate by nm and is etched back. As a result, the sidewall 107 is formed on the side surface of the gate electrode 104. Further, using the sidewall 107 as a mask, for example, arsenic is implanted into the substrate 101 at 50 keV and 5E15 cm ⁻² to form a high concentration diffusion layer (n + high concentration layer) 108 having a higher impurity concentration than the low concentration diffusion layer 106. To do. Next, as the interlayer insulating film 109, for example, an HDP oxide film is formed with a film thickness of 1000 nm, and the interlayer insulating film 109 is 300 nm thick.
MP polishing. Then, a resist pattern 134 is formed on the interlayer insulating film 109. Then, using the resist pattern 134 as a mask, the etching stopper film 11 is formed.
The interlayer insulating film 109 is dry-etched under the etching condition (main etching) having a high selection ratio with respect to 0. As a result, a contact hole 120 having a diameter of 0.2 μm on the surface of the interlayer insulating film 109 and reaching the surface of the etching stopper film 110 from the surface is formed. Here, since the etching is performed under the condition that the etching stopper film 110 has a high selection ratio, that is, the condition that the silicon nitride film has a high selection ratio,
Even when a plurality of contact holes having different depths are formed at the same time, etching damage is not given to the active region of the substrate 101. Further, the etching stopper film 110
Are etched under etching conditions (over etching) having a high selection ratio with respect to the element isolation insulating film 102 and the substrate 101. As a result, the contact hole 12 reaching from the surface of the interlayer insulating film 109 to the surface of the substrate 101.
0 is formed. Here, since the etching stopper film 110 having a relatively small thickness and a uniform thickness can be removed in a short time, etching damage given to the substrate 101 can be reduced. That is, by forming the contact hole 120 in two steps, etching damage to the substrate 101 and the element isolation insulating film 102 can be reduced. Further, by forming the etching stopper film 110 at the boundary between the high concentration diffusion layer 108 and the element isolation insulating film 102, it is possible to prevent the edge portion of the element isolation insulating film 102 from being etched.

Finally, as shown in FIG. 8, a barrier metal 121a made of, for example, TiN / Ti is formed in the contact hole 120 to a film thickness of 20 nm / 20 nm, and a tungsten 121b is further formed by CVD (Chemical Vapor Deposit).
Ion) method is used to form a film with a thickness of 200 nm.
The unnecessary tungsten is removed by using the echanical Polishing method. As a result, the tungsten plug 121b
Is formed. That is, the barrier metal 121a and the tungsten plug 121 are provided in the contact hole 120.
A contact 121 made of b is formed. Further, for example, TiN / Ti with a film thickness of 20/20 nm is formed as a barrier metal 122a on the contact 121.
2b is formed with a film thickness of 100 nm. And barrier metal 1
22a and the tungsten film 122b are patterned. As a result, the second wiring layer 1 is formed on the contact 121.
22 is formed.

As described above, in the first embodiment, the boundary between the active region and the element isolation region, that is, the high concentration diffusion layer 10 is formed.
A silicon nitride film as an etching stopper film 110 was formed at the boundary between the element isolation insulating film 102 and the element isolation insulating film 102. As a result, etching damage given to the substrate 101 when the contact hole 120 is formed (particularly during overetching) can be reduced. Therefore, a good contact junction with a small leak current can be formed. Further, when the contact hole 120 is formed, the element isolation insulating film 102 at the boundary portion, that is, the edge portion of the element isolation insulating film 102 is not etched into a slit shape, so that the shape of the bottom portion of the contact hole 120 is improved. can do. Therefore, the barrier metal 121a and the tungsten 1 are formed in the contact hole 120.
21b can be formed with good coverage, and a good contact 121 with high reliability can be formed.

In the first embodiment, the etching stopper film 110 is simultaneously formed not only on the circuit portion but also on the mark portion. Then, the etching stopper film 110 formed in the mark portion was used as an overlay inspection mark. Since the etching stopper film 110 has a high contrast, the position of the etching stopper film 110, that is, the overlay inspection mark can be easily and accurately measured. Therefore, the overlay inspection of the resist pattern (for example, the resist pattern 123 shown in FIG. 5) and the underlying layer can be performed accurately.

In the first embodiment, the case where the etching stopper film 110 of the mark portion is used as the overlay inspection mark has been described, but it can also be used as the alignment inspection mark. That is, the photomask alignment inspection (rough alignment inspection, fine alignment inspection) can be performed using the etching stopper film 110 as an alignment inspection mark. In this case as well, the position of the alignment inspection mark can be accurately measured, as in the overlay inspection mark. Therefore, the alignment inspection of the photomask can be performed accurately. Therefore, the resist pattern can be formed with high accuracy (the same applies to Embodiments 2 to 5 described later). Therefore, for example, the resist pattern 123 can be formed with high accuracy, and it is possible to prevent the N-type region and the P-type region in the polysilicon film 104a from overlapping and the implantation position from being displaced.

In the first embodiment, the overlay inspection of the resist pattern 123 for injecting the N-type dopant has been described. Not limited to this, it can also be applied to patterning gate electrodes, patterning when forming dual gate oxide films separately, or performing overlay inspection of resist patterns formed by patterning for capacitance formation of analog circuit section. You can

In the first embodiment, the case where the etching stopper film 110 is oversized up to the high-concentration diffusion layer 108 in the active region has been described, but the etching stopper film 110 is formed at least at the bottom of the contact hole 120. It should have been done. That is,
The formation region of the etching stopper film 110 may be appropriately changed according to the diameter of the contact hole 120.

In the first embodiment, the etching stopper film 110 is formed of a silicon nitride film single layer.
It may be a multilayer film including a silicon nitride film. For example,
An etching stopper film 110 made of a laminated insulating film may be formed by forming a silicon oxide film (non-doped silicon oxide film) and laminating a silicon nitride film on the silicon oxide film. In this case, the stress on the edge portion of the element isolation insulating film 102 can be relaxed (the same applies to Embodiments 2 to 5 described later).

In addition, the insulating film 105 as a hard mask.
Is not limited to the silicon nitride film, and may be a silicon oxide film or a laminated film of a silicon oxide film and a silicon nitride film. Further, a normal resist pattern may be used instead of the insulating film 105 (the same applies to Embodiments 2 to 5 described later).

The surface of the high-concentration diffusion layer 108 may be silicidized (cobalt silicide, titanium silicide, etc.) to reduce the resistance. Also in this case, the etching stopper film 110 can be used as an inspection mark. (The same applies to Embodiments 2 and 4 described later).

Embodiment 2. In the first embodiment described above,
The element isolation insulating film was formed so that the surface of the substrate in the active region and the surface of the element isolation insulating film were at the same height, and the etching stopper film was formed so as to cover the edge portion of the surface of the element isolation insulating film. In the second embodiment, the surface of the element isolation insulating film in the circuit portion and the mark portion is made lower than the substrate in the active region, and the etching stopper film is formed at the edge portion of the surface of the element isolation insulating film.

FIG. 9 is a sectional view for explaining the circuit portion of the semiconductor device according to the second embodiment of the present invention. Figure 10
FIG. 9 is a diagram for explaining a mark portion of the semiconductor device according to the second embodiment of the present invention. 9 and 10,
The same reference numerals as those in FIG. 1 or FIG. 2 indicate the same parts, and therefore the description thereof will be simplified or omitted.

As shown in FIG. 9, the element isolation insulating film 102
By embedding the element isolation groove with a film thickness of 250 nm,
The element isolation insulating film 102 was formed so that the surface thereof was lower than the surface of the substrate 101. Further, a silicon nitride film as the etching stopper film 111 is formed so as to cover at least the edge portion of the element isolation insulating film 102. In addition, the element isolation trenches 1 on the element isolation insulating film 102, that is, in the portions where the element isolation insulating film 102 is not embedded.
The 01a side wall is covered with the etching stopper film 111. Further, as shown in FIG. 10, the etching stopper film 111 was formed so as to cover the edge portion of the element isolation insulating film 102 in the mark portion as well as the circuit portion. Etching stopper film 1 formed on the mark part
Reference numeral 11 is used as an overlay inspection mark for inspecting overlay of the resist pattern 123 of the circuit portion and the underlying layer (described later).

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. 11 to 16 are views for explaining the method for manufacturing the semiconductor device according to the second embodiment. First, as shown in FIG. 11, a thermal oxide film 131 is formed on the substrate 101 to have a film thickness of 30 nm, for example. Next, a silicon nitride film 132 is formed on the thermal oxide film 131, for example, with a film thickness of 150 n.
Form with m. Then, a resist pattern (not shown) covering the active region is formed on the silicon nitride film 132, and the silicon nitride film 132 and the thermal oxide film 131 are dry-etched using the formed resist pattern as a mask. Further, the etched silicon nitride film 13
The substrate 101 is dry-etched using the 2 and the thermal oxide film 131 as a mask. As a result, in the substrate 101,
For example, the element isolation trench 101a having a depth of 300 nm is formed.
Next, the element isolation insulating film 102 is formed in the element isolation trench 101a.
As an example, an HDP oxide film is deposited to a film thickness of 500 nm, and C
Perform MP polishing. Then, the element isolation insulating film 102 is wet-etched to a film thickness of 200 nm, for example.

Next, as shown in FIG. 12, the silicon nitride film 132 and the silicon oxide film 131 are wet-etched. As a result, the element isolation insulating film 1 is formed so that the surface of the element isolation insulating film 102 is lower than the surface of the substrate 101.
02 is formed. Next, the etching stopper 111
Forming a silicon nitride film as a film having a thickness of 30 nm on the entire surface of the substrate. Then, a resist pattern 135 is formed on the etching stopper 111. Here, the resist pattern 135 is formed so as to cover the edge portion of the element isolation insulating film 102.

Next, as shown in FIG. 13, the etching stopper 11 is formed using the resist pattern 135 as a mask.
1 is wet-etched. At the same time, the etching stopper 111 at the mark portion is also patterned (see FIG. 1).
4). Next, the resist pattern 135 is removed.
Then, as the gate insulating film 103, for example, a silicon oxynitride film (SiON) is formed with a film thickness of 3 nm. Further, a non-doped polysilicon film 104 is formed on the gate insulating film 103.
a is formed with a film thickness of 100 nm. Next, the polysilicon film 10
4a, a resist pattern 1 which is a mask for injecting an N-type dopant into the polysilicon film 104a.
23 is formed. Further, as shown in FIG. 14, the resist pattern 123 is also formed on the mark portion at the same time.

After forming the resist pattern 123, the etching stopper film 111 in the mark portion is used as an overlay inspection mark to form the resist pattern 12 in the circuit portion.
3 and the overlay layer are inspected. In this overlay inspection, the position of the inspection mark (etching stopper film 111) can be accurately measured. Therefore, the overlay inspection of the resist pattern 123 can be performed accurately. The resist pattern 123 in the mark portion is the resist pattern 12 formed in the circuit portion.
Pattern with a dimension close to the minimum rule of 3. Thereby, the influence of the aberration of the lens in the exposure apparatus can be suppressed, and the accuracy of overlay inspection can be improved.

Next, N-type and P-type dopants are implanted into the polysilicon film 104a by the same method as in the first embodiment.

Next, as shown in FIG. 15, a tungsten film 104b is formed to a thickness of 100 nm on the polysilicon film 104a. Then, the insulating film 105 is formed with a thickness of 100 nm on the tungsten film 104b. Then, the insulating film 10
5, the insulating film 10 is patterned.
Using 5 as a mask, the tungsten film 104b and the polysilicon film 104a are dry-etched. As a result, the gate electrode 104 is formed. Then, a low-concentration diffusion layer (n-low-concentration layer) 106, for example, arsenic (As ⁺ ) 3
It is formed by implanting into the substrate 101 at 0 keV, 1E14 cm ^-2 and 45 degrees. Then, for example, a silicon nitride film with a film thickness of 50
It is formed on the entire surface of the substrate by nm and is etched back. As a result, the sidewall 107 is formed on the side surface of the gate electrode 104. Further, using the sidewall 107 as a mask, for example, arsenic is implanted into the substrate 101 at 50 keV and 5E15 cm ⁻² to form a high concentration diffusion layer (n + high concentration layer) 108 having a higher impurity concentration than the low concentration diffusion layer 106. To do. Next, as the interlayer insulating film 109, for example, an HDP oxide film is formed with a film thickness of 1000 nm, and the interlayer insulating film 109 is 300 nm thick.
MP polishing. Then, a resist pattern 134 is formed on the interlayer insulating film 109.

Then, using the resist pattern 134 as a mask, under the etching (main etching) condition having a high selection ratio with respect to the etching stopper film 111,
The interlayer insulating film 109 is dry-etched. As a result, a contact hole 120 having a diameter of 0.2 μm on the surface of the interlayer insulating film 109 and reaching the surface of the etching stopper 111 from the surface is formed. here,
Even if a plurality of contact holes having different depths are simultaneously formed by etching under the condition of having a high selection ratio with respect to the etching stopper 111, that is, a high selection ratio with respect to the silicon nitride film, the active region of the substrate 101 is Does not give etching damage. Further, the etching stopper 111 on the substrate 101a is provided on the element isolation insulating film 102 and the substrate 101 (high concentration diffusion layer 108).
Etching is performed under etching conditions (over etching) having a high selection ratio. As a result, a contact hole 120 reaching from the surface of the interlayer insulating film 109 to the surface of the substrate 101 is formed. Here, the etching stopper film 111 that is uniform and has a relatively thin film thickness can be removed in a short time. That is, the contact hole 12 in two steps
By forming 0, etching damage to the substrate 101 and the element isolation insulating film 102 can be reduced. In addition, the high concentration diffusion layer 108 and the element isolation insulating film 10
By forming the etching stopper 111 at the boundary between the two, it is possible to prevent the edge portion of the element isolation insulating film 102 from being etched.

Finally, as shown in FIG. 16, a barrier metal 121a made of, for example, TiN / Ti is formed in the contact hole 120 to a film thickness of 20 nm / 20 nm, and further, a tungsten 121b is formed to a film thickness of 200 nm by the CVD method. Then, unnecessary tungsten is removed by using the CMP method. As a result, the tungsten plug 121b is formed. That is, the contact 121 including the barrier metal 121a and the tungsten plug 121b is formed in the contact hole 120. In addition, contact 1
21. For example, TiN / Ti with a film thickness of 20/20 nm is formed as the barrier metal 122a, and the tungsten film 122b is formed with a film thickness.
Form at 100 nm. Then, the barrier metal 122a and the tungsten film 122b are patterned. As a result, the second wiring layer 122 is formed on the contact 121.

As described above, in the second embodiment, the boundary between the active region and the element isolation region, that is, the high concentration diffusion layer 10 is formed.
8 and the element isolation insulating film 102 were formed with an etching stopper film 111. As a result, etching damage given to the substrate 101 when the contact hole 120 is formed (particularly during overetching) can be reduced. Further, it is possible to form a good contact junction with a small leak current. Further, when the contact hole 120 is formed, the element isolation insulating film 102 at the boundary portion, that is, the edge portion of the element isolation insulating film 102 is not etched into a slit shape, so that the shape of the bottom portion of the contact hole 120 is improved. can do.
Therefore, the barrier metal 12 is formed in the contact hole 120.
1a and tungsten 121b can be formed with good coverage, and the contact 121 is highly reliable.
Can be formed.

Further, in the second embodiment, the etching stopper film 111 is simultaneously formed not only on the circuit portion but also on the mark portion. Then, the etching stopper film 111 formed in the mark portion was used as an overlay inspection mark. Since the etching stopper film 111 has a good contrast, the position of the etching stopper film 111, that is, the position of the overlay inspection mark can be easily and accurately measured. Therefore, the overlay inspection can be performed accurately.

Further, in the second embodiment, the surface of the element isolation insulating film 102 is made lower than the surface of the active region. As a result, the film thickness of the etching stopper film 111 formed at the boundary between the element isolation insulating film 102 and the active region, that is, the edge portion of the element isolation insulating film 102 effectively increases. Therefore, the etching damage given to the substrate 101 at the time of forming the contact hole 120 can be further reduced as compared with the first embodiment. Further, the current driving capability of the transistor can be improved by making the surface of the element isolation insulating film 102 fall, which is effective for speeding up in the logic part of eDRAM (embeded DRAM), for example. The same applies to 3.)

Embodiment 3. In the second embodiment described above,
The surface of the element isolation insulating film in the circuit portion and the mark portion was made to fall below the active region, and an etching stopper film was formed on the edge portion of the surface of the element isolation insulating film by patterning. In the third embodiment, the surface of the element isolation insulating film in the circuit portion and the mark portion is made lower than the active region, and the etching stopper film is formed in a self-aligned manner only on the edge portion of the surface of the element isolation insulating film.
Further, in the third embodiment, the upper layer of the high concentration diffusion layer is
A silicide layer was formed.

FIG. 17 is a sectional view for explaining a circuit portion of a semiconductor device according to the third embodiment of the present invention. Figure 1
FIG. 8 is a diagram for explaining a mark portion of the semiconductor device according to the third embodiment of the present invention. 17 and 18, the same reference numerals as those in FIG. 9 or 10 denote the same parts, and therefore the description thereof will be simplified or omitted.

As shown in FIG. 17, the element isolation insulating film 10 is formed.
By embedding No. 2 in the element isolation groove with a film thickness of 250 nm, the element isolation insulating film 102 was formed so that the surface thereof was lower than the surface of the substrate 101. Further, the silicon nitride film as the etching stopper film 112 was formed in self-alignment with the edge portion of the element isolation insulating film 102. Further, the etching stopper film 112 covers the element isolation insulating film 102, that is, the sidewall of the element isolation trench 101a in which the element isolation insulating film 102 is not embedded. Further, a silicide layer was formed on the high-concentration diffusion layer 108. Further, as shown in FIG. 18, similarly to the circuit portion, the etching stopper film 112 was formed so as to cover the edge portion of the element isolation insulating film 102 also in the mark portion.
Etching stopper film 112 formed on the mark portion
Is used as an overlay inspection mark for inspecting the overlay of the resist pattern 123 and the underlying layer (described later). As a result, the same effect as in the second embodiment can be obtained.

Next, a method of manufacturing the semiconductor device according to the third embodiment will be described. 19 to 24 are views for explaining the method of manufacturing the semiconductor device according to the third embodiment. First, the process shown in FIG. 19 is performed. Since the process shown in FIG. 19 is the same as the process shown in FIG. 11 in the second embodiment, description thereof will be omitted.

Next, as shown in FIG. 20, the silicon nitride film 132 and the silicon oxide film 131 are wet-etched. As a result, the element isolation insulating film 1 is formed so that the surface of the element isolation insulating film 102 is lower than the surface of the substrate 101.
02 is formed. Then, as the gate insulating film 103, for example, a silicon oxynitride film (SiON) is formed with a film thickness of 3 nm. Next, a non-doped polysilicon film 104a is formed to a thickness of 100 nm on the gate insulating film 103. Then, the polysilicon film 10 is formed by the same method as in the first embodiment.
N-type and P-type dopants are implanted in 4a. Next, the tungsten film 10 is formed on the polysilicon film 104a.
4b is formed with a film thickness of 100 nm. Further, an insulating film (silicon nitride film) 105 is formed on the tungsten film 104b.
Form at 100 nm. Next, the insulating film 105 is patterned, and the tungsten film 104b and the polysilicon film 104a are patterned using the patterned insulating film 105 as a mask.
Dry etching. Then, for example, arsenic (As ⁺ )
Is injected into the substrate 101 at 30 keV, 1E14 cm ^-2 and 45 degrees to form a low concentration diffusion layer (n-low concentration layer) 106. Then, for example, a silicon nitride film having a film thickness of 50 nm is formed on the entire surface of the substrate and etched back. As a result, the sidewall 107 is formed on the side surface of the gate electrode 104, and the etching stopper film 112 that covers the edge portion of the element isolation insulating film 102 is formed in a self-aligned manner.

Next, as shown in FIG. 21, with the sidewall 107 as a mask, for example, arsenic is added at 50 keV, 5E15 cm ^-2.
The low concentration diffusion layer 1
A high concentration diffusion layer (n + high concentration layer) 108 having an impurity concentration higher than that of 06 is formed. Then, a silicide protection film 136 made of a silicon oxide film is formed on the entire surface of the substrate. Next, a resist pattern (12) which is a mask for patterning the silicide protection film 136 is formed on the silicide protection film 136.
4) is formed. Here, the resist pattern (124)
Is an opening in the portion where the silicide is formed. Further, as shown in FIG. 22, the resist pattern 12
4 is also formed in the mark portion at the same time. After forming the resist pattern 124, the overlay inspection of the resist pattern 124 and the underlying layer is performed using the etching stopper film 112 of the mark portion as an overlay inspection mark. In this overlay inspection, the position of the inspection mark (etching stopper film 112) can be accurately measured. Therefore, the overlay inspection of the resist pattern 124 can be performed accurately. The resist pattern 124 of the mark portion is patterned with a dimension close to the minimum rule of the resist pattern (124) formed in the circuit portion, for example, from the minimum dimension to about twice the minimum dimension. Accordingly, the influence of the aberration of the lens, that is, the aberration due to the difference between the exposure apparatuses can be suppressed, and the accuracy of overlay inspection can be improved.

Next, as shown in FIG. 23, a metal film of cobalt or the like is formed on the entire surface of the substrate and heat treatment (silicidation) is performed. As a result, the silicide layer 125 is formed in the portion not covered with the silicide protection film 136, that is, in the upper layer of the high concentration diffusion layer 108. Then, the silicide protection film 136 is removed by wet etching. Then, as the interlayer insulating film 109, for example, an HDP oxide film is formed with a film thickness of 1000 nm, and the interlayer insulating film 109 is
Polish with mCMP. Then, a resist pattern 134 is formed on the interlayer insulating film 109. Further, using the resist pattern 134 as a mask, the interlayer insulating film 109 is dry-etched under an etching condition having a high selection ratio with respect to the active region 108 and the etching stopper film 112. As a result, a contact hole 120 having a diameter of 0.2 μm on the surface of the interlayer insulating film 109 and reaching from the surface to the surface of the substrate 101 is formed.

Finally, as shown in FIG. 24, barrier metal 121a made of, for example, TiN / Ti is formed in the contact hole 120 to a film thickness of 20 nm / 20 nm, and tungsten 121b is formed to a film thickness of 200 nm by the CVD method. Then, unnecessary tungsten is removed by using the CMP method. As a result, the tungsten plug 121b is formed. That is, the contact 121 including the barrier metal 121a and the tungsten plug 121b is formed in the contact hole 120. In addition, contact 1
21. For example, TiN / Ti with a film thickness of 20/20 nm is formed as the barrier metal 122a, and the tungsten film 122b is formed with a film thickness.
Form at 100 nm. Then, the barrier metal 122a and the tungsten film 122b are patterned. As a result, the second wiring layer 122 is formed on the contact 121.

As described above, in the third embodiment, the boundary between the active region and the element isolation region, that is, the high concentration diffusion layer 10 is formed.
The etching stopper film 112 was formed in a self-aligned manner at the boundary between the element isolation insulating film 102 and the element isolation insulating film 102. As a result, etching damage given to the substrate 101 when forming the contact hole 120 can be reduced. Further, it is possible to form a good contact junction with a small leak current. Further, when the contact hole 120 is formed, the element isolation insulating film 102 at the boundary portion, that is, the edge portion of the element isolation insulating film 102 is not etched into a slit shape, so that the shape of the bottom portion of the contact hole 120 is improved. can do. Therefore, the barrier metal 121a and the tungsten 121b can be formed in the contact hole 120 with good coverage, and the highly reliable contact 121 can be formed.

Further, in the third embodiment, the etching stopper film 112 is simultaneously formed not only in the circuit portion but also in the mark portion. Then, the etching stopper film 112 formed on the mark portion was used as an overlay inspection mark. Since the etching stopper film 112 has a good contrast, the position of the etching stopper film 112, that is, the overlay inspection mark can be easily and accurately measured. Therefore, the overlay inspection can be performed accurately.

In addition, since the etching stopper film 112 is formed in a self-aligned manner in the third embodiment, the number of steps can be reduced as compared with the second embodiment. Therefore, the manufacturing cost of the semiconductor device can be suppressed.

Next, a modification of the semiconductor device according to the third embodiment will be described. FIG. 25 is a sectional view for illustrating the modification of the semiconductor device according to the third embodiment.
The difference from the semiconductor device according to the third embodiment is that after forming the silicide layer 125, the silicon nitride film 126 is formed on the entire surface of the substrate to have a film thickness of 300 nm, for example. By forming the silicon nitride film 126 as in this modification, even if the superposition of the contact holes 120 deviates more than the sidewall width, the shape of the contact holes 120 does not become a slit shape and a good contact is obtained. The holes 120 can be formed.

Fourth Embodiment In the first embodiment described above,
The element isolation insulating film was formed so that the surface of the substrate in the active region and the surface of the element isolation insulating film were at the same height, and the etching stopper film was formed so as to cover the edge portion of the surface of the element isolation insulating film. In the fourth embodiment, the surface of the element isolation insulating film in the circuit portion and the mark portion is made higher than the substrate in the active region, and the etching stopper film is formed at the edge portion of the surface of the element isolation insulating film.

FIG. 26 is a sectional view for illustrating a circuit portion of a semiconductor device according to the fourth embodiment of the present invention. Figure 2
FIG. 7 is a diagram for explaining a mark portion of the semiconductor device according to the fourth embodiment of the present invention. 26 and 27, the same reference numerals as those in FIG. 1 or 2 denote the same parts, and therefore the description thereof will be simplified or omitted.

As shown in FIG. 26, the element isolation insulating film 10
2 was formed so that the surface thereof was higher than the surface of the substrate 101. Further, a silicon nitride film as the etching stopper film 113 was formed so as to cover the edge portion of the element isolation insulating film 102. In addition, as shown in FIG.
Similar to the circuit part, the element isolation insulating film 1 is also formed in the mark part.
The etching stopper film 113 was formed so as to cover the edge portion of 02. The etching stopper film 113 formed in the mark portion is used as an overlay inspection mark for inspecting the overlay of the resist pattern 123 and the underlying layer (described later).

Next, a method of manufacturing the semiconductor device according to the fourth embodiment will be described. 28 to 33 are diagrams for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.

First, as shown in FIG. 28, a thermal oxide film 131 is formed on the substrate 101 to have a film thickness of 30 nm, for example. Next, a silicon nitride film 132 is formed on the thermal oxide film 131, for example, with a thickness of 15
Form at 0 nm. Then, a resist pattern (not shown) covering the active region is formed on the silicon nitride film 132,
Using the formed resist pattern as a mask, the silicon nitride film 132 and the thermal oxide film 131 are dry-etched. Further, the etched silicon nitride film 1
Substrate 101 using 32 and thermal oxide film 131 as a mask
Dry etching. As a result, an element isolation groove 101a having a depth of 300 nm is formed in the substrate 101. Next, the element isolation insulating film 1 is formed in the element isolation groove 101a.
As 02, for example, an HDP oxide film is deposited with a film thickness of 500 nm, and CMP polishing is performed. Then, the element isolation insulating film 102
Is wet-etched to a film thickness of 50 nm, for example.

Next, as shown in FIG. 29, the silicon nitride film 132 and the silicon oxide film 131 are wet-etched. As a result, the element isolation insulating film 1 is formed so that the surface of the element isolation insulating film 102 is higher than the surface of the substrate 101.
02 is formed. Next, the etching stopper 113
Forming a silicon nitride film as a film having a thickness of 30 nm on the entire surface of the substrate. Then, a resist pattern 137 is formed on the etching stopper 113. Here, the resist pattern 137 is formed so as to cover the edge portion of the element isolation insulating film 102.

Next, as shown in FIG. 30, the etching stopper 11 is used with the resist pattern 137 as a mask.
3 is wet-etched. At the same time, the etching stopper 113 in the mark portion is also patterned (see FIG. 3).
1). Next, the resist pattern 137 is removed.
Then, as the gate insulating film 103, for example, a silicon oxynitride film (SiON) is formed with a film thickness of 3 nm. Further, a non-doped polysilicon film 104 is formed on the gate insulating film 103.
a is formed with a film thickness of 100 nm. Next, the polysilicon film 10
4a, a resist pattern 1 which is a mask for injecting an N-type dopant into the polysilicon film 104a.
23 is formed. Further, as shown in FIG. 31, the resist pattern 123 is simultaneously formed on the mark portion. After forming the resist pattern 123, the overlay inspection of the resist pattern 123 and the underlying layer is performed using the etching stopper film 113 of the mark portion as an overlay inspection mark. In this overlay inspection, the position of the etching stopper film 113 as an inspection mark can be accurately measured. Therefore, the overlay inspection of the resist pattern 123 can be performed accurately. The resist pattern 123 of the mark portion is patterned with a dimension close to the minimum rule of the resist pattern 123 formed in the circuit portion. As a result, the influence of lens aberration can be suppressed, and the accuracy of overlay inspection can be improved.

Then, similarly to the first embodiment, N-type and P-type dopants are implanted into the polysilicon film 104a.

Next, as shown in FIG. 32, a tungsten film 104b is formed to a thickness of 100 nm on the polysilicon film 104a. Then, the insulating film 105 is formed to have a film thickness of 100 nm. Next, the insulating film 105 is patterned, and the tungsten film 104b and the polysilicon film 104a are dry-etched using the patterned insulating film 105 as a mask. As a result, the gate electrode 104 is formed. Then, the low concentration diffusion layer (n-low concentration layer) 106 is
For example, arsenic (As ⁺ ) at 30keV, 1E14cm ^-2 , 45 degree substrate 1
It is formed by injecting into 01. Then, for example, a silicon nitride film having a film thickness of 50 nm is formed on the entire surface of the substrate and etched back. As a result, the sidewall 107 is formed on the side surface of the gate electrode 104. Furthermore, using the sidewall 107 as a mask, for example, arsenic is 50 keV, 5E15 cm.
By implanting into the substrate 101 at ^-2 , a high concentration diffusion layer (n + high concentration layer) 108 having an impurity concentration higher than that of the low concentration diffusion layer 106 is formed. Next, for example, an HDP oxide film having a film thickness of 1000 nm is formed as the interlayer insulating film 109, and the interlayer insulating film 109 is CMP-polished by a film thickness of 300 nm. And
A resist pattern 134 is formed on the interlayer insulating film 109.

Then, using the resist pattern 134 as a mask, under the etching (main etching) condition having a high selection ratio with respect to the etching stopper film 113,
The interlayer insulating film 109 is dry-etched. As a result, a contact hole 120 having a diameter of 0.2 μm on the surface of the interlayer insulating film 109 and reaching the surface of the etching stopper 113 from the surface is formed. here,
Even when a plurality of contact holes having different depths are simultaneously formed by performing etching under a condition having a high selectivity with respect to the etching stopper 113, that is, a high selectivity with respect to the silicon nitride film, the active region of the substrate 101 is formed. Does not give etching damage. Further, the etching stopper 113 is etched under an etching (over etching) condition having a high selection ratio with respect to the element isolation insulating film 102 and the substrate 101. As a result, a contact hole 120 reaching from the surface of the interlayer insulating film 109 to the surface of the substrate 101 is formed. Here, the etching stopper film 113 that is uniform and has a relatively thin film thickness
Can be removed in a short time. That is, the substrate 101 is formed by forming the contact hole 120 in two steps.
Further, etching damage to the element isolation insulating film 102 can be reduced. Further, the etching stopper 1 is provided at the boundary between the high-concentration diffusion layer 108 and the element isolation insulating film 102.
By forming 13, the edge portion of the element isolation insulating film 102 can be prevented from being etched.

Finally, as shown in FIG. 33, a barrier metal 121a made of, for example, TiN / Ti is formed in the contact hole 120 with a film thickness of 20 nm / 20 nm, and further, a tungsten 121b is formed with a film thickness of 200 nm by the CVD method. Then, unnecessary tungsten is removed by using the CMP method. As a result, the tungsten plug 121b is formed. That is, the contact 121 including the barrier metal 121a and the tungsten plug 121b is formed in the contact hole 120. In addition, contact 1
21. For example, TiN / Ti with a film thickness of 20/20 nm is formed as the barrier metal 122a, and the tungsten film 122b is formed with a film thickness.
Form at 100 nm. Then, the barrier metal 122a and the tungsten film 122b are patterned. As a result, the second wiring layer 122 is formed on the contact 121.

As described above, in the fourth embodiment, the boundary between the active region and the element isolation region, that is, the high concentration diffusion layer 10 is formed.
A silicon nitride film as an etching stopper film 113 was formed at the boundary between the element isolation insulating film 102 and the element isolation insulating film 102. As a result, etching damage given to the substrate 101 when the contact hole 120 is formed (particularly during overetching) can be reduced. Therefore, a good contact junction with a small leak current can be formed. Further, when the contact hole 120 is formed, the element isolation insulating film 102 at the boundary portion, that is, the edge portion of the element isolation insulating film 102 is not etched into a slit shape, so that the shape of the bottom portion of the contact hole 120 is improved. can do. Therefore, the barrier metal 121a and the tungsten 1 are formed in the contact hole 120.
21b can be formed with good coverage, and a good contact 121 with high reliability can be formed.

Further, in the fourth embodiment, the etching stopper film 113 is simultaneously formed not only in the circuit portion but also in the mark portion. Then, the etching stopper film 113 formed on the mark portion was used as an overlay inspection mark. Since the etching stopper film 113 has a good contrast, the position of the etching stopper film 113, that is, the position of the overlay inspection mark can be easily and accurately measured. Therefore, the overlay inspection of the resist pattern (for example, the resist pattern 123 shown in FIG. 30) and the underlying layer (lower layer pattern) can be accurately performed.

In the fourth embodiment, the element isolation insulating film 102 is formed so that the surface of the element isolation insulating film 102 is higher than the surface of the active region. With such a structure, the reverse narrow can be suppressed and the leakage current can be suppressed in the DRAM part of the eDRAM (the same applies to the fifth embodiment described later).

In the fourth embodiment, the surface of the element isolation insulating film 102 is made higher than the surface of the substrate 101 by adjusting the wet etching amount of the element isolation insulating film 102. However, the element isolation insulating film 102 is wet. It need not be etched. In addition to this, the element isolation insulating film 102 can be made to protrude by arranging the CMP dummy patterns densely in the vicinity of the element isolation insulating film 102.

Embodiment 5. In the fourth embodiment described above,
The surface of the element isolation insulating film in the circuit portion and the mark portion was formed to be higher than the substrate in the active region, and an etching stopper film was formed on the edge portion of the surface of the element isolation insulating film by patterning. In the fifth embodiment, the surface of the element isolation insulating film in the circuit portion and the mark portion is formed to be higher than the substrate in the active region, and only the edge portion of the surface of the element isolation insulating film is etched in a self-aligned manner. A stopper film was formed. Further, in the fifth embodiment, a silicide layer is formed on the high concentration diffusion layer.

FIG. 34 is a sectional view for illustrating the circuit portion of the semiconductor device according to the fifth embodiment of the present invention. Figure 3
FIG. 5 is a diagram for explaining a mark portion of a semiconductor device according to a fifth embodiment of the present invention. 34 and 35, the same reference numerals as those in FIG. 26 or FIG. 27 indicate the same parts, and therefore the description thereof will be simplified or omitted.

As shown in FIG. 34, the element isolation insulating film 10
2 was formed so that the surface thereof was higher than the surface of the substrate 101. Further, a silicon nitride film as the etching stopper film 114 was formed in a self-aligned manner so as to cover the edge portion of the element isolation insulating film 102. Further, as shown in FIG. 35, the etching stopper film 114 was formed so as to cover the edge portion of the element isolation insulating film 102 in the mark portion as well as in the circuit portion. The etching stopper film 114 formed on the mark portion is the resist pattern 1
It is used as an overlay inspection mark for inspecting overlay of 24 and the base layer (described later).

Next, a method of manufacturing the semiconductor device according to the fifth embodiment will be described. 36 to 41 are views for explaining the method of manufacturing the semiconductor device according to the fifth embodiment. First, the process shown in FIG. 36 is performed. Since the process shown in FIG. 36 is the same as the process shown in FIG. 28 in the fourth embodiment, description thereof will be omitted.

Next, as shown in FIG. 37, the silicon nitride film 132 and the silicon oxide film 131 are wet-etched. Thus, the surface of the element isolation insulating film 102 is made higher than the surface of the substrate 101 so that the element isolation insulating film 1
02 is formed. Then, as the gate insulating film 103, for example, a silicon oxynitride film (SiON) is formed with a film thickness of 3 nm. Next, a non-doped polysilicon film 104a is formed to a thickness of 100 nm on the gate insulating film 103. Then, the polysilicon film 10 is formed by the same method as in the first embodiment.
N-type and P-type dopants are implanted in 4a. Next, the tungsten film 10 is formed on the polysilicon film 104a.
4b is formed with a film thickness of 100 nm. Further, an insulating film (silicon nitride film) 105 is formed on the tungsten film 104b.
Form at 100 nm. Next, the insulating film 105 is patterned, and the tungsten film 104b and the polysilicon film 104a are patterned using the patterned insulating film 105 as a mask.
Dry etching. Then, for example, arsenic (As ⁺ )
Is injected into the substrate 101 at 30 keV, 1E14 cm ^-2 and 45 degrees to form a low concentration diffusion layer (n-low concentration layer) 106. Then, for example, a silicon nitride film having a film thickness of 50 nm is formed on the entire surface of the substrate and etched back. As a result, the sidewall 107 is formed on the side surface of the gate electrode 104, and the etching stopper film 114 that covers the edge portion of the element isolation insulating film 102 is formed in a self-aligned manner.

Next, as shown in FIG. 38, arsenic is used at 50 keV, 5E15 cm ^-2 with the sidewall 107 as a mask.
The low concentration diffusion layer 1
A high concentration diffusion layer (n + high concentration layer) 108 having an impurity concentration higher than that of 06 is formed. Then, the silicide protection film 13 made of a silicon oxide film is formed on the entire surface of the substrate 101.
6 is formed. Next, the silicide protection film 13
On the resist pattern (1) which is a mask for patterning the silicide protection film 136.
24) is formed. Here, the resist pattern (12
In 4), the portion forming the silicide is opened. In addition, as shown in FIG. 39, the resist pattern 1
24 is also formed in the mark portion at the same time. After forming the resist pattern 124, an overlay inspection of the resist pattern 124 and the underlying layer is performed using the etching stopper film 114 of the mark portion as an overlay inspection mark. In this overlay inspection, the position of the etching stopper film 112 as an inspection mark can be accurately measured. Therefore, the overlay inspection of the resist pattern 124 can be performed accurately. The resist pattern 124 of the mark portion has a dimension close to the minimum rule of the resist pattern (124) formed in the circuit portion,
For example, the patterning is performed with the minimum dimension to about twice the minimum dimension. Thereby, the influence of the aberration of the lens, that is, the aberration due to the difference between the exposure apparatuses can be suppressed, and the accuracy of overlay inspection can be improved.

Next, as shown in FIG. 40, a metal film of cobalt or the like is formed on the entire surface of the substrate and heat treatment (silicidation) is performed. As a result, the silicide layer 125 is formed in the portion not covered with the silicide protection film 136, that is, in the upper layer of the high concentration diffusion layer 108. Then, the silicide protection film 136 is removed by wet etching. Then, as the interlayer insulating film 109, for example, an HDP oxide film is formed with a film thickness of 1000 nm, and the interlayer insulating film 109 is
Polish with mCMP. Then, a resist pattern 134 is formed on the interlayer insulating film 109. Further, using the resist pattern 134 as a mask, the interlayer insulating film 109 is dry-etched under an etching condition having a high selection ratio with respect to the active region 108 and the etching stopper film 114. As a result, a contact hole 120 having a diameter of 0.2 μm on the surface of the interlayer insulating film 109 and reaching from the surface to the surface of the substrate 101 is formed.

Finally, as shown in FIG. 41, a barrier metal 121a made of, for example, TiN / Ti is formed in the contact hole 120 to a film thickness of 20 nm / 20 nm, and further, a tungsten 121b is formed to a film thickness of 200 nm by the CVD method. Then, unnecessary tungsten is removed by using the CMP method. As a result, the tungsten plug 121b is formed. That is, the contact 121 including the barrier metal 121a and the tungsten plug 121b is formed in the contact hole 120. In addition, contact 1
21. For example, TiN / Ti with a film thickness of 20/20 nm is formed as the barrier metal 122a, and the tungsten film 122b is formed with a film thickness.
Form at 100 nm. Then, the barrier metal 122a and the tungsten film 122b are patterned. As a result, the second wiring layer 122 is formed on the contact 121.

As described above, in the fifth embodiment, the boundary between the active region and the element isolation region, that is, the high concentration diffusion layer 10 is formed.
8 and the element isolation insulating film 102 were formed with an etching stopper film 114 in a self-aligned manner. As a result, etching damage given to the substrate 101 when forming the contact hole 120 can be reduced. Further, it is possible to form a good contact junction with a small leak current. Further, when the contact hole 120 is formed, the element isolation insulating film 102 at the boundary portion, that is, the edge portion of the element isolation insulating film 102 is not etched into a slit shape, so that the shape of the bottom portion of the contact hole 120 is improved. can do. Therefore, the barrier metal 121a and the tungsten 121b can be formed in the contact hole 120 with good coverage, and the highly reliable contact 121 can be formed.

Further, in the fifth embodiment, the etching stopper film 114 is simultaneously formed not only in the circuit portion but also in the mark portion. Then, the etching stopper film 114 formed in the mark portion was used as an overlay inspection mark. Since the etching stopper film 114 has a good contrast, the position of the etching stopper film 114, that is, the overlay inspection mark can be easily and accurately measured. Therefore, the overlay inspection of the resist pattern (124) and the underlying layer can be accurately performed.

Further, in the fifth embodiment, since the etching stopper film 114 is formed in a self-aligned manner, the number of steps can be reduced as compared with the fourth embodiment. Therefore, the manufacturing cost of the semiconductor device can be suppressed.

Next, a modification of the semiconductor device according to the fifth embodiment will be described. FIG. 42 is a sectional view for illustrating the modification of the semiconductor device according to the fifth embodiment.
The difference from the semiconductor device according to the fifth embodiment is that after forming the silicide layer 125, the silicon nitride film 126 is formed with a film thickness of, for example, 300 nm on the entire surface of the substrate. By forming the silicon nitride film 126 as in this modification, even if the superposition of the contact holes 120 deviates more than the sidewall width, the shape of the contact holes 120 does not become a slit shape and a good contact is obtained. The holes 120 can be formed.

[0102]

According to the present invention, the element isolation insulating film is not etched when the contact hole is formed by the etching stopper film covering the edge portion of the element isolation insulating film. This makes it possible to form a highly reliable contact plug. Further, an etching stopper film was formed on the element isolation insulating film in the mark portion, and the etching stopper film was used as an inspection mark. Therefore, the inspection mark can be accurately formed.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a circuit portion of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view for illustrating a mark portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining the manufacturing method for the semiconductor device according to the first embodiment of the present invention (No. 1).

FIG. 4 is a diagram for explaining the manufacturing method for the semiconductor device according to the first embodiment of the present invention (No. 2).

FIG. 5 is a diagram for explaining the manufacturing method for the semiconductor device according to the first embodiment of the present invention (No. 3).

FIG. 6 is a diagram for explaining the manufacturing method for the semiconductor device according to the first embodiment of the present invention (No. 4).

FIG. 7 is a diagram for explaining the manufacturing method for the semiconductor device according to the first embodiment of the present invention (No. 5).

FIG. 8 is a diagram for explaining the manufacturing method for the semiconductor device according to the first embodiment of the present invention (No. 6).

FIG. 9 is a sectional view for illustrating a circuit portion of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a diagram for explaining a mark portion of the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a diagram for explaining the manufacturing method for the semiconductor device according to the second embodiment of the present invention (No. 1).

FIG. 12 is a diagram for explaining the manufacturing method for the semiconductor device according to the second embodiment of the present invention (No. 2).

FIG. 13 is a diagram for explaining the manufacturing method for the semiconductor device according to the second embodiment of the present invention (No. 3).

FIG. 14 is a diagram for explaining the manufacturing method for the semiconductor device according to the second embodiment of the present invention (No. 4).

FIG. 15 is a diagram for explaining the manufacturing method for the semiconductor device according to the second embodiment of the present invention (No. 5).

FIG. 16 is a drawing for explaining the manufacturing method for the semiconductor device according to the second embodiment of the present invention (No. 6).

FIG. 17 is a sectional view for illustrating a circuit portion of a semiconductor device according to a third embodiment of the present invention.

FIG. 18 is a diagram for explaining a mark portion of the semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a diagram for explaining the manufacturing method for the semiconductor device according to the third embodiment of the present invention (No. 1).

FIG. 20 is a diagram for explaining the manufacturing method for the semiconductor device according to the third embodiment of the present invention (No. 2).

FIG. 21 is a diagram for explaining the manufacturing method for the semiconductor device according to the third embodiment of the present invention (No. 3).

FIG. 22 is a diagram for explaining the manufacturing method for the semiconductor device according to the third embodiment of the present invention (No. 4).

FIG. 23 is a diagram for explaining the manufacturing method for the semiconductor device according to the third embodiment of the present invention (No. 5).

FIG. 24 is a diagram for explaining the manufacturing method for the semiconductor device according to the third embodiment of the present invention (No. 6).

FIG. 25 is a sectional view for illustrating a modification of the semiconductor device according to the third embodiment of the present invention.

FIG. 26 is a sectional view for illustrating a circuit portion of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 27 is a diagram for explaining a mark portion of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 28 is a diagram for explaining the manufacturing method for the semiconductor device according to the fourth embodiment of the present invention (No. 1).

FIG. 29 is a diagram for explaining the manufacturing method for the semiconductor device according to the fourth embodiment of the present invention (No. 2).

FIG. 30 is a diagram for explaining the manufacturing method for the semiconductor device according to the fourth embodiment of the present invention (No. 3).

FIG. 31 is a diagram for explaining the manufacturing method for the semiconductor device according to the fourth embodiment of the present invention (No. 4).

FIG. 32 is a diagram for explaining the manufacturing method for the semiconductor device according to the fourth embodiment of the present invention (No. 5).

FIG. 33 is a diagram for explaining the manufacturing method for the semiconductor device according to the fourth embodiment of the present invention (No. 6).

FIG. 34 is a sectional view for illustrating a circuit portion of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 35 is a diagram for explaining a mark portion of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 36 is a diagram for explaining the manufacturing method for the semiconductor device according to the fifth embodiment of the present invention (No. 1).

FIG. 37 is a diagram for explaining the manufacturing method for the semiconductor device according to the fifth embodiment of the present invention (No. 2).

FIG. 38 is a diagram for explaining the manufacturing method for the semiconductor device according to the fifth embodiment of the present invention (No. 3).

FIG. 39 is a diagram for explaining the manufacturing method for the semiconductor device according to the fifth embodiment of the present invention (No. 4).

FIG. 40 is a diagram for explaining the manufacturing method for the semiconductor device according to the fifth embodiment of the present invention (No. 5).

FIG. 41 is a view for explaining the manufacturing method for the semiconductor device according to the fifth embodiment of the present invention (No. 6).

FIG. 42 is a sectional view for illustrating the modification of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 43 is a cross-sectional view illustrating a circuit portion of a conventional semiconductor device.

FIG. 44 is a diagram for explaining a mark portion of a conventional semiconductor device.

[Explanation of symbols]

101 substrate (semiconductor substrate), 101a element isolation groove, 102 element isolation insulating film (HDP oxide film), 1
03 gate insulating film (silicon oxide film), 104 gate electrode, 104a polysilicon film, 104b
Tungsten film, 105 insulating film, 106 low concentration diffusion layer (n−low concentration layer), 107 sidewall (silicon nitride film), 108 high concentration diffusion layer (n + high concentration layer), 109 interlayer insulating film (HDP oxide film) , 11
0,111,112,113,114 Etching stopper film (silicon nitride film), 120 contact hole, 121 contact (contact plug),
121a barrier metal, 121b tungsten plug, 122 second wiring layer, 122a barrier metal, 122b tungsten film, 123 resist pattern, 124 resist pattern, 125 silicide layer, 126 silicon nitride film, 131 thermal oxide film, 132 silicon nitride film, 133 , 134, 1
35, 137 resist pattern, 136 silicide protection film.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/08 331 H01L 29/78 301R 27/088 21/30 502M 29/78 F term (reference) 5F032 AA35 AA44 AA46 AA77 AA79 BA01 CA17 DA23 DA24 DA28 DA33 5F046 EA14 EB05 EB10 5F048 AA04 AA07 AB01 AC03 BA01 BB06 BB08 BF06 BF06 BF06 BF06 BF16 BF11 BF14 BF11 BF16 BF11 BF16 BF11 BF11 BJ17 BJ20 BJ27 BK01 BK13 BK14 BK27 BK30 CA02 CA03 CB04 CB10 CC01 CC03 CC08 CE06 CE07 CE20

Claims (20)

[Claims] 1. A method of manufacturing a semiconductor device having a circuit portion including an element isolation region for isolating an active region and a mark portion on a substrate, wherein an element isolation groove is formed in the element isolation region and the mark portion. A step of forming an element isolation insulating film in the element isolation trench, a step of forming an etching stopper film so as to cover at least an edge portion of the element isolation insulating film, and the step of forming the mark portion And a step of forming a circuit element in the circuit portion by using an etching stopper film as an inspection mark. 2. The manufacturing method according to claim 1, wherein the step of forming the circuit element includes a step of forming a gate insulating film on the substrate, and a step of forming a conductive film on the gate insulating film. A step of forming a first resist pattern on the conductive film; and a step of implanting an impurity into the conductive film using the first resist pattern as a mask. A method of manufacturing a semiconductor device, wherein the etching stopper film formed on the mark portion is used as an inspection mark. 3. The manufacturing method according to claim 1, wherein the step of forming the circuit element includes the step of forming a silicide protection film on the substrate, and the step of forming a second resist pattern on the silicide protection film. And a step of patterning the silicide protection film using the second resist pattern as a mask; and a step of forming a silicide layer on the upper layer of the substrate using the patterned silicide protection film as a mask, A method of manufacturing a semiconductor device, wherein the etching stopper film formed in the mark portion is used as an inspection mark in the step of forming a second resist pattern. 4. A method of manufacturing a semiconductor device having a circuit portion including an element isolation region for isolating an active region and a mark portion on a substrate, wherein an element isolation groove is formed in the element isolation region and the mark portion. A step of forming an element isolation insulating film in the element isolation groove, a step of forming a gate electrode in the active region, and a step of forming an impurity diffusion layer in the substrate adjacent to the gate electrode. A step of forming an insulating film on the entire surface of the substrate after forming the impurity diffusion layer, and a step of etching back the insulating film to form an etching stopper film covering an edge portion of the element isolation insulating film. And a step of forming a circuit element in the circuit part using the etching stopper film formed in the mark part as an inspection mark. Production method. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the etching stopper film is formed, and a sidewall is formed on a side surface of the gate electrode. 6. The manufacturing method according to claim 4, wherein the step of forming the circuit element includes a step of forming a silicide protection film on the substrate, and a step of forming a first resist pattern on the silicide protection film. A step of forming the silicide protection film using the first resist pattern as a mask, and a step of forming a silicide layer on the upper layer of the substrate using the patterned silicide protection film as a mask. A method of manufacturing a semiconductor device, wherein the etching stopper film formed on the mark portion is used as an inspection mark in the step of forming the first resist pattern. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the etching stopper film is formed in a self-aligned manner. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the inspection marks are alignment inspection marks and overlay inspection marks. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the etching stopper film includes a silicon nitride film. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the etching stopper film further includes a silicon oxide film below the silicon nitride film. 11. The manufacturing method according to claim 1, wherein a step of forming an interlayer insulating film on the entire surface of the substrate so as to cover the circuit element, and a step of forming a layer of the substrate from the surface of the interlayer insulating film. A method of manufacturing a semiconductor device, further comprising: a step of forming a contact hole reaching the surface; and a step of forming a contact plug in the contact hole. 12. The manufacturing method according to claim 1, wherein the element isolation insulating film is formed in the element isolation trench so that its surface is lower than the surface of the substrate. And a method for manufacturing a semiconductor device. 13. The manufacturing method according to claim 1, wherein the element isolation insulating film is formed in the element isolation trench so that its surface is higher than the surface of the substrate. And a method for manufacturing a semiconductor device. 14. A semiconductor device manufactured by using the manufacturing method according to claim 1. Description: 15. A semiconductor device having, on a substrate, a circuit portion including an element isolation region for isolating an active region, and a mark portion, the element isolation groove formed in the mark portion, and the element isolation groove. An element isolation insulating film formed therein, an etching stopper film covering at least a part of the surface of the element isolation insulating film, an interlayer insulating film formed on the entire surface of the substrate, and a surface of the interlayer insulating film from the surface of the interlayer insulating film. A semiconductor device comprising: a contact hole reaching the surface of the substrate. 16. The semiconductor device according to claim 15, wherein the element isolation trench, the element isolation insulating film, and the etching stopper film are further formed in the element isolation region of the circuit portion, and the contact hole is formed. A semiconductor device further formed in the active region of the circuit unit. 17. The semiconductor device according to claim 16, wherein the etching stopper film formed in the element isolation region covers an edge portion of the element isolation insulating film. 18. The semiconductor device according to claim 15, wherein the etching stopper film includes a silicon nitride film. 19. The semiconductor device according to claim 15, wherein the element isolation insulating film is formed in the element isolation trench so that its surface is lower than the surface of the substrate. Characteristic semiconductor device. 20. The semiconductor device according to claim 15, wherein the element isolation insulating film is formed in the element isolation trench so that its surface is higher than the surface of the substrate. A method for manufacturing a characteristic semiconductor device.