JP2003006864A - Optical disk apparatus and optical disk recording method - Google Patents

Abstract

(57) [Problem] To provide an optical disk device that can obtain an appropriate recording compensation amount with a small-scale configuration even for an optical disk device of a PRML signal processing method. SOLUTION: The optical disk is irradiated with a laser beam to write test sample data in a predetermined area, and then read the test write mechanism 21, 22, 23, PU, 11
To 14, a compensation amount control circuit 20 for determining a compensation amount of a recording waveform pulse for recording processing based on the read reproduction data S, and a recording waveform pulse P based on the write data R and the decided compensation amount. An optical disc apparatus comprising: a recording pulse control circuit 21 for generating the recording pulse data; and recording mechanisms 21, 22, PU for irradiating a recording area of the optical disc with a laser beam generated in response to the recording pulse control circuit 21 to record write data R.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laser beam waveform compensation method in, for example, an optical disk device, and more particularly to a waveform compensation method accompanied with PRML signal processing.

[0002]

2. Description of the Related Art Recently, DVD (Digital Versatile Dis)
Optical disk devices for performing recording / playback processing on optical disks such as c) have become widespread, and have been developed and manufactured under various specifications. Under such circumstances, for example, a technique for compensating the recording waveform pulse that makes the recording characteristics different according to the characteristics of each optical disk is required to have higher performance.

When high density mark length recording is performed in an optical disk device, thermal interference between adjacent marks causes
The recording condition is adversely affected. As a measure against this,
Japanese Patent Laying-Open No. 2000-90436 discloses the following technique. That is, information related to recording (a binarized signal related to the space before and after a recording mark, etc.) is reproduced from the optical disc, and the recording parameters (position / phase, width or height of the pulse before and after the recording waveform are recorded on the disc based on the reproduced information. Waveform correction amount) related to. Recording data RD based on the calculated recording parameters
Of the recording waveform pulse RWP. By recording on the disc by the generated recording waveform, the influence of thermal interference is reduced.

Furthermore, in Japanese Patent Laid-Open No. 2000-200418, the following measures are taken. That is, a standard recording pulse condition that specifies the position of the recording pulse is read from a writable optical disc for a plurality of possible combinations of mark length and space length, and test writing is performed under this standard recording pulse condition. Then, the recording pulse standard condition is uniformly or individually changed to obtain the optimum recording pulse condition to reduce the jitter.

Furthermore, "Matsushita Technical Journal
Vol. 45 NO.6 Dec. 1999 P.72 ”discloses the following device. That is, the mark front edge compensation operation that changes the laser irradiation start position for each combination of the self mark length and the front space length, and the mark rear edge compensation operation that changes the laser irradiation end position for each combination of the self mark length and the rear space length. I do. And
The laser irradiation position where the jitter of the mark edge is minimized is searched for, is determined as a table value, and recording compensation is performed using this value.

In the conventional optical disk device, the influence of the thermal interference and the countermeasure against the background of the present invention will be described in detail below. When performing mark length recording on an information recording medium using a phase change recording method, when the recording density becomes high and the distance between adjacent marks becomes small, laser heating for recording on the medium due to phase change causes a gap between adjacent marks. Thermal interference occurs. Therefore, the position of the edge of the recorded mark is displaced. When the mark having the shifted edge is reproduced, the reproduced signal is distorted and the read error rate is deteriorated.

As shown in FIG. 22, a laser beam for recording a mark is divided into pulse trains called multi-pulses and is irradiated. FIG. 22 is a waveform diagram showing an example of multi-pulses used in the optical disc device. In order to avoid thermal interference, the width of the leading pulse of the multi-pulse for recording the mark is changed depending on the relationship between the recorded mark length and the space before the mark. Similarly, the width of the final pulse of the multi-pulse for recording the mark is changed depending on the relationship between the recorded mark length and the space after the mark. As a result, the mark deviation due to thermal interference is corrected and recorded in advance. The correction amount (that is, the recording compensation amount) can take different values depending on the combination of the mark length and the spaces before and after the mark. Therefore, the recording compensation amount is determined using the table shown in FIG. In this table, T is the cycle of the channel clock CLK.

In an actual device, a table containing the conditions for performing this recording compensation is stored in a specific area of the device or disk, but it is stored due to variations in characteristics during mass production or changes in the environment. The recorded recording compensation amount is not always an appropriate value. Therefore, in the high-density recording / reproducing optical disk device, when recording information on a new recording medium, the values in the table are updated by trial writing so that an appropriate recording compensation amount is obtained.

FIG. 24 is a block diagram showing an outline of a system for updating the values in the table so that the recording compensation amount becomes appropriate by trial writing. In FIG. 24, the recording / reproducing unit uses a binarized signal and a channel clock CLK during reproduction.
Is supplied to the parameter calculation unit. The parameter calculator
Based on the supplied binarized signal and channel clock CLK, the deviation of the front and rear edges of the mark is detected, and the recording compensation amount is calculated. The obtained compensation amount is supplied to the pulse position / width control unit in the recording waveform. The pulse position / width control unit receives recording data from the outside and generates a recording waveform that does not cause thermal interference based on the supplied compensation amount. This recording waveform is shared by the recording / reproducing unit, and the recording laser light beam corresponding to the recording waveform pulse is applied to a predetermined portion of the phase change recording layer of the recording medium.

FIG. 25 is a block diagram showing an example of the internal structure of the recording / reproducing section of the system shown in FIG.
FIG. 26 is a block diagram showing an example of the internal configuration of the parameter calculation unit of the system shown in FIG. In the initial state immediately after the medium is inserted, the initial value of the recording compensation amount table is the value stored in the specific area of the device or the disc. The quantity is used to record a random series of data on the medium. The binarized signal corresponding to the reproduced signal of the recorded data and the channel clock CLK are input to the pattern determination unit and the edge phase difference pulse generation unit in the parameter calculation unit. In order to evaluate the amount of deviation between the leading edge and the trailing edge of the mark, the edge phase difference pulse generator generates the rising and falling edges of the binarized signal and the channel clock CLK.
Pulse with a width proportional to the phase difference between
The voltage conversion unit (T-V conversion) converts the voltage value. The parameter calculation unit inputs a voltage value proportional to the phase difference between the front space length, the mark length, and the rear space length determined by the pattern determination unit, and inputs each edge and the channel clock CL.
The value of the recording compensation table is updated by obtaining the average value of the phase difference (= jitter) from K.

Writing using the updated value of the recording compensation amount table and updating of the recording compensation table by reproducing the same are repeated until the value of the jitter of the mark to be recorded becomes a predetermined value or less.

[0012]

However, in the conventional apparatus, the position of the recording pulse at which the jitter of the mark edge becomes equal to or less than a predetermined value is used for the recording compensation, but this method is used for a large-capacity disk having a high recording density. P used in the device
Even if the PRML signal processing method is applied to the RML signal processing method, the PRML signal processing method is a method of performing signal processing with the amplitude value of the identification point at a discrete time point synchronized with the channel clock. “Jitter”, which is the amount of slice position deviation, cannot be used as an evaluation criterion. Therefore, in the recording / reproducing disk device of the PRML signal processing system, it becomes impossible to perform learning for adaptive recording compensation as in the conventional case, and there arises a problem that proper recording marks cannot be formed on the disk medium. Furthermore, there is also a problem that a dedicated circuit only for updating a table containing conditions for performing recording compensation needs to be provided separately from the reproduction signal processing circuit.

The present invention has been made with the intention of solving such a problem, and is suitable for an optical disk apparatus of the PRML signal processing system, which has a small structure and can obtain an appropriate recording compensation amount. The purpose is to provide a device.

[0014]

In order to solve the above-mentioned problems, the present invention provides an optical disk apparatus for recording data on an optical disk having a concentric circular or spiral recording area, wherein the optical disk is rotated at a predetermined rotational speed. Means for irradiating the rotating optical disk with a laser beam on the rotating optical disk to test-write predetermined data in a predetermined area, and then read the test-written predetermined data, and the trial-writing means. Compensation amount determining means for determining a compensation amount of a recording waveform pulse for recording processing based on the read predetermined data, and the compensation determined by the compensation amount determining means by subjecting recording data received from the outside to predetermined processing. A recording waveform pulse is generated based on the amount, and the laser beam generated in response to the pulse is irradiated to the recording area of the optical disc to record the recording data. An optical disk apparatus characterized by comprising a recording means.

According to the present invention having the above-mentioned structure, the amount of deviation of the mark edge due to thermal interference is compared with the ideal equalization value of the reproduction signal sample point at the discrete time sampled by the clock synchronized with the written data. It is evaluated by the amount of deviation. As a result, it is not necessary to evaluate the amount of edge jitter in the time direction, and it is possible to update the table containing the recording compensation conditions even in the PRML signal processing method.

Further, in the present invention, the above-mentioned compensation amount determining means is
It has phase comparison means for receiving the predetermined data read by the trial writing means and a channel clock corresponding to the predetermined data and outputting phase difference signals thereof, and based on this phase difference signal,
An optical disk device characterized by determining a compensation amount of a recording waveform pulse for a recording process.

According to the present invention, the signal for evaluating the deviation amount of the mark edge is supplied from the phase comparator of the PRML signal processing system by the above-mentioned configuration. This allows
Many memory areas for securing the sample data in the time direction for evaluating in the time direction and for evaluating this in the recording compensation amount control circuit, which had to be provided when the output of the phase comparator was not used. Is unnecessary.
Thus, the circuit scale for controlling the recording compensation amount can be reduced, and by providing the output of the phase comparator, it is possible to provide an optical disk device capable of performing the same recording compensation amount control with a small-scale configuration. Is possible.

[0018]

DETAILED DESCRIPTION OF THE INVENTION An optical disk device according to the present invention will be described in detail below with reference to the drawings.

<< First Embodiment >> The first embodiment presents a control method of a recording compensation amount that can be compatible with a PRML signal processing system, and uses a phase difference output of a phase comparator. The present invention provides an optical disk device that determines a recording compensation amount.

<Structure of Optical Disk Device and Data Processing Unit> FIG. 1 is a block diagram showing a part of a reproduction signal processing section and a writing control section in an example of an optical disk recording / reproducing apparatus using the PRML signal processing system according to the present invention. FIG. 2 is a block diagram showing the overall configuration of an example of an optical disc device according to the present invention.

(Structure of Optical Disk Device) In FIG.
The optical disk device A according to the present invention records data on or reproduces data from the optical disk D. The optical disk device A includes a tray 32 that carries an optical disk D housed in a disk cartridge, a motor 33 that drives the tray, and a clamper 3 that holds the optical disk D.
4 and a spindle motor 35 for rotating the optical disc D held thereby by a predetermined number of revolutions. Further, a CPU 46 that controls the entire operation as a control unit,
ROM storing basic programs for this control operation
47 and a RAM 48 rewritably storing each control program, application data, etc. are connected via a control bus. Further, they are respectively connected to control units such as the CPU 46 and drive a feed motor 36 for carrying the pickup PU, a focus / tracking actuator driver / feed motor driver 40 for carrying out focus and tracking control of the pickup, and a spindle motor 35. Spindle motor driver 41,
A tray motor driver 42 that drives the tray motor is provided.

Furthermore, a preamplifier 11 connected to the pickup PU for amplifying a detection signal, a servo amplifier 38,
Further, it has a servo seek control unit 39 for supplying a seek signal for performing a seek operation to the driver.
Further, the pickup PU, the preamplifier 11, the servo seek control unit 39 and the like are provided with a data processing unit 1 for processing a detection signal and a recording signal, and a RAM 43 for storing data used for these various processes. In order to transmit / receive the signal from the data processing unit 1 to / from an external device, the interface control unit 45
Are provided together with the RAM 44.

(Structure of Data Processing Unit) In such an optical disk device, according to the present invention, by forming the data processing unit 1 as shown in FIG. 1, proper waveform compensation is performed even when a digital method is used as an identification method. The function is enabled. That is, in FIG.
The preamplifier 11 that receives a signal from the unit PU is connected to the analog filter 12, and the analog filter 1
2 is connected to the A / D converter 13. Further, the A / D converter 13 is connected to a digital FIR filter 14 which is a waveform equalizer, which in turn is connected to a Viterbi detector 15 which is a maximum likelihood detector, and is connected to a subsequent signal processing unit (not shown). There is. Further, the digital FIR filter 14 is connected to supply the reproduction signal S to the phase comparator 16, which includes the loop filter 17,
The phase difference signal τ is supplied to each of the recording compensation amount control circuits 20. Loop filter 17 is VFO1
8 is connected. The VFO is connected to the A / D converter 13, the Viterbi detector 15, the phase comparator 16 and the recording compensation amount control circuit 20 in order to supply the channel clock. Further, the recording compensation amount control circuit is connected to the recording pulse control circuit 21 to supply a control signal C according to the determined recording compensation amount. The write pulse control circuit 21 is supplied with write data R and is further connected to a random pattern generating section 23 which is trial write data. Further, a laser drive circuit is supplied to the laser drive circuit 22 to supply a waveform-shaped record pulse train P. A drive signal is supplied to the pickup unit PU so that the laser drive circuit 22 is further connected to the laser drive circuit 22 to radiate a laser beam whose waveform has been compensated.

(Operation of Optical Disk Device) An optical disk device having the above-mentioned structure and provided for carrying out the present invention is
The reproduction process and the recording process of the optical disc are performed as follows. That is, when the optical disc D is loaded into the optical disc device A, the control information of the optical disc D recorded in the control data zone in the embossed data zone of the lead-in area of the optical disc D is used by using the pickup PU and the data processing unit 1. Is read, and CPU46
To be supplied to.

In the optical disk apparatus A of the present invention, the figure is shown under the control of the CPU 46 based on the operation information by the user, the control information of the optical disk D recorded in the control data zone in the optical disk, the current status and the like. Not activated by the laser control unit to generate a laser beam.

The generated laser beam is used for the objective lens 31.
Is converged by the laser beam and is irradiated onto the recording area of the disc.
As a result, data is recorded in the storage area of the optical disc D (generation of mark string: data is recorded on the optical disc D by the marks of variable length and the interval between marks and the length of each variable length mark), or The reflected wave corresponding to the stored data is reflected and detected, and this data is reproduced.

In FIG. 2, the laser control unit included in the pickup PU has its settings set by the data processing unit 1. The settings are the reproduction power for obtaining the reproduction signal S, the recording power for recording the data, and the data. It depends on the erase power to erase. Laser beam
The semiconductor control unit is energized by the laser control unit so that the semiconductor laser unit has three different power levels of the reproducing power, the recording power and the erasing power, and the laser beams of the respective powers are generated.

This laser control unit is composed of a resistor and a transistor (not shown), and a power supply voltage is applied to the resistor, the transistor and a semiconductor laser as a semiconductor laser unit. As a result, the amplification factor varies depending on the base current of the transistor, different currents flow through the semiconductor laser oscillator, and laser beams having different intensities are generated. Here, the recording waveform compensation is performed according to the characteristics of each optical disk, which is a feature of the present invention, which will be described in detail later, and the laser power is changed according to the recording waveform pulse P output from the recording pulse control circuit 21. Is generated and the recording process on the optical disc is performed.

Further, the optical disk D is directly or housed in a disk cartridge and conveyed by a tray 32 into the apparatus so that the optical disk D is arranged to face the objective lens 31. A tray motor 33 for driving the tray 32 is provided in the device. Also,
The loaded optical disc D is rotatably held on the spindle motor 35 by the clamper 34, and is rotated at a predetermined rotation speed by the spindle motor 35.

The pickup PU has a photodetector (not shown) for detecting a laser beam therein. This photodetector is reflected by the optical disc D, and the objective lens 31
The laser beam returned via the laser beam is detected. The detection signal (current signal) from the photodetector is the current / voltage converter (I /
V) is converted into a voltage signal, and this signal is converted to the preamplifier 1
1 and the servo amplifier 34. Preamplifier 11
From this, signals for reproducing the data in the header portion and reproducing the data in the recording area are output to the data processing unit 1. The servo signal (track error signal, focus error signal) from the servo amplifier 34 is output to the servo seek control unit 39.

Here, as a method of optically detecting the focus shift amount, for example, there are the following astigmatism method and knife edge method.

Astigmatism method, that is, an optical element (not shown) for generating astigmatism in the detection optical path of the laser light reflected by the light reflecting film layer or the light reflecting recording film of the optical disc D.
Is arranged to detect the shape change of the laser beam irradiated on the photodetector. The light detection area is divided into four diagonal lines. For the detection signal obtained from each detection area,
In the servo seek control unit 39, a difference between diagonal sums is calculated to obtain a focus error detection signal (focus signal).

Knife edge method, that is, optical disk D
This is a method of disposing a knife edge that asymmetrically shields a part of the laser light reflected by. The light detection region is divided into two, and the difference between the detection signals obtained from each detection region is taken to obtain the focus error detection signal.

Normally, either the astigmatism method or the knife edge method is adopted.

The optical disc D has spiral or concentric tracks, and information is recorded on the tracks.
Information is reproduced or recorded / erased by tracing a focused spot along this track. In order to stably trace the focused spot along the track, it is necessary to optically detect the relative displacement between the track and the focused spot.

As the track deviation detecting method, there are generally the following phase difference detecting method, push-pull method, twin spot method and the like.

Differential Phase Detecti
on) method, that is, a change in the intensity distribution of the laser light reflected by the light reflecting film layer or the light reflecting recording film of the optical disc D on the photodetector is detected. The light detection area is divided into four diagonally. For the detection signal obtained from each detection area,
In the servo seek control unit 39, a phase difference between diagonal sums is calculated to obtain a track error detection signal (tracking signal).

In the push-pull method, that is, in this method, the change in the intensity distribution of the laser light reflected by the optical disc D on the photodetector is detected. The light detection area is divided into two, and the difference between the detection signals obtained from each detection area is taken to obtain the track error detection signal.

Twin-Spot method, that is, a diffraction element is arranged in the light transmission system between the semiconductor laser element and the optical disc D to divide the light into a plurality of wavefronts and irradiate the optical disc D ± 1 next time The change in the reflected light amount of the broken light is detected. Separately from the light detection area for reproducing signal detection, a light detection area for individually detecting the reflected light quantity of the + 1st order diffracted light and the reflected light quantity of the −1st order diffracted light is arranged, and the difference between the respective detected signals is taken to detect the track error detection signal. To get

By such focus control and track control, the focus signal, the tracking signal and the feed signal are sent from the servo seek control unit 39 to the focus and tracking actuator driver and the feed motor driver 40, and the objective lens 31 is driven by this driver 40. Focus servo control and tracking servo control are performed. Further, an energizing signal is supplied from the driver 40 to the feed motor 36 according to the access signal, and the pickup PU is controlled to be conveyed.

The servo seek control unit 39 is controlled by the data processing unit 1. For example, an access signal is supplied from the data processing unit 1 to the servo seek control unit 39 to generate a feed signal.

Further, the spindle motor driver 41 and the tray motor driver 42 are controlled by the control signal from the data processing unit 1, the spindle motor 35 and the tray motor 33 are energized, and the spindle motor 35 is rotated at a predetermined rotation speed. The tray motor 33 will properly control the tray.

The reproduction signal S corresponding to the data of the header portion supplied to the data processing unit 1 is supplied to the CPU 46. As a result, the CPU 46 determines the sector number as the address of the header portion based on the reproduction signal S and compares it with the sector number as the address to access (record data or reproduce recorded data). It has become.

As the reproduction signal S corresponding to the data in the recording area supplied to the data processing unit 1, the necessary data is stored in the RAM 48, and the reproduction signal S is processed by the data processing unit 1 and the interface control section 45 is processed. The reproduction processing signal is supplied to an external device such as a personal computer.

<Recording Compensation Amount Control Method> The optical disc device for performing the recording / reproducing process as described above will be described in detail below with reference to the drawings, which is a feature of the present invention. .

The control method of the recording compensation amount according to the present invention is explained by the operation in the data processing unit 1 shown in FIG. 1. The reproduction signal S read from the pickup unit PU is After the amplitude value is adjusted by the preamplifier 11, the high frequency noise is removed by the analog filter 12, and the channel clock CLK is removed by the A / D converter 13.
Is converted into a sampled value of the amplitude in discrete time synchronized with the cycle of. The sample value series of the reproduction signal S that has been A / D converted is equalized by the digital filter 14 to the response characteristic of the partial response (PR), and is maximum likelihood detected (ML) by the Viterbi detector 15 to be converted into a binary series. To be done.

The binary sequence output from the Viterbi detector 15 is changed from a channel modulation code to a data sequence with ECC by a demodulator (not shown), and after error correction by an error correction circuit (not shown), a personal computer or the like through an interface. Sent to the host device.

Here, in FIG. 1, in order to recover the channel clock CLK based on the reproduction signal S, the phase comparator 16 receives the PR equalized reproduction signal which is the output of the digital filter. From the deviation of the amplitude value between the ideal PR equalized waveform and the digital filter output waveform,
The phase difference τ between the channel clock CLK of the VCO 18 and the reproduction signal S is detected. The detected phase difference τ is
It is supplied to the VCO 18 through the filter 17 and is controlled so as to synchronize the phase of the channel clock CLK with the channel clock CLK.

On the other hand, regarding the recording process of the write data on the optical disc, when the binary sequence of the write data R output from the encoder for the channel modulation code (not shown) is input to the recording pulse control circuit 21, it is converted into a recording pulse train. After that, the mark is sent to the laser drive circuit 22 and a mark at a position where a proper waveform compensation is applied is formed on the optical disc. As a result, an appropriate amount of data recording processing can be performed by appropriately compensating for the shift amount of the edge of the mark due to thermal interference based on the reproduction signal S of the trial writing data. Further, at this time, the compensation amount is determined by using the phase difference output of the phase comparator 16, so that a lot of sample data of the time axis component is not required unlike the conventional apparatus, and the circuit scale is greatly reduced. can do.

(PRML Processing Method) Next, the PRML signal processing method according to the present invention will be described with reference to FIG. FIG. 3 is a timing chart for explaining the PRML signal processing method according to the present invention.

FIG. 3A shows a binary series of write data output from the encoder. FIG. 3B shows a recording pulse train output from the recording pulse control circuit 21. These are controlled by the recording compensation amount control circuit 20 of FIG. 1, and the positions of the leading edge and the trailing edge of the recording pulse are adjusted according to the recording compensation amount as indicated by the arrows in the figure. FIG. 3C shows the marks formed on the medium corresponding to the write data. FIG. 3D illustrates the PR response of the reproduction signal. In this example, the PR class (response class of partial response) is assumed to be 1221 (hereinafter, referred to as PR1221). The PR1221 response waveform is a reproduction response waveform corresponding to "1" of the write signal (a) over four clocks of the channel clock CLK, and the values thereof are "1", "2", "2", "respectively". 1 ”. PR the playback signal corresponding to a series of write data
The equalized waveform is a linear superposition of the individual responses. FIG. 3E is a waveform in which the amplitude value obtained by subtracting the value “3” is plotted in order to set the amplitude value “3” of the PR equalized waveform obtained by the linear superposition to the central value “0”. FIG. 3 (f) shows
The channel clock CLK synchronized with the reproduction signal S recovered by a timing recovery circuit that includes a phase comparator 16, a loop filter 17, and a VCO 18 is shown. 3G shows the result of detection of the PR equalized signal of FIG. 3E by the Viterbi detector 15, which is in agreement with the write data of FIG. 3A.

(Learning of Recording Compensation Amount) Hereinafter, learning of the recording compensation amount according to the present invention will be described in detail.

Laser light for recording marks is divided by a recording pulse control circuit 21 shown in FIG. 1 into pulse trains called multi-pulses as shown in FIG. In order to correct and record the mark deviation due to thermal interference in advance, the width of the leading pulse of the multi-pulse for recording the mark is changed depending on the relationship between the recorded mark length and the space in front of the mark. In addition, the width of the final pulse of the multi-pulse for recording the mark is also changed depending on the relationship between the recorded mark length and the space after the mark. The recording pulse control circuit 21 reads a compensation amount from a table in the recording compensation control unit that stores the recording compensation amount that changes depending on the combination of the mark length and the spaces before and after, and generates a predetermined pulse.

Here, the table containing the recording compensation amount immediately after the optical disc D for recording is loaded is stored in the value stored in the ROM 47 in the apparatus or in a specific area of the optical disc D. It is initialized to the value read from the table. However, since the stored recording compensation amount is not always an appropriate value for the inserted optical disk due to variations in characteristics during mass production and changes in the environment, trial recording will provide an appropriate recording compensation amount. To update the values in the table.

Write data R generated by modulating the random data generated by the random data generator 23 of FIG. 1 with a channel code is converted into a recording pulse train by the recording pulse control circuit 21 and is written into an area for trial writing on the optical disc D. Written. At this time, the recording pulse control circuit 21
Generates a recording pulse train using the initial value in the table as the write compensation amount.

The trial-written random data is immediately read and evaluated in order to update the recording compensation amount to an appropriate value. The data format of the recording / reproducing optical disc D is not limited to the trial writing data, and is recorded in the sector format as shown in FIG. FIG. 4 is a diagram showing an example of a layout of a sector field showing a sector format according to the present invention, FIG. 5 is a graph showing a signal waveform at the time of trial writing of the PRML signal processing system according to the present invention, FIG.
FIG. 0 is a block diagram showing another example of the phase comparator used in the PRML signal processing circuit according to the present invention.

After reading the ID of the header section and confirming that it is a desired sector, the data field is read. Since the phase of the channel clock CLK of the data written in the recording field does not match the phase of other portions depending on the write timing, the VCO clock is synchronized with the data recorded in the VFO pattern portion. The VFO pattern is, for example, a single frequency pattern in which the 8-channel clock CLK is one cycle,
There is much phase difference information, and it is possible to pull in at high speed. After bit synchronization with the VFO pattern, PS
The pattern is byte-synchronized and the channel modulation code is demodulated. However, in the process of updating the recording compensation amount, it is sufficient that bit synchronization is achieved. For example, the resync process when the byte-synchronization is lost is described in this section. It is not necessary to consider it, so it is omitted.

In the read random data pattern of the trial writing, the phase comparator 16 of FIG. 1 indicates that the deviation amount of the mark edge is the difference between the amplitude value and the expected amplitude value of the ideal PR equalization waveform. To be detected. As an example, the write data of the waveform shown in FIG. 3 is “000111111”.
Consider the mark edge of the part that is.

As shown in FIG. 5B, when the edge of the recorded mark is shifted to the left in the drawing as shown by the dotted line, the PR equalized waveform of the reproduced signal is as shown in FIG. As indicated by the dotted line in (a) of FIG.
The amplitude value at the identification point in synchronization with is shifted in the positive direction. Similarly, as shown in FIG. 5D, when the edge of the recorded mark is shifted to the right in the drawing as shown by the dotted line, the PR equalized waveform of the reproduced signal is as shown in FIG. 5
As indicated by the dotted line in (c) of FIG.
The amplitude value at the identification point synchronized with K shifts in the negative direction. In the signal processing method of PR1221 equalization, when the value of d constraint ((minimum value of continuous length of 0 or 1 of write data) -1) of the channel modulation code is "1" or "2" ( For example, (1,7) RLL modulation or 8-16 modulation), at the edge of the mark, PR
Since the amplitude value after equalization passes the amplitude value 0, it is possible to evaluate the deviation amount of the mark edge by evaluating the deviation of the amplitude value at the identification point of level 0.

In the embodiment of the present invention, the phase error detection process for synchronizing the channel clock CLK and the VCO clock and the evaluation of the mark edge shift amount due to thermal interference are used together by the same phase comparator 16. Is possible. Only by observing the reproduced signal, it is possible that the deviation of the amplitude value of the signal identification point corresponding to each mark edge is caused by the phase shift of the clock or the mark position is shifted by the thermal interference. It is not possible to determine if there is. However, V in the VFO pattern part
The phase alignment of the CO clock should have been completed, and the follow-up characteristic to the rotation fluctuation and the like thereafter is suppressed to a sufficiently low frequency band (= averaged) by the loop filter. Therefore, there is no problem even if the deviation of each mark edge depending on the mark length and the space lengths before and after is detected as a phase deviation from the averaged VCO clock.

(Structure / Operation of Phase Comparator) Next, the phase comparator used in the PRML signal processing circuit according to the present invention will be described in detail. FIG. 6 is a block diagram showing an example of the phase comparator 16 used in the PRML signal processing circuit according to the present invention.

FIG. 6 is a block diagram showing an example of the structure of a general phase difference comparator, and FIG. 10 is a phase comparator provided with wiring for supplying the phase difference signal τ to the recording compensation control circuit 20. 3 is a block diagram showing an example of the configuration of FIG.
In FIG. 10, a zero level amplitude error signal, a slope error signal, and a detection signal are provided in addition to the configuration of the phase comparator of FIG.

Here, prior to the description of the operation of detecting the amplitude deviation amount for evaluating the deviation amount of the mark edge due to thermal interference, the normal phase comparator 1 in the PRML signal processing circuit is described.
The operation of No. 6 will be described first.

Here, the PR class is (1, 2, 2,
1) and the d constraint is 1 or more. In FIG. 6, the amplitude value y (n + 1) is input to the delay circuit 101, and the output amplitude value y (n) is the delay circuit 102.
And the amplitude value y (n-1), which is the output thereof, is output.

Similarly, the delay circuits 109 to 110 are also means for delaying the input sample value by one sampling cycle and outputting the sample values. When the input of the threshold value judging circuit 353 is g (n), the delay circuits 109 to 110 respectively. The output is g (n-
1) and g (n-2).

Here, g (n) is the amplitude value y of the reproduced signal sampled in the nth sampling period.
The level of (n) is a reference value after PR equalization +2 or more, −
It is a value indicating which of 1, 0, +1 and -2 should be considered. "+1" when the amplitude value should be considered to be +2 or more, "0" when the amplitude value should be considered to be -1, 0, +1, and "0" when the amplitude value should be considered to be -2 or less. It shall take the value of -1 ". This g (n) will be called a judgment level.

In the present embodiment, whether or not the amplitude judgment value before and after the sampling of the judgment level 0 is the judgment value -1 or +1 at which the amplitude gradient becomes large, and if the conditions are met, the phase error gradient is checked. The calculation formula is switched according to the condition to calculate the value.

More specifically, the judgment level (g (n)
The combination of g (n-1) g (n-2)) is (-1 0 0) (1 0 0) (-1 0 1) (1 0 -1) (0 0 1) (0 0 -1 ), The phase error gradient calculation formula is switched according to the condition to calculate the value.

The threshold judgment circuit 353 judges the value to be taken by the judgment level g (n) from the value of the output of the selection element 352. The selection element 352 outputs “y (n) which is the output of the adder 350 when the value of the determination level g (n−1) is“ 0 ”.
+1) + y (n) "is selected and the judgment level g (n-1) is selected.
If the value of is other than "0", "y (n) + y (n-1)" which is the output of the adder 351 is selected.

FIG. 7 shows how the waveform transitions when the value of the judgment level g (n-1) is other than "0". Figure 7
FIG. 8 is a graph for explaining the transition of the waveform when the determination level g (n-1) in the PRML signal processing circuit according to the present invention is a value other than 0. FIG. It is a graph explaining the transition of the waveform when the value of n-1) is 0.

In the case of FIGS. 7A and 7B, g (n-
1) = − 1, y (n−1) and y (n) are both −2 or less, and in the case of (c), g (n−1) = − 1 and y
Since (n-1) and y (n) are "-2" and "0", for example, in the case of (a) and (b), if -ε = -2.5 of the threshold value determination means 353 is set. The judgment level "-1",
In the case of (c), it can be determined that the determination level is “0”. Similarly, at the trailing edge of the waveform, the judgment level "+1" can be set in the cases (d) and (e), and the judgment level "0" can be set in the case (f).

FIG. 8 shows the transition of the waveform when the value of the judgment level g (n-1) is "0". In the case of (a) and (b) of FIG. 8, g (n-1) = 0 and y
(N) and y (n + 1) are both “+2” or more,
In the case of (c), g (n-1) = 0 and y (n) and y
Since (n + 1) is “+1” and “0”, for example, if ε = 2.5 of the threshold value judging means 353, the judgment levels “+1” and (c) in the cases of (a) and (b) are set. In this case, it can be determined that the determination level is “0”. Similarly, at the trailing edge of the waveform, in the cases of (d) and (e), the judgment level "-
In the case of 1 "and (f), the determination level can be set to" 0 ".

The phase error gradient Δτ 107 is calculated by the adder 380.
Thus, the result of adding the outputs of the multipliers 363 and 381 is output only when the determination level g (n-1) is "0".

The multiplier 363 outputs the product of y (n-1) and the output of the coefficient determining means 364.

The multiplier 381 outputs the product of the output of the coefficient determining means 383 and the output of the adder 382. Adder 38
2 outputs the sum of y (n) and y (n-2).

These operations will be described more specifically with reference to FIG.

In the case of (a), g (n) = 0, g (n-
1) = 0 and g (n−2) = − 1, the comparator 36
9, the output of the comparator 370 is "0", the output of the comparator 371 is "0", the output of the comparator 372 is "0", and the phase error gradient is y (n-1). ) * 1 + (y (n) + y (n-2)) * 0. For y (n-1), the amplitude value 203 in the case where the phases match, the actual sample value 204 is
If the amplitude value is + γ due to the phase error τ2, then y (n−1) × 1 = + γ. The deviation γ from the PR equalization reference value is output as the equalization error gradient.

In the case of (b), g (n) = 1, g (n-
1) = 0 and g (n−2) = − 1, the comparator 3
The output of 69 is "1", the output of the comparator 370 is "1", the output of the comparator 371 is "0", the output of the comparator 372 is "0", and the phase error gradient is y (n-1). ) * 1 + (y (n) + y (n-2)) * 1. For y (n-1), the amplitude value 203 in the case where the phases match, the actual sample value 204 is
It is assumed that the amplitude value is “+ γ” due to the phase error τ2.
Amplitude value 20 when y (n-2) is in phase
1, the actual sampled value 202 is the phase error τ1
Therefore, the amplitude value is “−2 + β”. Also, y
(N) is the amplitude value 205 when the phases match, and the actual sample value 206 is + γ + (+ 2 + δ) + (when the amplitude value is “+ 2 + δ” because of the phase error τ3. -2 + β) = + γ + β + δ. The deviations γ, β and δ from the PR equalization reference value are output as the equalization error gradient.

In the case of (c), g (n) = 1, g (n-
1) = 0 and g (n-2) = 0, the comparator 369
Is "0", the output of the comparator 370 is "1", the output of the comparator 371 is "0", the output of the comparator 372 is "0",
Therefore, the phase error gradient is calculated from y (n-1) × 1 + (y (n) + y (n-2)) × 0. For y (n-1), the amplitude value 203 in the case where the phases match, the actual sample value 204 is
If the amplitude value is “+ γ” due to the phase error τ2, then y (n−1) × 1 = + γ. The deviation γ from the PR equalization reference value is output as the equalization error gradient.

In the case of (d), g (n) = 0 g (n-
1) = 0 g (n-2) = 1, the comparator 36
The output of 9 is "0", the output of the comparator 370 is "0", the output of the comparator 371 is "1", the output of the comparator 372 is "0", and the phase error gradient is y (n-1). ) *-1+ (y (n) + y (n-2)) * 0. For y (n-1), the amplitude value 203 in the case where the phases match, the actual sample value 204 is
If the amplitude value is “−γ” due to the phase error τ2, then y (n−1) × −1 = −γ × −1 = + γ. The deviation γ from the PR equalization reference value is output as the equalization error gradient.

In the case of (e), g (n) =-1, g (n-
1) = 0 and g (n−2) = 1, the comparator 369
Is "0", the output of the comparator 370 is "0", the output of the comparator 371 is "1", the output of the comparator 372 is "1",
And the phase error gradient is y (n−1) × −1 + (y (n) + y (n−2)) × −
Calculate from 1. For y (n-1), the amplitude value 203 in the case where the phases match, the actual sample value 204 is
It is assumed that the amplitude value is “−γ” due to the phase error τ2.
Amplitude value 20 when y (n-2) is in phase
1, the actual sampled value 202 is the phase error τ1
Therefore, the amplitude value is “+ 2-β”. Also, y
(N) is −γ × when the amplitude value 205 in the case where the phases match is the actual sample value 206, assuming that the amplitude value is “−2δ” due to the phase error τ3. -1 + ((-2-δ) + (+ 2-β)) × -1
= + Γ + β + δ. The deviations γ, β and δ from the PR equalization reference value are output as the equalization error gradient.

In the case of (f), g (n) =-1 g (n-
1) = 0 g (n−2) = 0, the comparator 36
The output of 9 is "0", the output of the comparator 370 is "0", the output of the comparator 371 is "0", the output of the comparator 372 is "1", and the phase error gradient is y (n-1). It is calculated from × −1 + (y (n) + y (n−2)) × 0. For y (n-1), the amplitude value 203 in the case where the phases match, the actual sample value 204 is
If the amplitude value is “−γ” due to the phase error τ2, then y (n−1) × −1 = −γ × −1 = + γ. The deviation γ from the PR equalization reference value is output as the equalization error gradient.

Such operations are summarized in the flow chart showing the procedure for generating the output to the recording compensation amount control circuit in the phase comparator of FIG. FIG.
In the flowchart of FIG. 6, when the amplitude value y (n) is input (S11), Gin is calculated according to the polarity of the determination level g (n-1) (S12) (S13, S1).
4). Furthermore, the determination level g (n) is defined according to the magnitude relationship between Gin and ε (S15 to S19), and thereafter,
After setting T2 = 0 (S20), each determination level g (n)-
Depending on the magnitude relationship of g (n-2) (S21, S22, S
26, S27) and after T2 is defined (S23, S2
8) If the determination level g (n-1) becomes "0" (S2
4) The amplitude error signal is sent as T2 and the tilt error signal is sent as g (n) (S29). If not, the number is incremented and the same processing is repeated (S25).

<Operation in Recording Compensation Amount Control Circuit 20> Next, the phase comparator 1 in the PRML signal processing circuit
The operation of detecting the amplitude deviation amount for evaluating the deviation amount of the mark edge due to thermal interference will be described from the signal of No. 6.

In the signal processing method of the PR1221 equalization, it is already possible to evaluate the deviation amount of the mark edge by evaluating the deviation of the amplitude value at the level 0 discrimination point corresponding to the edge of the mark. Stated. In the phase comparator 16 of FIG. 6, when the output of the delay circuit 109 is “0”, that is, the expected value of y (n−1) is level 0, the output of the comparator 345 becomes “1”. At this time,
The output of the multiplier 363 is a value obtained by multiplying the amount of deviation of the amplitude from the level 0 of the discrimination point of y (n-1) by the gradient of the signal, and this value is the value to be evaluated as the amount of mark edge slippage. It has become. Further, the value of g (n) at the time of g (n-1) indicates that the leading edge of the mark is "+1", and indicates that the trailing edge of the mark is "-1". ing.

Therefore, with only these three signals, the recording compensation amount control circuit 20 can evaluate the deviation amount of the mark edge and update the contents of the table containing the recording compensation.

FIG. 11 is a block diagram showing an example of the recording compensation amount control circuit 20 used in the PRML signal processing circuit according to the present invention, and FIG. 12 explains the operation of the recording compensation amount control circuit 20 shown in FIG. 19 is a flow chart showing a control procedure for updating the recording compensation table in the recording compensation amount control circuit.

In FIG. 11, the recording compensation amount control circuit 20 connected to the phase comparator 16 is a register A5.
1 and a register B connected thereto, a table value calculation circuit 53 to which an amplitude error value is supplied, and a recording compensation table 54. Further, the comparator 55 to which the inclination polarity signal is supplied from the phase comparator 16, the mark length counter 56 connected to the comparator 55 and the register C connected to the mark length counter 56 are further connected between the comparator 55 and the table value calculation circuit 53. Further provided are AND circuits 58 and 59, and a space length counter 60 connected to the comparator 55 and provided with a register D61.

Such a recording compensation amount control circuit 2
At 0, at the timing indicated by the pulse 501 in the timing chart of FIG. 12 of the detection signal from the phase comparator 16, the register A51 receives an amplitude error signal indicating the positional deviation of the leading edge of the mark 1 from the phase comparator 16. Set. The mark length counter 56, when the detection signal is “1” and the tilt polarity signal is “1”,
The measurement of the mark length is started by counting the channel clock CLK. Since the inclination polarity signal from the phase comparator 16 has a value of "1" or "-1", when it is input to the recording compensation amount control circuit 20, it passes through the comparator,
Converted to "1" and "0". The space length counter has a detection signal of "1" and an inclination polarity signal of "1".
If it is, the counting is ended. Therefore, pulse 50
At the timing of 1, the counting of the length of the space 1 is stopped. The length of the space 1 measured by the space length counter 60 is set in the register D61.

At the timing indicated by the pulse 502 of the detection signal, the amplitude error signal indicating the positional deviation of the trailing edge of the mark 1 from the phase comparator 16 is set in the register A51. The amplitude error signal indicating the positional deviation of the leading edge of the mark 1 from the phase comparator 16 set in the register A51 is shifted and set in the register B52. The mark length counter 56 has a detection signal of "1".
When the tilt polarity signal is 0, the mark length measurement is stopped. The length of the mark 1 measured by the mark length counter 56 is set in the register C57. When the detection signal is 1 and the tilt polarity signal is 0, the space length counter 60 starts the measurement of the space length by counting the channel clock CLK. The length of space 1 remains set in the register D61.

The previous space length / mark length signal 505 is the amplitude error signal of the register B, and the previous space length is the register D.
Indicates that the mark length indicates the positional deviation of the edge when the mark length is the value of the register C. The table value calculation circuit 53 in FIG. 11 integrates and averages the positional deviation amounts of the edges corresponding to the combination of the preceding space length and the mark length, and updates the value stored in the recording compensation table 54.

At the timing shown by the pulse 503 of the detection signal, the amplitude error signal τ indicating the positional deviation of the leading edge of the mark 2 from the phase comparator 16 is stored in the register A51.
Is set. Register B52 has register A51
The amplitude error signal indicating the positional deviation of the trailing edge of the mark 1 from the phase comparator 16 which has been set to is shifted and set. Since the detection signal is "1" and the tilt polarity signal is "1", the mark length counter 56 starts measuring the mark length of the mark 2 by counting the channel clock CLK. The length of the mark 1 remains set in the register C57. The space length counter 60 stops counting the length of the space 2 because the detection signal is 1 and the inclination polarity signal is 0. The length of the space 2 measured by the space length counter 60 is set in the register D61.

The mark length / rear space length signal 506 is the amplitude error signal of the register B52, and the mark length is the register C.
The value of 57 indicates that the position of the edge is displaced when the rear space length is the value of the register D61. The table value calculation circuit 53 of FIG. 11 integrates and averages the positional deviation amounts of the edges corresponding to the combination of the mark length and the rear space length, and updates the values stored in the recording compensation table 54.

The writing of the random pattern 23 in the trial writing area using the updated value of the recording compensation amount table 54 thus obtained and the updating of the recording supplementary table 54 by reproducing the same are performed for the marks to be recorded. The process is repeated until the jitter value becomes equal to or less than the predetermined value.

Such a recording compensation amount control circuit 2
The processing of 0 is summarized in the flowchart of FIG. In the flowchart, when the detection signal 1 is detected while reading the trial writing data (S31) (S3)
2) The amplitude error signal is transferred to the register A, and the signal stored in the register A is transferred to the register B (S33).
When the tilt polarity signal is positive (S34), the mark length counter 56 starts counting and the space length counter 60 ends counting. Then, the count value of the space length counter is stored in the register D (S35). Next, using the mark length as the register C, the rear space length as the register D, and the amplitude error amount as the register B, the error amounts for the set of the mark length and the rear space length are integrated (S3).
6).

When the inclination polarity signal is negative (S34), the mark length counter 56 finishes counting, and the space length counter 60 starts counting. Then, the count value of the mark length counter 56 is stored in the register C (S3).
7). Next, using the previous space length as the register D, the mark length as the register C, and the amplitude error amount as the register B, the error amounts for the set of the previous space length and the mark length are integrated (S38). After confirming that all the trial writing data has been read, the integrated values of the error amounts for the respective groups of the front space length and the mark length and the mark length and the rear space length are averaged. Then, based on this value, the value of the write compensation amount in the table corresponding to the combination of the mark length and the space length is updated (S39).

As described above in detail, the first aspect of the present invention
According to the embodiment of the present invention, by using the phase difference detector, the recording for compensating the mark deviation and the like due to the thermal interference even in the optical disc device of the PRML signal processing system with a small-scale configuration as compared with the conventional device. It is possible to provide an optical disk device capable of performing compensation processing.

<< Second Embodiment >> The second embodiment presents a method of controlling the recording compensation amount that can be applied to the PRML signal processing method. The maximum likelihood sequence detector (= Viterbi detection) Optical disc device that determines the amount of recording compensation by using the output of the device.

The details will be described below with reference to the drawings. Figure 1
0 is a block diagram showing another example of the phase comparator used in the PRML signal processing circuit according to the present invention, and FIG. 13 shows one example of a reproduction signal processing section and a writing control section in another example of the optical disk recording / reproducing apparatus. 14 is a block diagram showing an example of a Viterbi detector, FIG. 15 is a block diagram showing an example of a recording compensation amount control circuit, and FIG.
3 is a flowchart showing a control procedure for updating a recording compensation table in the recording compensation amount control circuit.

In these figures, in the configuration shown in FIG. 1, the recording compensation amount control circuit 20 updates the value of the table containing the recording compensation amount using the signal generated by the phase comparator 16. There is. On the other hand, in the second embodiment, as shown by the data processing unit shown in FIG. 13, recording is performed using the output of the Viterbi detector 15 (= maximum likelihood sequence detector) and the delayed amplitude value of the identification point. The value of the table containing the compensation amount is updated. In FIG. 13, the phase difference signal τ from the phase comparator 16 is not directly supplied to the recording compensation amount control circuit 20, but the output B of the Viterbi detector 15 is supplied. Further, a zero phase starter 24 is provided and connected to the VFO 18. The other configurations are the same as those in FIG.

As described above, instead of using the phase difference signal τ from the phase comparator 16 as in the first embodiment, the output of the Viterbi detector 15 having a longer sequence is supplied and the compensation amount is determined based on this output. By doing so, it is possible to provide an optical disk device that enables more accurate recording complement amount processing.

FIG. 14 is a block diagram showing an example of the Viterbi detector used in the PRML signal processing system according to the present invention. Unlike the conventional Viterbi detector, which determines 0 and 1 depending on whether or not the signal value exceeds a threshold value for each bit, the sample point sequence of the reproduced signal, the PR equalization class, and the d of the modulation code are different. In this method, the most probable signal sequence is selected by calculating the Euclidean distance with the combination of signal sequences that can be taken from the state transitions determined by the constraints. In the figure, the Viterbi detector 15 has, as an example, a branch metric calculation unit 71, an ACS 72, a path metric memory 73 connected thereto, a path memory 74, and a path selection unit 75. Since the detailed operation of the Viterbi detector is not directly related to the operation of the present invention, its explanation is omitted.

The characteristic relating to the present invention is that the output binary series is obtained through a kind of shift register called a path memory in order to select the most probable series from the signal sample point series having waveform interference. Therefore, after the sample value is input, 0 corresponding to that point
Alternatively, there is a delay of from several tens of clocks to several tens of clocks until the data of 1 is output. Therefore, this method is used when importance is attached to accuracy rather than speed.

FIG. 15 shows a recording compensation amount control circuit 20 used in the PRML signal processing system according to the present invention.
It is a block diagram showing an example. In FIG. 15, a preprocessing unit that generates an amplitude error signal, a detection signal, and a tilt polarity signal,
That is, the delay circuit 62 and the D flip-flop circuit 51
0, ExOR circuit 511 and the like are the same as the recording compensation amount control circuit 20 shown in FIG. Therefore, the part that generates the amplitude error signal, the detection signal, and the inclination polarity signal from the output of the Viterbi detector and the delayed amplitude value of the identification point will be described.

At the leading edge of the mark, the detected binary data changes from 0 to 1. At the trailing edge of the mark, the detected binary data changes from 0 to 1. Therefore, the edge detection signal is the output of the current Viterbi detector 14 and the output of the D flip-flop 510.
The exclusive OR with the output of the Viterbi detector 14 at the time before the clock can be generated by the ExOR circuit 511.

As the tilt polarity signal, the signal shown in FIG. 12 can be obtained by using the output of the Viterbi detector 14 as it is. The amplitude error signal is obtained by delaying the output signal sample value of the digital filter by the same time as the delay due to the path memory of the Viterbi detector, and then doubling the slope polarity signal and subtracting 1 from 1 to 0 to − It can be generated by taking the product of the signal converted to 1. That is, the fact that the deviation amount of the edge in the time direction and the polarity of the deviation of the amplitude value are reversed between the leading edge and the trailing edge of the edge is corrected using the inclination polarity signal.

FIG. 20 is a flow chart showing the control procedure for updating the recording compensation table in the recording compensation amount control circuit when the output of the Viterbi detector is used. In this flowchart, the recording compensation amount control circuit 20 reads the test writing data (S
31) Within a range in which the Viterbi output one clock before does not become the current output (S41), the detection signal is set to "1", the tilt polarity signal is set to the current Viterbi output, and the amplitude error x (tilt error signal x 2-1 ) Value is set as the amplitude error. Moreover,
The amplitude error signal is transferred to the registers A and B (S42).

Next, if the inclination polarity signal is 1, (S4
3) The mark length counter 56 starts counting, and the space length counter 60 finishes counting. Then, the count value of the space length counter is stored in the register D (S35). Next, using the mark length as the register C, the rear space length as the register D, and the amplitude error amount as the register B, the error amounts for the set of the mark length and the rear space length are integrated (S36).

When the tilt polarity signal is not 1 (S43),
The mark length counter 56 finishes counting, and the space length counter 60 starts counting. Then, the count value of the mark length counter 56 is stored in the register C (S
37). Next, let the previous space length be register D, the mark length be register C, and the amplitude error amount be register B.
The error amount for the set of the preceding space length and the mark length is integrated (S38). After confirming that all the trial writing data has been read, the integrated values of the error amounts for the respective groups of the front space length and the mark length and the mark length and the rear space length are averaged. Then, based on this value, the value of the write compensation amount in the table corresponding to the combination of the mark length and the space length is updated (S39).

(Other Embodiments) As still another embodiment, not only the zero-level amplitude value of the PR equalized signal,
An optical disk device for performing recording compensation processing that also considers the amplitude error of adjacent bits is added.

That is, in the description of the embodiment using FIGS. 1 and 13, the shift amount of the zero-level amplitude value of the PR equalization signal is used to evaluate the shift amount of the mark edge due to thermal interference. . The PRML signal processing method allows the response waveform from the mark to cause a predetermined amount of waveform interference in adjacent bits. That is, the response corresponding to the rising or falling of the mark edge also affects adjacent bits.

Therefore, in evaluating the influence of the mark edge shift on the PR equalized waveform, more accurate evaluation can be obtained by considering not only the zero level but also the amplitude error of the adjacent bit.

FIG. 9 is a graph for explaining the operation of the phase comparator according to the present invention. PR class is PR122
1, the modulation code is used in the current DVD,
In the case of 8-16 modulation in which the d constraint is 2, the write data after modulation as shown in FIG.
In the binary series converted into the I format, at least 3 pieces of 1 or 0 data continue. Therefore, the waveforms at the leading and trailing edges of the written mark are (d) in FIG.
And (e), -2, 0, +2 and +2,
It will take the values 0 and -2. Therefore, in FIG. 9 explaining the operation of the phase comparator 16 shown in FIG.
Only the pattern of (b) or (c) appears. As a result, the output 107 of the phase comparator 16 in FIG. 6 always outputs a value obtained by adding the amount of deviation between the zero level and the amplitude values before and after the zero level.

From the above, in order to evaluate the influence of the mark edge shift on the PR equalized waveform, in order to evaluate not only the zero level but also the amplitude error of the adjacent bit, as shown in FIG. Of the amplitude error signal 107 output from the gate 355 and the phase error information of the phase comparator 16
It turns out that you can change to.

FIG. 17 shows a recording compensation amount control circuit 20 for updating the value of the table containing the recording compensation amount using the output of the Viterbi detector and the delayed amplitude value of the discrimination point. A configuration in which not only the zero level but also the amplitude error of an adjacent bit is considered for the evaluation is shown. The configuration of the latter part of FIG. 17 is the same as that of FIG. 15 and is therefore omitted, and the part that generates the amplitude error signal, the detection signal, and the inclination polarity signal from the output of the Viterbi detector and the delayed amplitude value of the identification point is mainly shown. . Since not only the zero level but also the amplitude error of adjacent bits is evaluated, the PR response waveforms 1, 2 ,,
Flip-flop circuits 513 to 521 that convolutionally integrate 2, 1 and generate an ideal PR equalized waveform that serves as a reference for comparison.
Is added, and a delay circuit 62 for adjusting the delay amount of the convolution integration circuit is added.

FIG. 21 is a flow chart showing a control procedure for updating the recording compensation table in the recording compensation amount control circuit 20 of FIG.

That is, in this flowchart,
The recording compensation amount control circuit 20 reads the trial writing data (S31) and outputs the Viterbi output and the PR1221.
The convolution integral with the response waveform is obtained, this is used as the ideal PR equalized signal, and the difference between the ideal PR equalized signal and the delayed filter output is obtained, and this is used as the amplitude error signal (S4).
5). Next, after confirming that the Viterbi output three clocks before is not equivalent to the Viterbi output two clocks before, the detection signal is set to "1", the tilt polarity signal is set to the current Viterbi output, and the amplitude error x (tilt error The value of signal × 2-1) is set as the amplitude error. Then, the amplitude error signal is transferred to the register A,
Transfer to the register B (S42).

Next, if the inclination polarity signal is 1, (S4
3) The mark length counter 56 starts counting, and the space length counter 60 finishes counting. Then, the count value of the space length counter is stored in the register D (S35). Next, using the mark length as the register C, the rear space length as the register D, and the amplitude error amount as the register B, the error amounts for the set of the mark length and the rear space length are integrated (S36).

When the inclination polarity signal is not 1 (S43),
The mark length counter 56 finishes counting, and the space length counter 60 starts counting. Then, the count value of the mark length counter 56 is stored in the register C (S
37). Next, let the previous space length be register D, the mark length be register C, and the amplitude error amount be register B.
The error amount for the set of the preceding space length and the mark length is integrated (S38). After confirming that all the trial writing data has been read, the integrated values of the error amounts for the respective groups of the front space length and the mark length and the mark length and the rear space length are averaged. Then, based on this value, the value of the write compensation amount in the table corresponding to the combination of the mark length and the space length is updated (S39).

By the above procedure, the recording compensation process can be performed in consideration of not only the zero-level amplitude value of the PR equalized signal but also the amplitude error of the adjacent bit, and a more accurate and appropriate recording compensation amount can be obtained. It is possible to provide an optical disk device that can provide

The various embodiments described above enable those skilled in the art to implement the present invention. However, various modifications of these embodiments will be readily apparent to those skilled in the art, and the disclosed principle in a broad sense can be applied to various embodiments without inventive ability. is there. As described above, it goes without saying that the present invention covers a wide range that does not contradict the disclosed principle and novel features, and is not limited to the above-described embodiments.

[0122]

As described in detail above, according to the present invention, P
Since it is possible to evaluate the deviation amount of the mark edge by evaluating the deviation of the amplitude value at the level 0 discrimination point where the amplitude value after R equalization passes the amplitude value 0, it is possible to evaluate the PRML.
Even in digital signal processing methods that use discrete time sample points, such as signal processing methods, the values in the table that evaluates the amount of mark edge deviation and contains the conditions for recording compensation are compatible with the actual conditions for optical disks and optical disk devices. Therefore, it is possible to provide an optical disc device capable of performing the above.

Further, a signal for evaluating the deviation amount of the mark edge is evaluated by the phase comparator 16 of the PRML signal processing system.
It is possible to provide an optical disc device having a simplified circuit for updating the recording compensation table.

Furthermore, the signals for evaluating the deviation amount of the mark edge may be supplied from the output of the Viterbi detector of the PRML signal processing system and the output of the equalizer.
It is possible to provide an optical disk device capable of updating the optimum recording compensation table even for the PRML signal processing method with higher accuracy than the output of the phase comparator.

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of a reproduction signal processing section and a write control section in an example of an optical disc recording / reproducing apparatus using a PRML signal processing system according to the present invention.

FIG. 2 is a block diagram showing the overall configuration of an example of an optical disc device according to the present invention.

FIG. 3 is a timing chart illustrating a PRML signal processing method according to the present invention.

FIG. 4 is a diagram showing an example of a layout of a sector field showing a sector format according to the present invention.

FIG. 5 is a graph showing a signal waveform at the time of trial writing in the PRML signal processing method according to the present invention.

FIG. 6 is a block diagram showing an example of a phase comparator used in the PRML signal processing circuit according to the present invention.

FIG. 7 is a graph for explaining the transition of the waveform when the determination level g (n−1) has a value other than 0 in the PRML signal processing circuit according to the present invention.

FIG. 8 is a graph illustrating transition of a waveform when the determination level g (n−1) has a value of 0 in the PRML signal processing circuit according to the present invention.

FIG. 9 is a graph for explaining the operation of the phase comparator according to the present invention.

FIG. 10 is a block diagram showing another example of the phase comparator used in the PRML signal processing circuit according to the present invention.

FIG. 11 is a block diagram showing an example of a recording compensation amount control circuit used in the PRML signal processing circuit according to the present invention.

FIG. 12 is a timing chart for explaining the operation of the recording compensation amount control circuit shown in FIG.

FIG. 13 is a block diagram showing a part of a reproduction signal processing section and a write control section in another example of the optical disc recording / reproducing apparatus using the PRML signal processing system according to the present invention.

FIG. 14 is a block diagram showing an example of a Viterbi detector used in the PRML signal processing method according to the present invention.

FIG. 15 is a block diagram showing an example of a recording compensation amount control circuit used in the PRML signal processing system according to the present invention.

FIG. 16 is a block diagram showing another example of the phase comparator used in the PRML signal processing circuit according to the present invention (the output of the multiplier 363 is used as the phase error information of the phase comparator).

FIG. 17 is a block diagram showing another example of the recording compensation amount control circuit used in the PRML signal processing circuit according to the present invention (the table value is updated using the output of the Viterbi detector and the delayed amplitude value of the identification point). Fig.

FIG. 18 is a flowchart showing a procedure for generating an output to the recording compensation amount control circuit in the phase comparator according to the present invention.

19 is a flowchart showing a control procedure for updating a recording compensation table in the recording compensation amount control circuit shown in FIG.

20 is a flowchart showing a control procedure for updating the recording compensation table in the recording compensation amount control circuit shown in FIG.

21 is a flowchart showing a control procedure for updating the recording compensation table in the recording compensation amount control circuit shown in FIG.

FIG. 22 is a waveform diagram showing an example of multi-pulses used in the optical disc device.

FIG. 23 is a diagram showing an example of a table for determining the recording compensation amount of the optical disc device.

FIG. 24 is a block diagram showing an example of a system used in an optical disk device for updating a table value so as to obtain an appropriate recording compensation amount by trial writing.

25 is a block diagram showing an example of an internal configuration of a recording / reproducing unit of the system shown in FIG.

26 is a block diagram showing an example of an internal configuration of a parameter calculation unit of the system shown in FIG.

[Explanation of symbols] D ... Optical disc PU ... Pickup unit 1 ... Data processing unit 11 ... Variable gain amplifier 12 ... Analog filter 13 ... A / D converter 14 ... Digital filter 15 ... Viterbi detector 16 ... Phase comparator 17 ... Loop filter 20. Recording compensation amount control circuit 21 ... Recording pulse control circuit 22 ... Laser drive circuit 23 ... Random pattern generator

Claims (12)

[Claims] 1. An optical disk device for recording data on an optical disk having a concentric or spiral recording area, comprising: rotating means for rotating the optical disk at a predetermined number of revolutions; and a laser beam on the optical disk on which the rotating means rotates. Irradiate, write predetermined data in a predetermined area as a trial write, then
The trial writing means for reading the predetermined data written by the trial writing, the compensation amount determining means for determining the compensation amount of the recording waveform pulse for the recording processing based on the predetermined data read by the trial writing means, and the external receiving means The recording data is subjected to a predetermined process, a recording waveform pulse is generated based on the compensation amount determined by the compensation amount determining means, and a laser beam generated in response to this is applied to a recording area of the optical disc to record the recording data. An optical disk device comprising: a recording unit for recording 2. The compensation amount determining means includes a phase comparing means for receiving the predetermined data read by the trial writing means and a channel clock corresponding to the predetermined data and outputting a phase difference signal between them. The optical disk device according to claim 1, wherein a compensation amount of a recording waveform pulse for recording processing is determined based on the signal. 3. The compensation amount determining means receives the predetermined data read by the trial writing means and an output of a maximum likelihood sequence detector to which the predetermined data is supplied, and based on these, outputs a recording process. The optical disc device according to claim 1, wherein a compensation amount of the recording waveform pulse is determined. 4. The amplitude between the reproduction signal and the ideal signal corresponding to the combination of the mark length and the space length before and after the sample point and a plurality of sample points before and after the sample point. 2. The optical disk device according to claim 1, wherein the compensation amount of the recording waveform pulse for the recording process is determined by evaluating the deviation amount of each. 5. An optical disk recording method for recording data on an optical disk having a concentric or spiral recording area, wherein a predetermined beam of predetermined data is irradiated by irradiating a laser beam on the optical disk rotated at a predetermined number of rotations by a rotating means. Based on the predetermined data read in the trial writing step, and the trial writing step of reading the trial writing in the area and then reading the predetermined data written in the trial writing,
A compensation amount determining step of determining a compensation amount of a recording waveform pulse for recording processing, a predetermined process is performed on recording data received from the outside, and a recording waveform pulse is generated based on the compensation amount determined in the compensation amount determining step. An optical disk recording method, comprising: a recording step of generating and irradiating a recording area of the optical disk with a laser beam generated in response to the recording data. 6. The compensation amount determining step uses a phase comparator for receiving the predetermined data read in the trial writing step and a channel clock corresponding to the predetermined data, and outputting a phase difference signal between them. The optical disc recording method according to claim 5, wherein the compensation amount of the recording waveform pulse for the recording process is determined based on the phase difference signal. 7. The compensation amount determining step receives the predetermined data read in the trial writing step and an output of a maximum likelihood sequence detector to which the predetermined data is supplied, and based on them, a recording process is performed. The optical disc recording method according to claim 5, wherein a compensation amount of the recording waveform pulse is determined. 8. The compensating amount determining step comprises, for a sample point and a plurality of sample points before and after the sample point, an amplitude between a reproduction signal and an ideal signal corresponding to a combination of a mark length and a space length before and after the mark point. 6. The optical disc recording method according to claim 5, wherein the compensation amount of the recording waveform pulse for the recording process is determined by evaluating the respective shift amounts. 9. The compensation amount determining means evaluates an error amount to be compensated by a reproduction signal sampling point at a discrete time sampled by a channel clock corresponding to the predetermined data read by the trial writing means, 2. The optical disk device according to claim 1, further comprising means for determining a compensation amount of a recording waveform pulse for recording processing according to. 10. The trial writing unit irradiates a laser beam onto the optical disc rotated by the rotating unit to test-write predetermined data, which is random data, in a predetermined area, and then, the trial-written random data. 2. The optical disk device according to claim 1, further comprising means for reading the predetermined data that is 11. The compensation amount determining step evaluates an error amount to be compensated by a reproduction signal sample point at a discrete time sampled by a channel clock corresponding to the predetermined data read in the trial writing step, 6. The optical disk recording method according to claim 5, further comprising the step of determining the compensation amount of the recording waveform pulse for the recording process according to. 12. The trial writing step irradiates a laser beam onto the optical disc rotated by the rotating means to test write predetermined data, which is random data, to a predetermined area, and then, the trial written random data. 6. The optical disk recording method according to claim 5, further comprising means for reading the predetermined data that is