JP2003060201A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS device having a laminated spacer structure in which a SAC technique is applied, where a short circuit is prevented from occurring between a source and a drain, and the current drive performance of an n-channel MISFET is kept well balanced with that of a p-channel MISFET. SOLUTION: An etching stopper layer for a contact hole bored in an interlayer insulating film is formed of a laminated film 16 composed of a silicon nitride film 16a deposited through a thermal CVD method, and a silicon nitride film 16b deposited through a plasma CVD method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a MISFET (metal insulator se).
Applied to a semiconductor device having a contact hole in contact with a semiconductor region forming a source and a drain, which is formed by a self aligned contact (SAC) technique that allows misalignment with a gate electrode of a conductor field effect transistor). And about effective technology.

[0002]

2. Description of the Related Art MISF is becoming more popular as semiconductor devices become more highly integrated.
The miniaturization of ET is progressing and, for example, CMOS (completion
mentary metal oxide semiconductor) device is formed by a processing technique having a minimum processing dimension of 0.2 μm or less.

However, the alignment margin between the contact hole and the gate electrode provided in contact with the semiconductor region forming the source and drain of the MISFET becomes small,
It has become necessary to form contact holes with dimensions below the processing limit of photolithography technology. Therefore, the formation of contact holes using the SAC technique, which allows the misalignment between the contact hole and the gate electrode, is being studied.

Regarding the contact hole using the SAC technique, for example, Japanese Unexamined Patent Publication No. 9-55479 or International Electr.
on Device Meetings "A Novel Borderless Contact / Int
erconnect Technology UsingAluminum Oxide Etch Stop
for High Performance SRAM and Logic "pp441 ~ 444,
1993) and the like.

Further, as the miniaturization of the MISFET progresses, the resistance of the source and the drain with respect to the on-resistance of the MISFET increases, which causes a problem that high speed operation cannot be obtained even if the MISFET is miniaturized. So the source,
A self-aligned low-resistance silicide layer, such as cobalt silicide or titanium silicide, is formed on the surface of the semiconductor region forming the drain to reduce the resistance of the source and drain (self aligned silicid).
e: SALICIDE) technology is being studied.

However, since there is a concern about the problem of junction leakage due to the silicide layer, a method of forming a laminated spacer on the side wall of the gate electrode has been proposed as one of the countermeasures.

[0007] For example, IMD
ternational Electron Device Meetings "A 130 nm Gen
eration Logic Technology Featuring 70nm Transistor
s, Dual Vt Transistors and 6 layers of Cu Intercon
nects "2000) or VLSI Technology Symposium" A 0.15 μm CMOS
Foundry Technology with 0.1 μm Devices for High
Performance Applications "2000).

[0008]

The following is a method of manufacturing a MISFET having a laminated spacer structure to which the SAC technique has been studied, which has been studied by the present inventor, and the outline thereof is as follows.

First, as shown in FIG. 17, the semiconductor substrate 5
After forming the gate insulating film 52 and the gate electrode 53 of the MISFET on the main surface of No. 1, a semiconductor region 54 that constitutes a source and a drain is formed. Then, the semiconductor substrate 51
After the first insulating film 55 and the second insulating film 56 are sequentially deposited on the second insulating film 55, the second insulating film 56 is subjected to RIE (reactive ion etchin) using the first insulating film 55 as an etching stopper layer.
g) anisotropic etching. Then exposed first
The insulating film 55 is removed by wet etching to form a spacer made of the first insulating film 55 and the second insulating film 56 on the sidewall of the gate electrode 53.

Next, plasma CVD is performed on the semiconductor substrate 51.
A silicon nitride film 57 is deposited by (chemical vapor deposition) method. This silicon nitride film 57 is SAC
It functions as an etching stopper layer for the contact hole formed by using the technique.

Although not shown in the subsequent steps, next, an interlayer insulating film made of a silicon oxide film is deposited on the semiconductor substrate 51, and then the interlayer insulating film is dry-etched by using the photoresist pattern as an etching mask. By processing, a contact hole is formed above the semiconductor region 54 forming the source and drain. Then, using the interlayer insulating film as an etching mask, the exposed silicon nitride film 57 is removed to expose a part of the semiconductor region 54 forming the source and drain. After that, a metal film is embedded in the contact hole to form a plug, and a first-layer wiring electrically connected to the semiconductor region 54 forming the source and drain through the contact hole is formed.

However, the present inventor has found that the following problems occur in a CMOS device having a laminated spacer structure to which the SAC technique is applied.

That is, as shown in FIG. 17, when forming the laminated spacer, the second insulating film 56 is anisotropically etched using the first insulating film 55 as an etching stopper layer, and then exposed by a wet etching method. The removed first insulating film 55 is removed, but the etching proceeds isotropically by the wet etching method.

Therefore, the first insulating film 55 is also laterally etched, and an undercut portion 58 is formed under the second insulating film 56. The undercut portion 58 is
Even if the etching conditions for the second insulating film 56 are optimized, the first
It is difficult to prevent so long as the wet etching method is used for removing the insulating film 55.

When an undercut portion 58 is formed under the second insulating film 56, a silicon nitride film 57 serving as an etching stopper layer is deposited by the plasma CVD method in the SAC technique. 57 is not filled, and a cavity 59 is generated starting from this undercut portion 58. When a contact hole is formed in the interlayer insulating film on the cavity 59, the metal film, which is a constituent material of the plug, enters the cavity 59 and causes a short circuit between the source and the drain.

As a measure against the above, a method of adopting a silicon nitride film having a relatively good coating property deposited by a thermal CVD method on an etching stopper layer was examined. Although this silicon nitride film can fill the undercut portion under the second insulating film, the n-channel MI is different from the case where the silicon nitride film deposited by the plasma CVD method is used.
It has been clarified that the balance of the current driving capability between the SFET and the p-channel MISFET changes greatly. This is because the silicon nitride film deposited by the thermal CVD method has a larger tensile stress than the silicon nitride film deposited by the plasma CVD method.
The current drive capability of SFET increases, but p-channel MI
It is considered that this is because the current drive capability of the SFET is reduced.

An object of the present invention is to provide a source, in a CMOS device having a laminated spacer structure to which SAC technology is applied.
Prevents short circuit between drains, and also n channel MI
It is an object of the present invention to provide a technique capable of ensuring the balance of the current driving capabilities of the SFET and the p-channel MISFET.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0019]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

The present invention comprises a step of sequentially depositing a silicon oxide film and a silicon nitride film on an upper layer of a gate electrode of a CMOS device formed on a main surface of a semiconductor substrate, and a silicon nitride film using the silicon oxide film as an etching stopper layer. Is anisotropically etched, and then the exposed silicon oxide film is wet-etched to form a spacer having a laminated structure composed of a silicon nitride film and a silicon oxide film on the side wall of the gate electrode.
A step of sequentially depositing a first silicon nitride film by a VD method and a second silicon nitride film by a plasma CVD method to form a laminated film, and then depositing an interlayer insulating film; and using the laminated film as an etching stopper layer, And a step of forming a contact hole in the interlayer insulating film by etching using the resist pattern as a mask.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a CMOS device according to an embodiment of the present invention will be described with reference to the sectional views of the essential part of the semiconductor substrate shown in FIGS. Q in the figure
n is an n-channel MISFET, Qp is a p-channel MIS
It is a FET.

First, as shown in FIG. 1, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is prepared. Next, the semiconductor substrate 1 is thermally oxidized to have a thickness of 0.
A thin silicon oxide film 2 having a thickness of about 01 μm is formed, and then a silicon nitride film 3 having a thickness of about 0.1 μm is deposited on the silicon oxide film 2 by a CVD method.

After that, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are sequentially dry-etched using the resist pattern as a mask to form a device isolation groove having a depth of about 0.35 μm in the semiconductor substrate 1 in the device isolation region. 4a is formed.

Next, as shown in FIG. 2, after the silicon nitride film 3 is removed by a wet etching method using hot phosphoric acid, the silicon oxide film 4b deposited on the semiconductor substrate 1 by a CVD method is etched back or CMP (chemical mechani
The silicon oxide film 4b is left inside the element isolation groove 4a to form an element isolation region. Then, the semiconductor substrate 1 is annealed at about 1000 ° C. to densify the silicon oxide film 4b embedded in the element isolation trench 4a.

Next, after removing the silicon oxide film 2 using a hydrofluoric acid-based aqueous solution, the semiconductor substrate 1 is thermally oxidized,
A protective film 5 is formed on the surface of the semiconductor substrate 1. Next, boron for forming the p-type well 6 is ion-implanted into the formation region of the n-channel MISFET Qn of the semiconductor substrate 1,
The n-type well 7 is formed in the formation region of the p-channel MISFET Qp.
Is ion-implanted to form the.

Next, as shown in FIG. 3, after removing the protective film 5, the semiconductor substrate 1 is thermally oxidized to form a gate insulating film 8 on each surface of the p-type well 6 and the n-type well 7.
It is formed with a thickness of about nm. Then, after depositing an amorphous silicon film with a thickness of about 200 nm on the semiconductor substrate 1 by the CVD method, an n-type impurity such as phosphorus is ion-implanted into the amorphous silicon film in the formation region of the n-channel MISFET Qn to form the p-channel MISFET Qp. A p-type impurity such as boron is ion-implanted into the amorphous silicon film in the formation region.

Subsequently, for example, 950 is applied to the semiconductor substrate 1.
A heat treatment is performed at 60 ° C. for about 60 seconds to activate the n-type impurities and the p-type impurities introduced into the amorphous silicon film, and the amorphous silicon film in the formation region of the n-channel MISFET Qn is changed to the n-type polycrystalline silicon film 9n.
In s, the amorphous silicon film in the formation region of the p-channel MISFET Qp is changed to the p-type polycrystalline silicon film 9ps.

Thereafter, as shown in FIG. 4, these polycrystalline silicon films 9ns and 9ps are etched using the resist pattern as a mask to form a gate electrode having a gate length of about 0.1 to 0.12 μm in the formation region of the n-channel MISFET Qn. 9n is formed, and at the same time, a gate electrode 9p having a gate length of about 0.1 to 0.12 μm is formed in the formation region of the p-channel MISFET Qp. Thereafter, the semiconductor substrate 1 is subjected to a dry oxidation process at 800 ° C., for example.

Next, after covering the n-type well 7 with a resist film, an n-type impurity such as arsenic is ion-implanted into the p-type well 6 using the gate electrode 9n of the n-channel MISFET Qn as a mask to form the source / source of the n-channel MISFET Qn.
A relatively low-concentration source / drain extension region 10a forming a part of the drain is formed. Similarly, after covering the p-type well 6 with a resist film, the p-channel MISFETQ is formed.
A relatively low-concentration source / drain extension region forming part of the source / drain of the p-channel MISFET Qp by ion-implanting a p-type impurity such as boron fluoride into the n-type well 7 using the p gate electrode 9p as a mask. 11a
To form.

Next, as shown in FIG. 5, a silicon oxide film 12 having a thickness of about 10 to 20 nm and a silicon nitride film 13 having a thickness of about 80 nm are sequentially deposited on the semiconductor substrate 1. The silicon oxide film 12 is formed of, for example, TEOS (tetr
a ethyl ortho silicate: plasma CVD method using Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as source gas,
Alternatively, it can be deposited by a CVD method by thermal decomposition of organic silane.

Next, as shown in FIG. 6, the silicon oxide film 12 is used as an etching stopper layer for the silicon nitride film 13.
Is anisotropically etched by RIE to form an n-channel MIS
FET Qn gate electrode 9n and p-channel MISF
A spacer 14 is provided on each side wall of the ET gate electrode 9p.
To form.

Thereafter, as shown in FIG. 7, the exposed silicon oxide film 12 is removed by a wet etching method using an aqueous solution of hydrofluoric acid, so that the silicon nitride film 13 is removed.
2 by the spacer 14 and the silicon oxide film.
Layer spacers are formed. At this time, the silicon oxide film 12
The etching proceeds isotropically, so that an undercut portion 15 of about 20 nm from the end of the spacer 14 is formed under the spacer 14.

Next, as shown in FIG. 8, after covering the n-type well 7 with a resist film, an n-type impurity such as arsenic is added to the p-type well 6 using the gate electrode 9n and the spacer 14 of the n-channel MISFET Qn as a mask. Ion implantation,
A relatively high-concentration source / drain diffusion region 10b forming another part of the source / drain of the n-channel MISFET Qn is formed. Similarly, after covering the p-type well 6 with a resist film, p-type impurities such as boron fluoride are ion-implanted into the n-type well 7 using the gate electrode 9p and the spacer 14 of the p-channel MISFET Qp as a mask to form the p-channel MISFET Qp. A relatively high concentration source / drain diffusion region 11b forming another part of the source / drain is formed.

Next, a silicon nitride film 16a having relatively good coverage is deposited on the semiconductor substrate 1 by a thermal CVD method,
The undercut portion 15 formed under the spacer 14 is filled with the silicon nitride film 16a. Then, the semiconductor substrate 1
A silicon nitride film 16b is deposited on top by plasma CVD. Laminated film 16 composed of silicon nitride films 16a and 16b
Serves as an etching stopper layer for contact holes formed in the interlayer insulating film in a later step. For this reason,
The total film thickness is determined by the film thickness required for the etching stopper layer.

However, since the silicon nitride film 16a has a relatively large stress, its thickness is set to a thickness that does not affect the current driving capability of the MISFET, for example, about 20 nm. Further, the film thickness of the silicon nitride film 16b formed by the plasma CVD method is set to a thickness necessary for the laminated film 16 to function as an etching stopper layer.

Next, as shown in FIG. 9, after forming an interlayer insulating film 17 made of a silicon oxide film on the semiconductor substrate 1, the interlayer insulating film 17 is processed by a dry etching method using the resist pattern as a mask. , A contact hole 18n is formed above the source / drain diffusion region 10b of the n-channel MISFET Qn, and at the same time, the source / drain diffusion region 11 of the p-channel MISFET Qp is formed.
A contact hole 18p is formed above b. The laminated film 16 provided under the interlayer insulating film 17 is a material having an etching selection ratio with respect to the interlayer insulating film 17, and the laminated film 16 can stop the etching of the contact holes 18n and 18p. Although not shown, a contact hole reaching the gate electrode 9n of the n-channel MISFET Qn and the gate electrode 9p of the p-channel MISFET Qp is also formed at the same time.

Then, after the resist pattern is removed, the laminated film 16 exposed by using the interlayer insulating film 17 as an etching mask is removed, and the n-channel MISFET Qn is removed.
Source and drain diffusion regions 10b and p-channel M
A part of the source / drain diffusion region 11b of the ISFET Qp is exposed.

Then, a metal film, for example, a tungsten film is deposited on the semiconductor substrate 1 and the surface of the metal film is flattened by, for example, the CMP method to bury the metal film in the contact holes 18n and 18p.
9 is formed. Then, the metal film deposited on the interlayer insulating film 17 is etched to form the wiring layer 20, whereby the CMOS device of the first embodiment shown in FIG. 10 is substantially completed. In addition, you may form a multilayer wiring in the upper layer of the wiring layer 20 as needed.

Although the silicide layer for reducing the resistance of the source and drain is not formed in the first embodiment,
For example, the silicide layer may be formed using the following salicide technique.

First, before the step of depositing the laminated film 16,
For example, after depositing a cobalt film having a thickness of about 10 nm on the semiconductor substrate 1 by the sputtering method, 500 to 600 ° C.
A heat treatment of about 60 seconds is applied to the semiconductor substrate 1 to form a source / drain diffusion region 1 of the n-channel MISFET Qn.
0b surface and p-channel MISFET Qp source,
A thickness of 30n is selectively applied to the surface of the drain diffusion region 11b.
A silicide layer of about m is formed. At this time, the gate electrode 9n of the n-channel MISFET Qn and the p-channel M
A silicide layer may be formed on each surface of the gate electrode 9p of the ISFET Qp. After this, the semiconductor substrate 1
Heat treatment at about 700-800 ° C for about 90 seconds,
The resistance of the silicide layer is reduced.

As described above, according to the first embodiment, S
The etching stopper layer in the AC technique is the silicon nitride film 16a and plasma CV deposited by the thermal CVD method.
It is composed of a laminated film 16 made of a silicon nitride film 16b deposited by the D method. As a result, the undercut portion 15 generated by the two-layer spacer is filled with the silicon nitride film 16a, so that a defect due to the cavity, such as a short circuit between the source and the drain, can be prevented. In addition, since there is no cavity, n-channel MISFETQn
Since the contact hole 18n can be arranged in the vicinity of the gate electrode 9n, the distance between the gate electrode 9n and the contact hole 18n can be reduced, and similarly, the contact hole 18p can be formed in the vicinity of the gate electrode 9p of the p-channel MISFET Qp. Since they can be arranged, the distance between the gate electrode 9p and the contact hole 18p can be reduced, and the CMOS device can be highly integrated.

Further, the total film thickness of the laminated film 16 is set to a thickness necessary for the laminated film 16 to function as an etching stopper layer, but the thickness of the silicon nitride film 16a is set to the undercut portion 15. Since the minimum film thickness required to fill the gate can be obtained, the etching stopper layer is heated by CV.
The stress of the etching stopper layer can be reduced as compared with the case where the silicon nitride film deposited by the D method alone is used. As a result, it is possible to secure the balance of the current driving capabilities of the n-channel MISFETQn and the p-channel MISFETQp.

(Embodiment 2) A method of manufacturing a CMOS device according to another embodiment of the present invention will be described with reference to the sectional views of the essential part of the semiconductor substrate shown in FIGS.

First, as shown in FIG. 11, the gate electrode 9n of the n-channel MISFET Qn and the gate electrode 9p of the p-channel MISFET Qp are formed by the same method as in the first embodiment, and then part of the source / drain is formed. Source / drain diffusion region 10 having relatively low concentration
a and 11a are formed. The steps up to this point are the same as the steps shown in FIGS. 1 to 4 of the first embodiment.

Next, as shown in FIG. 12, the semiconductor substrate 1
A silicon oxide film 21 having a thickness of about 10 to 20 nm,
Silicon nitride films 22 and 60n having a thickness of about 20 nm
A silicon oxide film 23 having a thickness of about m is sequentially deposited. The silicon oxide films 21 and 23 can be deposited by, for example, a plasma CVD method using TEOS and ozone as source gases or a CVD method by thermal decomposition of organic silane.

Next, as shown in FIG. 13, the silicon oxide film 2 is formed by using the silicon nitride film 22 as an etching stopper layer.
3 is anisotropically etched by the RIE method to obtain an n-channel MI.
Gate electrode 9n and p-channel MIS of SFETQn
A spacer 2 is provided on each side wall of the FET gate electrode 9p.
4 is formed. Then, the exposed silicon nitride film 22 is removed by a dry etching method.

Next, as shown in FIG. 14, the exposed silicon oxide film 21 is removed by a wet etching method using a hydrofluoric acid-based aqueous solution, whereby the silicon oxide film 2 is removed.
A three-layer spacer is formed by the spacer 24 composed of 3, the silicon nitride film 22, and the silicon oxide film 21. At this time, since the etching of the silicon oxide film 21 proceeds isotropically, an undercut portion 25 of about 20 nm is formed below the spacer 24 from the end portion of the spacer 24.

After that, in the same manner as in the first embodiment,
As shown in FIG. 15, a silicon nitride film 16a having relatively good coverage is deposited on the semiconductor substrate 1 by a thermal CVD method,
The undercut portion 25 formed under the spacer 14 is filled with the silicon nitride film 16a. Then, the semiconductor substrate 1
A silicon nitride film 16b is deposited on top by plasma CVD.

Subsequently, the interlayer insulating film 17 is formed on the semiconductor substrate 1.
After the formation of the n-channel MISFE
Contact hole 18n of TQn and p channel M
The contact hole 18p of the ISFET Qp is punched, and then the exposed laminated film 16 is removed to remove the n-channel MI.
Source / drain diffusion region 10b of SFET and source / drain diffusion region 11b of p-channel MISFET.
Expose part of. Next, contact holes 18n,
By forming the plug 19 inside the 18p and then etching the metal film deposited on the semiconductor substrate 1 to form the wiring layer 20, the C of the second embodiment shown in FIG. 16 is formed.
MOS device is almost completed.

As described above, according to the second embodiment, even when the three-layer spacers are provided on the side walls of the gate electrodes 9n and 9p, the undercut portion produced by the three-layer spacers is the same as in the first embodiment. 25 is filled with the silicon nitride film 16a to prevent defects due to cavities, such as short-circuit between the source and drain.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the silicon nitride film deposited by the thermal CVD method is used as the insulating film that functions as the etching stopper layer in the SAC process and fills the undercut portion generated in the laminated spacer. It is possible to use an insulating film other than those having an etching selection ratio with respect to the interlayer insulating film and having relatively good coverage.

[0054]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

By forming the etching stopper layer of the contact hole with a laminated film including a first insulating film having a relatively good covering property and a second insulating film having a relatively small stress, a laminated spacer is formed. The formed undercut portion is filled with the first insulating film, and the stress exerted on the CMOS device is made relatively small. As a result, it is possible to prevent the occurrence of cavities in the laminated film, prevent a short circuit between the source and drain of the CMOS device, and ensure the balance of the current driving capabilities of the n-channel MISFET and the p-channel MISFET.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device which is an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to another embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to another embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a CMOS device according to another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a CMOS device according to another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device which is another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a CMOS device according to another embodiment of the present invention.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a CMOS device examined by the present invention.

[Explanation of symbols]

1 Semiconductor substrate 2 Silicon oxide film 3 Silicon nitride film 4a Element isolation groove 4b Silicon oxide film 5 protective film 6 p-type well 7 n-type well 8 Gate insulation film 9ns n-type polycrystalline silicon film 9ps p-type polycrystalline silicon film 9n gate electrode 9p gate electrode 10a Source / drain extension region 10b Source / drain diffusion region 11a Source / drain extension region 11b Source / drain diffusion region 12 Silicon oxide film 13 Silicon nitride film 14 Spacer 15 Undercut part 16 laminated film 16a Silicon nitride film 16b Silicon nitride film 17 Interlayer insulation film 18n contact hole 18p contact hole 19 plug 20 wiring layers 21 Silicon oxide film 22 Silicon nitride film 23 Silicon oxide film 24 spacer 25 Undercut part 51 Semiconductor substrate 52 Gate insulating film 53 Gate electrode 54 Semiconductor area 55 First insulating film 56 Second insulating film 57 Silicon nitride film 58 Undercut part 59 cavity Qn n-channel MISFET Qp p channel MISFET

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinichiro Mitani             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center (72) Inventor Yohei Yanagida             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F-term (reference) 4M104 BB01 BB18 BB19 DD02 DD04                       DD07 DD08 DD09 DD16 DD17                       DD78 DD84 EE09 EE15 EE17                       GG10 GG14                 5F033 HH04 HH07 JJ19 KK01 KK25                       QQ09 QQ13 QQ16 QQ19 QQ25                       QQ37 QQ48 QQ70 QQ73 RR04                       RR06 SS01 SS03 SS04 SS11                       SS15 TT02 TT08                 5F048 AA01 AB03 AC03 BA01 BB06                       BB07 BB08 BC06 BE03 BF06                       BF07 BF16 BG14 DA23 DA25                       DA27 DA30                 5F140 AA05 AA08 AA14 AA24 AA39                       AB03 BA01 BE03 BE07 BF01                       BF04 BF11 BF18 BG09 BG10                       BG12 BG14 BG28 BG30 BG32                       BG33 BG34 BG41 BG52 BG53                       BH14 BH15 BJ01 BJ07 BJ08                       BJ11 BJ17 BJ27 BK02 BK13                       BK27 BK29 BK34 CB04 CB08                       CC01 CC03 CC08 CC12 CC13                       CE07 CF04

Claims (4)

[Claims] 1. (a) A step of forming a spacer having a laminated structure composed of two or more insulating films on a sidewall of a gate electrode of a CMOS device formed on a main surface of a semiconductor substrate,
(B) First with relatively good coverage on the semiconductor substrate
And the second insulating film having a relatively small stress are sequentially deposited to form a laminated film, and then an interlayer insulating film is deposited, and (c) the laminated film is used as an etching stopper layer, and a resist is used. And a step of processing the interlayer insulating film by etching using a pattern as a mask. 2. (a) A step of forming a spacer having a laminated structure composed of two or more insulating films on the side wall of the gate electrode of the CMOS device formed on the main surface of the semiconductor substrate,
(B) a step of sequentially depositing a first silicon nitride film by a thermal CVD method and a second silicon nitride film by a plasma CVD method on the semiconductor substrate to form a laminated film, and then depositing an interlayer insulating film; And (c) a step of processing the interlayer insulating film by etching using the laminated film as an etching stopper layer and a resist pattern as a mask. 3. A step of (a) sequentially depositing a silicon oxide film and a silicon nitride film on an upper layer of a gate electrode of a CMOS device formed on a main surface of a semiconductor substrate, and (b) anisotropically forming the silicon nitride film. Of the silicon oxide film exposed by wet etching after wet etching to form a spacer having a laminated structure composed of the silicon nitride film and the silicon oxide film on the side wall of the gate electrode, and (c) the semiconductor. A step of sequentially depositing a first silicon nitride film by a thermal CVD method and a second silicon nitride film by a plasma CVD method on a substrate to form a laminated film, and then depositing an interlayer insulating film; And a step of processing the interlayer insulating film by etching using the laminated film as an etching stopper layer and a resist pattern as a mask. And a method for manufacturing a semiconductor device. 4. (a) A step of sequentially depositing a first silicon oxide film, a silicon nitride film and a second silicon oxide film on an upper layer of a gate electrode of a CMOS device formed on a main surface of a semiconductor substrate, (B) by anisotropically etching the second silicon oxide film, dry etching the exposed silicon nitride film, and then wet etching the exposed first silicon oxide film,
A step of forming a spacer having a laminated structure composed of the second silicon oxide film, the silicon nitride film, and the first silicon oxide film on a sidewall of the gate electrode, and (c) a thermal CVD method on the semiconductor substrate. A step of sequentially depositing a first silicon nitride film and a second silicon nitride film by a plasma CVD method to form a laminated film, and then depositing an interlayer insulating film; and (d) using the laminated film as an etching stopper layer. And a step of processing the interlayer insulating film by etching using a resist pattern as a mask.