JP2002318264A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To eliminate the need for a signal input pin for switching between a test mode and a normal mode without affecting the original circuit or circuit element. SOLUTION: A shift register 11 counts an elapsed time from the time when a reset signal (/ RES) arrives using a clock (CP) which is a system clock, and when the counting result reaches zero, a decoder. 12 resets the flip-flops 13 and 14 that store the operation mode, and thereafter, every time the mode switching signal included in the reset signal (/ RES) is input, the count value of the shift register 11 is incremented by +1. The decoder 12 determines the operation mode (either the normal mode or the test mode) stored in the flip-flops 13 and 14 based on the count value of the shift register 11 after the addition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an ASIC (Application Specif.) Capable of switching to a test mode without having an interface with a CPU.
ic integrated circuit).

[0002]

2. Description of the Related Art Conventionally, when testing (testing) a semiconductor integrated circuit such as an ASIC, a self-test circuit having a multiplexer added inside is formed. A method of switching from a test mode to a test mode has been implemented. As a method of switching the internal circuit, when the ASIC has an interface with the CPU, the problem can be solved by writing data (parameter used at the time of change) from the CPU to a register or the like in the ASIC. For an ASIC that is used without having an interface of the above, a test pin (input terminal for forming a test mode) is separately provided in addition to the input pin of the original ASIC. A method using a test pin was used. FIG. 3 is a block diagram showing a configuration example of a connection terminal of an ASIC used without having an interface with a conventional CPU. The ASIC (91) shown in FIG.
On the input side, a clock terminal (pin), a / reset signal terminal, a test pin serving as a test pin, and an input signal terminal are arranged, and on the output side, only an output signal terminal is arranged. It is. By using the test pin on the input side, for example, a circuit change such as disconnecting a part of the circuit inside the ASIC (91) is enabled. A prior patent for a method of switching an internal circuit without using a test pin is disclosed in Japanese Patent Application Laid-Open No. 6-138191 entitled "Semiconductor Integrated Circuit". (Self-test circuit) to set the level of the system clock input from outside,
There is disclosed a method of causing the self-test circuit to perform the above-described switching operation depending on whether the power supply is set to a high level or a low level when the power is turned on.

[0003]

In the conventional ASIC test method, when the ASIC has no interface with the CPU, it is necessary to separately provide an input pin for test. These input pins are not necessary in the original use of the ASIC, and are not only wasted, but also cause erroneous use (erroneous wiring). Also, the installation of the input pin dedicated to the test has a problem in terms of cost. According to the method disclosed in "Semiconductor Integrated Circuit" of Japanese Patent Application Laid-Open No. 6-138191, the level of a system clock input from the outside is set to a high level in synchronization with the power-on time, or set to a low level. A circuit (device) that makes a difference is required outside the semiconductor integrated circuit, and an extra device load is generated. Also, the reset signal is not a general reset means because it is not a type that is introduced from the outside, but is a mechanism that is spontaneously issued when the power is turned on from a circuit called a “power-on reset circuit” installed inside ( Generally, a reset signal may not be input when the power is turned on, for example, during a restart process after an interruption.) In addition, there is a temporally unstable width at the time of power-on, and when the system clock is high-speed, it is difficult to completely match a predetermined position at the time of power-on. , Or the test mode is used, the determination becomes unstable, which is not suitable for practical use. The present invention has been made in view of the above-described problems in the conventional semiconductor integrated circuit, and switches between the test mode and the normal mode without affecting the original circuit or circuit element. It is an object of the present invention to provide a semiconductor integrated circuit which can eliminate the need for an input pin of a signal for the purpose.

[0004]

According to the present invention, in order to solve the above-mentioned problems, an internal circuit to be tested and a self-test circuit for switching the operation of the internal circuit between a normal mode and a test mode are described. The operation mode of the internal circuit is set to a normal mode by detecting a predetermined mode switching signal added to a reset signal for resetting the internal circuit. A semiconductor integrated circuit including a self-test circuit for switching to any one of the modes. Further, the self-test circuit can switch the current operation mode of the internal circuit to another operation mode by detecting the mode switching signal. Further, the self-test circuit counts an elapsed time from the reset time in units of a system clock interval, and resets a flip-flop that stores an operation mode when the counted result reaches zero. Each time a mode switching signal is detected, the count value is increased by a unit amount, and an operation mode to be stored in the flip-flop is determined to be one of a normal mode and a test mode based on the count value after the increase. can do. Also,
The self-test circuit can determine an operation mode to be stored in the flip-flop from the count value based on a decoding result of a decoder circuit that decodes the count value. That is, in the present invention, a self-test circuit is provided which applies a predetermined data pattern to the reset signal of the semiconductor integrated circuit, decodes the data pattern inside the semiconductor integrated circuit, and switches between the test mode and the normal mode. As a result, switching between the test mode and the normal mode is performed without affecting the original circuit or circuit element. In addition, with the above configuration, the configuration of the input terminal eliminates the need for a signal input pin for switching between the test mode and the normal mode.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one configuration example of a semiconductor integrated circuit according to an embodiment of the present invention.
The semiconductor integrated circuit according to the present embodiment has, as a self-test circuit, a shift register 11 for serial-to-parallel conversion of a reset signal (/ RES), and a value of the reset signal (/ RES) set in the shift register 11. And a flip-flop 13, 14 for stably fixing the output of the decoder 12 and switching out one of the normal mode signal (MODE1) and the test mode signal (MODE2). FIG.
, The code (CP) is a clock (system clock), the code (/ RES) is a reset signal, and the code (/ MO)
DERES) means an internal mode reset signal. Although the semiconductor integrated circuit according to the embodiment of the present invention has an input signal terminal (for a normal mode and a test mode) and a circuit to be tested in addition to the above-described self-test circuit, These are not shown. FIG. 2 is a timing chart showing an example of an input timing of a signal input to the semiconductor integrated circuit according to the embodiment of the present invention. The clock (CP) is a system clock that repeats a simple binary of a high level and a low level, and is input from the outside. Reset signal (/ RE
S) shows a case where the test mode is set. The conventional reset signal shown is flat, but the reset signal (/ RES) input to the semiconductor integrated circuit according to the present invention is in the test mode (MODE2).
In this case, for example, a rising portion indicated by “separation 1” shown in FIG. 2, a single rising portion shown thereafter, a rising portion indicated by “separation 1”, and the like are included.

Hereinafter, the operation of the self test circuit of the semiconductor integrated circuit according to the present embodiment will be described. The self test circuit of the semiconductor integrated circuit according to the present embodiment has a principle request that a predetermined mode switching signal is added to a reset signal (/ RES) for resetting an internal circuit. By detecting the switching signal,
The operation mode of the internal circuit is switched to one of the normal mode and the test mode. First, a reset signal (/ RES) arrives at the shift register 11 such that a value (data pattern) of “00000” is held.
As a result, the decoder 12 decodes the value "00000" and outputs the internal mode reset signal (/ MODERE).
S) is output at a low level. This allows the clock (C
Waiting for the next clock after P), the flip-flop 13,
14 is reset. A reset signal (/ RES) for setting the value of the shift register 11 to "00000"
Is the same as a conventional normal reset signal, and the arrival of such a reset signal (/ RES) resets the inside of the circuit as usual. Next, the reset signal (/ RES) becomes a high level at a portion (portion of the mode switching signal) indicated by “1 of the break” in FIG.
Waiting for a state where the value of the shift register 11 becomes “00001”, an internal mode reset signal (/ MODERES)
Changes to a high level, and the output of the decoder 12 (/
1) changes to low level, and this output is applied to the clock (C
Waiting for the next clock after P), the subsequent flip-flop 1
3 is inverted and the normal mode signal (MODE1) is output. After that, another reset signal (/ RES)
Each time the shift register 11 becomes high level (meaning the arrival of the next mode switching signal) and the value of the shift register 11 becomes "00010", the output (/ 2) of the decoder 12 turns to low level. Waits for the next clock after the clock (CP), is inverted and input to the flip-flop 14 at the subsequent stage, and the test mode signal (MODE2) is output.
In the above control process, if it is desired to execute only the normal mode without executing the test mode, the reset signal (/ RES) is supplied with the rising portion indicated by the "1" of the delimiter. It is sufficient to add only the (first mode switching signal) and not to add the subsequent rising portion (the next mode switching signal). It should be noted that the control process after the portion indicated by “Separation 2” in FIG. 2 can be controlled at the same timing as the control process after “Separation 1” as needed.

[0007]

As described above, according to the present invention, a predetermined data pattern is added to the reset signal of the semiconductor integrated circuit, and this data pattern is decoded inside the semiconductor integrated circuit to switch between the test mode and the normal mode. Since the self-test circuit for switching is provided, it is possible to switch between the test mode and the normal mode without affecting the original circuit or circuit element. In addition, the configuration of the input terminal can be a configuration that does not require the presence of a signal input pin for switching between the test mode and the normal mode.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one configuration example including a self-test circuit of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of an input timing of a signal input to the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a connection terminal of an ASIC used without having an interface with a conventional CPU.

[Explanation of symbols]

 11 shift register, 12 decoder, 13, 14 flip-flop, CP clock (system clock), / RES reset signal, / MODERES internal mode reset signal, MODE1 normal mode Signal, MODE2 …… Test mode signal

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Claims (4)

[Claims] 1. A semiconductor integrated circuit comprising: an internal circuit to be tested; and a self-test circuit for switching an operation of the internal circuit between a normal mode and a test mode in a chip. A self-test circuit for switching the operation mode of the internal circuit to one of a normal mode and a test mode by detecting a predetermined mode switching signal added to a reset signal for resetting the circuit; A semiconductor integrated circuit characterized by the above. 2. The semiconductor integrated circuit according to claim 1, wherein the self-test circuit switches a current operation mode of the internal circuit to another operation mode by detecting the mode switching signal. 3. The self-test circuit counts an elapsed time from the reset time in units of a system clock interval, and resets a flip-flop storing an operation mode when the counted result reaches zero. Thereafter, each time the mode switching signal is detected, the count value is increased by a unit amount, and the operation mode for storing in the flip-flop based on the increased count value is one of a normal mode and a test mode. 2. The semiconductor integrated circuit according to claim 1, wherein the decision is made on one side. 4. The self-test circuit according to claim 3, wherein an operation mode to be stored in the flip-flop is determined from the count value based on a decoding result of a decoder circuit that decodes the count value. Semiconductor integrated circuit.