JP2000321331A - Scan test circuit and semiconductor integrated circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately execute an operation test in an integrated circuit including an asynchronous circuit part with a simple configuration. SOLUTION: This scan test circuit 100 has a D-type flip-flop 102, a selector 104 for switching an operation mode, a delay circuit 106 inserted along a scan path 110, and a delay circuit 108 inserted along a clock path 112. The selector 104 switches data input between a normal operation and a scan operation on the basis of a mode select signal. That is, the selector 104 inputs normal data in the normal operation, while inputting a testing scan signal in the scan operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan test circuit built in a semiconductor integrated circuit composed of a plurality of logic circuits. In particular, the present invention relates to an improvement in a scan test circuit for a semiconductor integrated circuit including an asynchronous logic circuit operating at different clocks.

[0002]

2. Description of the Related Art A scan test circuit is widely used as an effective test method to enable a test to be performed for each functional block and to improve test efficiency and a failure detection rate. In the scan test method,
By treating a flip-flop circuit provided inside the semiconductor integrated circuit as a shift register, an arbitrary value is set and extracted from the flip-flop. Here, a path connecting the flip-flops is called a scan path.

[0005] The scan test method is originally applied to a synchronous circuit operating with the same clock. For this reason, conventionally, when performing a scan test of an asynchronous circuit that operates on a different clock, a special clock for the test is prepared and the test is performed using the special clock. That is, the asynchronous circuit is operated as a synchronous circuit only during the test.

FIG. 6 shows a configuration of a main part of a general scan test circuit (10) applied to a synchronous circuit. The scan test circuit 10 includes a selector 12 for switching operation modes and a D-type flip-flop 14. The selector 12 switches between a normal operation and a scan test operation based on the mode selector signal. The D-type flip-flop 14 operates according to a clock signal.

FIG. 7 shows a configuration of a general semiconductor integrated circuit (20) using a scan test circuit for a synchronous circuit. The semiconductor integrated circuit 20 includes a combinational circuit (logic circuit) 2
2a, 22b, 22c, flip-flop circuit 24,
26, 27, and 28. A clock signal is supplied to the flip-flop circuits 24, 26, 27, and 28 via a clock path 23. Flip-flop circuit 2
The scan signals are supplied to 4, 26, 27 and 28 via the scan path 25.

In the semiconductor integrated circuit shown in FIG. 7, during normal operation, flip-flops 24, 26, 27 and 28 are switched to a normal operation mode by a mode select signal, and data signals are applied to combinational circuits 22a, 22b and 22c.
And flip-flops 24, 26, 27, 28. On the other hand, during the scan test operation, flip-flops 24, 26, 2
7 and 28 are switched to the scan test mode, and a scan signal for test is output by the scan path 25 through the flip-flops 24, 26, 27 and 28. Then, the operation of the semiconductor integrated circuit is checked based on the scan output signal. All the flip-flop circuits 24, 26, 27, and 28 operate according to a clock signal (CLK) supplied via the clock path 23.

FIG. 8 shows an example in which a conventional scan test technique is applied to an asynchronous circuit. Scan test circuit 30
Includes flip-flop circuits 32, 34, and 36. Each of the flip-flops 32, 34, 36 is connected by a scan path 35 to receive a scan signal. The flip-flop circuit 3
2, 34 and 36 are supplied with a clock signal via a clock path 37. A delay circuit 38 is inserted on the clock path 37 immediately before the flip-flop 36.

FIG. 9 is a timing chart showing the operation of the scan test circuit shown in FIG. As can be seen from the figure, the clock input to the flip-flop 36 is changed by the operation of the delay circuit 38 to the other flip-flops 32,
Slightly behind 34. Therefore, the flip-flop 36
Does not operate as a shift register.

FIG. 10 shows a main part of a conventional scan test circuit 40 applied to an asynchronous circuit. The scan test circuit 40 includes a selector 42 for switching the operation mode of the data input, a selector 44 for switching the operation mode of the clock signal, and a D-type flip-flop 46. The selector 42 switches the data output between the normal operation and the scan test operation based on the mode select signal. The selector 44 switches the clock between the normal operation and the scan test operation based on the mode select signal. That is, a normal clock is supplied to the D-type flip-flop 46 during a normal operation, and a test clock is supplied to the D-type flip-flop 46 during a scan test operation. And D
The type flip-flop 46 operates according to a clock signal selectively supplied.

FIG. 11 shows a configuration of a conventional semiconductor integrated circuit (50) using a scan test circuit for an asynchronous circuit. The semiconductor integrated circuit 50 is a combinational circuit (logic circuit)
52a, 52b, 52c and a flip-flop circuit 5
4, 56, 58, and 60. A clock signal is supplied to the flip-flop circuits 54, 56, 58, and 60 via a clock path 64. A delay circuit 6 is provided on the clock path 64 between the flip-flop circuits 56 and 60.
2 has been inserted. Flip-flop circuits 54, 5
6, 58 and 60 are supplied with a scan signal via a scan path 66. Further, a test clock signal is supplied to the flip-flop circuits 54, 56, 58, and 60 via a path 68.

In the semiconductor integrated circuit shown in FIG. 11, during normal operation, flip-flops 54, 56, 58, and 60 are switched to a normal operation mode by a mode select signal, and normal data is transmitted to combinational circuits 52a, 52b, and 5.
2c and output via flip-flops 54, 56, 58, 60. At this time, the flip-flops 54 and 5
6, 58 and 60 operate according to the normal clock (CLK) supplied via the clock path 64.

On the other hand, during the scan test operation, the flip-flops 54, 56, 5
8 and 60 are switched to the scan test mode, and a test scan signal is output by the scan path 66 through the flip-flops 54, 56, 58 and 60. At this time, the flip-flops 54, 56, 58, 6
0 operates according to the test clock (test CLK) supplied via the path 68.

FIG. 12 shows a configuration of a conventional scan test circuit 70 built in a semiconductor integrated circuit including an asynchronous circuit. The scan test circuit 70 includes flip-flop circuits 72, 74, 76, 78, 80, 8 connected in series.
2 is comprised. These flip-flop circuits 72 to 82 are connected by a scan path 88. The flip-flop circuits 72 to 82 are supplied with a test clock via a test clock path 90 and a normal clock via a path 86. Flip-flop 7
A delay circuit 84 is inserted on a path 86 between the terminals 4 and 76.

Scan test circuit 7 configured as described above
At 0, during normal operation, a clock signal is provided to each flip-flop 72-82 via path 86.
Since the delay circuit 84 is inserted on the clock path 86 between the flip-flops 74 and 76, the flip-flops 72 and 74 and the flip-flops 76, 78 and 8
0 and 82 operate asynchronously.

On the other hand, when performing a scan test, a test clock is supplied to flip-flops 72 to 82 via a test clock path 90 instead of the normal clock. Since there is no delay circuit in test clock path 90, all flip-flops 72 to 82 operate in synchronization. This makes it possible to accurately test the operation of the semiconductor integrated circuit.

[0016]

However, in the above-described conventional scan test circuit, a test clock is used when testing an asynchronous circuit. That is, a clock is used so that the asynchronous circuit operates as a synchronous circuit only during the scan test. For this reason, a circuit for generating a test clock and a selector for changing an operation mode are indispensable, resulting in an increase in circuit scale.

The present invention has been made in view of the above situation, and has a simple configuration and a scan test circuit capable of accurately performing an operation test of a semiconductor integrated circuit including an asynchronous circuit portion. And a semiconductor integrated circuit using the same.

[0018]

In order to solve the above-mentioned problems, a scan test circuit according to the present invention includes a scan path for leading a test scan signal; and a delay circuit inserted in the middle of the scan path. ing. Further, a semiconductor integrated circuit according to the present invention includes a scan test circuit having the above configuration.

As described above, in the present invention, the delay (timing difference) of the clock is canceled by inserting the delay circuit in the middle of the scan path. Therefore, it is not necessary to use a special clock for the scan test, and the circuit scale does not increase. That is, the operation test of the semiconductor integrated circuit including the asynchronous circuit portion can be accurately performed with a simple configuration.

In the present invention, for example, while using a single clock, a delay circuit can be inserted in the middle of a clock path for leading the clock. At this time, the delay circuit inserted in the middle of the scan path is set to have a delay time corresponding to the delay circuit inserted in the middle of the clock path. Further, the delay circuit inserted in the middle of the scan path can include at least one of an even number of inversion circuits, buffer circuits, and delay elements.

[0021]

FIG. 1 shows the configuration of a main part of a scan test circuit 100 for an asynchronous circuit according to the basic concept of the present invention. The scan test circuit 100 includes a D-type flip-flop 102 and a selector 1 for switching an operation mode.
04, a delay circuit 106 inserted in the middle of the scan path 110, and a delay circuit 108 inserted in the middle of the clock path 112. The selector 104 switches data input between a normal operation and a scan test operation based on the mode select signal. That is, normal data is input during a normal operation, and a test scan signal is input during a scan test operation.

As the delay circuit 106, for example, a plurality (even number) of inverting circuits, buffers, delay elements and the like can be used. The delay circuit 106 is the delay circuit 1
It is designed to have a delay time corresponding to 08.
As a result, the flip-flop 102 operates as a shift register during the scan test.

FIG. 2 shows a semiconductor integrated circuit 20 according to the present invention.
0 is shown. The semiconductor integrated circuit 200 includes combinational circuits (logic circuits) 202a, 202b, and 202c, and flip-flop circuits 204, 206, 208, and 210. Flip-flop circuits 204, 206, 20
8, 210, a clock signal (CLK) is supplied via a clock path 216. Flip-flop circuit 20
6 and 208 on the clock path 216
4 has been inserted.

The flip-flop circuits 204, 206, 2
08 and 210 are also supplied with a scan signal via a scan path 218. Flip-flop circuit 20
6 and 208 on the scan path 218
2 has been inserted. As the delay circuit 212, for example, a plurality (even number) of inversion circuits, buffers, delay elements, and the like can be used. The delay circuit 212 is designed to have a delay time corresponding to the delay circuit 214. As a result, the flip-flops 208 and 210 operate as shift registers during the scan test.

In the semiconductor integrated circuit shown in FIG. 2, during normal operation, flip-flops 204, 206, 208, and 210 are switched to a normal operation mode by a mode select signal, and normal data is transferred to combinational circuits 202a and 20a.
2b, 202c and flip-flops 204, 206,
Output via 208 and 210. At this time, the flip-flops 204, 206, 208, 210 operate according to the clock (CLK) supplied via the clock path 216. Here, the flip-flop circuit 206
Delay circuit 214 on the clock path 216 between
Are inserted, the flip-flops 208 and 21
0 operates with a certain time delay from the flip-flops 204 and 206.

On the other hand, during the scan test operation, flip-flops 204, 206,
The scan signals 208 and 210 are switched to the scan test mode, and the scan signals for the test are sequentially supplied to the flip-flops 204, 206, 208 and 2 by the scan path 218.
It is output via 10. Here, since the delay circuit 212 is inserted on the scan path 218 between the flip-flop circuits 206 and 208,
8, 210 operate correctly as a shift register despite the delayed operation by the delay circuit 214. Therefore, data obtained as a scan output shows an accurate value.

FIG. 3 shows a configuration of a scan test circuit 300 according to another embodiment of the present invention. FIG. 4 shows the operation of the scan test circuit 300. The scan test circuit 300 includes flip-flop circuits 304 and 308. The flip-flop circuits 304 and 308 include:
A clock signal is supplied via the clock path 314. A delay circuit 310 is inserted in the middle of the clock path 314, and the flip-flop circuit 308 operates with a certain time delay from the flip-flop circuit 304.
The flip-flop circuits 304 and 308 are connected by a scan path 316b. Scan path 316
A delay circuit 312 is inserted in the middle of b.

FIG. 5 shows a configuration of a scan test circuit 400 according to still another embodiment of the present invention. The scan test circuit 400 includes flip-flop circuits 402, 404, 406, 408, 410, and 412 connected in series. These flip-flop circuits 402 to 4
12 are connected by a scan path 418.
A clock is supplied to the flip-flop circuits 402 to 412 via a clock path 420. On the clock path 420 between the flip-flops 404 and 406,
A delay circuit 416 is inserted. Correspondingly, scan path 418 between flip-flops 404 and 406
A delay circuit 414 is also inserted above.

In the scan test circuit 400 shown in FIG. 5, a test scan signal is sequentially output by the scan path 418 via the flip-flops 402 to 412. Here, flip-flop circuits 404 and 406
Since the delay circuit 414 is inserted on the scan path 418 between the flip-flop 406 and the flip-flop 406, the flip-flop 406 and the subsequent operate with a certain delay time (in an asynchronous state). That is,
As a whole, the flip-flops 402 to 412 operate as shift registers. For this reason, data obtained as a scan output shows the same exact value as the actual operation state.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments at all, and can be modified within the scope of the technical idea shown in the claims. is there. For example, the scan test circuit of the present invention can be applied not only to a semiconductor integrated circuit in which a delay element is arranged in the middle of a clock path, but also to a semiconductor integrated circuit which operates using a fundamentally different clock.

[0031]

As described above, in the present invention, the delay (timing difference) of the clock is canceled by inserting the delay circuit in the middle of the scan path. Therefore, it is not necessary to use a special clock for a scan test, and an increase in circuit scale can be avoided. That is, the operation test of the semiconductor integrated circuit including the asynchronous circuit portion can be accurately performed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a scan test circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a scan test circuit according to another embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of the scan test circuit shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration of a scan test circuit according to still another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a general scan test circuit used for a scan test of a synchronous circuit.

FIG. 7 is a block diagram showing a configuration of a general semiconductor integrated circuit including a scan test circuit for a synchronous circuit.

FIG. 8 is a block diagram showing a configuration of a conventional scan test circuit used for a scan test of an asynchronous circuit.

FIG. 9 is a timing chart showing an operation of the scan test circuit shown in FIG. 8;

FIG. 10 is a block diagram showing a configuration of a conventional scan test circuit used for a scan test of an asynchronous circuit.

FIG. 11 is a block diagram showing a configuration of a conventional semiconductor integrated circuit incorporating a scan test circuit for asynchronous circuits.

FIG. 12 is a block diagram showing a configuration of a conventional scan test circuit used for a scan test of an asynchronous circuit.

[Explanation of symbols]

100, 300, 400 Scan test circuit 106, 212, 312, 414 Delay circuit (on scan path) 108, 214, 310, 416 Delay circuit (on clock path) 110, 218, 316a, 316b, 418 Scan path 112, 216 , 314,420 Clock path 200 Semiconductor integrated circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA00 AC10 AD06 AG07 AK16 AL00 5B048 AA20 CC18 DD07 5F038 BE05 DF01 DT06 EZ20

Claims (6)

[Claims] 1. A scan test circuit used for an operation test of an integrated circuit that operates with a plurality of clocks having different timings, wherein: a scan path for leading a test scan signal; And a delay circuit for canceling the timing difference between the clocks. 2. The method according to claim 1, wherein the plurality of clocks are generated by using a single clock and inserting a delay circuit in a clock path for guiding the clock. Scan test circuit. 3. A delay circuit inserted in the middle of the scan path has a delay time corresponding to a delay circuit inserted in the middle of the clock path.
The scan test circuit according to 1. 4. The delay circuit inserted in the middle of the scan path includes at least one of an even number of inverting circuits, buffer circuits, and delay elements. Scan test circuit. 5. A scan test circuit used for an operation test of a semiconductor integrated circuit having a clock path for leading a clock and a first delay circuit inserted in the middle of the clock path, wherein a plurality of test flip-flops are provided. A flip-flop circuit; a scan path connecting the flip-flop circuits and introducing a test scan signal to the flip-flop circuits; A scan circuit, wherein the first and second delay circuits have substantially the same delay time. 6. A semiconductor integrated circuit that operates with a plurality of clocks having different timings, comprising: a scan test circuit used for an operation test of the integrated circuit; wherein the scan test circuit scans a test scan signal. And a delay circuit inserted in the middle of the scan path to cancel a timing difference between the plurality of clocks.