JP2002368201A - Solid-state imaging device and imaging system using the same - Google Patents

Abstract

(57) [Problem] To provide a solid-state imaging device capable of obtaining a distortion-free image even for a moving subject by setting the start and end timings of a signal accumulation operation to all pixels simultaneously. SOLUTION: An N-type semiconductor region 21 serving as a signal charge holding portion formed in a channel portion immediately below a transfer gate 19,
The N-type semiconductor region 2 formed between the charge holding region 21 and the floating diffusion region 18 and completely depleted when the potential of the floating diffusion region 18 is sufficiently reverse biased to the P-type well 16.
2. The light-shielding layer 23 is formed so as to block light from entering the charge holding region 21. The operation of one pixel is as follows: signal charge accumulation in the photodiode region 17 → signal charge accumulated in the photodiode region 17
→ transfer of signal charges from the charge holding region 21 to signal floating from the charge holding region 21 to the floating diffusion region 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device used in a digital imaging system or the like.

[0002]

2. Description of the Related Art Conventionally, CCDs have been widely used as solid-state imaging devices because of their excellent S / N ratio. On the other hand, so-called amplifying solid-state imaging devices that have advantages of low power consumption and ease of use have been developed. An amplification type solid-state imaging device is one that guides signal charges accumulated in a photodiode to a control electrode of a transistor provided in a pixel, and amplifies and outputs an output corresponding to the signal charge amount from a main electrode of the transistor. . Particularly, a so-called CMOS sensor using a MOS transistor as a transistor is a CMOS sensor.
The focus is on development because of good matching with the process and the possibility of on-chip drive circuits and signal processing circuits.

FIG. 4 is a circuit diagram showing a typical example of a CMOS sensor pixel. 1 is a unit pixel, 2 is a photodiode for storing signal charges generated by incident light,
Reference numeral 3 denotes an amplifying MOS transistor serving as an amplifying means for outputting an amplified signal output in accordance with the amount of signal charge. Reference numeral 4 denotes a floating diffusion portion which receives the signal charge and is connected to the gate electrode of the MOS transistor 3; A MOS transistor as a transfer means for transferring electric charges to the floating diffusion unit 4, a MOS transistor 6 for resetting the floating diffusion unit 4, and a MOS transistor 7 for selecting an output pixel.

Reference numeral 8 denotes a control line for applying a pulse to the gate of the MOS transistor 5 to control the charge transfer operation, and reference numeral 9 denotes a control line for applying a pulse to the gate of the MOS transistor 6 to control the reset operation. 10 is MOS
A control line 11 for applying a pulse to the gate of the transistor 7 to control the selection operation, a power supply line 11, and a drain of the amplifying MOS transistor 3 and a reset MO
It is connected to the drain of the S transistor 6 and supplies a power supply potential to them. Reference numeral 12 denotes an output line for outputting an amplified signal of a selected pixel, 13 denotes a constant current source, a MOS transistor forming a source follower with the amplifying MOS transistor 3, and 14 denotes a MOS transistor 13 which operates at a constant current. This is a wiring for supplying a high potential to the gate electrode of the MOS transistor 13.

When the pixels 1 are arranged in a two-dimensional matrix, they form a pixel area of a two-dimensional solid-state image pickup device. In the matrix configuration, an output line 12 is a common line of pixels in each column and a control line 8. , 9, and 10 are common lines for the pixels in each row, and only the pixels in the row selected by the control line 10 are output as signals to the output line 12.

Next, the operation of the pixel will be briefly described. First, a pulse is applied to the control line 9 for the pixels in the row where the selection MOS transistor is turned on by the control line 10, and the floating diffusion unit 4 is reset. Since a source follower is formed by the amplification MOS transistor 3 and the constant current MOS transistor 13,
An output potential corresponding to the reset potential appears on the output line 12. Next, when a signal charge accumulated in the photodiode 2 is transferred to the floating diffusion portion 4 by applying a pulse to the control line 8, the potential of the floating diffusion portion 4 changes by a voltage corresponding to the signal charge amount. Then, the potential change appears on the output line 12. Since the reset potential appearing on the output line 12 includes noise such as threshold voltage variation of the amplifying MOS transistor 3 and reset noise when resetting the floating diffusion unit 4, the potential change corresponding to the signal charge amount Is a signal without noise.

In the two-dimensional CMOS sensor, a readout circuit for removing the noise and extracting only a signal is connected to the output line 12. This readout circuit includes one that removes the above noise by a clamp circuit, noise and noise +
Several configurations have been proposed, such as one that holds the pure signal separately and guides it to the final stage differential amplifier during horizontal scanning readout to eliminate noise, but there is a direct relationship with the present invention. Since there is no detailed description, it is omitted.

Next, the photodiode of the pixel and the transfer MO
FIG. 5 shows a cross-sectional structure of the S transistor and the floating diffusion. In the figure, reference numeral 15 denotes an N-type semiconductor substrate, 16 denotes a P-type well, 17 denotes an N-type semiconductor region formed in the well 16, and a photodiode is formed by 16 and 17; Signal charges are accumulated. Reference numeral 18 denotes an N-type semiconductor region formed in the well 16 and serving as a floating diffusion.
Is a gate electrode of the transfer MOS transistor 5, and regions 17 and 18 are a source region and a drain region of the transfer MOS transistor. Reference numeral 20 denotes a wiring connected to the region 18, which is connected to the gate of the amplification MOS transistor 3. The signal charges accumulated in the region 17 are all transferred to the floating diffusion 18 during the transfer operation.
The N-type impurity concentration in the region 17 is set so that the region 17 is completely depleted immediately after the transfer. Therefore, the accumulation of the signal charge in the photodiode is immediately after the transfer of the signal charge. When the accumulation of the signal charge is completed, the row to which the pixel belongs is selected again, and the signal charge accumulated in the photodiode is transferred.

[0009]

However, in the above conventional example, rows for reading are sequentially selected. Since the start and end timings of the accumulation of the photodiodes of the pixels are determined at the time of signal charge transfer, the start and end timings of the accumulation of the photodiodes are shifted for each row. In a two-dimensional solid-state imaging device, a signal of one screen, that is, one field is formed by pixel signals of all rows.
If the accumulation timing of each row is shifted, there is a problem that the shape of a subject moving at a high speed is distorted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid-state imaging device capable of obtaining a distortion-free image even with a moving subject by enabling start and end timings of a signal accumulation operation for all pixels simultaneously.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the conventional CMOS sensor, the present invention provides a photodiode for storing signal charges generated by incident light;
Transfer means for transferring the signal charge, a floating diffusion region to which the signal charge is transferred, and amplification means for outputting a signal amplified based on the signal charge transferred to the floating diffusion region. A signal charge holding region provided in a part of a channel below a transfer gate of the transfer means for holding the signal charge; A potential barrier portion for providing a potential barrier between the region and the floating diffusion region.

Active pixel type CMO for signal amplification
In the pixel configuration of the S sensor, a signal charge holding region having a low potential for holding signal charges accumulated by a photodiode is provided in a part of a channel portion below a gate for transferring signal charges, and a floating diffusion region and the holding region are provided. And a potential barrier portion made of a semiconductor region which provides a potential barrier and is completely depleted. The signal charge holding region can perform operations such as signal charge transfer from the photodiode, signal charge holding, and signal charge transfer to the floating diffusion region by controlling the transfer gate potential. In the above configuration, the signal charge transfer from the photodiode to the charge holding region is performed simultaneously for all pixels, and the charge transfer from the charge holding region to the floating diffusion portion is performed line-sequentially as in the related art. Since it is the same for pixels,
Even if a high-speed moving subject is imaged, an image without distortion can be obtained.

It is also preferable to provide a light shielding means for blocking light from entering the holding area.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view of a part of a pixel which best illustrates the features of the present invention. The photodiode, a charge transfer MOS transistor as a transfer means, and an amplifying means (not shown) 4 shows the structure of the portion of the floating diffusion connected to the input node of FIG. 4, and the same members as those in FIG. In FIG. 1, reference numeral 21 denotes an N-type semiconductor region serving as a signal charge holding portion formed in a channel portion immediately below the transfer gate 19; 22 denotes a floating diffusion region formed between the charge holding region 21 and the floating diffusion region 18; The N-type semiconductor region 23 whose impurity concentration is controlled so that the region 18 is fully depleted when the potential of the region 18 is sufficiently reverse-biased with respect to the P-type well 16 blocks light from entering the charge holding region 21. The light shielding layer is formed as described above.

FIGS. 4A, 4B and 4C show that the potential of electrons from the region 17 to the floating diffusion region 18 through the charge transfer channel portion, the regions 21 and 22 depends on the potential of the gate electrode 19. This is how it changes. Note that since electrons have a negative charge, the lower the potential, the higher the potential for electrons.

Next, the operation of this embodiment will be described. The operation of one pixel is as follows: (1) signal charge accumulation in the photodiode, (2) signal charge accumulated in the photodiode to the charge holding region 21, (3) signal charge holding in the charge holding region 21, (4) Signal charge transfer from the charge holding region 21 to the floating diffusion region 18 is basically performed.

The operation of the above (1) is the same as the conventional one, so that the description is omitted.

(2) FIG. 1A shows the potential during the operation of transferring the signal charges accumulated in the photodiode to the charge holding region 21. At this time, the transfer gate electrode 19 has a high potential. VH is applied. Area 1
The value of VH is determined so that the channel potential below the transfer gate separating the region 7 from the region 21 is sufficiently higher than the potential of the region 17, and the signal charges accumulated in the photodiode are transferred to the charge holding region 21. You. At this time, the potential of the floating diffusion region 18 is set to a high potential so that the region 22 is completely depleted, and the charges transferred to the charge holding region 21 It does not flow to 18.

(3) The operation shifts to the operation of retaining signal charges in the charge retaining region 21. In this operation, the potential of the transfer gate electrode 19 is set to VM lower than VH,
The potential at that time is shown in FIG. At this time, the value of VM is determined so that the channel potential under the transfer gate separating region 17 and region 21 is lower than the potential of region 17, but the potential of charge holding region 21 is higher than the potential of region 22. . The signal charges in the charge holding region 21 are isolated by potential barriers existing at both ends thereof, and the light-shielding layer 23 prevents electrons generated by photoexcitation from entering the region 21. Can work.

(4) The operation shifts to the operation of transferring signal charges from the charge holding region 21 to the floating diffusion region 18. In this operation, the potential of the transfer gate electrode 19 is set to VL which is lower than VM, and the potential at that time is shown in FIG. At this time, the value of VL is determined so that the potential of the charge holding region 21 is lower than the potential of the region 22. In this state, there is no potential barrier between the charge holding region 21 and the floating diffusion region 18, and the signal charges in the charge holding region 21 are transferred to the floating diffusion region 18.

If a two-dimensional sensor is formed by the pixels having the above configuration and operation, the operation of "transferring the signal charge accumulated in the photodiode to the charge holding region 21" can be performed simultaneously for all the pixels. Therefore, since the start and end timings of the signal accumulation operation are the same for all pixels, an image without distortion can be obtained. FIG.
Since the floating diffusion region 18 is not in contact with the transfer gate 19, the total parasitic capacitance of the floating diffusion portion 4 does not include the capacitance with the transfer gate as in the conventional configuration. As a result, there is an effect that the total parasitic capacitance of the floating diffusion portion can be reduced as compared with the conventional case, the charge conversion coefficient is large, and the sensitivity is increased.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 2 is a cross-sectional view of a part of a pixel representing the embodiment of the present invention, showing a structure of a photodiode, a charge transfer MOS transistor as a transfer unit, and a floating diffusion portion connected to an input node of an amplification unit (not shown). The same reference numerals are given to the same members as those in FIG. In FIG. 2, reference numeral 24 denotes a first P-type well,
Reference numeral 25 denotes a second P-type well, in which a photodiode 17 is formed, and a charge holding region 21 is formed in 25.

During the holding operation, if a charge generated by incident light near the photodiode enters the charge holding region 21, it becomes a false signal. Therefore, when the P-type well 25 in which the charge holding region is formed is configured to have a high impurity concentration, a high potential barrier for electrons is formed and a false signal can be suppressed.

On the other hand, in the P-type well 24, since it is desired to collect the charges generated by the incident light in the photodiode 17 as much as possible, it is preferable that the P-type well 24 be configured to have a deep and low impurity concentration. As described above, in the second embodiment, two P-type wells having different configurations are formed in accordance with the characteristics of the portions having different purposes such as the photodiode and the charge holding region. As a result, the start and end timings of the signal accumulation operation can be simultaneously performed for all the pixels, and a sensor pixel with high sensitivity and small generation of false signals in the charge holding region can be realized.

In the first and second embodiments, the completely depleted regions such as the photodiode 17 and the potential barrier region 22 have a buried type, that is, a structure having a surface layer of the same conductivity type as the well. It may be a diode. Further, the charge holding region 21 may be of a bulk channel type, that is, the charge holding region may be formed in the semiconductor bulk slightly away from the interface during the holding operation.

(Third Embodiment) Next, an imaging system using the solid-state imaging devices of the first and second embodiments will be described.

FIG. 3 is a block diagram showing an example in which the solid-state imaging device according to the present invention is applied to a "still video camera". Reference numeral 101 denotes a barrier functioning both as protection of a lens and a main switch. Reference numeral 102 denotes an optical image of a subject.
A lens for forming an image at 04, a stop 103 for varying the amount of light passing through the lens 102, a solid-state image sensor 104 for taking in a subject image formed by the lens 102 as an image signal, and a solid-state image sensor 106 Analog of an image signal output via the imaging signal processing circuit 105
An A / D converter 107 that performs digital conversion is a signal processing unit that performs various corrections on the image data output from the A / D converter 106 and compresses the data. Also, 1
08 is a solid-state imaging device 104, an imaging signal processing circuit 105,
A timing generation unit that outputs various timing signals to the A / D converter 106 and the signal processing unit 107; 109, a general control / calculation unit that controls various calculations and the entire still video camera; 110, temporarily stores image data Memory unit 111, an interface unit for recording or reading on a recording medium, a detachable recording medium 112 such as a semiconductor memory for recording or reading image data, and a communication unit 113 with an external computer or the like. Interface section for performing

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.

When the barrier 101 is opened, the main power is turned on, the power of the control system is turned on, and the power of the imaging system circuit such as the A / D converter 106 is turned on.

Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the solid-state image sensor 104 is converted by the A / D converter 106, followed by signal processing. The data is input to the unit 107. The overall control / arithmetic unit 109 calculates the exposure based on the data.

The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.

Next, based on the signal output from the solid-state image pickup device 104, a high-frequency component is extracted, and the overall control / arithmetic unit 109 calculates the distance to the subject. Thereafter, the lens is driven to determine whether or not the lens is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

Then, after the focus is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit by the overall control / calculation 109. Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. External I / F 1
The image may be processed by inputting it directly to a computer or the like through the computer 13.

[0035]

As described above, according to the present invention,
Since the start and end timings of the signal accumulation operation can be performed simultaneously for all pixels, an image without distortion can be obtained even for a moving subject. Further, high sensitivity can be obtained because the parasitic capacitance of the floating diffusion portion is small.

Further, a photodiode is formed in the first well, and a signal charge holding region is formed in the second well.
If the well is formed to have a lower impurity concentration and a deeper depth than the second well, in addition to the above-described effects, it is possible to realize a sensor having higher sensitivity and less generation of a false signal.

[Brief description of the drawings]

FIG. 1 is a cross-sectional structural view of a pixel for describing a first embodiment of the present invention.

FIG. 2 is a cross-sectional structure diagram of a pixel for describing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example in which the solid-state imaging device of the present invention is applied to a still video camera.

FIG. 4 is a circuit diagram of a conventional pixel.

FIG. 5 is a cross-sectional structural view of a conventional pixel.

[Explanation of symbols]

 1: Pixel 2: Photodiode 3: Amplification MOS transistor 4: Floating diffusion part 5: Signal charge MOS transistor 6: Reset MOS transistor 7: Selection MOS transistor 8: Gate control line 9: Gate control line 10: Gate control line 11: Power supply line 12: Pixel output line 13: Constant current supply MOS transistor 14: Gate control line 15: Semiconductor substrate 16: Semiconductor well 17: Photodiode region 18: Floating diffusion region 19: Transfer gate 20: Wiring 21: Charge holding region 22: Completely depleted region 23: Light shielding layer 24: First well 25: Second well

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA10 AB01 BA14 CA03 CA17 DA23 DD04 FA06 FA33 FA35 GB02 5C024 AX01 CX41 DX04 DX07 GX03 GY38 GZ04 GZ10 HX23 HX57 JX30 5F049 MA01 NA01 NB05

Claims (6)

[Claims] 1. A photodiode for storing signal charges generated by incident light, a transfer unit for transferring the signal charges, a floating diffusion region to which the signal charges are transferred, and a transfer to the floating diffusion region. A solid-state imaging device configured by arranging a plurality of unit pixels each including an amplifying unit for outputting a signal amplified based on the obtained signal charge, a part of a channel below a transfer gate of the transfer unit A solid-state imaging device comprising: a signal charge holding region provided for holding the signal charge; and a potential barrier portion providing a potential barrier between the signal charge holding region and the floating diffusion region. apparatus. 2. The solid-state imaging device according to claim 1, wherein the potential barrier is completely depleted in a state where the signal charge is held in the signal charge holding region. 3. The solid-state imaging device according to claim 1, further comprising a light blocking layer for blocking light incident on the signal charge holding region. 4. A semiconductor substrate of a first conductivity type, a first well of a conductivity type opposite to the semiconductor substrate, and a first well of the same conductivity type as the first well. A second well having a different impurity concentration and depth from the first well is formed.
2. The solid-state imaging device according to claim 1, wherein the photodiode is formed in the well, and the signal charge holding region is formed in the second well. 5. The solid-state imaging device according to claim 4, wherein said first well has a lower impurity concentration and a deeper depth than said second well. 6. An imaging optical system for imaging light from a subject, and the solid-state imaging device according to claim 1, which photoelectrically converts the formed image. And a signal processing circuit for converting the output signal of the digital signal into a digital signal for processing.