JP2000165755A - Solid-state imaging device - Google Patents

Abstract

(57) Abstract: Sensitivity can be changed in accordance with signal charges stored in a photoelectric conversion unit. SOLUTION: In a solid-state imaging device having a photoelectric conversion unit 3 and a charge-voltage conversion unit that converts a signal charge transferred from the photoelectric conversion unit 3 into a signal voltage, the charge-voltage conversion unit has different voltage dependencies. Consists of multiple capacities.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a photoelectric conversion unit and a charge-to-voltage conversion unit that converts signal charges transferred from the photoelectric conversion unit into signal voltages. .

[0002]

2. Description of the Related Art Conventionally, to expand the dynamic range in a solid-state imaging device, for example, two types of signals having different accumulation times are read from the same pixel, and these two types of signals are combined. There is a method of expanding a dynamic range, that is, a method of expanding a dynamic range by combining a signal having a high sensitivity but a small dynamic range and a signal having a low sensitivity and a large dynamic range.

[0003]

However, in the above method, after accumulating signal charges for a certain accumulation time, it is necessary to again accumulate the signal charges by changing the accumulation time. Are image signals in different accumulation periods.

An object of the present invention is to provide a solid-state imaging device capable of changing the sensitivity in accordance with the signal charge stored in the photoelectric conversion unit.

[0005]

According to a first aspect of the present invention, there is provided a solid-state imaging device comprising: a photoelectric conversion unit; and a charge-voltage conversion unit that converts a signal charge transferred from the photoelectric conversion unit into a signal voltage. In the imaging apparatus, the charge-voltage converter includes a plurality of capacitors having different voltage dependencies.

Further, according to a second solid-state imaging device of the present invention, in the first solid-state imaging device, the charge-voltage converter is provided with:
The plurality of capacitors having an impurity diffusion region and a MOS component, and having different voltage dependencies, are formed by a capacitor formed in the impurity diffusion region and a capacitor formed in the MOS component. Features.

According to a third solid-state imaging device of the present invention, in the above-mentioned first solid-state imaging device, the charge-to-voltage converter includes:
An impurity diffusion region and a buried semiconductor junction,
The plurality of capacitances having different voltage dependencies are constituted by a capacitance formed in the impurity diffusion region and a capacitance formed in the buried semiconductor junction.

According to a fourth solid-state imaging device of the present invention, in the above-mentioned third solid-state imaging device, the voltage dependence of the capacitance formed in the embedded semiconductor junction is determined by changing the voltage dependency of one of the semiconductor junctions. It is controlled by the impurity concentration or the depth of the one conductivity type semiconductor region.

According to a fifth solid-state imaging device of the present invention, in the above-mentioned third solid-state imaging device, the voltage dependence of the capacitance formed in the buried semiconductor junction is determined by changing the voltage dependence of one of the semiconductor junctions. It is controlled by the width of the one conductivity type semiconductor region.

A sixth solid-state imaging device according to the present invention, in any one of the first to fifth solid-state imaging devices, further comprising reset means for applying a reset voltage to reset the charge-voltage converter. The charge-voltage conversion efficiency of the charge-voltage converter is controlled by controlling the voltage value of the reset voltage.

According to a seventh solid-state imaging device of the present invention, in the sixth solid-state imaging device, the sampling means for sampling the amount of light incident on the photoelectric conversion unit; and the resetting means in response to a sampling signal from the sampling means. It is characterized by setting a voltage.

An eighth solid-state imaging device according to the present invention is characterized in that, in the seventh solid-state imaging device, the sampling signal is a signal one frame before.

In a ninth solid-state imaging device according to the present invention, in the seventh solid-state imaging device, the sampling signal is an overflow drain signal or a smear signal.

According to a tenth solid-state imaging device of the present invention, in the above-mentioned seventh solid-state imaging device, before the accumulation period of the signal charge, the second signal charge having an accumulation time shorter than the accumulation period is subjected to the impurity diffusion. And transferring the second signal charge to a sampling signal.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a schematic explanatory view showing the configuration of a solid-state imaging device according to the present invention. In FIG. 1, 1 is an N-type semiconductor substrate, 2 is a P-type well region formed on the N-type semiconductor substrate 1, 3 is an N-type diffusion region, and 4 is a P-type formed on the surface of the N-type diffusion region 3. Region, P-type well region 2, N
The type diffusion region 3 and the P type region 4 constitute a photodiode. Reference numeral 5 denotes a charge-to-voltage converter for transferring signal charges accumulated in the photodiode. This charge-to-voltage converter comprises an impurity diffusion region or the like, and voltage conversion is achieved by all the capacitors connected to this node. You. Generally, it is an area generally called a floating diffusion (FD) area including all the capacitance components.

Reference numeral 6 denotes a FD region 5 from the photodiode.
Is a transfer gate electrode for transferring a signal charge to the gate electrode. The N-type diffusion region 3 and the FD region 5 are connected to a transfer MOS transistor (M
TX) as source / drain regions. The FD region 5 is electrically connected to the gate of the output MOS transistor MSF and the drain of the reset MOS transistor MRES. The drain of the MOS transistor MSF is connected to the source of the MOS transistor MSEL serving as a selection switch, and the source is connected to a constant current source to form a source follower circuit. The signal charge transferred to the FD region 5 is applied to the gate of the MOS transistor MSF as a voltage signal, and a signal is output from the source follower circuit. The FD region 5 is set to a reset potential when the reset MOS transistor MRES is turned on.

The FD region 5 has a capacitance due to a junction capacitance with the P-type well region 2, a capacitance between wirings, and the like. As shown in FIG. 2, MOS components 7 and 8 are connected in series to the FD region 5, and a MOS capacitance is connected to the capacitance of the FD region 5. Here, the MOS capacitors are connected in series, but may be connected in parallel.

The FD region 5 and the MOS components 7 and 8 constitute a charge-voltage converter, and the MOS components 7 and 8 adjust well concentration, gate oxide film thickness, fixed voltage applied to the gate electrode, and the like. Thus, the capacitance can be set to have a voltage dependency different from that of the FD region. FD
The capacitance formed by the junction capacitance between the region 5 and the P-type well region 2, the capacitance between wirings, and the like actually has voltage dependency, but the change in the capacitance is small in the range of the use range.

FIGS. 3A to 3C are explanatory diagrams of the operation when the FD region and the MOS component have a step-like potential structure. FIG. 4A is a diagram showing a characteristic of VFD (floating diffusion voltage) -Q (signal charge amount), FIG. 4B is a diagram showing a characteristic of VFD-Cap (capacitance), and FIG. FIG. 4 is a diagram showing a light quantity-output characteristic (sensitivity characteristic). 4 (a) and 4 (b), a, b, and c indicate the characteristics of the operating states of FIGS. 3 (a), (b), and (c), respectively. Such a potential structure can be configured by connecting MOS capacitors in series or in parallel.

In FIG. 3, PD is a photodiode portion, TX is a transfer MOS transistor portion, FD is a floating diffusion portion, and MOS1 is a first MOS transistor.
The constituent part, MOS2, indicates a second MOS constituent part. FIG.
In (a) to (c), the transfer MOS transistor is turned on, the energy level falls below the level of the photodiode PD, and all the charges accumulated in the PD can be transferred to the FD region. The potential of the FD region is set to VDD by a reset MOS transistor MRES (not shown).
It is reset to -Vth (Vth is the voltage drop between the source and drain by the transfer MOS transistor).

Step-like potential structure (FD section, MOS
3A, when the signal charge accumulated in the photodiode portion (PD) is small (the light amount is small) as shown in FIG. 3A, the signal charge is transferred to a deep portion of the potential well. Is done. At this time, the floating diffusion voltage VFD is high, the accumulated signal charge Q is small (FIG. 4A), and the capacitance Cap is small (FIG. 4A).
(B)), the change rate of the output with respect to the light quantity is large, and the sensitivity is increased (FIG. 4 (c)).

Then, as shown in FIGS. 3B and 3C, when the signal charges accumulated in the photodiode portion (PD) increase, the MOS components (MOS1, MO1)
The signal charge is transferred stepwise also to the shallow portion of the step potential of S2). At this time, the floating diffusion voltage VFD decreases, the signal charge amount Q stored increases (FIG. 4A), and the capacitance Cap
Gradually increases (FIG. 4B), the rate of change of the output with respect to the light quantity decreases, and the sensitivity decreases (FIG. 4C). In this manner, the sensitivity can be changed according to the amount of transferred signal charges.

As shown in FIGS. 5 (a) to 5 (c),
It is also possible to construct an inverted “concave” shaped potential structure. Such a potential structure can be configured by connecting MOS capacitors in series.

In this case, when the signal charge stored in the photodiode portion (PD) is small, the signal charge is transferred to the potential well of the FD region as shown in FIG. When the signal charge accumulated in the photodiode portion increases, as shown in FIG. 5B, the signal charge is transferred to the potential well formed by the MOS capacitor of the MOS2, and the signal charge further increases. Figure 5
As shown in (c), the signal charges are also transferred to the MOS capacitance portion of MOS1. FIG. 6A shows the characteristic of VFD (floating diffusion voltage) -signal charge amount at this time, and FIG. 6 shows the characteristic of VFD-Cap.
FIG. 6 shows (b) the light amount-output characteristic (sensitivity characteristic).
(C). A, b, c in each of FIGS. 6 (a) and 6 (b)
Indicates the characteristics of the operating states of FIGS. 5A, 5B, and 5C, respectively.

In this embodiment, the case where the potential structure has a stepped shape and the case where the potential structure is an inverted “concave” shape has been described.
The present invention is not particularly limited to such a potential structure.

Next, FIGS. 7 and 8 are schematic plan views of the solid-state imaging device having the above-mentioned MOS capacitance.

7 and 8, reference numeral 11 denotes a photodiode (PD), 12 denotes a gate of a transfer MOS transistor, and 13 denotes a floating diffusion region (F).
D) and 14 are the gates of the reset MOS transistors,
Reference numerals 15 and 16 denote gate electrodes for constituting a MOS capacitor. (Second Embodiment) The step-like potential structure shown in FIG. 3 and the inverted "concave" potential structure shown in FIG.
An example in which a buried PN junction is used instead of a capacitor will be described below.

FIG. 9 is a schematic sectional view showing the FD region and the buried PN junction. In the figure, 21 is an FD area,
22 is a high concentration surface P region (PSR), 26 is PSR22
An N-type diffusion region DN, 25 forming a PN junction with the N-type diffusion region (DN1, DN2) 26 is a PW forming a PN junction.
L (P-well region). When a reverse bias voltage is applied to the PN junction, the depletion layer expands. As shown in FIG. 9, the depletion layer extends from the PN junction between the PSR 22 and the N-type diffusion region DN26 (depletion layer width a) and the N-type diffusion region DN.
26 (depletion layer width b) extending from the PN junction between PWL 26 and PWL 25. Now, as both depletion layers expand, no charge is stored in the depletion layer, so that no charge is accumulated and the capacitance becomes smaller. When the reverse bias voltage increases and the depletion layers come into contact with each other (w = a + b; w
Is the depth of the N-type diffusion region DN26), and the capacitance at this portion is almost eliminated. Therefore, as shown in FIG. 10, when the floating diffusion voltage VFD is high and the reverse bias voltage VR is large, the capacitance is substantially composed of only the capacitance CFD in the FD region, but the floating diffusion voltage VFD decreases and the reverse bias voltage decreases. When the voltage VR becomes smaller than the threshold value V1, the depletion layer width (a + b) becomes (a + b).
b) <w, and the capacitance CBPN of the buried PN junction is added to the capacitance CFD. The threshold value V1 can be arbitrarily changed by changing the impurity concentration and the depth w of the N-type diffusion region. By providing another N-type diffusion region in which the impurity concentration and the depth w of the N-type diffusion region are changed, the step-like potential structure in FIG. 3 and the inverted “concave” potential structure in FIG. Can be.

FIG. 11 shows an FD in the case of forming a step-like potential structure or an inverted “concave” shape potential structure.
FIG. 4 is a schematic cross-sectional view showing a region and a buried PN junction. In the figure, 21 is an FD region, 22 is a high-concentration surface P region (PSR), 23 and 24 are N-type diffusion regions (DN1, DN2) forming a PN junction with the PSR 22, and 25 is a PWL (P
Well region). The N-type diffusion region 23 and the N-type diffusion region 24 are set to have different impurity concentrations, and the impurity concentration is appropriately set so that a step-like potential structure or an inverted “concave” potential structure can be formed. When forming a stepped potential structure, the N-type diffusion regions may be connected in series or in parallel. However, when forming an inverted “concave” shape potential structure, the N-type diffusion regions are connected in series. Connect to Note that the depth w of the N-type diffusion region may be changed instead of or in addition to the impurity concentration.

FIG. 12 is a schematic plan view of the solid-state imaging device having the embedded PN junction. The same components as those in FIG. 7 are denoted by the same reference numerals. FIG.
, 21 to 23 indicate PN junctions, respectively.

The threshold value V1 can be arbitrarily changed by changing not only the impurity concentration and the depth w of the N-type diffusion region but also the planar shape (eg, width) of the N-type diffusion region.

Referring to the DN area 26 in FIG.
6 has only P regions above and below the FD region 21, while the region closer to the tip has a P region on the side of the DN region 26.
Since it comes into contact with the region, it is easily depleted. That is, since the vicinity of the side surface of the N-type diffusion region is more likely to be depleted, if the width of the N-type diffusion region is small, the threshold value V1 becomes small due to the influence of the side surface PN junction.

FIG. 14 is a plan view of the N-diffusion region when the inverted “concave” potential structure shown in FIG. 5 is formed.
Shown in FIG. 13 shows a planar shape of the N-diffusion region in a case where the voltage-capacity characteristics as shown in FIG. 29 are obtained. N in FIG.
In the diffusion region DN1, the width d2 of the region closer to the tip is smaller than the width d1 of the region closer to the FD region, and the region closer to the tip is more likely to be depleted (the depletion voltage is higher). Low). In the N diffusion region DN1 in FIG.
The width d2 of the constricted area is smaller than the width d1 of the area closer to the area, and the constricted area is easily depleted. (Third Embodiment) In the first and second embodiments described above, signal charges are transferred with the reset voltage set to a predetermined fixed potential (VDD). However, the sensitivity is changed by appropriately changing the reset voltage. Can be switched.

First, the operation of the solid-state imaging device according to the present invention will be described with reference to FIGS. FIG. 15 is a schematic configuration diagram of a solid-state imaging device including a reset MOS transistor. FIGS. 16A to 16D are potential diagrams showing a light accumulation operation, a reset operation, a noise read operation, and a signal transfer / signal read operation, respectively.

As shown in FIG. 16A, a transfer transistor MTX and a reset MOS transistor MRES
Is turned off, light enters the photodiode PD, and optical signal charges are accumulated.

Next, as shown in FIG. 16B, the reset MOS transistor MRES is turned on to reset the FD region. Here, the reset voltage is VDD, and the FD region is set to the potential of (VDD-Vth). The signal charge overflowing from the photodiode is discharged via the reset MOS transistor MRES.

Next, as shown in FIG. 16C, the reset MOS transistor MRES is turned off to read a noise signal.

Next, as shown in FIG. 16D, the transfer transistor MTX is turned on, and the photodiode P is turned on.
The signal charge is transferred from D to the FD region, and the signal charge is read as a voltage signal. A signal from which noise has been removed can be obtained by performing a process of subtracting the previously read noise signal from this signal.

In such a solid-state imaging device, the sensitivity can be changed by appropriately changing the reset potential.
Hereinafter, an example in which the FD region and the MOS component have a step-like potential structure will be described.

For example, when the reset voltage is VRES1 (= VDD)
Then, as shown in FIG. 17A, signal charges are accumulated in a deep portion of the potential well of the FD region. On the other hand, if the reset voltage is VRES2 (<VRES1), FIG.
As shown in FIG. 7B, the FD region and the MOS component M
Signal charges are accumulated in a shallower portion of the potential well of OS1. That is, when the reset voltage is lowered, the charge corresponding to the reset voltage is stored in advance in a deep portion of the potential well of the FD region, so that the signal charge is stored in a larger capacity state. Therefore, the sensitivity can be switched by controlling the reset voltage. FIG. 18 is a characteristic diagram showing light quantity-output characteristics (sensitivity characteristics). In FIG.
The characteristic at the time of RES1 and the characteristic b when the reset voltage is VRES2.

Hereinafter, the above solid-state imaging device is defined as one pixel,
A method of applying a reset voltage when the pixels are arranged in a matrix will be described. The components of the pixel described below are the same as those shown in FIG.

To make all the pixels have the same sensitivity, a fixed reset voltage is applied to all the pixels. In this case, as shown in FIG. 19, the sources of the transfer MOS transistors MRES of all the pixels are connected to a voltage source that supplies the reset voltage VRES.

In order to arbitrarily set the sensitivity of each pixel, an arbitrary reset voltage is set and applied to each pixel. In this case, the reset voltage may be applied to each column and the reset may be scanned for each row. In the pixel of FIG. 20, a power supply line for applying a reset voltage is provided for each column, and the sources of the transfer MOS transistors MRES arranged in the same column are commonly connected.
By applying a reset signal to the gate of the transfer MOS transistor MRES for each row, an arbitrary reset voltage can be applied to each pixel. In the pixel of FIG. 21, a power supply line for applying a reset voltage is also used as an output signal line. Since the reset operation and the signal read operation are performed at different timings, the output signal line is connected to the source of the transfer MOS transistor MRES in this way, and a reset signal is applied to the gate of the transfer MOS transistor MRES for each row. By doing so, an arbitrary reset voltage can be applied to each pixel.

In this embodiment, since the sensitivity can be switched by changing the reset voltage, the solid-state imaging device which samples the amount of light incident on the pixel in advance and sets the reset voltage according to the sampling result. Can be configured. In the pixel configuration of FIG. 19, the reset voltage is changed for all pixels.
In one pixel configuration, the reset voltage of a part of the pixel can be changed.

FIG. 22 is a block diagram of a camera device using a solid-state imaging device for setting a reset voltage according to a sampling result. In the figure, reference numeral 31 denotes a solid-state imaging device (sensor) whose reset voltage can be arbitrarily set, and 32 denotes a CD.
S (correlated double sampling circuit) and AGC (auto gain control circuit), 33 is an A / D converter, 34
Denotes a camera signal processing IC for performing signal processing such as outputting as an NTSC signal, and 35 denotes a saturation bit memory.

In the above-mentioned camera device, the camera signal processing IC 34 determines whether or not the input signal is saturated if the input value is equal to or more than a certain value, and stores a saturation bit in a saturation bit memory 35 according to the result. Is input to the sensor 31. Based on the saturation bit signal, it is determined whether or not the pixel is saturated, and the reset voltage is controlled based on the result (in this case, the signal one frame before is used as the sampling signal).

Further, as shown in FIG. 23, during the accumulation period of the signal charge, the reset MOS transistor MRES is closed,
A signal overflowing from the photodiode PD, that is, an overflow drain (OFD) signal (or a smear signal) is accumulated on the FD region, and the signal is used as a sampling signal to determine saturation based on the sampling signal. The reset voltage can be switched before the signal charge transfer from the PD based on the result. In this case, the saturation determination can be performed in the sensor chip.

Further, a signal having a short storage time is transferred from the PD to the FD region before storing the signal charge.
Holding the signal on the area and before reading out the signal charge,
The signal held in the FD region is read out as a sampling signal, saturation determination is performed, and the reset voltage is switched based on the result. In this case, the saturation determination can be performed in the sensor chip.

Next, the configuration of an area sensor in which the above-described pixel cells are arranged in a matrix will be described.

FIG. 24 is a schematic configuration diagram showing the configuration of the area sensor. As shown in the figure, the scanning in the row direction of the pixel cells arranged in a matrix is performed by a vertical scanning circuit 100, and signals φRES, φTX, and φSEL are sent for each row, and a noise signal and a sensor are sent for each row. The signal is output to the vertical output line, and is stored in a noise signal storage capacitor and a sensor signal storage capacitor connected to the vertical output line via a switching MOS transistor. The noise signal and the sensor signal accumulated in each capacitor are scanned for each column by the horizontal scanning circuit 101, and the noise signal N and the sensor signal S are sequentially output for each column via a horizontal output line to the inverted input of the differential amplifier A. The signal is sent to the terminal (-) and the non-inverting input terminal (+), and a subtraction process is performed to obtain a signal SN for each pixel. Note that MCHR1 and MCHR2 are controlled by a signal φCHR and reset the horizontal output line to a predetermined potential.
OS transistor. φTN and φTS are switching MOSs for transferring noise signals and sensor signals to each capacitor.
This is a signal for controlling the transistor.

FIG. 25 is a block diagram showing a video camera device using the solid-state imaging device of this embodiment.

In FIG. 25, reference numeral 41 denotes a lens system.
42 is an aperture, 43, 45 and 47 are motors, 44 is a variable power lens driving means for controlling the motor 43, 46 is a motor 45
Mechanism driving means for driving the aperture 42 by controlling
Is a focus competition lens driving means for controlling the motor 47. Reference numeral 49 denotes a solid-state imaging device for photoelectrically converting an optical signal incident from the lens system 41. The solid-state imaging device 49 capable of switching the reset voltage of the present embodiment described above is used.
The reset voltage is set by the output selection signal from. 50 is a CDS / AGC and 51 is an AD converter.
52 is a camera signal processing circuit, 52a is a Y / C separation circuit, 52b is a luminance signal processing circuit, 52c is a color signal processing circuit, 52d is a color suppression circuit, 52e is a digital output conversion circuit, and 52f is a saturated pixel determination measurement. Circuit. The determination of the saturated pixel by the saturated pixel determination measurement circuit 52f is performed based on the luminance signal and the color signal. The determination result of the saturated pixel is input to the microcomputer 55, and an output selection signal is output based on the determination result. Further, the microcomputer 55 controls the variable-magnification lens driving unit 44, the aperture mechanism driving unit 46, and the focus compensation lens driving unit 48 based on the signal from the camera signal processing circuit 52.

The output from the camera signal processing circuit 52 is passed through a digital decoder and DA converter 53 to monitor means 5.
4 for image display, and then to a VTR.

FIG. 26 is a block diagram showing a conventional video camera apparatus, which is different from this embodiment in that no saturated pixel determination measuring circuit 12f is provided as in this embodiment, and no output selection signal is output. (Fourth Embodiment) FIG. 27 is a block diagram showing the configuration of a fourth embodiment of the solid-state imaging device according to the present invention. FIG. 28 is a timing chart showing the operation of the solid-state imaging device.

In the present embodiment, in a circuit which once holds the noise signal from the sensor unit and the noise + optical signal in the signal holding unit as in the above-described embodiment and reads them out, the following reading method is used. went. (1) As shown in FIG. 28, the reset switch (reset MOS transistor MRES) is turned off during the accumulation period before the signal is read. (2) Before reading out the noise signal, read out a light quantity sampling signal which is a signal corresponding to the incident light quantity accumulated in the FD area (FIG. 28). Note that this signal is FD
An optical signal that enters the area is used. In CCDs, such optical signals are prevented by layout and shading.
In the present embodiment, the light amount sampling signal is obtained by positively using such an optical signal. In some cases, the upper part of the FD region is opened, and a signal is further taken in, so that a larger sampling signal can be obtained. (3) After resetting the FD area by turning on / off the reset switch, the noise signal is read out (FIG. 2).
8). (4) Using the or signal in FIG. 28, the amount of incident light is determined in the reset voltage control circuit, and the reset voltage is determined in accordance with the determination. (5) Set to the reset voltage determined in (4) above,
The FD area is reset again. Here, the voltage V2 was selected as the reset voltage from the voltages V1 to V4 shown in FIG. (6) Read out the noise signal after reset (FIG. 28). (7) The transfer switch (transfer transistor MTX) is turned on / off by the transfer pulse to transfer the signal charge from the photodiode to the FD region, and read out the noise + optical signal (FIG. 28). The signal of FIG. 28 was used to read the main signal which is an image signal.

As described above, in the present embodiment, a variety of image signals can be obtained by controlling the sensitivity according to the light amount by the reset voltage using the sampling signal.

The present invention is not limited to the area sensor,
It can also be used for line sensors.

[0058]

As described above, according to the present invention,
The sensitivity can be changed in accordance with the signal charges stored in the photoelectric conversion unit, and a signal with an expanded dynamic range can be obtained.

Also, by appropriately changing the reset voltage,
Switching of the sensitivity can be performed.

For this reason, if necessary, a signal having a high sensitivity but a small dynamic range and a signal having a low sensitivity but a large dynamic range can be switched and output. Therefore, the present invention can be used, for example, for backlight correction.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory diagram showing a configuration of a solid-state imaging device according to the present invention.

FIG. 2 is a schematic explanatory diagram illustrating a configuration of a solid-state imaging device according to the present invention.

FIG. 3 is an explanatory diagram in a case where an FD portion and a MOS component have a step-like potential structure.

4A is a diagram showing characteristics of VFD-Q, and FIG.
FIG. 3C is a diagram illustrating characteristics of FD-Cap, and FIG. 3C is a diagram illustrating light amount-output characteristics.

FIG. 5 is an explanatory diagram in a case where an FD section and a MOS component section have an inverted “concave” shape potential structure.

FIG. 6A is a diagram showing characteristics of VFD-Q, and FIG.
FIG. 3C is a diagram illustrating characteristics of FD-Cap, and FIG. 3C is a diagram illustrating light amount-output characteristics.

FIG. 7 is a schematic plan view of a solid-state imaging device including a MOS capacitor.

FIG. 8 is a schematic plan view of another example of the solid-state imaging device including a MOS capacitor.

FIG. 9 is a schematic sectional view showing an FD region and a buried PN junction.

FIG. 10 is a characteristic diagram showing a relationship between a reverse bias voltage and a capacitance.

FIG. 11 is a schematic sectional view showing an FD region and a buried PN junction.

FIG. 12 is a schematic plan view of a solid-state imaging device having a buried PN junction;

FIG. 13 shows N in the case of forming a step-like potential structure.
FIG. 3 is a plan view illustrating a planar shape of a diffusion region.

FIG. 14 is a plan view showing a planar shape of an N diffusion region when an inverted “concave” potential structure is formed.

FIG. 15 is a schematic configuration diagram of a solid-state imaging device including a reset MOS transistor.

FIGS. 16A to 16D are potential diagrams showing a light accumulation operation, a reset operation, a noise reading operation, and a signal transfer / signal reading operation, respectively.

FIG. 17 is a potential diagram showing an operation of changing sensitivity by changing a reset potential.

FIG. 18 is a characteristic diagram showing a light amount-output characteristic (sensitivity characteristic).

FIG. 19 is a pixel configuration diagram for explaining a method of applying a reset voltage.

FIG. 20 is a pixel configuration diagram for explaining a method of applying a reset voltage.

FIG. 21 is a pixel configuration diagram for explaining a method of applying a reset voltage.

FIG. 22 is a block diagram of a camera device using a solid-state imaging device that sets a reset voltage according to a sampling result.

FIG. 23 is a potential diagram illustrating a detection operation of a sampling signal.

FIG. 24 is a schematic configuration diagram showing a configuration of an area sensor.

FIG. 25 is a block diagram illustrating a video camera device using the solid-state imaging device according to the present embodiment.

FIG. 26 is a block diagram showing a conventional video camera device.

FIG. 27 is a block diagram showing a configuration of a fourth embodiment of the solid-state imaging device according to the present invention.

FIG. 28 is a timing chart showing the operation of the solid-state imaging device of the embodiment.

FIG. 29 is a diagram showing characteristics of VFD-Cap.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-type semiconductor substrate 2 P-type well region 3 N-type diffusion region 4 P-type region 5 Floating diffusion (FD) region 6 Transfer gate electrode 7, 8 MOS constituent part 11 Photodiode (PD) 12 Gate of transfer MOS transistor 13 Floating Diffusion region (FD) 14 Gate of reset MOS transistor 15, 16 Gate electrode for constituting MOS capacitance 21 FD region 22 High concentration surface P region (PSR) 23, 24 N-type diffusion region (DN1, DN2) 25 PWL (P-well region) 26 N-type diffusion region (DN) 31 Solid-state imaging device (sensor) 32 CDS / AGC 33 A / D converter 34 Camera signal processing IC 35 Saturation bit memory

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takumi Hiyama 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Katsuhito Sakurai 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Katsuhisa Ogawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yutake Ueno 3-30-2, Shimomaruko 3-chome, Ota-ku, Tokyo Canon Inc. ( 72) Inventor Narutoshi Sugawa 3- 30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Hideyuki Arai 3-30-2 Shimomaruko 3-chome, Ota-ku, Tokyo F-term in Canon Inc. Reference) 4M118 AA02 AB01 BA14 CA04 CA18 DA24 DD04 DD09 DD10 DD12 FA06 FA33 5C024 AA01 CA15 DA01 DA07 FA01 GA01 GA33 GA43 GA48 GA49 HA21 HA27 JA31

Claims (10)

[Claims] 1. A photoelectric conversion unit, and a charge-voltage conversion unit that converts a signal charge transferred from the photoelectric conversion unit into a signal voltage.
The solid-state imaging device according to claim 1, wherein the charge-voltage conversion unit includes a plurality of capacitors having different voltage dependencies. 2. The charge-to-voltage converter includes an impurity diffusion region and a MOS component, and the plurality of capacitors having different voltage dependencies include a capacitor formed in the impurity diffusion region and the MOS component. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured by a capacitor formed in the solid-state imaging device. 3. The charge-to-voltage converter includes an impurity diffusion region and a buried semiconductor junction, and the plurality of capacitors having different voltage dependencies include a capacitor formed in the impurity diffusion region and a buried semiconductor junction. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device includes a capacitor formed at the embedded semiconductor junction. 3. 4. The method according to claim 1, wherein a voltage dependence of a capacitance formed in the buried semiconductor junction is controlled by an impurity concentration or a depth of one of the one conductivity type semiconductor regions constituting the semiconductor junction. The solid-state imaging device according to claim 3. 5. The semiconductor device according to claim 3, wherein the voltage dependence of the capacitance formed at the buried semiconductor junction is controlled by the width of one of the one conductivity type semiconductor regions constituting the semiconductor junction. The solid-state imaging device according to claim 1. 6. A charge-voltage conversion unit comprising: reset means for applying a reset voltage to reset the charge-voltage conversion unit; and controlling the voltage value of the reset voltage to control the charge-voltage conversion efficiency of the charge-voltage conversion unit. Claim 1 characterized by the following:
The solid-state imaging device according to claim 5. 7. The solid-state imaging device according to claim 6, wherein a sampling unit that samples a light amount incident on the photoelectric conversion unit, and the reset voltage is set according to a sampling signal of the sampling unit. 8. The solid-state imaging device according to claim 7, wherein the sampling signal is a signal one frame before. 9. The solid-state imaging device according to claim 7, wherein the sampling signal is an overflow drain signal or a smear signal. 10. The method according to claim 1, wherein a second signal charge having a shorter accumulation time than the accumulation period is transferred to the impurity diffusion region before the accumulation period of the signal charge, and the second signal charge is used as a sampling signal. The solid-state imaging device according to claim 7.