JP2002368124A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a circuit to operate at a high speed under a low-power supply voltage, and to reduce power consumption at standby time of an LSI. SOLUTION: The semiconductor regions of P-type well regions 2 and 20, with which transistors Qn1 and Qn2 are formed, are mutually electrically disconnected. The substrate potential of the transistor Qn1 is set to 0 V by a first substrate bias circuit VBGEN1 and the substrate potential of the transistor Qn2 is set to -1 V by a second substrate bias circuit VBGEN2. At standby, the substrate potential of each of transistors Qn1 and Qn2 is set to a high substrate potential, such as -5 V.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a substrate bias means for controlling a threshold voltage of a MOS field effect transistor.

[0002]

2. Description of the Related Art FIG.
This will be described with reference to FIG.

An N-type well region 2 and a P-type well region 3 are formed adjacent to a surface of a P-type semiconductor substrate 1. In the N-type well region 2, a P-channel MOS field effect transistor Qp1 (hereinafter, abbreviated as transistor QP1) is formed. On the other hand, in the P-type well region 3, an N-channel MOS field-effect transistor Qn1 (hereinafter, abbreviated as transistor Qn1) is formed.

The transistor Qp1 has a gate electrode 3, a gate insulating film (not shown) formed between the gate electrode 3 and the N-type well region 2, a P-type drain region 4, and a P-type source region 5. . Further, an N-type layer 6 for setting the substrate potential of the N-type well region 2 in which the transistor Qp1 is formed is formed. A power supply voltage Vcc is supplied to the P-type source region 5 and the N-type layer 6.

On the other hand, the transistor Qn1 has a gate electrode 7,
It has a gate insulating film (not shown) formed between the gate electrode 7 and the P-type well region 3, an N-type source region 8, and an N-type drain region 9. Further, a p-type layer 10 for setting the substrate potential of the p-type well region 3 in which the transistor Qn1 is formed is formed. In the N-type source region 8,
The ground potential Vss is supplied. Further, a substrate bias voltage VB is supplied to the p-type layer 10. FIG. 7 shows an inverter circuit as an example of a circuit configured using the transistors Qp1 and Qn1.

Conventionally, the N-type well region 2 in which the transistor Qp1 is formed is biased by the power supply potential Vcc.
The P-type well region 3 where the transistor Qn1 was formed was biased by the substrate bias potential VB (0 V or -1 V). That is, the transistor operation is performed in a state where a single voltage is applied to the substrate on which the transistor is formed.

[0007]

The recent LS
In I, the required operation speed varies depending on the characteristics of a circuit integrated in the LSI, and therefore, for a circuit that requires high-speed operation, the threshold voltage of a transistor constituting the circuit is reduced. Set lower. Therefore, transistors having a plurality of thresholds are formed on the same semiconductor substrate for transistors of the same conductivity type.

However, for example, when the power supply voltage Vcc is 3.
Even when the voltage is as low as 3 V, the threshold voltage of the transistor must be set low to operate the circuit at high speed. Then, the leakage current of the transistor increases particularly during standby (standby) when the operation of the circuit is stopped, and the power consumption of the entire LSI increases. For this reason, the threshold voltage cannot be lowered from a certain limit, so that there is a limit in increasing the speed of the circuit.

Further, in order to form a transistor having a plurality of thresholds on the same semiconductor substrate, a plurality of ion implantation steps are performed to change the impurity concentration of the channel region for each transistor. Therefore, there is a problem that the number of steps of ion implantation increases.

An object of the present invention is to enable high-speed operation of a circuit under a low power supply voltage. Also,
Another object of the present invention is to reduce power consumption during standby of an LSI. Still another object of the present invention is to enable threshold voltages of a plurality of transistors to be set to different values without increasing the number of steps of ion implantation.

[0011]

In the semiconductor device of the present invention, the semiconductor regions in which a plurality of MOS field effect transistors are formed are electrically separated from each other, so that different substrate potentials can be applied. If different substrate potentials are set by the plurality of substrate bias means, the threshold voltages of the plurality of MOS field effect transistors can be set to different values due to the back gate bias effect.

As a result, the threshold voltage of the MOS field-effect transistor can be lowered, and the speed of the circuit can be increased. Also, without increasing the number of ion implantation steps,
The threshold voltages of the plurality of transistors can be set to different values.

Further, among the plurality of substrate bias means,
At least one of them outputs a substrate bias voltage higher than the substrate bias voltage during normal operation in accordance with the standby signal, so that power consumption during standby can be reduced.

[0014]

Next, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

On the surface of a P-type semiconductor substrate 1, an N-type well region 2 and a first P-type well region 3 are formed adjacent to each other. In the N-type well region 2, a P-channel MOS field effect transistor Qp1 (hereinafter, abbreviated as transistor QP1) is formed. The first P-type well region 3 has a first N-channel MOS field effect transistor Q
n1 (hereinafter abbreviated as transistor Qn1).

In the N-type well region 2, a second P-type well region 20 is formed. In the second P-type well region 20, a second N-channel type MOS field effect transistor Qn2 (hereinafter abbreviated as transistor Qn2) is formed.

The transistor Qp1 has a gate electrode 3, a gate insulating film (not shown) formed between the gate electrode 3 and the N-type well region 2, a P-type drain region 4, and a P-type source region 5. . Further, an N-type layer 6 for setting the substrate potential of the N-type well region 2 in which the transistor Qp1 is formed is formed. A positive power supply potential Vcc (for example, +3.3 V) is supplied to the P-type source region 5 and the N-type layer 6.

On the other hand, the transistor Qn1 has a gate electrode 7,
It has a gate insulating film (not shown) formed between the gate electrode 7 and the P-type well region 3, an N-type source region 8, and an N-type drain region 9. Further, a p-type layer 10 for setting the substrate potential of the p-type well region 3 in which the transistor Qn1 is formed is formed. In the N-type source region 8,
The ground potential Vss (0 V) is supplied.

The p-type layer 10 is supplied with a substrate bias potential from a first substrate bias circuit VBGEN1. First
The substrate bias circuit VBGEN1 is configured to output 0 V during normal operation and output a higher substrate potential, for example, -5 V during standby, in response to the standby signal STBY.

Here, the threshold voltage Vt of a MOS transistor is generally expressed by the following equation.

[0021]

(Equation 1)

Here, φB is a bulk potential, K is a substrate constant, VB is a substrate bias potential, and VFB is a flat band voltage. φB and K are expressed as follows.

[0023]

(Equation 2)

Here, KB is the Boltzmann constant, T is the absolute temperature, q is the electron charge, N is the impurity concentration of the substrate, and ni is the electron concentration of the intrinsic semiconductor.

[0025]

(Equation 3)

Here, ε0 is a dielectric constant in a vacuum, εs is a relative dielectric constant of a semiconductor, and Ci is a gate capacitance.

Therefore, the first substrate bias circuit VBGE
By changing the substrate bias potential VB (potential of the first P-type well region 3) supplied by N1, the transistor Qn1
Can be changed.

The transistor Qn2 formed in the second P-type well region 20 includes a gate electrode 21, a gate insulating film (not shown) formed between the gate electrode 21 and the P-type well region 20, and an N-type It has a source region 22 and an N-type drain region 23. Further, a p-type layer 24 for setting the substrate potential of the p-type well region 20 where the transistor Qn2 is formed is formed. The ground potential Vss (0 V) is supplied to the N-type source region 22.

As described above, since the power supply potential Vcc is supplied to the N-type well region 2, the first P-type well region 3 and the second P-type well region 20 are set to a potential lower than the power supply potential Vcc. If set, they are electrically isolated from each other. Thereby, the first P-type well region 2 and the second P-type well region 20 can be set to potentials independent of each other.

Therefore, a substrate bias potential is supplied to the p-type layer 24 from the second substrate bias circuit VBGEN2. The second substrate bias circuit VBGEN2 is configured to output -1 V during normal operation and output a higher substrate potential, for example, -5 V during standby, in response to the standby signal STBY.

That is, during the normal operation, the first P-type well region 3 is set to 0 V by the first substrate bias circuit VBGEN1.
, The threshold value Vtn1 of the transistor Qn1
Is 0.5 V, for example. Therefore, a high-speed CMOS circuit can be realized using the transistors (Qn1, Qp1). FIG. 5 shows an example in which an inverter circuit is configured.

In the normal operation, the second P-type well region 20 is set to -1 V by the second substrate bias circuit VBGEN2, so that the threshold value Vtn2 of the transistor Qn2 becomes higher than this. , For example, 0.8V. Therefore, a low-speed CMOS circuit can be realized using the transistors (Qn2, Qp1).

In the standby mode, the first P-type well region 3 is set to a deep substrate potential of, for example, -5 V by the first substrate bias circuit VBGEN1, so that the threshold value Vtn1 of the transistor Qn1 is as high as 2 V, for example. Become. Similarly, the second P-type well region 20 is set to a deep substrate potential of, for example, -5 V by the second substrate bias circuit VBGEN2, so that the threshold value Vtn2 of the transistor Qn2 is, for example, 2
V. As a result, the leakage current is suppressed, so that the current consumption during standby can be reduced.

Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the first substrate bias circuit VBGEN1 switches and outputs the substrate potential VB inside the circuit. In the present embodiment, the substrate bias circuit for setting the potential of the first P-type well region 3 has a ground potential of 0 V
And a substrate bias circuit VBGE for generating a substrate potential of -5 V
N1B is provided separately. The output 0 V and −5 V are switched by the switch circuit SW 1 in accordance with the standby signal STBY and supplied to the P-type layer 10.

As for the substrate bias circuit for setting the potential of the second P-type well region 20, a substrate bias circuit VBGEN2A for generating a substrate potential of -1V and a substrate bias circuit of -5V
And a substrate bias circuit VBGEN2B that generates a substrate potential of
1 V and -5 V are switched by the switch circuit SW2 and supplied to the P-type layer 24. The operation of this semiconductor device is the same as in the first embodiment.

Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. In the present embodiment, a third P-type well region 30 is further formed in the N-type well region 2.

The transistor Qn3 formed in the third P-type well region 30 includes a gate electrode 31, a gate electrode 3
, A gate insulating film (not shown) formed between the P-type well region 30, the N-type source region 32, and the N-type drain region 3.
Three. In addition, p for setting the substrate potential of the P-type well region 30 in which the transistor Qn3 is formed.
A mold layer 34 is formed. In the N-type source region 32,
The ground potential Vss (0 V) is supplied.

The p-type layer 34 has a third substrate bias circuit
The substrate bias potential is supplied from VBGEN3. The third substrate bias circuit VBGEN3 responds to the standby signal STBY
It is configured to output −2 V during normal operation and output a higher substrate potential, for example, −5 V, during standby.

According to this semiconductor device, during the normal operation, the first P-type well region 3 is set to 0 V by the first substrate bias circuit VBGEN1, so that the transistor Q
The threshold value Vtn1 of n1 is, for example, 0.5V. Further, the second P-type well region 20 is provided with a second substrate bias circuit VB.
Since the voltage is set to -1 V by GEN2, the transistor Qn2
Is, for example, 0.8V. Also, the third
P-type well region 30 is provided with a third substrate bias circuit VBGE
Since it is set to −2 V by N 3, the threshold value Vtn 3 of the transistor Qn 3 is, for example, 1.0 V.

Therefore, the transistors (Qn1, Qp1)
To form a high-speed CMOS circuit, and to form a medium-speed CMOS circuit using transistors (Qn2, Qp1).
A low-speed CMOS circuit can be configured using the transistors (Qn3, Qp1).

At the time of standby, the outputs of the first substrate bias circuit VBGEN1 to the third substrate bias circuit VBGEN3 are switched to -5V, so that the transistors Qn1 to Qn
By increasing the threshold value of n3, the leakage current can be reduced.

Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the substrate bias circuit for setting the potential of the first P-type well region 3 includes a ground potential of 0 V,
A substrate bias circuit VBGEN1B for generating a substrate potential of 5 V is provided separately. Then, the standby signal STBY
The output of 0 V and −5 V are switched according to the
And supply to the P-type layer 10.

The substrate bias circuit for setting the potential of the second P-type well region 20 includes a substrate bias circuit VBGEN2A for generating a substrate potential of -1 V and a substrate bias circuit of -5 V
And a substrate bias circuit VBGEN2B that generates a substrate potential of
1 V and -5 V are switched by the switch circuit SW2 and supplied to the P-type layer 24.

Further, regarding a substrate bias circuit for setting the potential of the third P-type well region 30, a voltage of -2V
Bias circuit VBGEN3A and -5 to generate substrate potential
A substrate bias circuit VBGEN3B for generating a substrate potential of V is separately provided, and the output of −2 V and −5 V is switched by a switch circuit SW 3 in accordance with a standby signal STBY and supplied to the P-type layer 34. . The operation of this semiconductor device is the same as that of the third embodiment.

Although the four embodiments of the present invention have been described above, the present invention is not limited to these. For example, a P-type well region is additionally formed in the N-type well region 2, a MOS transistor is formed therein, and a substrate bias circuit for setting the potential of the P-type well region can be provided. .

In the four embodiments of the present invention, the threshold voltages are set to different values by setting the substrates of the N-channel MOS transistors to different potentials. Can be similarly configured.

[0047]

According to the present invention, since a different substrate potential is set for each MOS transistor by a plurality of substrate bias means, the threshold voltages of the MOS transistors can be set to different values.

Thus, a MOS transistor having an appropriate threshold voltage can be formed according to the operation speed of the circuit.

Further, according to the present invention, at the time of standby of the LSI, the threshold value of the MOS transistor can be increased by the substrate bias means, and the power consumption can be reduced.

Further, according to the present invention, since the threshold voltage of the MOS transistor is made variable by an electric method, the threshold voltages of the plurality of transistors can be reduced without increasing the number of ion implantation steps. It can be settable to different values.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing an inverter circuit to which the semiconductor device according to the embodiment of the present invention is applied.

FIG. 6 is a cross-sectional view showing a semiconductor device according to a conventional example.

FIG. 7 is a diagram showing an inverter circuit to which a semiconductor device according to a conventional example is applied.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 27/092 H03K 19/00 F-term (Reference) 5F038 BG09 DF01 EZ20 5F048 AA07 AB04 AB10 AC01 AC03 BA01 BB15 BE02 BE03 BE04 BE09 5J056 AA03 BB02 BB17 BB59 DD12 DD45 GG09 KK02

Claims (8)

[Claims] A plurality of semiconductor regions formed on the same semiconductor substrate and electrically separated from each other; a plurality of MOS field-effect transistors formed in each of the semiconductor regions; A plurality of substrate bias means provided for each semiconductor region to set different substrate potentials;
And a threshold voltage of the plurality of MOS field-effect transistors can be set to different values. 2. The method according to claim 1, wherein at least one of the plurality of substrate bias units outputs a substrate bias voltage higher than a substrate bias voltage in a normal operation in response to a standby signal. The semiconductor device according to claim 1. 3. The substrate biasing means, wherein at least one substrate biasing means outputs a first substrate biasing voltage, and a second substrate biasing higher than the first substrate biasing voltage. A second substrate bias means for outputting a voltage; and a switch circuit for switching so as to output the first substrate bias voltage during normal operation and to output the second substrate bias voltage during standby. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein the plurality of semiconductor regions include at least one semiconductor region.
2. The method of claim 1, wherein the at least one well region comprises at least one well region.
The semiconductor device according to any one of 2 and 3. 5. A plurality of semiconductor regions formed on the same semiconductor substrate and electrically separated from each other; a plurality of MOS field-effect transistors formed in the semiconductor regions; and a plurality of MOS field-effect transistors A plurality of substrate bias means for setting the semiconductor region to different substrate potentials in order to set the threshold voltages of the transistors to different values; A high-speed operation circuit using a low-voltage MOS field effect transistor and a high threshold voltage MOS
A semiconductor device comprising a circuit that operates at a low speed using a field-effect transistor. 6. A method according to claim 1, wherein at least one of the plurality of substrate bias units outputs a substrate bias voltage higher than a substrate bias voltage in a normal operation in response to a standby signal. 6. The semiconductor device according to claim 5, wherein: 7. The substrate bias unit, wherein at least one substrate bias unit outputs a first substrate bias voltage, and a second substrate bias unit that is higher than the first substrate bias voltage. A second substrate bias unit that outputs a bias voltage; and a switch circuit that switches so as to output the first substrate bias voltage during normal operation and to output the second substrate bias voltage during standby. 6. The semiconductor device according to claim 5, wherein 8. The semiconductor device according to claim 5, wherein the plurality of semiconductor regions include at least one well region.
8. The semiconductor device according to any one of 7.