JP2002368118A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a high quality factor Q by disposing a thick film inductor above a bipolar transistor.
To provide a semiconductor device which is easy to manufacture and low in cost while having the above. SOLUTION: An interlayer insulating film 41 is formed on a second layer wiring 35 on a bipolar transistor 30 and spin-coated thereon to form an SOG film 42, which is etched back and flattened. Further, an interlayer insulating film 43 is formed, and a spin coating is performed thereon to form an SOG film 44, which is etched back and flattened. Next, an Al thick film is formed on the interlayer insulating film 45 formed thereon, and a third layer wiring 46 including the thick film inductor 52 is formed by dry etching by RIE through a patterned resist film. A semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having an inductor on a high-speed bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a semiconductor device, particularly a semiconductor device used in a high-frequency circuit of a wireless communication system represented by a mobile phone, is required to have higher speed and higher integration. Therefore, bipolar transistors that operate at high speed, and among them, single-polysilicon bipolar transistors and double-polysilicon bipolar transistors having a washed-emitter configuration have been adopted for higher speed.

On the other hand, a high quality factor Q (described later) is required for an inductor for high-frequency oscillation, and a relatively large area occupies a relatively large area when the inductor is formed into a planar spiral shape. Since this is an obstacle to high integration, it is desired to reduce the occupied area as much as possible.Therefore, it is unavoidable to use an inductor as an on-chip inductor placed above a bipolar transistor. ing.

FIG. 13 is a plan view showing a planar spiral inductor, and FIG. 14 is [1] in FIG.
FIG. 4 is a cross-sectional view taken along line [4]-[14]. 13 and 14
Referring to FIG. 1, an inductor 110 is provided on a semiconductor substrate 101, a lower wiring 103 is formed on an insulating film 102, an interlayer insulating film 104 is formed thereon, and the lower wiring and the inductor are further formed on the interlayer insulating film 104. A contact electrode 105 is formed. Then, on the interlayer insulating film 104, an upper wiring 106 and a spiral inductor 110 are integrally formed subsequently to the upper wiring 106.
The other end of the inductor 110 is connected to the contact electrode 105 with the lower wiring 103.

As is well known, an inductor has L (inductance) and Q (quality factor: sharpness of oscillation).
, And the characteristic is represented by the following equation (1). Q = ωL / R Equation (1) Here, ω is the angular frequency, and R is the wiring resistance of the inductor. Therefore, to obtain a high Q, it is necessary to increase L and decrease R. That is, to increase L, the number of turns of the spiral inductor (inductor 110 in FIG. 13) is increased, and to decrease R, inductor 110 is increased.
It is necessary to increase the surface area and the film thickness of the film.

However, increasing the number of turns of the inductor and increasing the surface area of the inductor in a semiconductor device for high integration increases the area occupied by the inductor. On the other hand leads to increasing R. Therefore, there remains a method of making the inductor a thick film, but a thick film inductor is liable to cause a shape defect when dry-etching a metal thick film into a spiral shape, and is liable to leave a processing residue. There is a problem in that only a semiconductor device having poor reliability can be obtained even if it is incorporated.

In such a situation, Japanese Patent Laid-Open No.
334137 discloses that semi-insulating GaAs is applied to inductors 115, 116 and 117 formed on an insulating passive circuit board 104 as shown in the plan view of FIG.
A hybrid integrated circuit in which an FET element chip 103 formed on an s substrate is mounted by a flip chip bonding method is disclosed. Since this integrated circuit is in a different region from the inductors 115, 116, 117 and the FET element chip 103, it requires a large area as a whole. In addition, since the inductor and the FET are individually manufactured and assembled. The cost is great.

On the other hand, Japanese Patent Application Laid-Open No. 3-263366 discloses an inductor as shown in FIG.
That is, in FIG. 16, a plurality of ring-shaped metal wiring layers 251, 252, 253 are stacked on an insulating film 259 on a circuit element region 240 formed on a semiconductor substrate via interlayer insulating films 256, 257 therebetween. Has been
Through holes 25 provided in interlayer insulating films 256 and 257
4, 255, the ring-shaped metal wiring layers 251, 25
An inductor 250 to which the second and the second 253 are connected is provided.

Japanese Patent Publication No. 2904086 discloses a first conductive pattern 3 similar to an ordinary inductor.
No. 01, and an inductor composed of a second conductive pattern 302 which is formed in an overlapping relationship with the upper and lower positions and which are electrically connected to each other. 17A is a plan view of the inductor, and FIG. 17B is a sectional view taken along the line [B]-[B] in FIG. 17A. As shown by a solid line in FIG. 17A, a spiral-shaped first conductive pattern 301 is formed on the insulating film 300, and in the insulating film 300 thereunder, avoid overlapping in FIG. 17A. A second conductive pattern 302 indicated by a slightly larger broken line is formed, and the first conductive pattern 301 and the second conductive pattern 302 are electrically connected to each other by a vertical and elongated flat contact 303. . Then, the illustrated first conductive pattern 301 and the second conductive pattern
Each of the conductive patterns 302 has a thickness of 0.5 to 1.0 μm.
It has been.

[0010]

SUMMARY OF THE INVENTION The above-mentioned JP-A-3-26.
The semiconductor device disclosed in Japanese Patent No. 3366 discloses an inductor 250
Are arranged on the circuit element region 240, so that the entire required area is small, but the inductor 250 is formed of the ring-shaped metal wiring layers 251, 252, 253 and the interlayer insulating films 256, 25.
7 are alternately stacked, which complicates the manufacturing process and increases the wiring resistance of the inductor 250. Also, the semiconductor device according to Japanese Patent Publication No. 2904086 discloses a first conductive pattern 301 in forming an inductor.
There is a drawback in that fine processing must be repeated like the formation of the second conductive pattern 302 and the formation of the second conductive pattern 302. That is, in these semiconductor layer devices, the Q
In order to increase the thickness of the inductor, the inductor is formed in a two-layer structure or a three-layer structure instead of increasing the thickness of the inductor, which requires complicated processing.

However, as described above, even if an attempt is made to form a thick-film inductor in order to simplify the process of forming the inductor, for example, if an attempt is made to process a thick aluminum film into a spiral shape, the spiral shape defect will not occur. The generation of processing residues, prolonged processing, and other various problems that may become a bottleneck in the process occur. Especially, the processing residues remaining in the inductor have a great effect on the characteristics and reliability of the inductor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a semiconductor device for high-speed communication, which is small in size but easy to manufacture and low in cost, is provided by disposing a thick film inductor above a bipolar transistor. It is an object to provide a manufacturing method.

[0013]

Means for Solving the Problems The above problems can be solved by the structure of claim 1 or claim 6. The means for solving the problems is as follows.

According to a first aspect of the present invention, there is provided a semiconductor device having a bipolar transistor and an inductor.
This is a semiconductor device in which a spiral thick-film inductor is formed on a planarized interlayer insulating film on a bipolar transistor. Such a semiconductor device provides a miniaturized and highly integrated semiconductor device because the thick film inductor is formed above the bipolar transistor.

According to a second aspect of the present invention, the thick film inductor is formed integrally with the wiring by processing a metal thick film formed on the interlayer insulating film. Such a semiconductor device is low-cost because the inductor and the bipolar transistor are not manufactured independently, but the wiring of the bipolar transistor and the inductor are formed integrally by processing a metal thick film. . Claim 2
The semiconductor device according to claim 3 is a semiconductor device in which the material of the metal thick film is aluminum (Al), tungsten (W), or molybdenum (Mo). Such a semiconductor device is easy to form a thick metal film and to form a thick film inductor by processing the thick metal film, and provides a low-cost inductor.

A semiconductor device according to a fourth aspect of the present invention is a semiconductor device in which a spiral thick film inductor is formed by repeating an octagon having four corners cut off. Such a semiconductor device is easy to process from a metal thick film and is low in cost. In addition, it is possible to increase the surface area of the thick film inductor and reduce the resistance of the inductor to increase Q. The semiconductor device according to claim 5 is a semiconductor device in which the bipolar transistor is a double polysilicon type bipolar transistor or a single polysilicon type bipolar transistor. Such a semiconductor device provides a low-cost semiconductor device capable of higher-speed communication than a conventional semiconductor device for high-speed communication.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device having a bipolar transistor and an inductor, a step of flattening an interlayer insulating film formed on the bipolar transistor is provided. A manufacturing method includes a step of forming a thick metal film on an insulating film and a step of processing the thick metal film to form a thick-film inductor in a spiral shape integrally with wiring. In such a method of manufacturing a semiconductor device, a metal thick film formed on a flattened interlayer insulating film is processed into a spiral-shaped thick-film inductor, so that the processing is performed smoothly and no defective shape of the inductor or processing residue occurs. .

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the step of flattening the interlayer insulating film is performed by spin-coating the interlayer insulating film to form a spin-on-glass film. This is a manufacturing method which is a step of performing etch back. In such a method of manufacturing a semiconductor device, the concave portions on the interlayer insulating film are filled, and the convex portions are removed to easily flatten the interlayer insulating film. In the method of manufacturing a semiconductor device according to claim 7, the step of flattening the interlayer insulating film includes forming the interlayer insulating film, spin-coating the spin-on-glass film on the formed interlayer insulating film. And a step of repeating the combination with the etch-back of the spin-on-glass film twice or more. The method for manufacturing such a semiconductor device is as follows.
In addition to enabling the interlayer insulating film to be further flattened, it also enables the wiring and the thick-film inductor to be formed in the third or fourth layer. According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a thick metal film is processed by a reactive ion etching method. Such a method of manufacturing a semiconductor device enables fine processing of a thick-film inductor to be performed accurately and at high speed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, in a semiconductor device having a bipolar transistor and a spiral-shaped inductor, a semiconductor device and a method of manufacturing the same according to the present invention are provided on a flattened interlayer insulating film on the bipolar transistor. This is a semiconductor device on which a spiral-shaped thick film inductor is formed.

The formation of the thick-film inductor is performed after the surface of the interlayer insulating film is flattened, but the lower bipolar transistor electrode and its lead-out wiring are used as the first layer, and the two layers are provided via the interlayer insulating film thereover. When a thick-film inductor is formed on the wiring of the eye, the interlayer insulating film is flattened by spin-coating the interlayer insulating film to form an SOG (spin-on-glass) film having excellent flatness, and furthermore, the surface of the SOG film. This is done by etching back from the side. If the surface of the interlayer insulating film has large irregularities and steps and sufficient flatness cannot be obtained by a single combination of the SOG film formation and the etch back, an interlayer insulating film is further formed thereon. And SO
The spin coating and the etch back of the G film are repeated. In the case where the thick film inductor is provided integrally with the third or fourth layer wiring, the surface step generally becomes large, so that the interlayer insulating film is formed, the SOG film is spin-coated, and the SOG film is formed. It is necessary to repeat the etchback combination at least twice. Note that these operations are simple in terms of the process and do not significantly increase the manufacturing cost of the semiconductor device.

The thick film inductor according to the present invention is not formed separately as an inductor and connected to a wiring, but is formed integrally with the wiring by processing a metal thick film formed on an interlayer insulating film into a pattern. Is done. Therefore, the manufacturing cost can be significantly reduced as compared with the case where an inductor is separately formed, and a highly integrated, low-cost semiconductor device can be obtained. As a material for the wiring and the thick film inductor, Al (aluminum) is selected from the viewpoint that it is easy to form a metal thick film and process the metal thick film and that it is inexpensive, but W (tungsten) and Mo ( Molybdenum) can be used almost equally.

The thickness of the thick-film inductor to be formed is set to 2 to 3 μm or more, and the real area per occupied area of the inductor is made as large as possible to reduce the resistance R in the equation (1). A high quality factor Q can be obtained. In addition, the spiral shape of the inductor may be any shape such as a repetitive unit spiral having a circular shape, a triangular shape, or the like. Reduce costs. The processing of the metal thick film is performed by the RIE (Reactive Ion Etching) method, which is capable of high-speed etching, high selectivity, low damage, and high-precision processing. The RIE method includes an ECR (electron cyclotron resonance) type, a magnetron type, a triode type, a narrow gap type, and the like.
The R shape is preferable because it has excellent fine workability and low damageability.

The thick film inductor is a semiconductor layer device for communication in combination with a bipolar transistor which operates at high speed and is relatively easy to integrate. Among the bipolar transistors, the emitter is made of polysilicon to further increase the speed. A single-polysilicon type bipolar transistor in which impurities As etc. are implanted and diffused into the base to form a washed-emitter structure, and a double-polysilicon type in which the emitter and the base are made of polysilicon for a more stable performance. Bipolar transistors are preferably combined with thick film inductors.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a semiconductor device according to the present invention;

(Embodiment 1) Hereinafter, a semiconductor device having an on-chip inductor formed by forming a double polysilicon type bipolar transistor on a substrate and forming a thick film inductor on an interlayer insulating film on the bipolar transistor will be described. As an example, the manufacturing method will be described with reference to FIGS.

As shown in FIG. 1A, an n ⁺ -type buried layer 2 is selectively formed on a p-type silicon semiconductor substrate 1 by a known technique, and then the entire surface including the buried layer 2 has a resistivity of about 10%. An n-type epitaxial layer 3 having a thickness of about 1 .OMEGA.
m of silicon oxide (SiO 2) having a thickness of about 30 nm on the epitaxial layer 3 by a thermal oxidation method.
₂ ) The film 4 and low pressure silicon nitride (LP-Si ₃
N ₄ ) A film 5 is deposited. Subsequently, as shown in FIG. 1B, after a resist film 6 is formed on the entire surface, an element isolation region can be formed by a LOCOS (local silicon oxidation) method, that is, an element formation in a central portion in the figure. The resist film 6 is patterned so that the resist film 6 remains on the region. Then, using the resist film 6 as a mask,
The silicon nitride film 5 is removed by a known dry etching technique, and the silicon oxide film 4 is also removed. Therefore, the low-pressure-silicon nitride film 5 remains in a portion to be an element formation region.

Next, after the resist film 6 is stripped with a mixed solution of sulfuric acid and hydrogen peroxide solution (sulfated solution), the thermal oxide film is removed except for the portion where the low-pressure silicon nitride film 5 remains. 7 is formed to a thickness of about 800 nm. Subsequently, the low-pressure silicon nitride film 5 is etched with a chemical such as hot phosphoric acid. Thereafter, as shown in FIG. 2A, n-type P (phosphorus) ions are buried through a patterned resist film 8 in which a portion to be a lead portion of the buried layer 2 (a portion for forming a plug) is opened. The implantation is performed with energy and dose (about 50 keV, about 4.5E15 cm ⁻² ) so as to come into contact with the layer 2. Subsequently, after the resist film 8 is peeled off, a silicon oxide film is deposited to a thickness of about 300 nm on the upper portion thereof by a CVD method using TEOS (tetraethoxyorthosilicate) as a source gas (not shown). Then, after a resist film is formed on the entire surface, the entire surface is etched back by about 130 nm by RIE to planarize the wafer surface as shown in FIG. 2B.

Next, as shown in FIG. 3A, a silicon oxide film 10 having a thickness of about 30 nm is formed on the entire surface by thermal oxidation, and a patterned resist film 11 having an opening at a portion serving as an element isolation region 12 is formed. And p-type B (boron) ions are implanted. That is, ions are implanted with an energy and a dose (about 50 keV, about 4.5E13 cm ⁻² ) so as to be connected to the p-type silicon semiconductor substrate 1. Then, the resist film 11 is peeled off. Subsequently, as shown in FIG.
A silicon oxide film 13 is deposited to a thickness of about 100 nm from TEOS on the surface of the silicon oxide film 10 by a CVD method.
In FIG. 3B, the silicon oxide film 13 and the silicon oxide film 10 are shown integrally. Then, after forming a resist film 14 on the entire surface, the silicon oxide film 1 in the active region is used as a patterned resist film 14 in which a region (active region) for forming an npn transistor is opened.
3 is removed by dry etching, the resist film 14 is removed.
Is peeled off.

Next, as shown in FIG. 4A, a polysilicon film 15 having a thickness of about 150
It is deposited to about nm. Further, BF ²⁺ ions are implanted into the polysilicon film 15 at an energy of about 40 keV and a dose of 5.5E14 cm ⁻² to form a base extraction resistance. Then, a resist film 17 patterned so as to leave a portion of the polysilicon film 15 serving as a base take-out resistance is provided, and after the polysilicon film 15 is removed by dry etching, the resist film 17 is removed. Subsequently, after a silicon oxide film 18 is deposited to a thickness of about 350 nm on the entire surface by a CVD method, a heat treatment (about 600 nm) is performed.
(180 ° C., 180 minutes) to densify the silicon oxide film 18 and improve the film quality. Then, as shown in FIG.
A patterned resist film 19 having an opening at a portion corresponding to an intrinsic base region 21 described later is formed, and the silicon oxide film 1 is formed.
8. The polysilicon film 15 is removed by dry etching, and then the resist film 19 is stripped.

Next, although not shown, a silicon oxide film is deposited to a thickness of about 10 nm on the entire surface by a thermal oxidation method, and then an intrinsic base region 21 is formed as shown in FIG. B ⁺ ions are implanted at an energy of about 30 keV and a dose of 1.0E12 cm ⁻² . Then, a silicon oxide film 22 using TEOS as a source gas is deposited to a thickness of about 550 nm by a CVD method, and the silicon oxide film 22 from which the BF ²⁺ ions have been implanted is transferred from the polysilicon film 15 to the single-crystal n-type epitaxial layer 3. Is heat-treated at about 900 ° C. for 15 minutes so as to form a graft base region 23 by diffusion. As a result, the transistor base region (intrinsic
The graft bases 21 and 23 are completely formed. Subsequently, as shown in FIG. 5B, the silicon oxide film 2 of FIG.
By removing the portion corresponding to the second base region 20 and removing the other portion by the RIE method, the sidewall 24 is formed in the emitter opening immediately above the intrinsic base region 21.

Next, a polysilicon film 25 is deposited to a thickness of about 150 nm on the entire surface by, eg, CVD.
Then, as shown in FIG. 6, in order to form a washed emitter configuration, As ⁺ ions are implanted into the polysilicon film 25 at an energy of about 60 keV and a dose of 2.0E16 cm ⁻² , and the implanted As ⁺ is injected into the intrinsic base. Heat treatment (about 850 ° C., 30 minutes) for diffusing into the region 21 is performed to form the emitter 26 by self-alignment. Then, the polysilicon film 25 other than the emitter extraction portion is removed by a known technique such as photolithography or dry etching, and then a base extraction electrode 27, a collector extraction electrode 28, and an emitter extraction electrode 29 are formed. Thus, a double-polysilicon-type bipolar transistor 30 having a washed-emitter configuration is formed. Thereafter, each electrode 27, 28, 29 includes T
A first layer of Al wiring having an i-type barrier metal is formed and annealed at about 400 ° C. for 20 minutes.

7 and thereafter, the bipolar transistor 30 shown in FIG.
The processing performed around the first-layer Al wiring 31 including 7, 28, and 29 and the formation of the inductor will be described.
7A shows the first-layer Al wiring 31 on the silicon oxide film 18 shown in FIG. Then, as shown in FIG. 7B, CV is formed as an interlayer insulating film on the entire surface on the Al wiring 31.
A silicon oxide film 32 is deposited to a thickness of about 500 nm from TEOS in a plasma atmosphere by method D. Thereafter, an SOG film 33 is spin-coated on the entire surface, and etched back by RIE to flatten a portion having a step. Subsequently, as shown in FIG. 7C, a silicon oxide film 34 is deposited from TEOS over the entire surface in a plasma atmosphere by a CVD method. An opening is formed in the silicon oxide film 34 by RIE in the presence of a patterned resist film (not shown) for a contact electrode between the first-layer Al wiring 31 and a second-layer Al wiring to be formed later. 34 'is provided to remove the resist film.

Next, a silicon oxide film 34 which is an interlayer insulating film
An Al film for forming a second-layer Al wiring 35 is formed thereon with a thickness of 2.5 μm by a sputtering method or the like. Then, as shown in FIG. 8A, the Al film is processed by the RIE method via the patterned resist film to form the second-layer Al wiring 3 including the thick-film inductor 51 and the contact electrode 35 '.
5 is formed. Next, as shown in FIG. 8B, a passivation film 36 is formed on the entire surface by a known process technique so as to cover the second-layer Al wiring 35 including the thick-film inductor 51, thereby forming a double polysilicon type. A semiconductor device for high-speed communication including the thick film inductor 51 above the bipolar transistor 30 is obtained.

(Embodiment 2) The semiconductor device 2 of Embodiment 2
Since the steps up to the formation of the bipolar transistor 30 and the first-layer Al wiring 31 are completely the same as those of the first embodiment, the description will be omitted with reference to FIGS. 1 to 6 described in the first embodiment. Description will be made from FIG. 9 which is similar to FIG.

FIG. 9A shows the first-layer Al wiring 31 shown in FIG. Then, as shown in FIG. 9B, a silicon oxide film 32 having a thickness of about 500 nm is formed on the entire surface of the Al wiring 31 from TEOS in a plasma atmosphere by a CVD method, for example.
Deposit to a degree. Thereafter, an SOG film 33 is spin-coated on the entire surface, and etched back by RIE to flatten a portion having a step.

Subsequently, as shown in FIG.
A silicon oxide film 34 is deposited from TEOS as an interlayer insulating film on the entire surface under a plasma atmosphere by a VD method. Then, the first-layer Al wiring 31 and the second-layer Al
An opening 34 'is formed in the silicon oxide film 34 by RIE in the presence of a patterned resist film (not shown) for a contact electrode with the wiring 35, and the resist film is peeled off. Next, as shown in FIG. 10B, the second layer A
An Al film for forming the l wiring 35 is formed by a sputtering method or the like. Then, although not shown, a second layer Al wiring 35 and a contact electrode 35 'are formed by RIE based on the patterned resist film.

Subsequently, as shown in FIG. 11A, a silicon oxide film 41 of about 55 nm in thickness is formed from TEOS as an interlayer insulating film over the entire surface under a plasma atmosphere by, for example, a CVD method.
Deposit about 0 nm. Subsequently, the SOG film 42 is spin-coated to a thickness of about 450 nm, and then etched back to a thickness of about 550 nm by RIE to flatten the stepped portion. Subsequently, a silicon oxide film 43 is deposited on the entire surface as an interlayer insulating film from TEOS to a thickness of about 500 nm in a plasma atmosphere by, for example, a CVD method, and then an SOG film 44 is spin-coated to a thickness of about 450 nm. Then, about 550 nm of etch back is performed by the RIE method to flatten the stepped portion. Then, a silicon oxide film 45 is deposited to a thickness of about 600 nm from TEOS in a plasma atmosphere by, for example, a CVD method over the entire surface. Next, as shown in FIG. 11B, the presence of a patterned resist film (not shown) for contact electrodes between the second-layer Al wiring 35 and the third-layer Al wiring to be formed later is also shown. And silicon oxide films 45, 4 by RIE.
An opening 45 'penetrating through 3 and 41 is provided, and the resist film is peeled off.

Subsequently, as shown in FIG. 12A, an Al film is deposited to a thickness of about 2.5 μm on the entire surface of the silicon oxide film 45 by a sputtering method. In the presence of the film, the thick film inductor 52 and the third-layer wiring 46 including the contact electrode 46 'are formed by RIE. Next, as shown in FIG.
A passivation film 47 is formed on the entire surface including the thick-film inductor 52, which is also the third-layer Al wiring 46, and the contact electrode 46 'by a well-known process technique. A semiconductor device for high-speed communication including the thick film inductor 52 above the bipolar transistor 30 is obtained.

Although the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to these, and various modifications can be made based on the technical concept of the present invention.

For example, in the present embodiment, a double polysilicon type bipolar transistor is exemplified as a bipolar transistor combined with a thick film inductor, but the present invention is also applicable to a semiconductor device combined with a single polysilicon type bipolar transistor. Is applied.

In this embodiment, a silicon oxide film made of TEOS is used as the interlayer insulating film. However, a PSG (phosphosilicate glass) film or a BPSG film is used as the interlayer insulating film.
(Borophosphosilicate glass) film is formed, 900 ° C
About what was reflowed and flattened at the temperature before and after,
An SOG film may be formed, etched back, and further planarized.

In this embodiment, the thick-film inductor and the wiring are formed of Al. However, materials other than Al may be used. The material is not limited as long as processing by the method is possible. For example, Cu (copper) or Ta (tantalum) may be used in addition to Al, W, and Mo described above. Further, in this embodiment, the flattening after the formation of the SOG film is performed by the etch back by the RIE method, but may be flattened by the chemical mechanical polishing method.

[0043]

The semiconductor device and the method of manufacturing the same according to the present invention are embodied in the form described above, and have the following effects.

According to the semiconductor device of the first aspect, since the spiral thick-film inductor is formed on the planarized interlayer insulating film on the bipolar transistor, processing of the thick-film inductor is easy and high quality. Factor Q
And has become highly reliable,
It is applied as a portable high-speed communication terminal, for example, a mobile phone capable of high-speed communication, an in-vehicle terminal for an automatic toll collection system ETC, and an in-vehicle terminal in a car navigation system for providing detailed information.

According to the semiconductor device of the second aspect, since the thick film inductor is formed integrally with the wiring by processing the metal thick film, the inductor is easily formed, and the semiconductor device has high reliability. In addition, the cost has been reduced. According to the semiconductor device of the third aspect, it is easy to form a thick film as a material of a metal thick film to be processed into a thick film inductor, and Al, W, which can be easily processed by RIE.
Alternatively, since Mo is used, a semiconductor device provided with a highly reliable inductor that does not cause processing defects when processing the spiral shape of the thick film inductor is obtained.

According to the semiconductor device of the fourth aspect, since the spiral shape of the thick film inductor is a repeating unit of an octagon cut off at four corners of a square, processing from a metal thick film is easy. A semiconductor device having an inductor with a high quality factor Q with a large effective area and a small resistance of the thick film inductor is obtained. According to the semiconductor device of the fifth aspect, since the on-chip thick film inductor and the double polysilicon type bipolar transistor or the single polysilicon type bipolar transistor are combined, the cost is lower than that of the conventional communication semiconductor device. Enables high-speed communication.

According to the semiconductor device manufacturing method of the sixth aspect, the interlayer insulating film formed on the bipolar transistor is flattened, and the thick metal film formed on the interlayer insulating film is processed into a spiral-shaped thick film inductor. Therefore, processing is performed smoothly, processing accuracy is high, and quality factor Q
And a highly reliable semiconductor device for communication. According to the method of manufacturing a semiconductor device of the seventh aspect, the planarization of the interlayer insulating film is performed by forming a spin-on-glass film to be spin-coated and subsequently etching back the spin-on-glass film.
The thick metal film formed thereon is flattened, and the thick metal film is processed to provide a semiconductor device having a thick film inductor with high processing accuracy.

According to the semiconductor device manufacturing method of the eighth aspect, the combination of the formation of the interlayer insulating film, the spin coating of the spin-on-glass film, and the etch-back of the spin-on-glass film is repeated at least twice. In this case, the interlayer insulating film is flattened, so that the interlayer insulating film is further flattened, and a thick film inductor can be formed on the third and fourth wiring layers of the semiconductor device. According to the method of manufacturing a semiconductor device of the ninth aspect, since the processing of the metal thick film is performed by the reactive ion etching method, the fine processing of the thick film inductor can be performed precisely and at high speed.

[Brief description of the drawings]

FIGS. 1 to 6 are views showing a method for manufacturing a double-polysilicon bipolar transistor in a semiconductor device according to a first embodiment. FIG. 1A shows a method of forming a buried layer and an epitaxial layer on a semiconductor substrate. B shows a state in which a thermal oxide film and an LP silicon nitride film are formed thereon, and B shows a state in which a resist film is left in an element formation region and preparations are made for forming element isolation regions on both sides thereof.

FIG. 2 is a view following FIG. 1, wherein A shows a state in which a thermal oxide film for element isolation is formed, and then impurities are ion-implanted to form a lead portion of a buried layer; After forming, a plug is formed in the buried layer by diffusing impurities by heat treatment, and the surface is flattened.

3A shows a state in which B ions are implanted through a resist film to form an element isolation region, and FIG. 3A shows a state in which a silicon oxide film is removed in an npn transistor formation region, following FIG. It shows the state where it was done.

FIG. 4A shows a state in which a polysilicon film serving as a base extraction resistance is formed and BF ²⁺ ions are implanted, and FIG. 4A shows a state in which a silicon oxide film is formed on the polysilicon film; After formation, the silicon oxide film and the polysilicon film are etched to form the intrinsic base region of the npn transistor.

FIG. 5A is a graph of FIG. 5A in which B ions are implanted to form an intrinsic base region, a silicon oxide film is formed and heat treatment is performed, and B ions are diffused from the polysilicon film to form a graft. B shows a state in which the base layer is formed, and B shows a state in which the silicon oxide film is dry-etched to form a sidewall at the emitter opening.

FIG. 6 shows a method of forming a polysilicon film in an emitter formation region;
This shows a state in which As is ion-implanted, heat treatment is performed to diffuse As, an emitter is formed, and a base electrode, a collector electrode, and an emitter electrode are further provided.

7 and 8 are views showing a method for manufacturing a thick-film inductor in the semiconductor device of Example 1, and FIG. 7A shows a first-layer wiring including the electrodes of FIG. B is a state in which a silicon oxide film is formed, an SOG film is spin-coated, the SOG film is etched back, and the surface is flattened. This shows a state in which an opening for a contact electrode for connecting to a wiring in a layer is provided.

FIG. 8A shows a state in which a thick Al film formed on an interlayer insulating film is processed to form a thick film inductor and a second-layer wiring including a contact electrode, following FIG. 7; , B show a state in which a passivation film is formed on the entire surface.

FIGS. 9 to 12 are views showing a method of manufacturing a thick-film inductor in the semiconductor device of Example 2; FIGS.
A in FIG. 6 shows the first layer wiring in FIG. B shows a state in which after forming a silicon oxide film, an SOG film is spin-coated, and the SOG film is etched back to flatten the surface.

10A is a state in which an interlayer insulating film is further formed after forming FIG. 9 and an opening for a contact electrode for connecting a first-layer wiring and a second-layer wiring is provided, and FIG. This shows a state where a second-layer wiring is formed.

FIG. 11A is a view of FIG. 11A, in which an operation of spin-coating a SOG film after forming a silicon oxide film and etching back the SOG film is repeated twice, and an interlayer insulating film of silicon oxide is formed thereon; Is formed, B is the wiring of the second layer and 3
This shows a state in which an opening for a contact electrode with the wiring of the layer is provided.

FIG. 12A shows a state in which an Al thick film is formed and then processed to form a third-layer wiring including a thick-film inductor and a contact electrode, and FIG. This shows a state in which a film has been formed.

FIG. 13 is a plan view of a planar spiral inductor.

14 is a sectional view taken along the line [14]-[14] in FIG.

FIG. 15 is a plan view of a conventional hybrid integrated circuit.

FIG. 16 is a perspective view of an inductor in another conventional semiconductor device.

17A and 17B are diagrams showing an inductor in another conventional semiconductor device, where A is a plan view and B is a cross-sectional view of A taken along the line [B]-[B].

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Embedding layer, 3 ... Epitaxial layer, 7 ... Thermal oxide film for element isolation, 9 ... Impurity diffusion plug, 12 ... Impurity diffusion region for element isolation, 15,
25 ... polysilicon film, 27 ... base, 28 ... collector, 29 ... emitter, 30 ... double polysilicon type bipolar transistor, 32, 34, 41, 4
3, 45 ... silicon oxide film, 33, 42, 44 ... SO
G film, 31... First layer Al wiring, 35... Second layer A
1 wiring, 46... third-layer Al wiring, 36, 47... passivation film, 51, 52.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/06 29/732 F-term (Reference) 5F003 BA12 BB06 BB07 BC08 BE07 BJ18 BP06 BP15 BS06 5F033 HH04 HH08 HH11 HH18 HH19 HH20 HH33 JJ01 JJ04 JJ08 JJ18 JJ33 KK01 KK04 KK08 LL04 MM05 MM13 NN06 NN07 PP06 PP15 QQ08 QQ09 QQ11 QQ13 QQ31 QQ37 QQ48 QQ59 QQ65 QQ73 QQ74 QQ75 QQ11 RR04 RR09 RR04 RR04 RR04 RR04 RR04 RR04 RR04 RR04 RR04 RR04 RR04 BA26 BC01 BC14 DA06 DA07 DA09 DA10 EA12 EA31

Claims (9)

[Claims] 1. A semiconductor device having a bipolar transistor and an inductor, wherein a spiral-shaped thick-film inductor is formed on a flattened interlayer insulating film on the bipolar transistor. . 2. The semiconductor device according to claim 1, wherein said thick-film inductor is formed integrally with a wiring by processing a metal thick film formed on said interlayer insulating film. 3. The method according to claim 1, wherein the material of the metal thick film is aluminum (A).
l), tungsten (W), or molybdenum (Mo)
The semiconductor device according to claim 2, wherein 4. The semiconductor device according to claim 1, wherein the spiral shape of the thick-film inductor is formed by repeating an octagon having four corners cut off. 5. The semiconductor device according to claim 1, wherein said bipolar transistor is a double polysilicon type bipolar transistor or a single polysilicon type bipolar transistor. 6. A method of manufacturing a semiconductor device having a bipolar transistor and an inductor, wherein: a step of flattening an interlayer insulating film formed on the bipolar transistor; and forming a metal thick film on the flattened interlayer insulating film. Forming a thick film inductor into a spiral shape integrally with a wiring by processing the metal thick film. 7. The method according to claim 1, wherein the step of flattening the interlayer insulating film is a step of spin-coating the interlayer insulating film to form a spin-on-glass film, and subsequently etching back the spin-on-glass film. Item 7. A method for manufacturing a semiconductor device according to Item 6. 8. The step of flattening the interlayer insulating film includes forming the interlayer insulating film, spin-coating the spin-on-glass film on the formed interlayer insulating film, and etching back the spin-on-glass film. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the combination is a step of repeating the combination two or more times. 9. The method according to claim 6, wherein the processing of the thick metal film is performed by a reactive ion etching method.