JP2002343037A - Digital signal recording / reproducing system, digital signal recording device, digital signal reproducing device, and digital signal recording / reproducing method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To perform efficient error correction. SOLUTION: A digital signal reproducing apparatus uses a Reed-Solomon code and an arbitrary data sequence as a unit.
The recording data is read from the recording medium on which the recording data with C is recorded. The digital conversion means 5 of the digital signal reproducing apparatus inputs a reproduced signal reproduced from a recording medium and generates a digital reproduced signal. The binary identification means 6 generates a binary identification signal from the digital reproduction signal. The error correcting means 7 uses the Reed-Solomon code to
Error correction of the value identification signal is performed, and a pseudo reproduction signal is generated based on the binary identification signal. By comparing the pseudo reproduction signal with the digital reproduction signal, a candidate having a high possibility of an error in the binary identification signal is identified. Then, a candidate having a high possibility of error is corrected and verified by CRCC, and a correct correction is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing system, a digital signal recording device, a digital signal reproducing device and a digital signal recording / reproducing method, and more particularly to a method for recording data recorded with a predetermined error correction code added thereto. The present invention relates to a digital signal recording / reproducing system, a digital signal recording apparatus, a digital signal reproducing apparatus, and a digital signal recording / reproducing method for performing error correction using the error correction code during reproduction.

[0002]

2. Description of the Related Art Conventionally, in a digital signal recording / reproducing system such as a digital VTR, a recording-side digital signal recording apparatus appropriately blocks recording data and adds an error correction code. FIG. 18 shows a recording format of a general digital VTR. In a general digital VTR, a block of about 100 bytes (1 byte: 8 bits) includes a synchronization byte, an ID byte, and a video data byte, and a parity (N byte) of a Reed-Solomon code is added as an inner code. Have been.

In the digital signal reproducing apparatus on the reproducing side, at the time of reproduction, error correction is performed using the parity of the Reed-Solomon correction code.

[0004]

However, the error correction by the conventional Reed-Solomon code has a problem that it is difficult to correct the error in high-density recording.

[0005] In recording / reproducing digital signals, if the track density or the linear density is increased and high-density recording is promoted, random errors increase, and it becomes difficult to correct only by the inner code using the conventional Reed-Solomon correction code. It is becoming.

[0006] However, it is difficult to improve the error correction capability by increasing the number of added parities. FIG. 19 is a diagram illustrating the error correction capability using the Reed-Solomon code. When the input error rate exceeds 10 ^-4 , the output error rate increases. When the input error rate exceeds 10 ^-2 , correction becomes difficult regardless of the added parity. For example, 80
If a 1-bit error occurs in the bit data, the error rate becomes 10 ^-1 byte, and it cannot be corrected by adding a practical parity.

Therefore, in the conventional digital VTR, a design having a sufficient recording density is required so that an error rate before correction is about 10 ^-5 . The present invention has been made in view of such a point, and an object of the present invention is to provide a digital signal recording / reproducing system, a digital signal reproducing apparatus, and a digital signal recording / reproducing method for performing efficient error correction.

[0008]

According to the present invention, in order to solve the above-mentioned problem, a predetermined error correction code is added to recording data of a digital signal and recorded, and the error correction is performed using the error correction code during reproduction. In the digital signal recording / reproducing system to be performed, the recording data is divided into blocks to generate a recording data block to which the predetermined error correction code is added, and an arbitrary continuous or appropriately interleaved data sequence of the recording data is divided into blocks. CR
A digital signal recording device that has a recording data processing means for arranging a CRCC block to which a CC is added in the recording data block, records the recording data block on a predetermined recording medium, and reproduces a reproduction signal obtained from the recording medium. Digital conversion means for converting to digital to generate a digital reproduction signal, binary identification means for identifying a binary of the digital reproduction signal to generate a binary identification signal, and recording data using the error correction code In addition to performing error correction for each block, detecting an error in the CRCC block, selecting a plurality of candidates having a high possibility of error using the binary identification signal, and performing temporary correction, and performing the temporary correction by the CRCC. Error correction means for verifying and selecting a correct correction, and a digital signal reproducing device having A digital signal recording and reproducing system that, is provided.

In the digital signal recording / reproducing system having such a configuration, the digital signal recording device blocks recording data of the digital signal by the recording data processing means to generate a recording data block to which a predetermined error correction code is added. At the same time, an arbitrary continuous or appropriately interleaved data sequence of the recording data is divided into blocks to generate a CRCC block to which a CRCC is added, and arrange the CRCC blocks in the recording data block. The generated recording data block is recorded on a recording medium. In the digital signal reproducing device, the digital conversion means converts a reproduction signal obtained from the recording data recorded on the recording medium into a digital signal, and generates a digital reproduction signal. The binary identification means generates a binary identification signal by identifying the binary of the digital reproduction signal.
The error correction means performs error correction for each recording data block using an error correction code. With this, CRC
An error in the C block is detected, a plurality of candidates having a high possibility of error are selected using the binary identification signal, and provisional correction is performed.
The RCC verifies whether the provisional correction is correct, and selects the correct correction. In this way, errors in the CRCC block are corrected.

According to another aspect of the present invention, there is provided a digital signal recording apparatus for recording by adding a predetermined error correction code to recording data of a digital signal and recording the recording data by blocking the recording data. A recording data processing unit for generating the added recording data block, and arranging a CRCC block to which an arbitrary continuous or appropriately interleaved data sequence of the recording data is added and a CRCC is added to the recording data block, A digital signal recording device for recording a digital signal on a digital signal recording device for recording the recording data block on a predetermined recording medium.

In the digital signal recording apparatus having such a configuration, the recording data of the digital signal is divided into blocks by the recording data processing means to generate a recording data block to which a predetermined error correction code is added, and an arbitrary part of the recording data. A continuous or appropriately interleaved data sequence is divided into blocks to generate a CRCC block to which a CRCC is added, and the CRCC block is arranged in a recording data block. The generated recording data block is recorded on a recording medium.

According to another aspect of the present invention, there is provided a digital signal reproducing apparatus for performing error correction using the error correction code when reproducing recorded data added with a predetermined error correction code. A reproduction signal obtained from a recording medium in which a recording data block in which a CRCC block to which an arbitrary continuous or appropriately interleaved data sequence of the recording data is added and a CRCC is added in addition to the error correction code is recorded. To digital to generate a digital reproduction signal, a binary identification means for identifying a binary of the digital reproduction signal to generate a binary identification signal, and the recording using the error correction code. While performing error correction for each data block, detecting an error of the CRCC block,
Error correction means for selecting a plurality of candidates having a high possibility of error using the binary identification signal and performing provisional correction, verifying the provisional correction by the CRCC and selecting a correct correction,
And a digital signal reproducing device characterized by having:

In the digital signal reproducing apparatus having such a configuration, the digital conversion means includes, in addition to the predetermined error correction code, an arbitrary continuous or appropriately interleaved data sequence of the recording data as a block and a CRCC added thereto. A reproduction signal obtained from a recording medium on which a recording data block in which blocks are arranged is recorded is converted into a digital signal to generate a digital reproduction signal. The binary identification means receives the digital reproduction signal, identifies the binary, and generates a binary identification signal. The error correction means performs error correction for each recording data block using an error correction code.
At the same time, an error in the CRCC block is detected, a plurality of candidates having a high possibility of error are selected using the binary identification signal, and provisional correction is performed. Select correction. In this way, errors in the CRCC block are corrected.

According to another aspect of the present invention, there is provided a digital signal recording / reproducing method in which a predetermined error correction code is added to recording data of a digital signal for recording, and the error is corrected using the error correction code during reproduction. A digital signal recording apparatus for recording the digital signal, wherein the recording data is divided into blocks to generate a recording data block to which the predetermined error correction code is added, and any continuous or appropriately interleaved data of the recording data. CRC with CRCC added by blocking columns
A step of arranging the C block in the recording data block and recording it on a predetermined recording medium, and a digital signal reproducing apparatus for reproducing the digital signal converts a reproduction signal obtained from the recording medium into a digital signal to reproduce the digital signal. Generating a binary signal of the digital reproduction signal to generate a binary identification signal, performing error correction for each recording data block using the error correction code, and detecting an error of the CRCC block. And selecting a plurality of candidates having a high possibility of error using the binary identification signal, performing a temporary correction, verifying the temporary correction by the CRCC, and selecting a correct correction. And a digital signal recording / reproducing method.

[0015] In the digital signal recording / reproducing method of such a procedure, the recording-side digital signal recording device generates the recording data block to which the recording data is divided into blocks to which a predetermined error correction code is added, and the recording data is recorded. An arbitrary continuous or appropriately interleaved data sequence is divided into blocks, and a CRCC block to which a CRCC is added is arranged in a recording data block and recorded on a predetermined recording medium. The digital signal reproducing device on the reproducing side converts the reproduced signal obtained from the recording medium into a digital signal to generate a digital reproduced signal, identifies the binary of the digital reproduced signal, and generates a binary identification signal. Subsequently, error correction is performed for each recording data block using the error correction code, an error in the CRCC block is detected, and a plurality of candidates having a high possibility of error are selected using the binary identification signal, and provisional correction is performed. Then, it is verified by the CRCC whether the provisional correction is correct, and a correct correction is selected.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. A digital signal recording / reproducing system according to the present invention includes a recording-side digital signal recording device,
And a digital signal reproducing device on the reproducing side.
Here, a case where CRCC is added to a Reed-Solomon code used for a digital VTR will be described.
The CRCC check circuit consists of a shift register and EXOR
Therefore, even if the error correction circuit according to the present invention is added, the speed of conventional decoding processing is not reduced.

First, the digital signal recording device on the recording side will be described. FIG. 1 is a configuration diagram of a digital signal recording device in a digital signal recording and reproducing system according to an embodiment of the present invention.

The digital signal recording device according to the present invention comprises:
Outer code adding means 1 for adding an outer code (hereinafter simply referred to as an outer code) based on Reed-Solomon code, time series converting means 2 for performing time series conversion on recording data to which the outer code is added, inner code based on Reed-Solomon code (Hereinafter simply referred to as inner code) and an inner code C
An RCC addition unit 3 and a synchronization signal addition unit 4 for adding a synchronization signal are provided. The outer code adding means 1 receives the recording data, calculates an outer code for each predetermined block, and adds the outer code to the recording data. The time series conversion means 2 performs time series conversion on the recording data to which the outer code is added,
Output to CRCC adding means 3. By doing so, even if the inner code block becomes NG continuously to some extent due to a burst error due to dropout or the like, it is possible to correct it with the outer code. The processing up to this point is the same as in the related art.

The inner code / CRCC adding means 3 adds the inner code and CRCC to the recording data that has been subjected to the outer code and time-series converted. The CRCC is added in units of a continuous or appropriately interleaved data string.
A block composed of this data string and CRCC is represented by C
Let it be an RCC block. The CRCC block can be arranged in the inner code block of the Reed-Solomon code, or can be arranged to have a product code configuration with the inner code. The configuration of the inner code / CRCC adding means 3 is CRC
The details will be described later, since they differ depending on the embodiment of how the C blocks are arranged.

The synchronizing signal adding means 4 adds a synchronizing signal to a predetermined block to which an outer code, an inner code and a CRCC are added, and generates a recording data block. The recording data block generated in this way is recorded on a predetermined recording medium.

Next, the digital signal reproducing apparatus on the reproducing side will be described. FIG. 2 is a configuration diagram of a digital signal recording device in a digital signal recording and reproducing system according to an embodiment of the present invention.

The digital signal reproducing device converts a reproduction signal obtained from a recording medium to generate a digital reproduction signal, and generates a binary identification signal from the digital reproduction signal generated by the digital conversion means. It has a value discriminating means 6 and an error correcting means 7 for correcting errors of the binary discriminating signal and generating reproduced data.

The digital conversion means 5 inputs the reproduction signal, performs digital conversion, and digitizes the reproduction signal. The digitized digital reproduction signal is output to the binary identification means 6 and the error correction means 7. The binary identification means 6 performs a binary identification of the digital reproduction signal to generate a binary identification signal. The binary identification signal is sent to the error correction unit 7.
Output to The error correction means 7 performs error correction using a Reed-Solomon code added in a predetermined block unit, detects an error in the CRCC block, and selects a candidate having a high possibility of error using a binary identification signal. And corrects errors in the CRCC block by selecting a correct correction using the CRCC.

The operation of the digital signal recording / reproducing system having such a configuration and the digital signal recording / reproducing method will be described. FIG. 3 is a diagram showing a recording data block configuration and operation of the digital signal recording / reproducing system according to one embodiment of the present invention. This is the digital VT
A plurality of CRCC blocks are arranged in an R conventional inner code block. In this example, 4-bit CRCC is added to 128-bit data to form a CRCC block.

An outer code adding means 1 of the digital signal recording apparatus adds an outer code to the recording data,
To perform time series conversion. Subsequently, the inner code / CRCC adding means 3 adds an inner code to the recording data to which the outer code has been added and the time series conversion has been performed, and also adds a CRCC for each 128-bit data as a CRCC block. Further, a synchronization signal is added by the synchronization signal adding means 4 to generate a recording data block. The recording data block generated in this manner is recorded on a predetermined recording medium. In the digital signal reproducing device, the digital conversion means 5 generates a digital reproduced signal from the reproduced signal obtained from the recording medium. The binary identification means 6 generates a binary identification signal from the digital reproduction signal. Error correction means 7
When an error in the CRCC block is detected, a plurality of candidates having a high possibility of error are selected, and provisional correction is performed for each candidate. The result of the provisional correction is verified by CRCC, and CR
The provisional correction determined to be correct by the CC is selected as the correct correction. Further, correction is performed using the conventional inner code and outer code.

The error correction using the CRCC will be described. In general, in CRCC, an error can be detected but its position cannot be specified. In the present invention, the error position is estimated by selecting candidates for the possibility of error using the information of the binary identification, and they are corrected, verified by CRCC, and selected correctly corrected, so that the error is corrected. Make corrections. Detection of a bit having a high possibility of error is performed by, for example, 2 bits.
A pseudo reproduction signal is generated from the value identification result, the difference between the pseudo reproduction signal and the original reproduction signal is calculated, and the probability that a bit having a large absolute value is incorrect is high.

In FIG. 3, the bit A, the bit B and the bit C of the data of the binary
Has been determined to have a high probability of error. The error correction means 7 prepares a correction pattern for provisional correction of bits A, B, and C, calculates CRCC for each pattern, determines whether the provisional correction is correct, and outputs a correct correction result. Thus, the error correction of this CRCC block is completed. In this example, only three bits (A, B, C) having a high error probability are selected, but if more bits having a high error probability are selected, correction can be performed for more errors. Becomes possible. Further, even if the number of erroneous bits is small, the probability that an erroneous bit exists in the erroneous bits increases, so that the probability of correction can be increased.

Since the CRCC check circuit includes only a shift register and EXOR, these circuits can be provided in parallel, and blocks corrected by the above error candidates can be simultaneously verified. There is no bottleneck in decoding speed. It is also effective to interleave and configure CRCC blocks in order to cope with continuous errors that are likely to occur in maximum likelihood decoding.

Next, the specific structure of the present invention will be described with reference to some embodiments. First, as Embodiment 1, a configuration in which a plurality of CRCC blocks are arranged in an inner code block will be described.

First, a recording digital signal recording apparatus will be described. FIG. 4 shows a first embodiment of a digital signal recording apparatus according to the present invention.
It is a block diagram of CC addition means.

The inner code / CRCC adding means 3-1 of the first digital signal recording apparatus according to the present invention comprises: an inner code addition unit 31 for adding an inner code to input recording data; And a CRCC addition 32 for adding a CRCC to the.

The inner code addition 31 calculates the inner code of the input recording data and adds it to the recording data. Inner code / CR
Since the recording data that has been subjected to the time-series conversion with the outer code added thereto is input to the CC adding unit 3-1, the inner code and the outer code have a product code configuration. The CRCC addition unit 32 adds the CRCC by blocking the recording data, calculates the CRC of the inner code as necessary, and generates a CRCC corresponding to the inner code.
Add CC.

The operation of the inner code / CRCC adding means 3-1 having such a configuration will be described. FIG. 5 is a configuration diagram of recording data generated in the digital signal recording device according to the first embodiment of the present invention.

The recording data to which the outer code has been added and which has been subjected to the time series conversion are input to the inner code addition 31, and the inner code is added.
At this time, the inner code and the outer code have a product code configuration. CR
The CC addition 32 arranges a plurality of CRCCs in the inner code block for which the inner code is calculated, calculates and adds each CRCC, and calculates and adds the CRCC of the inner code. Here, a plurality of CRCC blocks are arranged in the inner code block for which the inner code is calculated. However, in actual application, it is desirable that the CRCC blocks are appropriately interleaved.

Next, the digital signal reproducing apparatus on the reproducing side will be described. FIG. 6 is a configuration diagram of the error correction means according to the first embodiment in the digital signal reproducing apparatus according to the present invention.

The error correction means 7-1 of the first digital signal reproducing apparatus according to the present invention performs a CR operation on the binary identification signal.
CRCC correcting means 71 for performing correction using CC, CR
Inner code correcting means 72 for performing correction using the inner code on the binary identification signal corrected by the CC, time series conversion means 73 for converting the binary identification signal corrected for the inner code into a time series of the outer code, And an outer code correcting means 74 for performing correction using an outer code and outputting reproduced data.

The CRCC correction means 71 calculates a CRCC for each CRCC block and determines whether an error has occurred in the CRCC block. If an error has occurred, a pseudo reproduction signal is generated from the binary identification signal, and a difference from the digital reproduction signal is calculated to generate an error signal. Subsequently, 2 corresponding to the absolute value of the error signal in descending order.
A plurality of bits of the value identification signal are selected as candidates having a high possibility of error. The number of candidates to be selected is arbitrary, but at least two or more candidates are selected. Subsequently, the bit data of a candidate having a high possibility of error is inverted singly or in combination and subjected to provisional correction.
Check C to verify whether the tentative correction is correct. As a result of the verification, the CRCC selects a correct temporary correction pattern as a correct correction. The selected candidate is corrected by performing a single bit or a combination.

The inner code correcting means 72 corrects the binary identification signal corrected by the CRCC using the inner code. The time series conversion means 73 is a process for converting the time series of the input signal so that the code assigned before the time series conversion and the code assigned after the time series conversion have a product code configuration. In the case of the error correction means 7-1 shown in FIG. 6, the time series of the recording data converted by the inner code correction means 72 is converted into the outer code sequence of the outer code, and output to the outer code correction means 74. The outer code correcting means 74 performs correction using the outer code and outputs reproduced data. Inner code correction means 72, time series conversion means 73, and outer code correction means 74
Is the same as the conventional processing, so the details are omitted.

As described above, in the present invention, a pseudo reproduction signal is formed from the binary identification signal, an error signal is generated by taking a difference from the original reproduction signal, and the binary identification signal is corrected based on the information of the error signal. Then, it is verified by the CRCC whether or not it is correct, and a correct correction result is obtained.

Next, the details of the CRCC correction means 71 will be described together with the circuits constituting the digital conversion means 5 and the binary identification means 6. FIG. 7 is a block diagram of a main part of the digital signal reproducing apparatus according to the present invention.

The main parts of the digital signal reproducing apparatus according to the present invention include a Nyquist equalizer 51, a clock generator 52 and an analog / digital (hereinafter referred to as A / D) converter 53 constituting the digital conversion means 5. A binary discriminator 61 constituting the binary discriminating means 6, and a CRCC correcting means 71
711, an error signal detector 712, a synchronization detector 713, and an error position flag generator 71
4, a delay circuit 715 and a correction circuit 716.

In the digital conversion means 5, the reproduced signal is Nyquist-equalized by the Nyquist equalizer 51, and the Nyquist equalized signal is output to the clock generator 52 and the A / D converter 53. The clock generator 52 receives the Nyquist-equalized reproduction signal, generates a clock using a 1/0 edge generated by a comparator or the like, and generates A
Output to the / D converter 53. The A / D converter 53 A / D converts the Nyquist equalized signal with this clock and outputs the signal to the binary discriminator 61.

In the binary classifier 61, PRML (Partial
A binary identification represented by a Response Maximum Likelihood is performed to generate a binary identification signal. Up to this point, the configuration is the same as the conventional configuration.

Each part of the CRCC correction means 71 will be described. The pseudo reproduction signal generator 711 is a pseudo reproduction signal generating unit, and generates a pseudo reproduction signal based on the binary identification signal. The pseudo reproduction signal is simply a signal obtained by converting the binary identification signal into a dynamic range of the digital reproduction signal in order to compare the binary identification signal with the digital reproduction signal. For example, the dynamic range of the Nyquist equalized signal converted to digital by the A / D converter 53 is +
If it is from 31 to −31, 1 and 0 identified by the binary identifier 61 are generated corresponding to +31 and −31, respectively.

The error signal detector 712 is an error signal generating means that calculates a difference between the digital reproduction signal and the pseudo reproduction signal and outputs the difference as an error signal. The error signal is
The larger the absolute value, the higher the probability that the binary identification signal corresponding to the error signal is erroneous.

In practice, the digital reproduction signal and the pseudo reproduction signal do not need to be Nyquist equalized signals. For example, even if the digital reproduced signal and the pseudo reproduced signal are PR1 and PR2 signals or a combination of the PR1 signal and the Nyquist equalized signal. Good. PR1, PR2
The signal is obtained from the Nyquist equalized signal (NYQ) by the following calculation.

[0047]

## EQU00001 ## PR1 [i] = NYQ [i] + NYQ [i-1] (1)

[0048]

## EQU00002 ## PR2 [i] = PR1 [i] + PR1 [i-1] (2) In such an equalization method, high-frequency noise is suppressed, and more reliability is obtained. High results can be obtained.

The synchronization detector 713 is a detector for synchronizing the binary identification signal generated by the binary identification unit 61 with the error signal. The error position flag generator 714 is an error position detecting means, compares the absolute values of the error signals in the CRCC block, and determines the largest error signal and the next largest error signal as candidates having a high possibility of error. The bit position of the corresponding binary identification signal is detected. When a binary identification signal corresponding to the position is input to the correction circuit 716, an error position flag is set, and the error position is transmitted to the correction circuit 716. The details of the error position flag generator 714 will be described later.

The delay circuit 715 delays the binary identification signal in order to synchronize the flag set by the error position flag generator 714 with the binary identification signal. Specifically, since the error position flag is detected with a delay of one CRCC block, the corrected binary identification signal is delayed by the same amount.
The correction circuit 716 is a correction means, and performs tentative correction by inverting bit data of a candidate having a high possibility of error, for which a flag has been set by the error position flag generator 714, alone or in combination, and performing a tentative correction, and verifying this by CRCC. I do. As a result of the verification, a temporary correction determined to be correct is selected. Correction circuit 7
Details of 16 will be described later.

The operation of the digital signal reproducing apparatus having such a configuration will be described. The Nyquist equalizer 51 of the digital conversion means 5 receives the reproduced signal, equalizes it using a Nyquist equalization standard, and generates a Nyquist equalized signal. The clock generator 52 generates a clock based on the Nyquist equalization signal. The A / D converter 53 uses this clock to A / D-convert the Nyquist equalized signal to generate a digital reproduction signal. The digital reproduction signal is subjected to binary identification by the binary identification unit 61 to generate a binary identification signal. In the CRCC correcting means 71, the pseudo reproduction signal generator 711 generates a pseudo reproduction signal obtained by converting the binary identification signal into a dynamic range of the digital reproduction signal. Error signal detector 712 calculates the difference between the digital reproduction signal and the pseudo reproduction signal, and outputs the difference as an error signal. The error position flag generator 714 compares the absolute values of the error signals, selects the largest one and the next largest one as candidates having a high possibility of error, detects the bit position of the corresponding binary identification signal, and Generate a position flag. The correction circuit 716 receives the binary identification signal synchronized with the error position flag, and temporarily corrects a candidate having a high possibility of error. The tentative correction is verified using CRCC and the correct correction is selected.

Conventionally, when the error cannot be corrected by the inner code,
An uncorrectable flag is set in all of the inner code blocks, and erasure correction is performed by the outer code using this flag. However, in the digital signal reproducing apparatus described above, since the correction is performed in the CRCC block smaller than the inner code, even if an error is detected by the inner code, the flag is not set to all the inner code blocks,
The flag can be set by ANDing with the uncorrectable flag of the CRCC block included in the inner code. Therefore, in order to obtain an uncorrectable portion (the number of flags for which uncorrectable is set), it is possible to increase the correction probability in the outer code.

In the above description, the correction candidate is set to the CRC
Although two C blocks are used, the present invention is not limited to this. The more correction candidates are selected and the number of correction circuits thereby increases, the higher the probability of correction can be made. Although the CRC is added after the inner code is added at the time of recording by the digital signal recording device, a procedure of adding the inner stream code after the CRCC may be used. In this case, the error correction procedure of the digital signal reproducing device changes accordingly.

Next, the details of the error position flag generator 714 will be described. FIG. 8 is a block diagram of an error position flag generator according to one embodiment of the present invention. The error position flag generator compares the supplied error signal, detects MAXA having the largest absolute value of the error signal and MAXB having the next largest absolute value, and sets the A flag and B indicating the position of the binary identification data corresponding thereto. Generate a flag.

An error position flag generator 714 according to the present invention.
Is a MAXA register 7141a for holding the largest error signal in the CRCC block, a MAXB register 7141b for holding the next largest error signal, and a comparator A for comparing the input error signal with the MAXA register 7141a.
The comparator B (7143b) that compares the error signal input as (7143a) with the MAXB register 7141b and MA
XA register 7141a and MAXB register 7141b
C (7143c), comparators A, B,
MAX signal memory control circuit 7 for controlling information stored in a register according to an output signal from C
144, an address counter 7145 that receives a synchronization signal and counts a count indicating an address; Corresponding MAXB address register 7142b, MAXA address register 7142a determined for each CRCC block
A (7146a) holding the value of the register B and the register B holding the value of the MAXB address register 7142b
(7146b), and sets the A flag when the address counter 7145 matches the register A (7146a). The B flag is set when the address A match detection circuit 7147a and the address counter 7145 match the register B (7146b). Address B match detection circuit 7
147b.

The error position flag generator 7 having such a configuration is described.
The operation of No. 14 will be described. First, the MAXA register 7141a and the MAXB register 7141b
It is reset at the head of the block (actually one clock before) and becomes 0. Next, when an error signal larger than 0 is input to the two comparators A (7143a) and B (7143b), both become H. Comparator C (7143
c) is L because both are 0 in this case. Based on these signals, the MAX signal memory control circuit 7144 causes the MAXA register 7141a to load the value. Comparator A (7143a), Comparator B
FIG. 9 shows the operation of the MAX signal memory control circuit 7144 according to the values of the (7143b) and the comparator (7143c). The error signal is the MAXA register 71
When the output of the comparator A (7143a) and the output of the comparator B (7143b) are both L, the values of the registers are held. The error signal is larger than MAXA register 7141a and smaller than MAXB register 7141b, that is, the output of comparator A (7143a) is H
MAXA when the output of the comparator B (7143b) is L
The value of the error signal is loaded into the register 7141a. Similarly, the error signal is smaller than the MAXA register 7141a and larger than the MAXB register 7141b, that is, the output of the comparator A (7143a) is L and the comparator B (714
When the output of 3b) is H, the MAXB register 7141b
Is loaded with the value of the error signal. The error signal is larger than the data held in the MAXA register 7141a and the MAXB register 7141b, that is, the comparator A (714
3a) When both the output of the comparator B (7143b) is H, the comparator C (7143c) is referred to, and the MAXA register 7141a is smaller than the MAXB register 7141b, that is, the output of the comparator C (7143c) is L , MAXA register 7141a, MA in the opposite case
The value of the error signal is loaded into the XB register 7141b. By performing the recording control of the register in accordance with such conditions, the MAXA register 7141a holds the largest error signal, and the MAXB register 7141b holds the next largest error signal. Also, the MAXA register 71
When a value is loaded into the 41A and the MAXB register 7141b, an address is loaded into the MAXA address register 7142a and the MAXB address register 7142b.

Returning to FIG. The counter indicating the address in the CRCC block is an address counter 71
45. The counter is configured to return to 0 for each CRCC block, and the address (position)
According to the MAX signal memory control circuit 7144, the MAXA register 7141a is loaded with an error signal, and the MAXB register 7141b is loaded with an error signal according to the MAX signal memory control circuit 7144. Is loaded.

By repeating the above procedure for each error signal input, at the end of the CRCC block, the MAXA register 7141a stores the maximum error signal of the block, MAX
The address remains in the A address register 7142a. Similarly, the next largest error signal of the block remains in the MAXB register 7141b, and the address remains in the MAXB address register 7142b. In addition,
This address is moved to the register A (7146a) and the register B (7146b) of the next stage at the end of the CRCC block. As described above, the register A (7146a) and the register B (7146b) have the CRCC of one block before.
The address of a candidate having a high possibility of an error detected in the block is held. Address A match detection circuit 7
147a outputs an A flag for error correction when the address transferred to the register A (7146a) matches the address counter 7145. Similarly, the address B match detection circuit 7147b outputs a B flag when the address transferred to the register B (7146b) matches the address counter 7145. As can be seen from the operation, the A flag and the B flag are output one block later.

Next, the details of the correction circuit 716 will be described. FIG. 10 is a block diagram of a correction circuit according to an embodiment of the present invention. The correction circuit 716 according to the present invention
An OR circuit 1 for performing a logical sum of the A flag and the B flag, a correction circuit A (7161a) for performing correction according to the A flag,
A correction circuit B (7161) that performs correction according to the B flag
b) and a correction circuit A + B (7161c) for performing correction in accordance with both the A and B flags, a CRCC check 7162a for performing a CRCC check of the binary identification signal, and a correction circuit A
A CRCC check 7162b for performing a CRCC check of the correction signal of (7161a) and a correction circuit B (7161)
b) a CRCC check 7162c for performing a CRCC check of the correction signal, a CRCC check 7162d for performing a CRCC check of the correction signal of the correction circuit A + B (7161c), and CRCC checks 7162a and 7162.
b, 7162c, and 7162d, a delay circuit 71 for delaying the input signal and matching the phase with the result of the CRCC check.
63a, 7163b, 7163c, 7163d, and a selection circuit 7164 for selecting an output according to each CRCC check result.

The correction circuit A (7161a) corrects the data with the A flag set, that is, the bit data of the candidate having the highest possibility of error, by itself, and performs a CRCC check 7162b and a delay circuit 7163.
Output to b. The correction circuit B (7161b) corrects the data in which the B flag is set, that is, the bit data of a candidate having the next highest possibility of error, by itself, and performs a CRCC check 7162c and a delay circuit 7163.
Output to c. The correction circuit A + B (7161c) has A,
The data for which both the B flags are set are corrected by inverting the combined data and output to the CRCC check 7162d and the delay circuit 7163d.

CRCC check 7162a, 7162
b, 7162c, and 7162d calculate the CRCC of each input signal and output the result of determining whether or not the input signal has an error to the selection circuit 7164.

Delay circuits 7163a, 7163b, 716
3c and 7163d delay the input signal and
Check 7162a, 7162b, 7162c, 716
The phase with the determination result of 2d is matched and output to the selection circuit 7164.

The selection circuit 7164 performs the CRCC check 7
Based on the determination results of 162a, 7162b, 7162c, and 7162d, a correction signal having a correct correction result is selected and output. Here, the selection circuit 7164 includes a delay circuit 71
If a binary identification signal without correction has been input via 63a and there is no error, this signal is selected. Also,
Even if the error could not be corrected, select this signal,
Set the error detection flag.

In the correction circuit 716 having such a configuration, 2
The data whose values have been identified are stored in three correction circuits A (7161).
a), correction circuit B (7161b) and correction circuit A + B
(7161c) and outputs their corrected outputs to the CRC.
Verification is performed by C checks 7162b, 7162c, and 7162d, and a correct correction result is selected and output by a selection circuit 7164.

In the above description, the number of correction candidates is two in the CRCC block, and therefore, the correction circuits are A, B, and A + B.
However, if the number of correction candidates increases, the number of correction circuits increases accordingly.

Next, as a second embodiment, the inner code block and C
A configuration in which the RCC block and the RCC block are arranged in a product code configuration will be described. This configuration is different from the first embodiment.
The correction efficiency can be made higher.

First, a recording digital signal recording apparatus will be described. FIG. 11 shows a digital signal recording apparatus according to a second embodiment of the present invention,
It is a block diagram of an RCC addition means. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

The inner code / CRCC adding means 3-2 of the second digital signal recording apparatus according to the present invention comprises a CRCC adding unit 32 for adding a CRCC code to input recording data;
A time-series conversion unit 33 for performing time-series conversion of the recording data to which the CRCC code is added into an inner code sequence, and an inner code addition unit 31 for adding an inner code to the time-series converted recording data to which the CRCC is added. You.

To the inner code / CRCC adding means 3-2, record data which has been subjected to time series conversion with an outer code added is input. The CRCC addition 32 blocks recording data and adds a CRCC. In the subsequent time series conversion 33, the CRC
A process of converting the recording data of the C sequence into an inner code sequence is performed, and an inner code is added by an inner code addition 31.

FIG. 12 is a configuration diagram of recording data generated in the second embodiment in the digital signal recording apparatus according to the present invention. As shown in the figure, in the second embodiment, the inner code block and the CRCC block have a product code configuration. In addition, consecutive 8
Bits (1 byte) are included in the same CRCC block. With such a configuration, even if it cannot be corrected by the CRCC block, it is only a 1-byte flag when viewed with the inner code, so that erasure correction with the inner code is efficient. That is, in general, the correction by the inner code can correct 4 bytes with the parity of 8 bytes, but by setting the uncorrectable flag in the CRCC block, the position of the error can be known. It becomes possible. By making the outer code sequence diagonal as shown, that is, by making it a product code configuration for the CRCC block and the inner code block,
Even if the uncorrectable flag is set in the CRCC block and the inner code block, the erasure correction by the outer code is effectively performed because each flag is only a 1-byte flag when viewed from the outer code sequence.

The configuration of a reproducing-side digital signal reproducing apparatus corresponding to such recorded data will be described. FIG.
FIG. 3 is a configuration diagram of an error correction unit according to a second embodiment of the digital signal reproducing apparatus according to the present invention. The same elements as those in FIG. Here, the time series conversion circuits 73-1, 73-2, 73-3
Performs the same processing as the time series conversion means 73.

The error correction means 7-2 according to the present invention comprises: an inner code correction circuit 72-1 for inputting the binary identification signal generated by the binary identification circuit 61-2 and correcting the inner code; Time series conversion circuits 73-1, 73-2, 7 for converting series
3-3 and a CRCC correction circuit 71 for performing CRCC correction
-1 and an outer code correction circuit 74-1 for performing outer code correction
And

The operation of the error correcting means 7-2 having such a configuration will be described. The binary identification circuit 61-2 identifies the binary of the input digital reproduction signal to generate a binary identification signal, outputs the binary identification signal to the inner code correction circuit 72, and converts the input digital reproduction signal as it is into a time-series conversion circuit. 73
-2. As shown in FIG. 7, the digital reproduction signal can be taken into the error correction means 7-2 without passing through the binary identification circuit 61-2. The inner code correction circuit 72 receives the binary identification signal and performs correction using the inner code. The correction signal is converted into a CRCC sequence by the time series conversion circuit 73-1 and supplied to the CRCC correction circuit 71. Similarly, the digital reproduction signal output from the binary identification circuit 61-2 is converted into a CRCC sequence by the time series conversion circuit 73-2, and supplied to the CRCC correction circuit 71. The CRCC correction circuit 71 inputs the correction signal corrected by the inner code and the original digital reproduction signal, detects an error signal, selects a candidate having a high possibility of error, provisionally corrects the candidate, and verifies the candidate using the CRCC. And select the correct correction result. The data corrected by the CRCC correction circuit 71 is converted into an outer code sequence by the next time series conversion circuit 73-3, and the outer code correction circuit 74 corrects the data using an outer code.

Although not shown here, in an actual application, data corrected by the CRCC may be subjected to time series conversion again to perform inner code correction. An error processing procedure in this case will be described.

First, the conventional correction using the inner code is performed, and an uncorrectable flag is set for all the inner code blocks that cannot be corrected (when the number of errors exceeds the capability of the correction code).

Next, the CRCC block is corrected.
The method of this correction is as described above. Here, since it is known that the data of the inner code block in which the uncorrectable flag is not set by the inner code is not erroneous, if it is excluded from the correction candidates, the data becomes the correction target and the number of bits can be reduced. , It is possible to increase the probability of correction. For example, the error signal of the correct inner code block is set to 0. Also, the flags of all the blocks that have been corrected are cleared.

Subsequently, the processing from the correction of the inner code block is repeated again. Since the position of the error is known by setting the uncorrectable flag by the correction by the CRCC, when the correction by the inner code is performed again, the erasure correction is performed using this flag. It is also effective.

In the above description, in the digital signal recording apparatus, the time series conversion is performed after the CRCC is added and the inner code is added, but the time series conversion is performed after the inner code is added and the CRCC is added. You can also. The configuration on the reproducing side in this case will be described. FIG. 14 is a block diagram showing a digital signal reproducing apparatus according to a second embodiment of the present invention, which is a modification of the error correcting means according to the second embodiment. The same components as those in FIG. 13 are denoted by the same reference numerals, and description thereof is omitted.

In the error correction means 7-3, first, the CRCC
The correction is performed by the correction circuit 71, then converted into an inner code sequence by the time series conversion circuit 73-1, and the inner code correction circuit 72 performs correction using the inner code. C
The RCC correction circuit 71 has two bits from the binary identification circuit 61-2.
Since the value discrimination signal and the digital reproduction signal before the binary discrimination are input, the correction by CRCC is performed using both signals. Thereafter, the time series conversion circuit 73-1 converts the data into an inner code sequence, and performs correction using the inner code. Subsequent processing is the same as that of the error correction unit 7-2. Similarly to the above description, the inner code correction circuit 72 can perform erasure correction using the non-correctable flag set by the CRCC correction circuit 71. Further, after the correction by the inner code, the processing from the correction using the CRCC can be repeated again.

Next, as a third embodiment, a configuration in which CRCC blocks are arranged so as to have a product code configuration will be described. First, a recording digital signal recording apparatus will be described. FIG. 15 shows an inner code / CRCC according to a third embodiment of the digital signal recording apparatus according to the present invention.
It is a block diagram of an addition means. 4 and 11 are denoted by the same reference numerals, and description thereof is omitted. Here, the CRCC additions 32-1 and 32-2 perform the same processing as the CRCC addition 32, and the time series conversions 33-1 and 33-2 perform the same processing as the time series conversion 33.

The inner code / CRCC addition 3-3 of the third digital signal recording apparatus according to the present invention includes a CRCC addition 32-1 for adding a CRCC code to input recording data,
A time series conversion 33-1 for performing time series conversion on the recording data to which the CRCC code is added, a CRCC addition 32-3 for adding a CRCC as a product code, and a time series conversion 33-3 for performing a time series conversion on an inner code sequence. 2 and an inner code addition 31 for adding an inner code. CRCC addition 32
-1, 32-3 perform the same processing as CRCC addition 32.

To the inner code / CRCC adding means 3-3, record data to which an outer code has been added and subjected to time series conversion is input. The CRCC addition 32-1 adds the CRCC by blocking the recording data. In the subsequent time-series conversion 33-1, a CRCC sequence by the CRCC addition 32-1 (hereinafter, referred to as CRCC sequence 32-1).
The recording data of the CRCC sequence 2 is converted to a CRCC sequence (hereinafter, CRCC sequence 1) by the following CRCC addition 32-2.
Is performed, and CRCC is added. Subsequently, CRCC sequence 1 is performed by time series conversion 33-2.
Is converted to an inner code sequence, and an inner code is added by an inner code addition 31.

FIG. 16 is a configuration diagram of recording data generated in the third embodiment in the digital signal recording apparatus according to the present invention. As shown in the figure, in the third embodiment, CRCC sequence 2 and CRCC sequence 1 further include
It has a product code configuration. Therefore, the correction can be performed more effectively.

The configuration of a digital signal reproducing apparatus on the reproducing side corresponding to such recorded data will be described. FIG.
FIG. 7 is a configuration diagram of an error correction unit according to a third embodiment of the digital signal reproducing apparatus according to the present invention. 6 and 13 are denoted by the same reference numerals, and description thereof will be omitted. Here, the CRCC correction circuits 71-1 and 71-2 are combined with the CRCC correction circuit 71 and the time-series conversions 73-1 and 73-.
2, 73-3, 73-4, and 73-5 perform the same processing as the time series conversion unit 73.

The error correction means 7-4 according to the present invention includes an inner code correction circuit 72 for inputting the binary identification signal generated by the binary identification circuit 61-2 and correcting the inner code, and a time series of the input signal. Time series conversion circuits 73-1, 73-2, 73-
3, 73-4, 73-5 and CR for CRCC correction
It comprises CC correction circuits 71-1 and 71-2 and an outer code correction circuit 74 for performing outer code correction.

The operation of the error correction means 7-4 having such a configuration will be described. The binary identification circuit 61-2 identifies the binary of the input digital reproduction signal to generate a binary identification signal, outputs the binary identification signal to the inner code correction circuit 72, and converts the input digital reproduction signal as it is into a time-series conversion circuit. 73
-2. As shown in FIG. 7, the digital reproduction signal does not pass through the binary discriminator 61 and is output from the error correction means 7-
4 can also be taken. Inner code correction circuit 72
Inputs a binary identification signal and performs correction using an inner code. The correction signal is subjected to a CRC by the time series conversion circuit 73-1.
It is converted to C sequence 1 and supplied to CRCC correction circuit 71-1. Similarly, the digital reproduction signal output from the binary identification circuit 61-2 is converted into the CRCC sequence 1 by the time series conversion circuit 73-2, and the CRCC correction circuit 71-1
Supplied to The CRCC correction circuit 71-1 receives the inner code correction signal corrected by the inner code and the original digital reproduction signal, detects an error signal, selects a candidate having a high possibility of error, and temporarily corrects the CRCC. To verify and select the correct correction result. The correction signal generated in this way is output to the time series conversion circuit 73-3. Also,
The CRCC correction circuit 71-1 outputs, to the time series conversion circuit 73-4, a signal obtained by performing a time series conversion on the digital reproduction signal input from the time series conversion circuit 73-2, together with the corrected signal. The time-series conversion circuit 73-3 uses C
A time-series conversion for converting the corrected signal corrected by the RCC from the CRCC sequence 1 to the CRCC sequence 2 is performed.
Output to the CC correction circuit 71-2. Time series conversion circuit 73
-4 performs time series conversion of converting the digital reproduction signal converted to CRCC sequence 1 into CRCC sequence 2,
Output to the RCC correction circuit 71-2. The CRCC correction circuit 71-2 is supplied with a correction signal corrected by the inner code and CRCC, and a digital reproduction signal that has been time-series converted in the same manner as the correction signal. Similar to the CRCC correction circuit 71-1, the CRCC correction circuit 71-2 detects an error signal from the correction signal and the digital reproduction signal, performs a temporary correction, verifies the error signal with the CRCC, and selects a correct correction. The corrected data is converted into an outer code sequence by the next time series conversion circuit 73-5, and the outer code correction circuit 74 corrects the data using an outer code.

As described above, since the CRCC has a further product code configuration, more efficient correction is possible.
Also here, as in the second embodiment, the CRCC correction circuit 7
It is effective to perform the inner code correction again after the correction is performed according to 1-2. The reproduction procedure at this time will be described.

First, the correction by the inner code is performed as in the past, and if the error cannot be corrected (when the number of errors is large and exceeds the capability of the correction code), an uncorrectable flag is set to all the data of the inner code block.

Subsequently, the data is corrected by the CRCC correction circuit 71-1 and an uncorrectable flag is set to data corresponding to the CRCC block that could not be corrected. Next, correction is performed by the CRCC correction circuit 71-2. Here, the data in which the uncorrectable flag is not set is excluded from the correction candidates as in the case of the second embodiment.

Next, if necessary, the inner code is corrected again. At this time, it is also effective to perform erasure correction using an uncorrectable flag in the CRCC block in correcting the inner code block.

Subsequently, if necessary, the procedure of repeating the correction by CRCC is repeated. As described above, according to the present invention, it is possible to effectively correct even a signal having a low random error rate that cannot be corrected only by the conventional inner code based on the Reed-Solomon code. As a result, efficient error correction becomes possible with less redundancy,
It is possible to increase the density of digital VTRs, optical disks, HDDs, and the like. Further, with the conventional code configuration, even a signal having a low S / N that cannot be corrected can be corrected, and a digital signal recording / reproducing apparatus having robustness can be realized.

[0092]

As described above, in the digital signal recording / reproducing system according to the present invention, the digital signal recording apparatus adds a predetermined error correction code to each recording data block, and blocks an appropriate data string to perform CRC.
A CRCC block to which C is added is generated and arranged in a recording data block. The digital signal reproducing device generates a binary identification signal from the reproduced signal. The binary identification signal is subjected to error correction using an error correction code for each recording data block, and is subjected to error correction for each CRCC block in which an error is detected.

As described above, since error correction is performed using CRCC in addition to error correction using error correction codes, efficient error correction can be performed with a small degree of redundancy.
As a result, the density of digital signal recording can be increased.

Further, in the digital signal recording apparatus of the present invention, a predetermined error correction code is added to each recording data block, and an appropriate data string is divided into blocks to perform CRC.
A CRCC block to which C is added is generated and arranged in a recording data block. The recording data block is recorded on a recording medium.

As described above, in addition to the error correction code, CR
The addition of the CC enables effective error correction on the reproducing side. As a result, the density of digital signal recording can be increased.

In the digital signal reproducing apparatus according to the present invention, a binary identification signal is generated from a reproduced signal of recording data to which CRCC is added together with an error correction code. Error correction using an error correction code and error correction using a CRCC are performed.

As described above, since error correction is performed using CRCC in addition to error correction using error correction codes, efficient error correction can be performed with a small degree of redundancy.
As a result, the density of digital signal recording can be increased.

In the digital signal recording / reproducing method of the present invention, the recording-side digital signal recording apparatus includes an error correction code in block units and a C / C unit in arbitrary data strings.
The recording data to which the RCC is added is recorded on a recording medium. The digital signal reproducing device on the reproducing side generates a binary identification signal of the reproduced signal obtained from the recording medium. Error correction is performed using the error correction code, and error correction is performed using the CRCC.

As described above, CRCC is added in addition to the error correction code on the recording side, and CCC is added together with the error correction code on the reproduction side.
Since correction is performed using the RCC, efficient error correction can be performed with a small degree of redundancy. As a result, the density of digital signal recording can be increased.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital signal recording device in a digital signal recording / reproducing system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a digital signal reproducing device in a digital signal recording / reproducing system according to an embodiment of the present invention.

FIG. 3 is a diagram showing a recording data block configuration and operation of a digital signal recording and reproducing system according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of an inner code / CRCC adding unit according to the first embodiment in the digital signal recording device according to the present invention.

FIG. 5 is a configuration diagram of recording data generated in the digital signal recording device according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of an error correction unit according to the first embodiment in the digital signal reproduction device according to the present invention.

FIG. 7 is a block diagram of a main part in the digital signal reproducing apparatus according to the present invention.

FIG. 8 is a block diagram of an error position flag generator according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating an operation of a MAX signal memory control circuit according to an embodiment of the present invention.

FIG. 10 is a block diagram of a correction circuit according to an embodiment of the present invention.

FIG. 11 is a configuration diagram of an inner code / CRCC adding unit according to a second embodiment of the digital signal recording apparatus according to the present invention.

FIG. 12 is a configuration diagram of recording data generated in a digital signal recording device according to a second embodiment of the present invention.

FIG. 13 is a configuration diagram of an error correction unit according to a second embodiment of the digital signal reproducing apparatus according to the present invention.

FIG. 14 is a configuration diagram of a modified example of the error correction unit according to the second embodiment in the digital signal reproducing apparatus according to the present invention.

FIG. 15 is a configuration diagram of an inner code / CRCC adding means according to a third embodiment of the digital signal recording apparatus according to the present invention.

FIG. 16 is a configuration diagram of recording data generated in a digital signal recording device according to a third embodiment of the present invention.

FIG. 17 is a configuration diagram of an error correction unit according to a third embodiment of the digital signal reproduction device according to the present invention.

FIG. 18 shows a recording format of a general digital VTR.

FIG. 19 is a diagram illustrating an error correction capability using a Reed-Solomon correction code.

[Explanation of symbols]

1 ... Outer code addition means, 2 ... Time series conversion means, 3 ... Inner code / CRCC addition means, 4 ... Synchronization signal addition means, 5 ...
..Dizil conversion means, 6 ... binary identification means, 7 ... error correction means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 G11B 20/18 572G 20/10 301 20/10 301Z 20/12 20/12 103 103 H03M 13 / 29 H03M 13/29 H04N 5/92 H04N 5/92 H 7/24 7/13 A F term (reference) 5C053 FA21 GB07 GB15 5C059 RD03 RF01 RF04 TA11 TB08 5D044 AB05 AB07 BC01 CC03 DE12 DE68 DE83 5J065 AA01 AB01 AC03 AD04 AD11 AE02 AF02 AG07 AH05 AH06 AH15 AH17

Claims (15)

[Claims] 1. A digital signal recording / reproducing system for recording a digital signal recording data with a predetermined error correction code added thereto and performing error correction using said error correction code during reproduction, wherein said recording data is divided into blocks. While generating a recording data block to which the predetermined error correction code is added,
An arbitrary continuous or appropriately interleaved data sequence of the recording data is divided into blocks to form a CRCC (Cyclic Red
and a digital signal recording device for recording the recording data block on a predetermined recording medium, comprising a recording data processing means for arranging a CRCC block to which the undancy check code is added in the recording data block; Digital conversion means for converting a signal to digital to generate a digital reproduction signal; binary identification means for identifying a binary of the digital reproduction signal to generate a binary identification signal; Error correction is performed for each recording data block, an error in the CRCC block is detected, a plurality of candidates having a high possibility of error are selected by using the binary identification signal, and provisional correction is performed. A digital signal reproduction device having error correction means for verifying the correction and selecting the correct correction. And a digital signal recording / reproducing system. 2. The recording data processing means of the digital signal recording apparatus, wherein: an inner code adding means for adding an inner code by a Reed-Solomon code to the recording data to which an outer code by a Reed-Solomon code is added; And CRCC adding means for adding a CRCC to the recorded data, wherein the error correction means of the digital signal reproducing apparatus comprises:
Detecting an error in the CRCC block reproduced from the value identification signal; detecting a plurality of candidates having a high probability of occurrence of an error in the CRCC block in which the error is detected; CRC correction means for verifying the provisional correction by the CRCC and selecting a correct correction, and correcting the binary identification signal corrected by the CRCC correction means using the inner code. 2. The digital signal recording / reproducing system according to claim 1, further comprising: an inner code correcting unit. 3. The CRCC of the digital signal recording device.
3. The digital encoding apparatus according to claim 2, wherein said adding means arranges a plurality of said CRCC blocks in an inner code block which is a unit for adding said inner code, and adds a CRCC to said inner code as needed. Signal recording and playback system. 4. The CRCC of the digital signal reproducing device.
Correction means for generating a pseudo reproduction signal by matching the binary identification signal with the range of the digital reproduction signal; calculating a difference between the digital reproduction signal and the pseudo reproduction signal; Error signal generating means for generating a signal; comparing the absolute value of the error signal corresponding to each bit constituting the binary identification signal; Error position detecting means for selecting a plurality of candidates having a high possibility of error, and performing a temporary correction by inverting the bit data of the candidate having a high possibility of error alone or in combination, and performing a CRCC when the provisional correction is performed. Checking means for verifying whether or not the temporary correction is correct, and correcting means for selecting the correct temporary correction by the CRCC. Placing the digital signal recording and reproducing system. 5. A recording data processing means of the digital signal recording apparatus, wherein CRCC adding means for adding CRCC to recording data to which an outer code by Reed-Solomon code is added, and recording data of an inner code sequence to which the CRCC is added. A time series conversion means for converting the time series of the digital signal reproduction means, and an inner code addition means for adding an inner code by a Reed-Solomon code to the recording data whose time series has been converted by the time series conversion means, The error correction means of the device is
Inner code correction means for performing a correction using the inner code in an inner code block, which is a unit to which the inner code added from the value identification signal is added, to generate a correction signal; and converting a time series of the corrected signal. A time series conversion means for converting the time series of the digital reproduction signal in the same manner as the inner code correction signal, and detecting an error of the CRCC block reproduced from the correction signal time series converted by the time series conversion means. Then, in the CRCC block in which an error is detected, a plurality of candidates having a high probability of occurrence of an error are detected, and the plurality of candidates having a high possibility of the error are tentatively corrected alone or in combination, and the CRCC is used to perform the temporary correction. CRCC correction means for verifying the provisional correction and selecting the correct correction;
2. The digital signal recording / reproducing system according to claim 1, comprising: 6. The digital signal according to claim 5, wherein said error correction means further corrects the correction signal generated by said CRCC correction means by said inner code correction means as necessary. Recording and playback system. 7. The inner code correcting means of the error correcting means further sets an error correction impossible flag for the inner code block for which an error cannot be corrected by the inner code, and the CRCC correcting means further comprises: 6. The digital signal recording / reproducing system according to claim 5, wherein data belonging to the inner code block in which the error correction disable flag is not set is excluded from candidates for the provisional correction. 8. A recording data processing means of the digital signal recording apparatus, wherein: an inner code adding means for adding an inner code by a Reed-Solomon code to recording data to which an outer code by a Reed-Solomon code is added; A time series conversion unit for converting a time series of the recording data of the inner code sequence, and a CRCC adding unit for adding the CRCC to the recording data whose time series is converted by the time series conversion unit, The error correction means of the digital signal reproducing device is
An error of the CRCC block reproduced from the value identification signal is detected, a plurality of candidates having a high probability of occurrence of an error in the CRCC block in which the error is detected are detected, and a plurality of candidates having a high possibility of the error are detected. CRC that temporarily corrects candidates alone and in combination, verifies the temporary correction by the CRCC, selects a correct correction, and generates a correction signal
C correction means, time series conversion means for converting a time series of a corrected signal corrected using the CRCC, and an inner code block reproduced from the corrected signal whose time series has been converted by the time series conversion means. 2. The digital signal recording / reproducing system according to claim 1, further comprising an inner code correcting means for performing correction. 9. The apparatus according to claim 8, wherein said error correction means further performs, as necessary, a correction signal corrected by said inner code correction means by said CRCC correction means. Digital signal recording and playback system. 10. A recording data processing means of the digital signal recording apparatus, wherein recording data to which an outer code of Reed-Solomon code is added is blocked to form a second CRCC block, and a second CRCC to which the CRCC is added.
Adding means, time-series converting means for converting the time series of the recording data to which the CRCC is added, and forming the first CRCC block by blocking the recording data whose time series is converted by the time-series converting means. First CRCC adding means for adding a first CRCC for adding the CRCC, second time series converting means for converting a time series of recording data generated by the first CRCC adding means, 2
And an inner code adding means for adding an inner code by the Reed-Solomon code to the recording data that has been time-series converted by the time-series converting means.
Detecting an error in the first CRCC block reproduced from the value identification signal, and detecting the error in the first CRCC block;
A plurality of candidates having a high probability of occurrence of an error in the block are detected, and the plurality of candidates having a high possibility of the error are provisionally corrected alone or in combination, and the provisional correction is verified by the CRCC to correct the correctness. First CRCC correction means for selecting and generating a correction signal, time series conversion means for converting the time series of the corrected signal corrected by the first CRCC correction means, and time series conversion by the time series conversion means. Detecting an error in the second CRCC block reproduced from the converted correction signal, and detecting the error in the second CRCC block;
A plurality of candidates having a high probability of occurrence of an error in the RCC block are detected, and the plurality of candidates having a high possibility of the error are provisionally corrected alone and in combination, and the provisional correction is verified by the CRCC to correct the correctness. And a second CRCC correction means for generating a correction signal by selecting
Second time series conversion means for converting a time series of a correction signal corrected by the CC correction means, and correction of an inner code block reproduced from the correction signal whose time series has been converted by the second time series conversion. 2. The digital signal recording / reproducing system according to claim 1, further comprising: an inner code correcting means for performing. 11. The error correction means further sets an error correction disable flag for the first CRCC block for which an error could not be corrected by the first CRCC correction means, and further comprises: 11. The digital signal recording / reproducing system according to claim 10, wherein the means further excludes data belonging to the first CRCC block in which the error correction disable flag is not set from the candidates for the temporary correction. 12. The error correction means may further include, if necessary, the first CRCC correction means and the second CRCC correction means for adding a correction signal generated by the inner code correction means to the corrected signal. 11. The digital signal recording / reproducing system according to claim 10, wherein the correction is performed by: 13. A digital signal recording apparatus for recording by adding a predetermined error correction code to recording data of a digital signal, wherein the recording data is divided into blocks to generate a recording data block to which the predetermined error correction code is added. With
An arbitrary continuous or appropriately interleaved data sequence of the recording data is divided into blocks and CRCC is added.
A digital signal recording apparatus comprising: recording data processing means for arranging an RCC block in the recording data block; and a digital signal recording apparatus for recording the recording data block on a predetermined recording medium. 14. A digital signal reproducing apparatus for performing error correction using said error correction code at the time of reproducing recorded data recorded with a predetermined error correction code added thereto, wherein in addition to said predetermined error correction code, A reproduction signal obtained from a recording medium in which a recording data block in which a CRCC block to which an arbitrary continuous or appropriately interleaved recording data is added and a CRCC is added and which is added with a CRCC is recorded is converted into a digital signal and reproduced. Digital conversion means for generating a signal; binary identification means for identifying a binary of the digital reproduction signal to generate a binary identification signal; and performing error correction for each recording data block using the error correction code. At the same time, an error of the CRCC block is detected, and a complex with a high possibility of error is detected using the binary identification signal. The number of candidates is selected and provisional correction is performed.
Error correction means for verifying the provisional correction and selecting a correct correction according to the following. 15. A digital signal recording / reproducing method in which recording is performed by adding a predetermined error correction code to recording data of a digital signal and performing error correction using the error correction code during reproduction. A signal recording device blocks the recording data to generate a recording data block to which the predetermined error correction code is added, and adds a CRCC by blocking an arbitrary continuous or appropriately interleaved data sequence of the recording data. Arranging the CRCC block in the recording data block and recording it on a predetermined recording medium; and a digital signal reproducing device for reproducing the digital signal converts a reproduction signal obtained from the recording medium into a digital signal. A reproduction signal is generated, and the binary of the digital reproduction signal is identified. To generate a binary identification signal, perform error correction for each recording data block using the error correction code, detect an error in the CRCC block, and use the binary identification signal to determine the possibility of error. A method of selecting a plurality of candidates having a high probability, performing a temporary correction, verifying the temporary correction by the CRCC, and selecting a correct correction.