JP2000100084A - Signal processing device and magnetic disk device - Google Patents

Abstract

(57) [Problem] To reduce detection errors of a data synchronization signal with a simple configuration. SOLUTION: Input data 11 is inputted to a data discriminating means 1, and a data discriminating output 12, which is a sign bit output discriminated by the data discriminating means 1, is inputted to a postcode means 2, and predetermined postcode processing is performed. . An output 13 of the post code unit 2 is applied to a code demodulation unit 4 and a processing unit 5 for performing a process of modulo 2 adding an input value thereof and a value obtained by delaying the input value by a predetermined time to obtain an output value (1 + D). Is entered. (1 + D) processing output 1 of (1 + D) processing means 5
8 is input to the error detection / correction means 6 and is separated into an odd-numbered sequence and an even-numbered sequence.
Error detection / correction is performed, and the corrected error detection / correction output 1
Numeral 9 is input to the data synchronization signal detecting means 3 and is compared with the synchronization pattern 14 for each group. When the number of matching groups is equal to or greater than the threshold value 15, a synchronization signal detection output 16 is output to the code demodulation means 4. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing technique and a magnetic disk drive, and more particularly, to a data synchronization signal detection rate so that a data synchronization signal can be detected even if there is a data discrimination error in a data synchronization signal portion. The present invention relates to a data synchronization signal detection technology and a magnetic disk device and the like using the same.

[0002]

2. Description of the Related Art An example of a data synchronization signal detecting apparatus according to the present invention will be described below with reference to the accompanying drawings.

[0003] A method according to a reference technique will be described by taking a magnetic disk drive as an example. FIG. 20 shows an example of a recording format of the magnetic disk device. Data has an ID section and a DATA section for each sector which is a unit storage area. Each of the ID section and the DATA section has a PLL (Phase Locked Loo
PLO SYNC region 91, I for retraction of p)
A data synchronization signal 92 for detecting a start position of D (address information) or DATA to obtain a demodulation timing signal of a modulated code, and an I for actually recording and reproducing ID information.
There is a DATA area 93 for recording and reproducing D or data, and a CRC section or ECC section 94 for error detection and correction. Further, between the ID part and the DATA part or between the sectors, there is a GAP part 95 which is a pattern for absorbing various delay times.

Here, it is well known that accurate detection of the data synchronization signal 92 is very important for subsequent code demodulation of the ID and the DATA area 93. That is, even if the data demodulated in the ID or DATA area 93 has a very good error rate, if the detection of the data synchronization signal 92, which is usually about several bytes, is erroneous, the subsequent several tens to several hundreds of bytes in the ID or DATA area are used. 93 is not correctly demodulated.

More specifically, in detecting a data synchronization signal having a configuration as shown in FIG. 21, input data 511 is subjected to data discrimination by data discriminating means 501, and its data discrimination output 5 is output.
12 is subjected to predetermined post code processing (bit operation) by the post code means 502. This postcode processing generally performs processing corresponding to precoding processing at the time of recording, not shown. This is to make the encoding of data at the time of recording correspond to the demodulation of code at the time of reproduction. According to the method disclosed in Japanese Patent Application Laid-Open No. 9-223365,
It is possible to perform processing equivalent to performing postcode processing when outputting the result of the state transition inside the data discriminating means 501, and the postcode means 502 is not necessarily required in terms of configuration. Also in the case of the method, functionally, it can be considered that the function of the postcode processing is separated from the data discriminating means, and that the postcode means 502 is provided, or that the postcode processing for passing the code is provided. The post code output 513 is output from the code demodulation unit 50.
4 is input. Also, the same post code output 513 is input to the data synchronization signal detection means 503, and is collated with a predetermined synchronization pattern 514, and when they match, data synchronization signal detection is performed. The code demodulation unit 504 performs a code demodulation operation using the signal as a demodulation timing signal to obtain output data 517.

As a configuration of the data synchronization signal detecting means 503, as in the configuration disclosed in Japanese Patent Application Laid-Open No. H10-125002, a code sequence subjected to data discrimination is divided into an odd sequence and an even sequence to form a group. A data synchronization signal detection process that determines that a data synchronization signal has been detected when the number of matched groups exceeds a predetermined threshold 515, thereby achieving high data synchronization signal detection. It is known to gain the ability. Japanese Patent Application Laid-Open No. 8-096312 discloses a method in which a pattern in which data inversion is not continuous is used as a data synchronization signal.

Further, in order to improve the reproduction performance, J. Mo
on, a book "Maximum Transi" written by B. Brickner.
tion Run Codes for Data Storage Systems "(IEEE.
Trans. Mag. Vol.32, No.5 Sep. 1996), MTR (Maximum Transition Run) limiting the number of continuous magnetization reversals
Code has been proposed. Since this code is a code in which the recording data is inverted by 1, the precoding process when such a code is used is (1 / (1 + D)) processing (modulation of the input value and the output value delayed by a predetermined time). The post code processing corresponding thereto is (1 + D) processing (modulo 2 addition of an input value and a value obtained by delaying the input value by a predetermined time) to obtain an output value. Processing). By using the MTR code, the data reproduction performance is improved and the error length is shortened. However, for example, when the error in the data discriminating unit 501 is 1 bit, the (1 + D)
After the processing, a 2-bit continuous error occurs, and even if the code string is divided into an odd-numbered series and an even-numbered series, it is impossible to detect the data synchronization signal well.

Therefore, in such a configuration, if a one-bit data error occurs in the data synchronization signal 92, the detection of the data synchronization signal is erroneous, and the ID and the data area 9
All three would be wrong. (If bit loss occurs permanently in the data synchronization signal portion due to a defect in the medium or the like, data for one sector cannot be correctly reproduced.)

[0009]

As described above, if the detection of the data synchronization signal at the head of the data is erroneous (cannot be detected at the correct position or detected at the wrong position),
There is a technical problem that not only the detection error of the data synchronization signal, but also all of the subsequent code demodulation of several hundred bytes is erroneous, and significantly deteriorates the entire error rate.

An object of the present invention is to provide a signal processing technique capable of reducing detection errors in data synchronization signal detection.

Another object of the present invention is to provide a signal processing technique capable of improving the data synchronization signal detection performance of the data synchronization signal detection means in response to the improvement of the data section reproduction performance. .

Another object of the present invention is to provide a signal processing technique in which the configuration of the data synchronization signal detecting means is easy and the circuit scale thereof can be reduced.

Another object of the present invention is to provide a magnetic disk capable of achieving both an improvement in recording density by employing a signal processing system such as maximum likelihood decoding and a reduction in error rate by improving data synchronization signal detection performance. It is to provide a device.

Another object of the present invention is to achieve both a reduction in manufacturing cost by reducing the circuit scale of a signal processing system for detecting a data synchronization signal and a reduction in an error rate by improving data synchronization signal detection performance. It is to provide a possible magnetic disk device.

[0015]

According to the present invention, a code obtained by subjecting a bit string of data output from a data discriminating means to a predetermined post code processing (bit operation processing) is code-demodulated by a code demodulating means. In a data synchronization signal detection system of a signal processing device for reproducing a signal, a modulo 2 addition of an input value and a value obtained by delaying the input value for a predetermined time to a bit sequence of a code input to a code demodulation means is output. (1 + D) processing means for performing processing ((1 + D) processing) for converting a value into a value; separating a bit string of a code including the data synchronization signal after the (1 + D) processing into an odd-numbered bit string and an even-numbered bit string; And even-numbered bit strings are separated into one group or two or more bit strings of any pattern of 0 bit or more in each bit string. Means for outputting in loops, matching means provided for each group, and matching the output of each group with a corresponding predetermined synchronization pattern to determine match / mismatch; Delay means for delaying the output by a predetermined time; and majority decision means for receiving the output of each delay means and outputting a detection signal of a data synchronization signal to the code demodulation means when the number of matched groups is equal to or greater than a predetermined threshold. , Is provided.

Further, between the means for separating the bit string of the code output from the (1 + D) processing means into the odd-numbered bit string and the even-numbered bit string, and the pattern matching means for matching with a predetermined synchronization pattern, error detection and correction are performed. Providing means,
The output code separated into the odd-numbered bit string and the even-numbered bit string is subjected to error detection and correction, and the error-corrected code bit string is subjected to pattern matching with a predetermined synchronization pattern.

For this purpose, a pattern set as a predetermined synchronization pattern is selected and used for which error detection and correction can be performed and data inversion is not continuous.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Referring to FIG. 1, a first embodiment of the signal processing apparatus of the present invention will be described.
An example of the configuration will be described.

In the first configuration shown in FIG. 1, input data 11 is input to the data discriminating means 1, and a data discriminating output 12, which is a sign bit output discriminated by the data discriminating means 1, is input to the postcode means 2, Predetermined post code processing is performed. Further, the post code output 13 is input to the code demodulating means 4 and the (1 + D) processing means 5. The (1 + D) processing output 18 is input to the data synchronization signal detecting means 3,
The pattern is compared with the synchronization pattern 14 by a predetermined method, and when the number of pattern matches is equal to or greater than the threshold value 15, a synchronization signal detection output 16 is output. The synchronization signal detection output 16
Is input to the code demodulation means 4 and the post code output 13
The demodulated output data 17 is output from the code demodulation means 4.

Apart from the data reproduction system, the data discrimination output 1
A configuration is also possible in which a data synchronization signal is detected for a code string that has been subjected to post code processing and (1 + D) processing for No. 2. That is, a code string to be input to the code demodulation means 4 is not used. However, this is simply to provide post code processing in parallel, and it is clear that this is equivalent to the configuration of FIG. 1 described above.

Referring to FIG. 2, a second embodiment of the signal processing apparatus of the present invention will be described.
An example of the configuration will be described.

In the second configuration shown in FIG. 2, the input data 11 is input to the data discriminating means 1, and the data discriminating output 12, which is the sign bit output discriminated by the data discriminating means 1, is input to the postcode means 2, Predetermined post code processing is performed. Further, a post code output 13 of the post code means 2 is input to the code demodulation means 4 and the (1 + D) processing means 5. (1 + D) processing output 1 of (1 + D) processing means 5
8 is input to the error detection and correction means 6. The error detection and correction means 6 separates the (1 + D) processing output 18 into an odd sequence and an even sequence, and performs error detection on the bit strings grouped by a predetermined method to correct errors. The error-corrected error detection / correction output 19 is input to the data synchronization signal detection means 3, and is output to the synchronization pattern 14 by a predetermined method.
When the number of pattern matches is equal to or greater than the threshold value 15, the synchronization signal detection output 16 is output. The synchronizing signal detection output 16 is input to the code demodulation means 4 to give a demodulation timing of the code sequence of the post code output 13, whereby the code demodulation means 4 outputs the demodulated output data 1.
7 is output.

As described above, the (1 + D) processing is performed before the detection of the data synchronization signal, and further divided into an odd series and an even series, so that the types of error patterns can be reduced and the error pattern length can be shortened. it can. for that reason,
Error detection and correction can be easily realized. As a result, more accurate data synchronization signal detection can be performed.

Referring to FIG. 3, a first embodiment corresponding to the above-described first configuration of FIG. 1 will be described in detail and specifically. The synchronization pattern used is 18 bits.

In FIG. 3, the code demodulation means 4 is an MTR code demodulation means in which the number of consecutive 1s is limited to 3 or less.

The data discriminating means 1 includes an EEPRML (ExteML)
nded Extended Partial Responsewith Maximum Likelih
ood detection). This channel response is (1−D) (1 + D) ³ . It is also assumed that the MTR code has been optimized. The synchronization pattern at the data discrimination output 12 is “001111
1111110011000 "or" 1100000
0001100111 "are possible.

The post code means 2 has a characteristic of (1 + D). The synchronization pattern at postcode output 13 is
One type of 18-bit pattern "00100000000010010100" is obtained. When the data discrimination unit 1 outputs the state transition, the operation of the postcode unit 2 ((1
+ D) processing), the post code means 2 is not provided, and the data discrimination output 12 is “0010000
It is possible to output 00010010100 ″, but in such a case, it can be considered to have the function of the postcode means 2.

The (1 + D) processing means 5 provided before the data synchronizing signal detection means 3 comprises a unit time delay means 31 and an exclusive OR circuit 32. Post code output 1
3 is input to the unit time delay means 31 and the exclusive OR circuit 32. The output of the unit time delay means 31 is input to another remaining input terminal of the exclusive OR circuit 32.
The output of the exclusive OR circuit 32 is (1 + D) processing output 1
It becomes 8. The synchronization pattern at the (1 + D) processing output 18 is “180000000011011110”.
It becomes a bit pattern.

The (1 + D) processing output 18 is input to the shift register 21 in the data synchronization signal detecting means 3.
The shift register 21 here has a 17-bit configuration. This is because a 9-bit pattern is selected and used as the synchronization pattern. Shift register 21
Are output as shift register outputs 22 every other bit. By using the value of every other bit of the shift register 21, it is possible to divide the operation clock (not shown) into an odd series and an even series. The synchronization pattern at the shift register output 22 is "0100010".
11 "and" 010001110 ".

The shift register output 22 is input to the pattern matching means 27i and the pattern matching means 27j, and the synchronous pattern holding means 26i and the synchronous pattern holding means 26j
Are compared with the synchronization pattern. Each synchronization pattern is given as a synchronization pattern 14, and the synchronization pattern holding unit 26i holds a 9-bit pattern of "010001111" and the synchronization pattern holding unit 26j holds a 9-bit pattern of "010001110". In order to make the timings of the outputs of the pattern matching means 27i and the pattern matching means 27j uniform, the output of the pattern matching means 27i is delayed through the unit time delay means 28b and input to the majority decision means 29.

The majority decision means 29 compares the number of matches between the two obtained pattern matching results with the value of the threshold value 15,
When the number of matches of the pattern matching result is equal to or greater than the value given by the threshold value 15, the synchronization signal detection output 16
Output to Here, since 1 is given as the value of the threshold value 15, it can be realized by a 2-input OR circuit.

The synchronizing signal detection output 16 gives a code demodulation timing to the MTR code demodulation means 4. As a result, correct code demodulation is realized, and output data 17
Get.

An error pattern occurring in the case of the first embodiment shown in FIG. 3 will be described with reference to FIG. In FIG. 4, the leftmost column is the data discriminating means 1 (EE
PRML) in the data discrimination output 12. Here, x represents an error bit, and 0 represents a non-error bit. Here, x, xx, xx
Although there are six patterns of x, x0x, x00x, and x000x, five patterns excluding xxx occur as errors. The error pattern here is an error pattern that can occur between the time when the state transition path in the maximum likelihood decoder deviates from the original path due to an error and the time when it matches the correct path again (returns). Error pattern (error event).

The second column from the left indicates the distance between the codes of each error pattern and indicates the likelihood of occurrence of an error. An error is more likely to occur when the value of the distance is smaller.

The third column from the left shows the synchronization pattern used in the fourth embodiment to be described later and the PLO SYN before it.
The C pattern, specifically, “10” in the post code output 13
1010101010101010101101010101
010101010101010 1000 100 100
00010100 1010101010101010101
010101010101010 0010000000
10010100 100010101101010101
0 "indicates the occurrence ratio of each error pattern in a 128-bit pattern. From the 43rd bit and the 93rd bit, each of the 18 bits (underlined portion) is a synchronization pattern. , Xxx have the highest error occurrence frequency, but since the selected pattern has no portion where data inversion is continuous (that is, a portion where “1” is continuous 1), data inversion is limited to 3 bits or less. EEPRML optimized for MTR code
As a result, no xxx error pattern occurs. Therefore, here, the occurrence of the error pattern of x occupies nearly 90%. At this time, the bit error rate (error event occurrence rate with respect to the total number of bits to be reproduced) is 0.0004. Where the bit error rate is lower, for example 10 ^-6 to 10 ^-8 ,
The incidence of long error patterns such as x000x is even lower and negligible. Also, the other first
The same tendency also applies to the synchronization patterns used in the first to third embodiments. See also FIG. 4 for the second to fourth embodiments described below.

The fourth column from the left shows the post code output 1
3 shows each error pattern.

The fifth column from the left shows each error pattern at the (1 + D) processing output 18 for detecting a data synchronization signal.

The sixth column from the left shows each error pattern at the output 22 of the shift register after being divided into odd and even sequences for data synchronization signal detection. The error pattern of x in the data discrimination output 12 indicates that the shift register output 22 appears as a 2-bit continuous error (xx) in either the odd sequence or the even sequence.

From these facts, by newly providing (1 + D) processing means 5 for detecting the data synchronization signal, 9
Even if a one-bit error (x), which is an error pattern that occupies nearly a percentage, occurs after the separation into odd and even sequences, one of them does not include an error. It can be understood that it is dramatically improved.

The specific performance will be described with reference to FIG. FIG. 17 is a graph showing the performance of the first embodiment, based on computer simulation.

In FIG. 17A, the horizontal axis represents the signal-to-noise ratio at the input of the maximum likelihood decoder, and the vertical axis represents the bit error rate and the data synchronization signal detection error rate. Characteristic curve 175
Represents the bit error rate of the data at the data discrimination output 12. This is a characteristic when the data is considered to be random. A characteristic curve 171 is a characteristic of a data synchronization signal detection error rate when the data synchronization signal is detected under the condition that all 18 bits of the synchronization pattern match. The characteristic curve 172 is obtained by the method according to the reference technology that does not include the (1 + D) processing means 5 for detecting the data synchronization signal. The data is obtained under the condition that one of the 9-bit patterns divided into the odd sequence and the even sequence matches. This is a characteristic of a data synchronization signal detection error rate when the synchronization signal is detected. A characteristic curve 173 is a characteristic of a data synchronization signal detection error rate when the data synchronization signal is detected under the conditions of the first embodiment of the present invention. The signal-to-noise ratio is about 2 [d compared to the method of the reference technology.
B].

FIG. 17B shows the data discrimination output 1 on the horizontal axis.
2, the vertical axis represents the data synchronization signal detection error rate. This is obtained by converting and rewriting the graph of FIG. 17A with the characteristic curve 175 as a horizontal axis. The characteristic curve 176 corresponds to the characteristic curve 171, the characteristic curve 177 corresponds to the characteristic curve 172, and the characteristic curve 178 corresponds to the characteristic curve 173. When the occurrence ratio of the error event to the total number of output bits at the output of the data discriminating means 1 is Be (horizontal axis), and the occurrence ratio of the data synchronization signal detection error to the number of data synchronization signal detection requests is Se (vertical axis). , Be in the range of 0.1 or less, the characteristic curve 178 is approximated by Equation 1.

[0044]

[Formula 1]

A second embodiment corresponding to the second configuration of the present invention illustrated in FIG. 2 will be described with reference to FIG.

The structure of the data discriminating means 1, the post code means 2, the code demodulating means 4, and the (1 + D) processing means 5 in FIG. 9 are the same as those in the first embodiment in FIG. Also, the synchronization pattern to be used is the same as in the first embodiment.
This is an 8-bit pattern. Therefore, the synchronization pattern in each unit up to the (1 + D) processing output 18 is the same.

The (1 + D) processing output 18 is input to the shift register 21 in the error detection and correction means 6. The configuration of the shift register 21 is the same as that of the first embodiment. Therefore, the synchronization patterns at the shift register output 22 are “010001111” and “010001110”.
These are the 9-bit patterns. The shift register output 22 is input to a syndrome calculation unit 23a, a syndrome calculation unit 23b, an error correction unit 24a, and an error correction unit 24b.

As shown in FIG. 6, the configuration of the 9-bit synchronization pattern is a 4-bit code and a corresponding 5-bit CRCC (Cyclic Redundancy Check Cod).
e). The CRCC attaches five bits that are the remainder when the code is divided by the generator polynomial. Therefore,
If there is no error, the remainder of the 9-bit synchronization pattern generator polynomial is always 0, and if there is an error, the remainder of the 9-bit synchronization pattern generator polynomial indicates the corresponding value. This value of the remainder is called a syndrome value. If the syndrome value is not 0, it is known that there is an error, and the error can be detected. Based on the syndrome value, an error position can be detected and the error can be corrected (1 becomes 0, 0 becomes 1).

The synchronization pattern “01” used here
Looking at “0001011”, “0100” of 4 bits from the beginning is the original code, and “01000000”, which is shifted left by 5 bits, is divided by a fifth-order generator polynomial (X ⁵ + X ⁴ + X ² +1). The remainder is CRC
The five bits are "01011" of C. The synchronization pattern “0100010101” is converted to a fifth-order generator polynomial (X ⁵ + X
^The remainder after division by ( ⁴ + X ² +1) is zero. This generator polynomial corresponds to e in FIG.

The syndrome calculating means 23a is provided by the
The fifth-order polynomial (X ⁵ + X ⁴ + X ² +1) represented by the following equation is defined as a generator polynomial. In the syndrome calculating means 23a, division by a generator polynomial (X ⁵ + X ⁴ + X ² +1) is performed, and the remainder is set as a syndrome value 20a by 5
Output in bits. FIG. 12 shows a detailed configuration example of the syndrome calculation unit 23a. Here, the 9-bit input of the shift register output 22 is divided by 11 exclusive-OR circuits 301 to 311 at a stretch to generate a 5-bit syndrome value 20a. This operation can be obtained by an arithmetic operation method based on handwriting. As a result, the syndrome value 20a can be output each time to the shift register output 22 that is grouped and output into an odd-numbered sequence and an even-numbered sequence for each operation clock (not shown).

Similarly, the syndrome calculation means 23b can be configured as h (X ⁵ + X ⁴ + X ³ + X ² +1) in FIG. 5 corresponding to the synchronization pattern “010001110” as a generator polynomial.

Next, the value of the syndrome value 20a for the error pattern will be described with reference to FIG. FIG. 7 shows 10 error patterns of 1 to 2 bits. This is a two-bit continuous error pattern that frequently appears in the shift register output 22, and represents a one-bit pattern at the end of the 9-bit group. Syndrome values for these 10 error patterns are 22, 29, 20, 10, 5, 24, as shown in the column of the generator polynomial e in FIG. 7 corresponding to the polynomial e in FIG.
12, 6, 3, 1 and 10 different values are shown. The polynomials a to h in FIG. 5 correspond to the columns of the generator polynomials a to h in FIG. 7, respectively. Therefore, also in the other generator polynomials a to d and f to h, the syndrome values for the ten error patterns similarly indicate ten different values, so that for the eight generator polynomials in FIG. It can be seen that it is effective as a generator polynomial for error detection and correction.

The syndrome value 20a and the syndrome value 20b in FIG. 9 are input to the error correction means 24a and the error correction means 24b, respectively. The error correction means 24a corrects the corresponding error of the shift register output 22 by the value of the syndrome value 20a, and the error correction means 24b corrects the corresponding error of the shift register output 22 by the value of the syndrome value 20b. The generator polynomial (X ⁵ + X ⁴ + X ² +1) of e in FIG. 5 and the generator polynomial (X ⁵ + X ⁴ + X ³ + X ² +1) of h in FIG. 5, respectively.
Is performed, and if an error is detected, the corresponding correction is performed. The result is output as an error detection and correction output 19a and an error detection and correction output 19b.

FIG. 13 shows an example of a more detailed configuration of the error correction means 24a. The syndrome value 20a is calculated as 22, 29, 20, 1 by the comparing means 312 to 321.
It is compared with ten values 0, 5, 24, 12, 6, 3, 1. If there is an error and one of the comparison means matches, the result passes through the corresponding circuit of the OR circuit 322 to the OR circuit 330 and the corresponding result of the exclusive OR circuit 331 to the exclusive OR circuit 339. Come to the circuit. Exclusive OR circuit 3
Since the information of the error position and the shift register output 22 are input to the 31 to exclusive OR circuit 339, the bit corresponding to the error is inverted to correct the error. The result is output as an error detection and correction output 19a.

The error correction operation will be described in detail. For example, suppose that two bits from the beginning of the synchronization pattern “0100010101” are erroneous, and a value “100001011” appears in the shift register output 22. This is an error of the error pattern 2 in FIG. Syndrome value at this time is 20
a is as shown in FIG. At this time, in FIG. 13, the comparison result of the comparing means 313 matches, and 1 (true value) is output. The value is input to the logical sum circuit 322 and the logical sum circuit 323, and the output also becomes 1 (true value). As a result, since 1 is input to one of the inputs of the exclusive OR circuit 331 and the exclusive OR circuit 332, two bits of the MSB side of the shift register output 22 (corresponding to the head of the synchronization pattern) are inverted. And “100001011” becomes “01”.
000101 ". The correctly corrected pattern is output as the error detection and correction output 19a.

The error detection / correction output 19a and the error detection / correction output 19b are input to the pattern matching means 27a and the pattern matching means 27b of the data synchronization signal detecting means 3, and are output to the synchronization pattern holding means 26a and the synchronization pattern holding means 26b.
Are compared with the synchronization pattern. Each synchronization pattern is given as a synchronization pattern 14, and the synchronization pattern holding unit 26a holds a 9-bit pattern of “010001111” and the synchronization pattern holding unit 26b holds a 9-bit pattern of “010001110”. In order to make the timings of the outputs of the pattern matching means 27a and the pattern matching means 27b uniform, the output of the pattern matching means 27a is delayed through the unit time delay means 28a and input to the majority decision means 29.

The majority decision means 29 compares the obtained number of matches of the two pattern matching results with the threshold value 15. If the number of matching of the pattern matching results is equal to or greater than the value given by the threshold value 15, the synchronization signal The detection output 16 is output. Here, since 2 is given as the value of the threshold value 15, it can be realized by a two-input AND circuit. Error detection and correction means 6
When the error detection and correction is performed, the possibility of erroneously correcting the synchronization pattern increases because the data start position is unknown. Therefore, the threshold value needs to be 2 or more.

The synchronizing signal detection output 16 gives a code demodulation timing to the MTR code demodulation means 4. As a result, correct code demodulation is realized, and output data 17
Get.

Here, the performance in the case of the configuration of the second embodiment shown in FIG. 9 will be described with reference to FIG. In the first embodiment shown in FIG. 3, only the error pattern x can be repaired. However, in the second embodiment, since error detection and correction can be further performed for a 2-bit continuous error, it can be seen that the error patterns xx and x00x can be rescued. That is, (1 + D) processing means 5 is provided,
By detecting and correcting a 2-bit continuous error after being divided into an odd sequence and an even sequence, about 98.8 [%] of the generated error can be relieved, and the detection rate of the data synchronization signal 92 is further improved. Can understand.

The performance is shown in FIG.
7 will be described. Here, a characteristic curve 174 and a characteristic curve 179 are characteristics of a data synchronization signal detection error rate when the data synchronization signal is detected under the conditions in the second embodiment of the present invention. FIG. 17A shows that the signal-to-noise ratio of the maximum likelihood decoder input is improved by about 0.5 [dB] as compared with the first embodiment. The ratio of occurrence of error events to the total number of output bits at the output of the data discrimination means is represented by Be (horizontal axis), and the ratio of occurrence of detection errors of data synchronization signal detection to the number of data synchronization signal detection requests is represented by Se (vertical axis). At this time, the characteristic curve 179 is approximated by Expression 2 in the range where Be is 0.1 or less.

[0061]

[Formula 2]

A third embodiment of the signal processing device of the present invention will be described with reference to FIG. The basic configuration of FIG. 10 is the same as the configuration of the second embodiment of FIG.
Only the differences will be described in detail. The difference is
These are the synchronization pattern 14 to be used, the error detection and correction means 6, and the generator polynomial used in them.

The synchronization pattern used here is “0000000010010101001” in the post code output 13.
This is an 18-bit pattern of “0.” In the (1 + D) processing output 18, “00000000110111111011”
This is an 18-bit pattern. Shift register output 22
Then, "000101111" and "00011110"
1 ". The generator polynomial for error detection and correction of these patterns is d (X ⁵ + X ³ + X ² + X ¹ +
1) to be ^{h (X 5 + X 4 +} X 3 + X 2 +1).

The syndrome calculating means 23c and the syndrome calculating means 23d can be constituted by exclusive OR circuits as in the case of the second embodiment. The syndrome calculation means 23c calculates the generator polynomial (X ⁵ + X ³ + X ² +
X ¹ +1), the syndrome calculation means 23d
Corresponding to the generating polynomial ^{(X 5 + X 4 + X} 3 + X 2 +1).

Next, the value of the syndrome value 20c for the error pattern will be described with reference to FIG. FIG. 8 shows 19 error patterns of 1 to 2 bits. This is an error pattern appearing in the shift register output 22, which is a frequently occurring two-bit error pattern described in the second embodiment, and a one-bit error pattern at the end of the nine-bit group. , And the next most frequently occurring x0x error pattern, which is the one-bit error pattern at the end of the 9-bit group at the second bit from the end. Syndrome values for these 19 error patterns are 9, 26, 13, 17, 31, 24, 12, as shown in the column of the generator polynomial d in FIG. 8 corresponding to the polynomial d in FIG.
6, 3, 1, 19, 23, 28, 14, 7, 20, 1
Shows 19 different values of 0, 5, 2. Also, in the other generator polynomials h, the syndrome values for the 19 error patterns similarly show 19 different values, respectively. Therefore, two types of the generator polynomials d and h in FIG. Is effective as a generator polynomial for error detection and correction.

The syndrome value 20c and the syndrome value 20d in FIG. 10 are input to the error correction means 25c and the error correction means 25d, respectively. In the error correction means 25c,
The corresponding error of the shift register output 22 is corrected by the value of the syndrome value 20c and the error correction means 25d by the value of the syndrome value 20d. Each of the generator polynomials (X ⁵ + X ³ + X ² + X ¹ +
1) and the generator polynomial (X ⁵ + X ⁴ + X ³ + X ² ) of FIG.
Error detection corresponding to +1) is performed, and if an error is detected, correction corresponding to the error is performed. The result is output as an error detection and correction output 19c and an error detection and correction output 19d.

FIG. 1 shows a detailed configuration example of the error correction means 25c.
It is shown in FIG. The syndrome value 20c is calculated by comparing
By the comparing means 358, 19, 9, 23, 26, 28,
13, 14, 17, 7, 31, 20, 24, 10, 1
It is compared with 19 values of 2, 5, 6, 2, 3, and 1. If there is an error and any of the comparison means match, the result passes through the corresponding circuits of the OR circuit 359 to the OR circuit 383 and the exclusive OR circuit 384 to the exclusive OR circuit 39.
Comes to 2 corresponding circuit. Since the information on the error position and the shift register output 22 are input to the exclusive OR circuits 384 to 392, the bit corresponding to the error is inverted to correct the error. The result is output as an error detection and correction output 19c.

The error correction operation will be described in detail. For example, the second and fourth bits from the beginning of the synchronization pattern “000101111” are erroneous and “01000111”.
Assume that a value of 1 "appears in the shift register output 22. This is an error of the error pattern 13 in FIG. 8. The syndrome value 20c at this time is 28 from FIG. 8. At this time, in FIG. The comparison results match,
Outputs 1 (true value). The value is input to the logical sum circuit 362 and the logical sum circuit 367, and further, the logical sum circuit 363
Is output through the OR circuit 369, and the output is also 1
(True value). As a result, since 1 is input to one of the inputs of the exclusive OR circuit 385 and the exclusive OR circuit 387, the second and fourth bits from the MSB side of the shift register output 22 (corresponding to the head of the synchronization pattern) The eyes are bit-inverted, and “010001111” is changed
11 ". The correctly corrected pattern is output as an error detection and correction output 19c.

The error detection / correction output 19c and the error detection / correction output 19d are input to the pattern matching means 27c and the pattern matching means 27d of the data synchronization signal detection means 3, and are output to the synchronization pattern holding means 26c and the synchronization pattern holding means 26d.
Are compared with the synchronization pattern. Each synchronization pattern is provided as a synchronization pattern 14, and the synchronization pattern holding unit 26c holds a 9-bit pattern of "000101111" and the synchronization pattern holding unit 26d holds a 9-bit pattern of "000111101". In order to make the timings of the outputs of the pattern matching unit 27c and the pattern matching unit 27d uniform, the output of the pattern matching unit 27c is delayed through the unit time delay unit 28c and input to the majority decision unit 29.

The majority decision means 29 compares the number of coincidences of the two obtained pattern matching results with the threshold value 15. If the number of coincidences of the pattern matching result is equal to or greater than the value given by the threshold value 15, the synchronization signal The detection output 16 is output. Here, as in the second embodiment, 2 is given as the value of the threshold 15, so that it can be realized by a two-input AND circuit.

The synchronization signal detection output 16 gives a code demodulation timing to the MTR code demodulation means 4. As a result, correct code demodulation is realized, and output data 17
Get.

Here again, referring to FIG. 4, the third
The performance in the case of the configuration of the embodiment will be described. FIG.
In the second embodiment, the error pattern x, the error pattern xx, and the error pattern x00x could be repaired. In the third embodiment, the error pattern x0x
It can also be seen that relief is possible. That is, (1
+ D) A processing unit 5 is provided to detect and correct a 2-bit continuous error and an x0x 3-bit error after being divided into an odd-numbered sequence and an even-numbered sequence, thereby relieving about 99.9% of the generated errors. It can be understood that the detection rate of the data synchronization signal 92 is further improved.

The performance will be described with reference to FIG. FIG. 18 is a graph mainly showing the performance of the third embodiment, which is based on computer simulation.

In FIG. 18A, the horizontal axis represents the signal-to-noise ratio at the maximum likelihood decoder input, and the vertical axis represents the bit error rate and the data synchronization signal detection error rate. Characteristic curve 185
Represents the bit error rate of the data at the data discrimination output 12. This is a characteristic when the data is considered to be random. A characteristic curve 181 is a characteristic of a data synchronization signal detection error rate when the data synchronization signal is detected under the condition that all 18 bits of the synchronization pattern match. The characteristic curve 182 is obtained by the method of the reference technology which does not include the (1 + D) processing means for detecting the data synchronization signal, and performs data synchronization under the condition that either one of the 9-bit patterns divided into the odd series and the even series matches. It is a characteristic of a data synchronization signal detection error rate when signal detection is performed. A characteristic curve 183 indicates a characteristic of a data synchronization signal detection error rate when data synchronization signal detection is performed under the conditions (including (1 + D) processing means 5 and not performing error detection and correction) according to the first embodiment of the present invention. It is. A characteristic curve 184 is a characteristic of a data synchronization signal detection error rate when data synchronization signal detection is performed under the conditions of the third embodiment of the present invention. FIG. 18 (a)
From the result, the signal-to-noise ratio at the input of the maximum likelihood decoder is about 1 [dB] as compared with the first embodiment (this is about 0.1 dB in the signal-to-noise ratio compared to the second embodiment). 5 [dB]).

FIG. 18B shows the data discrimination output 1 on the horizontal axis.
2, the vertical axis represents the data synchronization signal detection error rate. This is obtained by converting and rewriting the graph of FIG. 18A with the characteristic curve 185 as a horizontal axis. The characteristic curve 186 corresponds to the characteristic curve 181, the characteristic curve 187 corresponds to the characteristic curve 182, the characteristic curve 188 corresponds to the characteristic curve 183, and the characteristic curve 189 corresponds to the characteristic curve 184. When the occurrence ratio of the error event to the total number of output bits at the output of the data discriminating means 1 is Be (horizontal axis), and the occurrence ratio of the data synchronization signal detection error to the number of data synchronization signal detection requests is Se (vertical axis). , Be in the range of 0.1 or less, the characteristic curve 189 is approximated by Expression 3.

[0076]

[Equation 3]

With reference to FIG. 11, a fourth embodiment of the signal processing device of the present invention will be described. The basic configuration of FIG. 11 is the same as the configuration of the second embodiment of FIG.
A different point is that four patterns of 9 bits are used as the synchronization pattern 14. As in the second embodiment, the error detection and correction method corresponds to correction of 10 error patterns for each synchronization pattern.

The synchronization pattern used here is “10001001000001010” in the post code output 13.
0 ”and“ 0010000000001 ”
0010100 "18-bit pattern, 36
Matches a bit pattern. Further, "10101010101" for preventing error propagation is provided between the two patterns.
A 32-bit pattern of “010101010101010110101010” is inserted. The above pattern is “1100” in the (1 + D) processing output 18.
11011000011110 "," 00110000
"0011011110", "111111111111"
11111111111111111111 ".
The patterns to be compared at the shift register output 22 are “101010011” and “101100110”.
And "010001011" and "010001110". The generating polynomial for error detection and correction of these patterns is f (X ⁵ + X ⁴ + X ² + X ¹ +1) in FIG.
And ^{h (X 5 + X 4 +} X 3 + X 2 +1) and e (X ⁵ + X ⁴
+ X ² +1) and h (X ⁵ + X ⁴ + X ³ + X ² +1).

The syndrome calculating means 23e to 23h can be constituted by exclusive OR circuits as in the case of the second embodiment. The syndrome calculating unit 23e calculates the generator polynomial (X ⁵ + X ⁴ + X ² +
X ¹ +1), the syndrome calculating means 23f calculates
Corresponding to the generator polynomial (X ⁵ + X ⁴ + X ³ + X ² +1)
The syndrome calculating unit 23g calculates the generator polynomial (X ⁵ + X
⁴ + X ² +1) and the syndrome calculation means 23h
Corresponds to the generator polynomial (X ⁵ + X ⁴ + X ³ + X ² +1). Here, since the syndrome calculating means 23f and the syndrome calculating means 23h perform calculations on the same generator polynomial, one syndrome calculating means may be shared.

The syndrome value for each of the 10 error patterns in the matching pattern is the value at the corresponding generator polynomial in the syndrome value column of FIG. That is, the syndrome value 20e is a column of the generator polynomial f, the syndrome value 20f is a column of the generator polynomial h, the syndrome value 20g is a column of the generator polynomial e, and the syndrome value 20h is a column of the generator polynomial h.

The syndrome values 20e to 20h in FIG. 11 are input to error correction means 24e to 24h, respectively. In the error correction means 24e,
The value of the syndrome value 20e, the value of the syndrome value 20f in the error correction means 24f, the value of the syndrome value 20g in the error correction means 24g, and the value of the syndrome value 20h in the error correction means 24h. Corrects the corresponding error in the shift register output 22. Each generator polynomial e in FIG. 5 and generator polynomial f of FIG. ^{5 (X 5 + X 4 +} X 2 + X 1 +1) with the production of h in FIG polynomial ^{(X 5 + X 4 + X} 3 + X 2 +1) (X 5 + X ⁴ + X ² +1) and error detection corresponding to the generator polynomial (X ⁵ + X ⁴ + X ³ + X ² +1) of h in FIG. 5, and if an error is detected, a corresponding correction is performed. The result is output to the error detection and correction output 19e ~
It is output as an error detection and correction output 19h. The detailed configuration of the error correction means 24e to 24h can be realized in the same manner as in FIG. Again, the error correction means 24f
And the error correction means 24h perform the same processing and may be shared.

The error detection / correction output 19e to the error detection / correction output 19h are input to the pattern matching unit 27e to the pattern matching unit 27h of the data synchronization signal detection unit 3, and are output from the synchronization pattern holding unit 26e to the synchronization pattern holding unit 26h.
Are compared with the synchronization pattern. Each synchronization pattern is given as a synchronization pattern 14. The synchronization pattern holding unit 26e is "101010011", the synchronization pattern holding unit 26f is "101100110", the synchronization pattern holding unit 26g is "0100001111", and the synchronization pattern holding unit 26h is "010001110". Are stored in each 9-bit pattern. Pattern matching means 27e ~
In order to align the timings of the outputs of the pattern matching unit 27h, the output of the pattern matching unit 27e is delayed by the delay unit 28e.
[T] (1 [T] is one unit time), and the output of the pattern matching means 27f is reduced by 50 by the delay means 28f.
[T], the output of the pattern matching means 27g is delayed by 1 [T] by the unit time delay means 28g and input to the majority decision means 29.

The majority decision means 29 compares the obtained number of matches of the four pattern matching results with the threshold value 15. If the number of matches of the pattern matching result is equal to or greater than the value given by the threshold value 15, the synchronization signal The detection output 16 is output. Here, 2 is given as the value of the threshold value 15 as in the second embodiment.

The synchronizing signal detection output 16 gives a code demodulation timing to the MTR code demodulation means 4. As a result, correct code demodulation is realized, and output data 17
Get.

The performance in the case of the configuration of the fourth embodiment shown in FIG. 11 will be described. In the second embodiment shown in FIG. 9, if one error pattern x0x or one error pattern x000x occurs, it cannot be detected. However, with this configuration, for all the error patterns shown in FIG. 4, it is possible to detect a data synchronization signal even if at least any two or less errors occur. If only the error pattern x occurs, a data synchronization signal can be detected for five or less errors. Therefore, it can be understood that the detection rate of the data synchronization signal 92 is dramatically improved.

The performance will be described with reference to FIG. FIG. 19 is a graph showing the performance of the fourth embodiment, which is based on computer simulation.

In FIG. 19A, the horizontal axis represents the signal-to-noise ratio at the maximum likelihood decoder input, and the vertical axis represents the bit error rate and the data synchronization signal detection error rate. Characteristic curve 195
Represents the bit error rate of the data at the data discrimination output 12. This is a characteristic when the data is considered to be random. A characteristic curve 191 is a characteristic of a data synchronization signal detection error rate when data synchronization signal detection is performed under the condition that all 36 bits of the synchronization pattern match. Compared with the characteristic curve 171 of FIG. 17 and the characteristic curve 181 of FIG. 18, it can be seen that the detection performance is somewhat degraded by the increase in the number of bits of the matching pattern.
A characteristic curve 192 represents (1 + D) for detecting a data synchronization signal.
The method according to the reference technology, which does not include the processing means 5, is a data synchronization signal when the data synchronization signal is detected under the condition that any one of four 9-bit patterns divided into an odd sequence and an even sequence matches. This is a characteristic of a detection error rate. The characteristic curve 193 indicates the characteristic of the data synchronization signal detection error rate when the data synchronization signal is detected under the conditions (including the (1 + D) processing means 5 and not performing error detection and correction) according to the first embodiment of the present invention. It is. A characteristic curve 194 is a characteristic of a data synchronization signal detection error rate when the data synchronization signal is detected under the conditions of the fourth embodiment of the present invention. From FIG. 19A, it can be seen that the signal-to-noise ratio is about 2-3 [dB] as compared with the configuration of the reference technology.
It can be seen that there is an improvement.

FIG. 19B shows the data discrimination output 1 on the horizontal axis.
2, the vertical axis represents the data synchronization signal detection error rate. This is obtained by converting and rewriting the graph of FIG. 19A with the characteristic curve 195 as a horizontal axis. The characteristic curve 196 corresponds to the characteristic curve 191, the characteristic curve 197 corresponds to the characteristic curve 192, the characteristic curve 198 corresponds to the characteristic curve 193, and the characteristic curve 199 corresponds to the characteristic curve 194. When the occurrence ratio of the error event to the total number of output bits at the output of the data discriminating means 1 is Be (horizontal axis), and the occurrence ratio of the data synchronization signal detection error to the number of data synchronization signal detection requests is Se (vertical axis). , Be in the range of 0.1 or less, the characteristic curve 198 is approximated by equation 4, and in the range of Be less than 0.1, the characteristic curve 199 is approximated by equation 5.

[0089]

(Equation 4)

[0090]

(Equation 5)

As described in the first to fourth embodiments, the pattern used as the synchronization pattern is such that the remainder of the division by the generator polynomial shown in FIG.
And they need not be easily mistaken for other patterns. FIG. 16 lists such 9-bit patterns. Here 4
There are four types of patterns. The patterns used in the first embodiment and the second embodiment correspond to No. 15,
No. The pattern used in the third embodiment is No. 17 in FIG. 3, No. The pattern used in the fourth embodiment is No. 7 in FIG. 15, N
o. 17, No. 33, no. 37.

When the data synchronization detecting means in the signal processing device of the present invention is to be realized by an integrated circuit, the circuit scale can be converted into a two-input NAND gate as one gate. The form is 1
About 0 gates, about 200 gates in the second embodiment,
A circuit having about 350 gates in the third embodiment and about 400 gates in the fourth embodiment increases the number of circuits compared to the method of the reference technology. This is an easily feasible range in view of recent advances in integrated circuit technology.

Further, the data synchronization signal detecting means of the present invention can be configured and realized as software.

As described above, in the signal processing apparatus of the present invention, the (1 + D) processing is performed before the detection of the data synchronization signal, and further divided into an odd series and an even series, thereby reducing the types of error patterns. Moreover, the error pattern length can be reduced. Therefore, error detection and correction can be easily realized. As a result, more accurate data synchronization signal detection can be performed.

As shown in FIGS. 17 to 19, in the method of detecting a data synchronization signal in the signal processing apparatus of the present invention, the signal-to-noise ratio at the input of the maximum likelihood decoder is about 2 compared to the method of the reference technology. There is an improvement effect of ３3 [dB], so that highly accurate data synchronization information can be obtained. Further, it is also possible to reduce data errors caused by erroneous data synchronization information of a signal processing circuit, an information recording / reproducing device, an information transmitting device and the like using the same.

FIG. 15 is a conceptual diagram showing an example of the configuration of a magnetic disk drive according to an embodiment of the present invention. In the magnetic disk device of FIG. 15, an example of a magnetic disk device using the above-described signal processing device of the present invention is shown.

The magnetic disk device 201 includes a magnetic disk 211 serving as a data recording medium and a magnetic disk 2
A magnetic head 212 for performing a data recording / reproducing operation with respect to the R.11 and an R for amplifying a data signal to be recorded / reproduced
/ W I / F between AMP 213 and host device 202
HDC microcomputer 21 for controlling and controlling the entire apparatus
4, a data buffer 215 for temporarily storing data transmitted and received between the host device 202, a servo processing circuit 216 for processing a servo control signal recorded on the magnetic disk 211, and a servo processing circuit 216. That performs a positioning operation of the magnetic head 212 based on a command from the
A mechanism driver 217 that controls a motor 219 that rotationally drives the M 218 and the magnetic disk 211; a coding and modulation process of data recorded on the magnetic disk 211; and a code demodulation process of data read from the magnetic disk 211. And the like.

The signal processing means 220 is composed of the signal processing device of the first to fourth embodiments described above or another configuration according to the present invention, and includes a data synchronization signal detection means 221 (data synchronization signal detection means). Means 3, (1 + D) processing means 5, and error detection and correction means 6). The magnetic disk device 201 having this configuration can realize a magnetic disk device with few errors in detecting a data synchronization signal.

That is, the magnetic disk 21 by employing a signal processing system such as the data discriminating means 1 comprising a maximum likelihood decoder and the like.
1 and the error rate reduction by improving the data synchronization signal detection performance by employing the data synchronization signal detection means 221.

Further, it is possible to achieve both a reduction in manufacturing cost by reducing the circuit scale of a signal processing system for detecting a data synchronization signal such as the data synchronization signal detection means 221 and a reduction in an error rate by improving data synchronization signal detection performance. It becomes possible.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say, there is.

For example, in the above description, the data synchronization signal detection system in the signal processing device of the present invention has been described by taking a magnetic disk device as an example, but other signal processing circuits for information processing, integrated circuits, optical circuits, and the like. It can also be used for magnetic disk devices, optical disk devices, floppy disk devices, and the like.

The features of the present invention other than those described in the claims are listed below.

(1). 2. The signal processing device according to claim 1, wherein the data discriminating means is a maximum likelihood decoder (Viterbi decoder), and the code demodulating means is configured such that the number of consecutive 1s is a predetermined number K (K = 1, 2, 3) A signal processing device characterized in that the signal processing means is a code demodulation means for codes limited to the following.

(2). 3. The signal processing device according to claim 1, wherein a predetermined threshold is set to 1, and a data synchronization signal is detected when the number of matched groups is one or more.

(3). 3. The signal processing device according to claim 2, wherein the matching means is provided for each of the groups before performing matching with a predetermined synchronization pattern, and performs predetermined error detection and error correction corresponding to the output of the group. A signal processing device comprising:

(4). (3) The signal processing device according to (3), wherein the error detection and correction means performs error detection and correction for a two-bit continuous error and a one-bit error at both ends of the group.

(5). (4) In the signal processing device described in (4), the error detection and correction means includes a two-bit error in which an error pattern is “x0x” (x is an error bit and 0 represents a non-erroneous bit); A signal processing device for performing error detection and correction on a 1-bit error of the second bit from both ends of a group.

(6). (3) The signal processing device according to any one of (5) to (5), wherein the predetermined threshold value is 2, and the data synchronization signal is detected when the number of matched groups is two or more.

(7). Claims 1 and 2 and (1)
An integrated circuit in which the signal processing device described in any one of (1) to (6) is integrated.

(8). Claims 1 and 2 and (1)
A magnetic disk device, a magneto-optical disk device, or an optical disk device using the signal processing device described in any one of (1) to (6) in a signal processing system.

[0112]

According to the signal processing apparatus of the present invention, an effect is obtained that detection errors can be reduced in data synchronization signal detection.

Further, according to the signal processing device of the present invention, the effect that the data synchronization signal detection performance of the data synchronization signal detection means can be improved corresponding to the improvement of the reproduction performance of the data portion is obtained. .

Further, it is possible to obtain the effect that the configuration of the data synchronization signal detecting means is easy and the circuit scale can be reduced.

Further, according to the magnetic disk drive of the present invention, it is possible to improve the recording density by adopting a signal processing system such as maximum likelihood decoding and to reduce the error rate by improving the data synchronization signal detection performance. Can be obtained.

Further, according to the magnetic disk drive of the present invention, the manufacturing cost can be reduced by reducing the circuit scale of the signal processing system for detecting the data synchronization signal, and the error rate can be reduced by improving the data synchronization signal detection performance. The effect that both can be achieved is obtained.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating an example of a first configuration of a signal processing device according to the present invention.

FIG. 2 is a conceptual diagram illustrating an example of a second configuration of the signal processing device of the present invention.

FIG. 3 is a conceptual diagram illustrating a first embodiment of a signal processing device according to the present invention corresponding to the first configuration illustrated in FIG. 1;

FIG. 4 is an explanatory diagram illustrating an error pattern at an output of a data discriminating unit.

FIG. 5 is an explanatory diagram showing a fifth-order polynomial used in a syndrome calculation unit.

FIG. 6 is an explanatory diagram illustrating a configuration example of a 9-bit synchronization pattern.

FIG. 7 is an explanatory diagram showing a relationship between an error position and a syndrome value.

FIG. 8 is an explanatory diagram showing a relationship between an error position and a syndrome value.

FIG. 9 is a conceptual diagram illustrating a second embodiment of the present invention corresponding to the second configuration illustrated in FIG. 2;

FIG. 10 is a conceptual diagram illustrating a third embodiment of the present invention corresponding to the second configuration illustrated in FIG. 2;

FIG. 11 is a conceptual diagram illustrating a fourth embodiment of the present invention corresponding to the second configuration illustrated in FIG. 2;

FIG. 12 is a conceptual diagram illustrating a configuration example of a syndrome calculation unit.

FIG. 13 is a conceptual diagram illustrating a configuration example of an error correction unit.

FIG. 14 is a conceptual diagram illustrating a configuration example of an error correction unit.

FIG. 15 is a conceptual diagram showing an example of a configuration of a magnetic disk device according to an embodiment of the present invention.

FIG. 16 is an explanatory diagram showing an example of a synchronization pattern used in the signal processing device of the present invention.

FIGS. 17A and 17B are diagrams illustrating an example of characteristics of the data synchronization signal detecting unit according to the first embodiment and the second embodiment of the present invention; FIGS.

FIGS. 18A and 18B are diagrams illustrating an example of characteristics of a data synchronization signal detecting unit according to the third embodiment of the present invention.

FIGS. 19A and 19B are diagrams illustrating an example of characteristics of a data synchronization signal detecting unit according to the fourth embodiment of the present invention.

FIG. 20 is an explanatory diagram illustrating an example of a format of recording data in a magnetic disk device.

FIG. 21 is a conceptual diagram illustrating a configuration of a signal processing device according to a reference technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data discrimination means, 2 ... Post code means, 3 ... Data synchronization signal detection means, 4 ... Code demodulation means, 5 ... (1+
D) processing means, 6 error detection and correction means, 11 input data, 12 data discrimination output, 13 post code output,
14: synchronization pattern, 15: threshold value, 16: synchronization signal detection output, 17: output data, 18: (1 + D) processing output, 19a to 19h: error detection and correction output, 20a to 20
h: draw value, 21: 17-bit shift register,
22: 9-bit output every other bit of the shift register,
23a to 23h: Syndrome calculation means, 24a, 24
b, 24e to 24h: error correcting means (corresponding to one error pattern); 25c, 25d: error correcting means (corresponding to two error patterns); 26a to 26j: synchronous pattern holding means;
27a-27j ... pattern matching means, 28a-28c,
28g, 31: unit time delay means, 28e to 28f: delay means, 29: majority decision means, 91: PLO SYNC,
92: data synchronization signal, 93: ID area or data area, 94: CRC section or ECC section, 95: GAP section,
322 to 330, 359 to 383 ... OR circuit, 32,
301-311, 331-339, 384-392 ... exclusive OR circuit, 312-321, 340-358 ... comparison means, 171, 172, 173, 174, 175, 1
76,177,178,179,181,182,18
3,184,185,186,187,188,18
9,191,192,193,194,195,19
6, 197, 198, 199: characteristic curve, 201: magnetic disk device, 211: magnetic disk, 212: magnetic head, 213: R / WAMP, 214: HDC microcomputer, 215: data buffer, 216: servo processing circuit, 217 ... Mechanism driver, 218 ... VCM, 219
... motor, 220 ... signal processing means, 221 ... data synchronization signal detection means, 501 ... data discrimination means, 502 ... postcode means, 503 ... data synchronization signal detection means, 5
04 code demodulation means, 511 input data, 512 data discrimination output, 513 post code output, 514 synchronization pattern, 515 threshold, 516 synchronization signal detection output, 517 output data.

Claims (6)

[Claims] A code demodulated by subjecting a bit string of data including a data synchronization signal output from a data discriminating means to a predetermined post code processing (bit operation processing) upon detection of the data synchronization signal. A signal processing apparatus for demodulating data by code demodulation by means, and modulating a bit sequence of a code input to the code demodulation means with an input value and a value obtained by delaying the input value by a predetermined time. (1 + D) processing means for executing (1 + D) processing for adding the output value, and data synchronization signal detecting means for detecting the data synchronization signal using the bit string of the code subjected to the (1 + D) processing. Wherein the data synchronization signal detecting means separates the bit sequence of the code including the data synchronization signal into an odd-numbered bit sequence and an even-numbered bit sequence, Means for outputting the first bit string and the even-numbered bit string in one group or two or more groups separated by a bit string having an arbitrary pattern of 0 bits or more in each bit string; A comparing means for comparing the output of each of the groups with a corresponding predetermined synchronization pattern to determine whether or not they match each other; a delay means for delaying the determination output of each of the matching means for a predetermined time; Majority output means for inputting the outputs of the individual delay means and outputting a detection signal of the data synchronization signal to the code demodulation means when the number of the groups matching the synchronization pattern is equal to or greater than a predetermined threshold value; A signal processing device comprising: 2. The signal processing device according to claim 1, wherein an error correction of a bit string of the code subjected to the (1 + D) processing is performed between the (1 + D) processing means and the data synchronization signal detecting means. A signal processing device provided with error detection and correction means. 3. A magnetic disk, a magnetic head for recording and reproducing data on and from the magnetic disk, and a code modulation process for the data recorded on the magnetic disk via the magnetic head and the data reproduced from the magnetic disk. 3. A magnetic disk drive, comprising: a signal processing device for performing a code demodulation process of data; wherein the signal processing device comprises the signal processing device according to claim 1 or 2. 4. The signal processing apparatus according to claim 1, wherein the 9-bit synchronization pattern to be compared is 00 bits.
0101001,0000101011,0001011
11,000110101,000110111,00
0111011, 000111101, 001001
11,001001101,001011110,00
1101110, 00110110, 0100001
01, 0100000111, 010001011, 01
0001101, 010001110, 0101100
01,01011010,01011001,01
0111100, 011010001, 0111000
01, 011101011, 011101100, 10
0001101, 100010110, 1000110
10, 100011100, 100100011, 10
1000111, 101001001, 1010100
11, 101010111, 101011000, 10
1011011, 101100110, 1011100
11, 110010111, 110101110, 11
0111000, 110111100, 1110100
11. A signal processing apparatus including any one of the 44 patterns of 11, 1110110110, and using a pattern in which data inversion is not continuous in a pattern of a code sequence before being divided into an even sequence and an odd sequence. 5. The data synchronization signal means of the signal processing device according to claim 1, wherein the total number of bits of the pattern to be compared is 18 bits or less, and an error event with respect to the total number of output bits at the output of the data discrimination means. When the occurrence ratio of the data synchronization signal detection error with respect to the number of data synchronization signal detection requests is represented by Se, and when Be is 0.1 or less, Se is expressed by the formulas 1 to 3. A signal processing device characterized by being approximated by: 6. The data synchronization signal detecting means of the signal processing device according to claim 1, wherein the total number of bits of the pattern to be matched is 36 bits or less, and an error with respect to the total number of output bits at the output of the data discriminating means. Assuming that the event occurrence ratio is Be and the occurrence ratio of the data synchronization signal detection / detection error with respect to the number of data synchronization signal detection requests is Se, Se is expressed by Expressions 4 and 5 in the range where Be is 0.1 or less. A signal processing device characterized in that it can be approximated by characteristics.