JP2002208291A - Non-volatile storage device - Google Patents

Abstract

(57) [Summary] In an EEPROM, as the number of times of rewriting increases, the oxide film of a memory cell transistor is damaged, and the erasing / writing characteristics are gradually deteriorated. It becomes shallow. As a result,
The margin of the read operation is reduced. For this reason, it is necessary to set the rewrite depth and read bias conditions in consideration of the characteristic deterioration due to rewrite, which causes excessive stress application to the memory cell transistor and unnecessary current consumption increase in the read circuit. Was. SOLUTION: A memory cell transistor 108 for storing a set value of a regulation circuit is provided, and the erase / write depth is verified after the erase / write operation, and when the judgment level is not satisfied, the control value of the voltage of the regulation circuit is stored. By setting the high voltage used for erasing / writing after rewriting the data of the memory cell transistor to be set higher than the existing value, the rewriting life of the EEPROM is greatly improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable / writable nonvolatile memory device.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional nonvolatile memory device 801 which can be electrically erased / written in a fixed time.

[0003] This is provided with a memory cell transistor array 802 in which memory cell transistors having floating gates are arranged. Around this memory cell transistor array 802, a decoder circuit 806 for selecting a bit line and a word line, a sense amplifier circuit 807 for reading data of a memory cell, and a high voltage necessary for erasing / writing are controlled and supplied to the decoder circuit 806. A regulating circuit 805 for outputting, a boosting circuit 804 for generating a high voltage for erasing / writing, and a control logic circuit 803 for controlling a circuit operation based on a signal input from the outside are provided.

[0004] The erasing / writing operation will be described. During the erase / write operation, the control logic circuit 8
03 generates a high voltage required for erasing / writing by operating the booster circuit 804. At this time, the control logic circuit 803 outputs to the regulation circuit 805 whether the operation state is the erase operation or the write operation.

The high voltage is applied to a regulation circuit 805 to determine a value corresponding to an erasing operation or a writing operation mode, and is constantly controlled to a constant voltage for each operation mode. The controlled high voltage is applied to an arbitrary memory cell transistor in the memory cell transistor array 802 selected by the decoder circuit 806 for a fixed time in accordance with the erase operation or the write operation.

The threshold voltage of the memory cell transistor is controlled by applying a high voltage to the memory cell transistor. That is, when erasing / writing data in the memory cell transistor, a constant voltage is always applied to the memory cell transistor for a fixed time. With the above operation, the erasing / writing of the memory cell transistor is performed.

Next, the read operation will be described. To read data written in the memory cell transistor, an arbitrary address in the memory cell transistor array 802 is selected by the decoder circuit 806, and the drain voltage of the memory cell transistor selected by the decoder circuit 806 is selected by the sense amplifier circuit 807. To read out the memory cell transistor by converting the value of the drain current flowing by applying the voltage into a voltage.

That is, when reading data from the memory cell transistor, a constant drain voltage is always applied to the memory cell transistor, and reading is performed according to a fixed criterion. With the above operation, reading of the memory cell transistor is performed.

[0009]

As described above, since a high voltage is applied to the memory cell transistor at the time of erasing / writing, a high voltage is applied to the thin tunnel oxide film between the floating gate of the memory cell transistor and the surface of the Si substrate. An electric field is applied, causing damage.

Therefore, as the erase / write operation is repeated, the tunnel oxide film gradually deteriorates, and the device characteristics of the memory cell transistor deteriorate. In addition, the high voltage at the time of erasing / writing is set to a high value at the design stage in consideration of manufacturing variations, inspection margins, and deterioration in capability after device characteristics are degraded due to repeated rewrites. EEPROM from start
It is necessary to always apply a high voltage during the period of use up to the lifetime of the device.

For this reason, as shown in FIG.
In the initial stage of the rewriting life of M, an excessive voltage stress more than necessary is applied to the memory cell transistor,
As a memory cell transistor, the amplitude of the threshold voltage after erasing and the amplitude of the threshold voltage after writing become large, and a particularly large electric field is applied to the tunnel oxide film at the beginning of the writing operation after the erasing and at the beginning of the erasing operation after the writing. This is one of the factors that shorten the erasing / writing life of the EEPROM. There is a problem that the rewriting life is shortened due to such erasing / writing voltage stress.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile memory device capable of relieving electrical stress on a memory cell transistor and greatly improving the number of times of rewriting.

[0013]

According to the nonvolatile memory device (EEPROM) of the present invention, the erase / write depth is verified by the sense amplifier circuit every time after the erase / write operation, and the erase / write depth is determined by the sense amplifier circuit. If the judgment level set in the memory cell transistor array is not satisfied, the control voltage of the regulation circuit included in the memory cell transistor array is stored. By setting the value higher than the value, the rewriting life of the EEPROM can be improved. That is, in the initial stage of the rewriting life of the EEPROM, the voltage applied to the memory cell transistor is reduced, and in the middle and later stages of the rewriting life, the voltage applied to the memory cell transistor is increased so that the memory cell transistor required for the EEPROM is increased. , And a state in which a normal operation can be performed is ensured.

Also, a nonvolatile storage device (EEPROM)
Has a nonvolatile memory cell transistor for storing the number of erase / write operations, and has a circuit for verifying the erase / write depth by the sense amplifier circuit at every fixed erase / write operation. The number of times of verification can be reduced.

Also, a nonvolatile storage device (EEPROM)
Has a redundant memory cell transistor for data error detection and correction in a memory cell transistor array, has an error detection and correction circuit, performs error detection during a read operation, and, when an error is detected, a memory cell. A circuit for rewriting data of a memory cell transistor for storing a control value of a voltage of a regulator circuit included in a transistor array and setting a high voltage to be used at the time of subsequent erasing / writing higher than an existing value is provided. The operation of verifying the depth can be eliminated.

Also, a nonvolatile storage device (EEPROM)
Indicates that each time the erase / write time is applied in a plurality of times during the erase / write operation, the erase / write
In a flash EEPROM that performs rewriting while verifying the writing depth, when a verify operation is performed after a certain erasing / writing time and the verification becomes NG, the voltage of the regulation circuit included in the memory cell transistor array is reduced. By providing a circuit for rewriting data of a memory cell transistor for storing a control value and setting a high voltage used for subsequent erasure / writing higher than the existing value, the rewriting life of the flash EEPROM can be improved.

Further, the nonvolatile memory device (EEP) of the present invention
In the manufacturing method of the ROM, since the control value of the voltage of the regulation circuit used at the time of erasing / writing is individually set based on the verification result of the erasing / writing depth of each product,
Variations in erasing / writing between products can be suppressed to optimize the stress on the memory cell transistor at an early stage of the rewriting life, thereby improving the rewriting life of the EEPROM.

Further, the nonvolatile memory device (EEP) of the present invention
ROM) is a memory cell transistor including a clock signal generating circuit for boosting operation in which the oscillation frequency can be changed in a boosting circuit, and a nonvolatile memory cell transistor for storing a control value of the oscillation frequency of the clock signal generating circuit. A nonvolatile array for storing a control value of an oscillation frequency of a clock signal generation circuit included in the memory cell transistor array when the erase / write depth does not satisfy a determination level set in the sense amplifier circuit. The oscillation frequency of the clock signal generation circuit for the boosting operation used for the erasing / writing after rewriting the data of the memory cell transistor is set higher than the existing value and the erasing / writing is performed.
By providing a circuit for setting the control value of the voltage of the regulation circuit used at the time of writing higher than the existing value, EE
It is possible to improve the rewriting life of the PROM and to reduce power consumption at an early stage of the rewriting life.

Further, the nonvolatile memory device (EEP) of the present invention
ROM) is a memory cell transistor including a bias generation circuit capable of changing a voltage applied to a memory cell transistor at the time of reading in a sense amplifier circuit, and a nonvolatile memory cell transistor for storing a control value of the bias generation circuit An array, and when the erase / write depth does not satisfy the determination level set in the sense amplifier circuit, a nonvolatile memory cell transistor storing a control value of a bias generation circuit included in the memory cell transistor array. By providing a circuit for changing the setting of the voltage applied to the memory cell transistor array at the time of reading after rewriting data to an existing value,
The drain current can be increased even after the drain current of the memory cell transistor is reduced by rewriting the EPROM, so that the rewriting life of the EEPROM can be improved and the power consumption can be reduced at the initial stage of the rewriting life.

According to this structure, the voltage stress of erasing / writing is reduced in the early stage of the rewriting life of the EEPROM, and after the device characteristics are degraded, the erasing / writing / reading voltage is set high again to set the memory cell transistor. By obtaining the threshold voltage required for
A state where normal operation can be performed as the EEPROM can be secured.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (Embodiment 1) FIGS. 1 and 2 show (Embodiment 1) of the present invention.

In FIG. 1, 101 is an EEPROM, 1
02 is a memory cell transistor array, 103 is a control logic circuit, 104 is a booster circuit, 105 is a regulator circuit, 106 is a decoder circuit, 107 is a sense amplifier circuit, and 108 is a memory cell transistor for storing a regulated circuit set value. Sense amplifier circuit 107
Is input to the regulation circuit 105.

Here, the sense amplifier circuit 10 shown in FIG.
7 is input to the regulation circuit 105, and the memory cell transistor 108 for storing the regulation circuit set value is connected to the memory cell transistor array 102.
The conventional EEPROM shown in FIG.
Is basically the same as

An erasing / writing operation in such an apparatus of the present invention will be described. At the time of the erase / write operation, the control logic circuit 103
Operate to generate a high voltage required for erasing / writing. At this time, the control logic circuit 1
03 outputs to the regulation circuit 105 whether the operation state is the erase operation or the write operation. This high voltage is applied to the regulation circuit 105, and is controlled by the result of reading the data of the memory cell transistor 108 for storing the regulation circuit set value by the sense amplifier circuit 107 and the value according to the erase or write operation mode. Output.

The high voltage output by this control is input to the decoder circuit 106 and applied to an arbitrary memory cell transistor in the memory cell transistor array 102 selected by the decoder circuit 106 for a fixed time in accordance with an erasing operation or a writing operation. Is done. The threshold voltage of the memory cell transistor is controlled by applying a high voltage to the memory cell transistor.

Here, the set value of the regulation voltage is set low in advance, and as shown in FIG.
The depth of Vt of the memory cell transistor becomes shallow with the deterioration due to erasing / writing of the ROM, and it is not necessary to satisfy the verify detection level which is stricter than the read detection level within the guaranteed number of rewrites. Further, after erasing / writing the EEPROM, a verify detection level which is stricter than the read detection level is set each time, and the verify determination is performed by the sense amplifier circuit 107. If this verify judgment is passed, the subsequent erasure / writing is also performed with the setting of the existing regulation circuit 105.

However, if the verify judgment fails, the output signal of the sense amplifier circuit 107 is input to the regulation circuit 105 to change the data set value of the regulated circuit set value storage memory cell transistor 108, and the next time At the time of subsequent erasing / writing, the setting is changed so that the value of the high voltage controlled and output by the regulation circuit 105 becomes higher than the existing voltage. By changing the set value of the data of the memory cell transistor 108 for storing the regulated circuit set value, as shown in the switching of the rewrite voltage in FIG. Can be secured.

By repeating the above for the subsequent erasing / writing, as for the memory cell transistor of the EEPROM, the damage to the tunnel oxide film at the time of erasing / writing is reduced, and the deterioration of the device characteristics is suppressed. , The rewriting life of the EEPROM can be improved. With the above operation, the erasing / writing of the memory cell transistor is performed.

(Embodiment 2) FIG. 3 shows (Embodiment 2) of the present invention. 301 is an EEPROM, 302 is a memory cell transistor array, 303 is a control logic circuit, 304 is a booster circuit, 305 is a regulation circuit, 306 is a decoder circuit, 307 is a sense amplifier circuit, 308 is a memory cell transistor for storing the number of times of erasing / writing. 309 is a counter circuit.

The difference between (Embodiment 2) and (Embodiment 1) is that a memory cell transistor 308 for storing the number of erase / write operations and a counter circuit 309 are added. Reference numeral 108 denotes a memory cell transistor for storing the regulation circuit set value shown in (Embodiment 1).

The erasing / writing operation in the device of the present invention will be described with respect to the difference from the (first embodiment). At the time of erasing / writing operation, the control logic circuit 303 stores the number of erasing / writing to the memory cell transistor 308 for storing the number of erasing / writing at the same time as erasing / writing to the normal memory cell transistor. The data on the number of times written in the memory cell transistor 308 for storing the number of times of writing / write is read by the sense amplifier circuit 307, and the read data is input to the counter circuit 309.

In the counter circuit 309, the number of times data is 1, 10, 100, 1000, 10,000, 10,000
When the number of times reaches a specific number such as zero, the sense amplifier circuit 307 is set to a verify detection level that is stricter than the read detection level, and is made to perform a verify determination. The subsequent operation based on the verification determination result is the same as that of the first embodiment.

With this configuration, the same effect as that of the first embodiment can be obtained even if the number of times of execution of the verify determination is reduced to the minimum. (Embodiment 3) FIG. 4 shows (Embodiment 3) of the present invention.

401 is an EEPROM, 402 is a memory cell transistor array, 403 is a control logic circuit, 404 is a booster circuit, 405 is a regulation circuit,
406 is a decoder circuit, 407 is a sense amplifier circuit,
08 is a data error detection / correction redundant memory cell transistor, and 409 is an error detection / correction circuit. The difference between the third embodiment and the first embodiment is that a redundant memory cell transistor 408 for data error detection and correction and an error detection and correction circuit 409 are added. Reference numeral 108 denotes a memory cell transistor for storing the regulation circuit set value shown in (Embodiment 1).

The difference between the operation of the apparatus of the present invention and the first embodiment will be described. Delete /
At the time of a write operation, the error detection / correction circuit 409 uses the data error detection / correction redundant memory cell transistor 408.
Then, data is written to the redundant memory cell transistor 408 for data error detection and correction at the same time as erasing / writing to the normal memory cell transistor.

In the read operation, the data of the redundant memory cell transistor 408 for data error detection and correction is read by the sense amplifier circuit 407 simultaneously with the data of the normal memory cell transistor, and the read data is read out by the error detection and correction circuit 409. Detect presence / absence.
If the detection result by the error detection and correction circuit 409 is a pass, the read data is normal, and even if the detection result is a failure, the data corrected by the error detection and correction circuit 409 is output. Becomes normal.

However, since it is possible to judge that the erasing / writing depth of the memory cell transistor is shallow based on the result of the correction by the error detection and correction circuit 409, the same as in the first embodiment Regulation circuit 4
05 control voltage is changed.

With this configuration, the same effect as that of the first embodiment can be obtained without performing the verify judgment. (Embodiment 4) FIG. 5 shows (Embodiment 4) of the present invention.

501 is a flash EEPROM, 502
Is a memory cell transistor array, 503 is a control logic circuit, 504 is a booster circuit, 505 is a regulation circuit, 506 is a decoder circuit, 507 is a sense amplifier circuit, and 509 is a verify circuit. Reference numeral 108 denotes a memory cell transistor for storing the regulation circuit set value shown in (Embodiment 1).

The difference between (Embodiment 4) and (Embodiment 1) is that a flash EEPROM is used and a verify circuit 509 is used. The difference between the operation of the device of the present invention and the first embodiment will be described.

When the verify operation becomes NG after performing a verify operation after a certain erase / write time,
It is configured to rewrite the data of the memory cell transistor that stores the control value of the voltage of the regulation circuit 505 included in the memory cell transistor array, and to set a high voltage to be used at the time of subsequent erasing / writing higher than the existing value. ing.

With this configuration, the same effect as in the first embodiment can be obtained in a flash EEPROM provided with a verify circuit 509. (Embodiment 5) In the inspection process of the nonvolatile memory device (EEPROM) of the above (Embodiment 1), the nonvolatile memory device is manufactured by executing the following process.

In the inspection process of the EEPROM, the erasing / writing depth of each product is verified, and based on the result, the control value of the voltage of the regulating circuit used at the time of erasing / writing is regulated for each product. The rate circuit set value is set in the memory cell transistor 108 for storage.

It goes without saying that the setting of the memory cell transistor 108 for storing the regulation circuit set value can be rewritten later according to the result of the verify judgment.
By this procedure, characteristic variations between products can be reduced. In addition, it can be similarly implemented in (Embodiment 2) to (Embodiment 4).

(Embodiment 6) FIG. 6 shows (Embodiment 6) of the present invention. 601 is an EEPROM, 602 is a memory cell transistor array, 603 is a control logic circuit, 604 is a booster circuit, 605 is a regulation circuit, 605 is a decoder circuit, 606 is a sense amplifier circuit, and 608 is an oscillation frequency storage of a clock signal generation circuit. A memory cell transistor 609 is a clock signal generation circuit.

(Embodiment 6) is different from (Embodiment 1) in that the memory cell transistor 608 for storing the oscillation frequency of the clock signal generation circuit and the clock signal generation circuit 60
9 is used. Reference numeral 108 denotes a memory cell transistor for storing the regulation circuit set value shown in (Embodiment 1).

Next, the difference between the operation of the apparatus according to the present invention and the first embodiment will be described.
A clock signal generating circuit 609 for boosting operation whose oscillation frequency can be changed is provided in a block of the boosting circuit 604, and a memory cell transistor 608 for storing the oscillation frequency of the clock signal generating circuit 609 is provided in the memory cell transistor array 602. If the erase / write depth does not satisfy the determination level set in the sense amplifier circuit 607, the nonvolatile memory cell storing the control value of the oscillation frequency of the clock signal generation circuit 609 included in the memory cell transistor array 602 The oscillation frequency of the clock signal generating circuit 609 for boosting operation used for erasing / writing after rewriting the data of the transistor is set higher than the existing value, and the control value of the voltage of the regulating circuit used for erasing / writing is set. Is configured to be higher than the existing value. To have.

With this configuration, it is possible to reduce the power consumption at the initial stage of the rewriting life of the EEPROM and to obtain the same effect as that of the first embodiment. (Embodiment 7) FIG. 7 shows (Embodiment 7) of the present invention.

701 is an EEPROM, 702 is a memory cell transistor array, 703 is a control logic circuit, 704 is a booster circuit, 705 is a regulation circuit,
706 is a decoder circuit, 707 is a sense amplifier circuit, 7
Reference numeral 08 denotes a memory cell transistor for storing a control value of the bias generation circuit, and reference numeral 709 denotes a bias generation circuit. 710 is a bias circuit of the memory cell transistor array 702. (Embodiment 7) is different from (Embodiment 1) in that a memory cell transistor 708 for storing a control value of a bias generation circuit and a bias generation circuit 709 are used. Reference numeral 108 denotes a memory cell transistor for storing the regulation circuit set value shown in (Embodiment 1).

Next, the difference between the operation of the apparatus of the present invention and the first embodiment will be described.
The sense amplifier circuit includes a bias generation circuit 709 capable of changing a drain applied voltage to a memory cell transistor at the time of reading, and a memory cell transistor array 702 including a memory cell transistor 708 for storing a control value of the bias generation circuit. If the erase / write depth does not satisfy the determination level set in the sense amplifier circuit, the data of the nonvolatile memory cell transistor storing the control value of the bias generation circuit 709 included in the memory cell transistor array 702 is stored. By providing a circuit for setting the drain applied voltage of the sense amplifier circuit 807 used at the time of reading after rewriting to a value higher than the existing value, the drain current is increased even after the drain current of the memory cell transistor is reduced due to rewriting of the EEPROM. Let it be Becomes possible, it is possible to lower power consumption at the initial stage of improving the rewriting life of the rewriting life of the EEPROM.

By the above operation, it is possible to reduce the power consumption at the initial stage of the rewriting life of the EEPROM and to obtain the same effect as that of the first embodiment. In this (Embodiment 7), the memory cell transistor 708 for storing control values and the bias generation circuit 7 are added to the configuration of (Embodiment 1).
Although the description has been made assuming that the configuration of No. 09 has been added, better performance can be obtained as compared with the related art even without the memory cell transistor 108 for storing the regulation circuit set value and its related parts.

[0052]

As described above, according to the EEPROM of the present invention, the voltage applied to the memory cell transistor is reduced in the initial stage of the rewriting life of the EEPROM, and the memory cell transistor is reduced in the middle and late stages of the rewriting life. The threshold voltage of the memory cell transistor required as the EEPROM can be secured by increasing the voltage applied to the EEPROM, and the normal operation can be ensured, thereby greatly improving the rewriting life of the EEPROM. There is an effect that can be done.

Further, in the initial stage of the rewriting life of the EEPROM, there is an effect that the oscillation frequency of the clock signal generating circuit for the boosting operation can be suppressed low to reduce the power consumption.

Further, in the initial stage of the rewriting life of the EEPROM, there is an effect that the drain application voltage of the sense amplifier circuit can be kept low to reduce the power consumption.

[Brief description of the drawings]

FIG. 1 shows an EEPROM according to a first embodiment of the present invention.
Configuration diagram of memory cell transistor array and its peripheral part

FIG. 2 is a diagram showing the number of rewrites and a change in Vt according to the embodiment;

FIG. 3 shows an EEPROM according to a second embodiment of the present invention.
Configuration diagram of memory cell transistor array and its peripheral part

FIG. 4 shows an EEPROM according to a third embodiment of the present invention.
Configuration diagram of memory cell transistor array and its peripheral part

FIG. 5 shows an EEPROM according to a fourth embodiment of the present invention.
Configuration diagram of memory cell transistor array and its peripheral part

FIG. 6 shows an EEPROM according to a sixth embodiment of the present invention.
Memory cell transistor array and its configuration diagram

FIG. 7 shows an EEPROM according to a seventh embodiment of the present invention.
Configuration diagram of memory cell transistor array and its peripheral part

FIG. 8 is a configuration diagram of a conventional memory cell transistor array of an EEPROM and its peripheral portion.

FIG. 9 is a diagram showing changes in the number of rewrites and Vt of a memory cell transistor of a conventional EEPROM.

[Explanation of symbols]

101, 301, 401, 601, 701 EEP
ROM 501 Flash EEPROM 102, 302, 402, 502, 602, 702
Memory cell transistor array 103, 303, 403 Control logic circuit 503, 603, 703 Control logic circuit 104, 304, 404, 504, 604, 704
Step-up circuit 105, 305, 405, 505, 605, 705
Regulation circuit 106, 306, 406, 506, 606, 706
Decoder circuit 107, 307, 407, 507, 607, 707
Sense amplifier circuit 108 Regulating circuit set value storage memory cell transistor 308 Erase / write count storage memory cell transistor 408 Data error detection and correction redundant memory cell transistor 608 Oscillation frequency storage memory cell transistor 708 of clock signal generation circuit 708 Bias generation Memory cell transistor 309 for storing control value of circuit 309 Counter circuit 409 Error detection and correction circuit 509 Verify circuit 609 Clock signal generation circuit 709 Bias generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 17/00 633D 633E 639C

Claims (8)

[Claims] 1. A decoder circuit for selecting a bit line and a word line of a memory cell transistor array around a memory cell transistor array composed of a group of electrically erasable / writable nonvolatile memory cell transistors. A sense amplifier circuit for reading data from the memory cell transistor array, a regulation circuit for controlling a high voltage necessary for erasing / writing and outputting the same to the decoder circuit, and a high voltage necessary for erasing / writing based on a control signal. A non-volatile memory device provided with a booster circuit that generates a voltage and a control logic circuit that controls a circuit operation based on a signal input from the outside, wherein the memory cell transistor array includes the regulation circuit A memory cell transistor for storing a voltage control value; The memory cell transistor and the sense amplifier are configured to change a read determination level during a normal read operation for reading data from a memory cell transistor array and during a verify read operation for verifying erase / write depth. After the erase / write operation, the sense amplifier circuit verifies the erase / write depth by the circuit and the regulation circuit. If the erase / write depth does not satisfy the determination level, the data of the memory cell transistor is rewritten. A non-volatile memory device configured to set a high voltage to be used at the time of subsequent erasing / writing higher than an existing value. 2. A decoder circuit for selecting a bit line and a word line of the memory cell transistor array around a memory cell transistor array composed of a group of electrically erasable / writable nonvolatile memory cell transistors. A sense amplifier circuit for reading data from the memory cell transistor array, a regulation circuit for controlling a high voltage necessary for erasing / writing and outputting the same to the decoder circuit, and a high voltage necessary for erasing / writing based on a control signal. A non-volatile memory device provided with a booster circuit that generates a voltage and a control logic circuit that controls a circuit operation based on a signal input from the outside, wherein the memory cell transistor array includes the regulation circuit A first memory cell transistor for storing a voltage control value; The Njisuta array providing the second memory cell transistors for storing the erase / write count, stored in said second memory cell transistor erase /
A counter circuit for verifying an erasing / writing depth to the sense amplifier circuit when the number of times of writing matches a predetermined number of times set in advance; and providing the first and second memory cell transistors with the sense circuit. An amplifier circuit, the regulation circuit, and the counter circuit verify the erasing / writing depth by the sense amplifier circuit at a constant erasing / writing frequency, and when the erasing / writing depth does not satisfy the determination level, A nonvolatile memory device configured to set a high voltage used at the time of erasing / writing after rewriting data of a memory cell transistor higher than an existing value. 3. A decoder circuit for selecting a bit line and a word line of the memory cell transistor array around a memory cell transistor array composed of electrically erasable / writable nonvolatile memory cell transistor groups. A sense amplifier circuit for reading data from the memory cell transistor array, a regulation circuit for controlling a high voltage necessary for erasing / writing and outputting the same to the decoder circuit, and a high voltage necessary for erasing / writing based on a control signal. A non-volatile memory device provided with a booster circuit that generates a voltage and a control logic circuit that controls a circuit operation based on a signal input from the outside, wherein the memory cell transistor array includes the regulation circuit A first memory cell transistor for storing a voltage control value; A redundant memory cell transistor for data error detection and correction is provided in the transistor array, writing is performed to the redundant memory cell transistor for data error detection and correction during an erase / write operation, and the memory cell is transmitted via the sense amplifier circuit during a read operation. An error detection and correction circuit is provided for reading data from the transistor array and detecting the presence or absence of an error in the read data. If the error is detected during a read operation, the data in the first memory cell transistor is rewritten. A non-volatile memory device configured to set a high voltage used for erasing / writing to a higher value than an existing value. 4. A flash EEPROM type having a verify circuit and performing rewrite while verifying the erase / write depth by the verify operation each time the erase / write time is applied in a plurality of times during the erase / write operation. Item 2. The non-volatile memory device according to Item 1, wherein when a verify operation is performed after a certain erase / write time and the verification becomes NG, the data of the memory cell transistor is rewritten and used for subsequent erase / write. A non-volatile memory device configured to set a high voltage to be higher than an existing value. 5. A decoder circuit for selecting a bit line and a word line of the memory cell transistor array around a memory cell transistor array composed of a group of electrically erasable / writable nonvolatile memory cell transistors. A sense amplifier circuit for reading data from the memory cell transistor array, a regulation circuit for controlling a high voltage necessary for erasing / writing and outputting the same to the decoder circuit, and a high voltage necessary for erasing / writing based on a control signal. When manufacturing a non-volatile memory device provided with a booster circuit for generating a voltage and a control logic circuit for controlling the circuit operation based on an externally input signal, erasing / writing individual products in an inspection process Based on the verification result of the depth, the control value of the voltage of the regulator And a method of manufacturing a nonvolatile memory device in which a control value of a voltage of the regulation circuit provided in the memory cell transistor array is individually set in a memory cell transistor storing the control value. 6. An erasing / writing depth, comprising: a clock signal generation circuit capable of changing an oscillation frequency of a booster circuit; and a nonvolatile memory cell transistor for storing a control value of the oscillation frequency of the clock signal generation circuit. Does not satisfy the determination level set in the sense amplifier circuit, the oscillation frequency of the clock signal generation circuit for the boosting operation used at the time of erasing / writing after rewriting the data of the memory cell transistor is set lower than the existing value. 2. The nonvolatile memory device according to claim 1, wherein the control value of the voltage of the regulation circuit used at the time of erasing / writing is set higher than the existing value. 7. A erasing / writing depth, comprising: a bias generating circuit capable of changing a voltage applied to a memory cell transistor array at the time of reading; and a nonvolatile memory cell transistor storing a control value of the bias generating circuit. If the data does not satisfy the determination level set in the sense amplifier circuit, the data in the nonvolatile memory cell transistor that stores the control value of the bias circuit of the memory cell transistor array is rewritten and the memory cell at the time of subsequent reading is rewritten. 2. The non-volatile memory device according to claim 1, wherein the voltage applied to the transistor array can be changed from an existing value. 8. A decoder circuit for selecting a bit line and a word line of the memory cell transistor array around a memory cell transistor array composed of electrically erasable / writable nonvolatile memory cell transistor groups. A sense amplifier circuit for reading data from the memory cell transistor array, a regulation circuit for controlling a high voltage necessary for erasing / writing and outputting the same to the decoder circuit, and a high voltage necessary for erasing / writing based on a control signal. A nonvolatile memory device provided with a booster circuit for generating a voltage and a control logic circuit for controlling a circuit operation based on an externally input signal, wherein the voltage applied to the memory cell transistor array at the time of reading is controlled. A bias generation circuit that can be changed, and a nonvolatile memory that stores a control value of the bias generation circuit. A memory cell transistor, wherein when the erasing / writing depth does not satisfy the determination level set in the sense amplifier circuit, data of a nonvolatile memory cell transistor storing a control value of a bias circuit of the memory cell transistor array A non-volatile memory device configured so that the voltage applied to the memory cell transistor array at the time of reading after rewriting can be changed from an existing value.