JP2002270794A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: When a dielectric film formed on a lower electrode of a DRAM capacitive element is heat-treated in an oxygen atmosphere, oxygen transmitted through the lower electrode oxidizes a barrier layer to form a high-resistance layer. To prevent malfunctions. SOLUTION: A lower electrode 31 made of a TaN film and a Ru film deposited on the TaN film is formed in a groove 27 formed in a silicon oxide film 24, and then a CV is formed on the lower electrode 31.
After depositing the tantalum oxide film 32a by the method D, in order to achieve crystallization of the tantalum oxide film 32a and to improve the film quality, a heat treatment at 300 to 400 ° C. is performed in an atmosphere containing oxygen to remove polycrystalline silicon. Plug 22 and lower electrode 31
To prevent the formation of a high-resistance oxide layer between them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a DRAM (Dynamic Random Access Memory).
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having an access memory.

[0002]

2. Description of the Related Art Generally, memory cells of a DRAM are arranged at intersections of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. One memory cell is connected to one MISFET (Metal
Insulator Semiconductor Field Effect Transistor)
And one information storage capacitor (capacitor) connected in series to the MISFET.

A memory cell selecting MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate insulating film, a gate electrode integrally formed with a word line, and a pair of semiconductors forming a source and a drain. It is composed of regions. MISFET for memory cell selection
Usually, two are formed in one active region, and these two MIs
One of the source and the drain (semiconductor region) of the SFET is shared in the center of the active region.

The bit line is connected to the memory cell selecting MIS.
It is arranged above the FET and is electrically connected to one of a source and a drain (semiconductor region) (a semiconductor region shared by two MISFETs) through a connection hole in which a plug made of polycrystalline silicon or the like is embedded. The information storage capacitor is disposed above the bit line, and is electrically connected to the other of the source and drain (semiconductor region) of the memory cell selection MISFET through a connection hole in which a plug made of polycrystalline silicon or the like is embedded. Connected to.

As described above, in recent DRAMs, as a countermeasure to compensate for the decrease in the amount of stored charge due to the miniaturization of memory cells,
A three-dimensional structure in which an information storage capacitor is arranged above a bit line is employed. However, in the case of a large-capacity DRAM of 256 megabits or more, in which the miniaturization of memory cells is further advanced, it is considered that it is difficult to compensate for a decrease in the amount of stored charges only by making the information storage capacitor three-dimensional.

Therefore, it has been studied to employ a high dielectric material such as tantalum oxide (Ta ₂ O ₅ ) as a dielectric film of the information storage capacitor. A high dielectric material such as a tantalum oxide film cannot obtain a high relative dielectric constant simply by forming a film, and has a large leak current. It is necessary to improve the film quality and film quality. Therefore, when a high-dielectric material is used for the dielectric film of the information storage capacitor, a problem such as a change in the characteristics of the MISFET due to the high-temperature heat treatment occurs.

Therefore, when a high dielectric material is used for the dielectric film, a platinum group metal represented by Ru (ruthenium) is used for the lower electrode serving as a base. This is because a high (dielectric film deposited on a platinum group metal surface, 65
Since the crystallization of the film and the improvement of the film quality can be achieved by a heat treatment at a temperature lower by 100 ° C. or more than a normal heat treatment of 0 ° C. to 600 ° C., the amount of heat treatment in the whole manufacturing process can be reduced, and M
This is because the characteristic fluctuation of the ISFET can be prevented.

On the other hand, when the above-mentioned platinum group metals are used as the lower electrode material, since these materials are easily permeable to oxygen, oxygen is formed after forming a high dielectric film on the surface of the lower electrode. When heat treatment is performed in an atmosphere, oxygen passes through the high dielectric film and the lower electrode and reaches the silicon plug therebelow, and the platinum group metal and silicon react with each other to form an undesirable metal silicide at the interface between the two. There is a problem that a resistance layer is formed. As a countermeasure, it has been proposed to form a barrier layer between the lower electrode made of a platinum group metal and the silicon plug to prevent a reaction between them.

Japanese Patent Application Laid-Open No. 10-79481 discloses a method of reflowing and flattening a silicon oxide film at 700 to 800 ° C.
To prevent the platinum group metal and silicon from interdiffusing due to the heat treatment to form a metal silicide layer, and further to prevent the metal silicide layer from being oxidized to form a silicon oxide layer having a small dielectric constant. Ti (titanium), W (tungsten), Ta as barrier layers
(Tantalum), Co (Cobalt), Mo (Molybdenum)
For example, a conductive layer (metal silicon nitride layer) containing a high melting point metal such as silicon and nitrogen has been proposed. It is said that this barrier layer is preferably a laminate of a first layer containing columnar crystals or amorphous and a second layer containing granular crystals. It is also preferable that a layer containing Ti for improving the adhesion between the barrier layer and the silicon plug is formed between the barrier layer and the silicon plug.

Japanese Patent Application Laid-Open No. Hei 10-209394 discloses that when a lower electrode is formed above a connection hole in which a silicon plug is embedded and a mask misalignment occurs between the two, a dielectric film formed above the lower electrode and a lower film are formed. As a result of contact with the silicon plug under the electrode, oxygen and silicon in the dielectric film react with each other to form a high-resistance silicon oxide film, or insufficient oxygen in the dielectric film increases leakage current. Point out the problem. As a countermeasure, this publication discloses a technique of providing a blocking film made of silicon nitride between a dielectric film and a silicon plug.

Japanese Patent Application Laid-Open No. 11-307736 relates to a ferroelectric memory, in which a lower electrode made of iridium oxide (IrO _x ) is formed on a silicon plug.
When forming a capacitive element composed of a dielectric film made of a ferroelectric material such as ZT (lead zirconate titanate) and an upper electrode made of a white metal such as Pt, tantalum is formed as a diffusion barrier layer above a silicon plug. A technique of forming a silicon nitride (TaSiN) film and forming an Ir film as an oxygen blocking film on the diffusion barrier layer is disclosed.

[0012]

As described above, in the prior art, after a lower electrode made of a platinum group metal is formed above a connection hole in which a silicon plug is buried, a high dielectric film is formed on the lower electrode. When heat treatment is performed, an undesirable reaction between the platinum group metal and the silicon plug is prevented by forming a barrier layer on the silicon plug in advance.

However, even when the barrier layer is formed on the silicon plug, if the heat treatment of the high dielectric film is performed in a high-temperature oxygen atmosphere, the oxygen transmitted through the lower electrode oxidizes the barrier layer itself, and There is a problem that an oxide layer having a low resistance and a low dielectric constant is formed.

Further, the present inventors have deposited a thick silicon oxide film over the connection hole in which the silicon plug is embedded,
Next, the silicon oxide film is etched to form a deep groove reaching the surface of the silicon plug, and then a lower electrode is formed by depositing a platinum group metal film on the inner wall of the groove. In addition, the present inventors have found a problem that peeling may occur between the lower electrode and the silicon oxide film during the manufacturing process due to low adhesiveness between the platinum group metal film and the silicon oxide film.

An object of the present invention is that when a dielectric film formed on a lower electrode of a capacitor is heat-treated in an oxygen atmosphere, oxygen transmitted through the lower electrode oxidizes a barrier layer to form a high resistance layer. It is an object of the present invention to provide a technology for preventing such a problem.

Another object of the present invention is to provide a technique for improving the adhesion between a platinum group metal film and a silicon oxide film constituting a lower electrode of a capacitor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a capacitive element including a pair of electrodes and a dielectric film sandwiched between the electrodes is formed with the inner wall of a groove formed in an insulating film as a main capacitive region. Forming a lower electrode made of a tantalum nitride film and a ruthenium film formed on the inner surface of a groove formed in the insulating film; and forming a lower electrode on the insulating film including a surface of the lower electrode. Depositing a tantalum oxide film by a CVD method, and then performing a heat treatment in an atmosphere containing oxygen to improve crystallization and film quality of the tantalum oxide film, and an upper electrode on the tantalum oxide film. And the step of forming

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a DRAM according to this embodiment will be described in the order of steps with reference to FIGS. In the DRAM manufacturing process described below, a memory cell selecting MISFET is formed on a main surface of a semiconductor substrate (hereinafter, referred to as a substrate), and then a memory cell selecting MISFET is formed.
The process up to the formation of the bit line above the FET is described in detail in, for example, Japanese Patent Application No. 11-166320 (Matsuoka et al.).

First, FIG. 1 (a plan view of a main part of the memory array), FIG. 2 (a cross-sectional view along the line AA in FIG. 1), FIG.
As shown in FIG. 1 (cross-sectional view along line BB in FIG. 1) and FIG. 4 (cross-sectional view along line CC in FIG. 1), the main surface of the substrate 1 made of, for example, p-type single crystal silicon The element isolation groove 2 is formed in the element isolation region. The element isolation groove 2 is formed by etching the surface of the substrate 1 to form a groove having a depth of about 300 to 400 nm. Then, the CVD (C) is formed on the substrate 1 including the inside of the groove.
After depositing a silicon oxide film 4 (thickness of about 600 nm) by a chemical vapor deposition (chemical vapor deposition) method, the silicon oxide film 4 is subjected to chemical mechanical polishing (CMP).
It is formed by polishing and flattening by a method. The silicon oxide film 4 is deposited by a plasma CVD method using, for example, oxygen (or ozone) and tetraethoxysilane (TEOS) as a source gas, and then is subjected to dry oxidation at about 1000 ° C. to densify the film (densification). ).

As shown in FIG. 1, by forming the element isolation groove 2, a large number of elongated island-shaped active regions (L) surrounded by the element isolation groove 2 are simultaneously formed. As described later, each of these active regions (L) is formed with two memory cell selecting MISFETs Qs sharing one of a source and a drain.

Next, a p-type well 3 is formed by ion-implanting B (boron) into the substrate 1 and then p-type well 3 is formed.
After cleaning the surface of the p-type well 3 with a HF (hydrofluoric acid) -based cleaning solution, the substrate 1 is thermally oxidized to form a silicon oxide-based clean gate insulating film 5 on the surface of the active region (L) of the p-type well 3. (Thickness: about 6 nm). Note that the gate insulating film 5 is not only a silicon oxide-based insulating film formed by thermal oxidation of the substrate 1, but also a silicon nitride-based insulating film and a metal oxide-based insulating film (a tantalum oxide film, an oxide Titanium film). These high dielectric insulating films are formed on the substrate 1 by a CVD method or a sputtering method.

Next, as shown in FIGS. 5 to 7, a gate electrode 6 is formed on the gate insulating film 5. Gate electrode 6
Functions as a word line (WL) in an area other than the active area (L). The gate electrode 6 (word line WL) is, for example, an n-type polycrystalline silicon film (about 70 nm thick) doped with P (phosphorus) or the like on the gate insulating film 5, WN (tungsten nitride) or TiN (titanium nitride) , A W (tungsten) film (about 100 nm in thickness) and a silicon nitride film 7 (about 150 nm in thickness) are sequentially deposited, and then, using a photoresist film as a mask, Is formed by dry-etching the film. The polycrystalline silicon film and the silicon nitride film 7 are deposited by a CVD method, and the barrier metal film and the W film are deposited by a sputtering method.

Next, as shown in FIGS. 8 to 10, As (arsenic) or P (phosphorus) is ion-implanted into the p-type well 3 and the n-type semiconductor region is formed in the p-type well 3 on both sides of the gate electrode 6. 8 (source, drain) is formed. Through the steps so far, the memory cell selecting MISFET Qs is substantially completed.

Next, as shown in FIGS. 11 to 14, a silicon nitride film 9 (thickness: 50 nm) and a silicon oxide film 10 (thickness: approximately 600 nm) are deposited on the substrate 1 by the CVD method. After the surface of the silicon film 10 is flattened by a chemical mechanical polishing method, the silicon oxide film 10 and the silicon nitride film 9 are dry-etched using a photoresist film (not shown) as a mask, thereby forming a memory cell selecting M.
Contact holes 11 and 12 are formed above the source and drain (n-type semiconductor region 8) of ISFET Qs.
The etching of the silicon oxide film 10 is performed under the condition that the selectivity to silicon nitride is large, and the etching of the silicon nitride film 9 is performed under the condition that the etching selectivity to silicon or silicon oxide is large. Thereby, the contact holes 11 and 12 can be formed by self-alignment (self-alignment) with the gate electrode 6 (word line WL).

Next, as shown in FIG. 15 and FIG.
A plug 13 is formed inside the contact holes 11 and 12. To form the plug 13, the silicon oxide film 10
P-doped n-type polycrystalline silicon film on top of
Contact holes 11 and 12
After the n-type polycrystalline silicon film is embedded in the inside of the substrate, the n-type polycrystalline silicon film outside the contact holes 11 and 12 is removed by a chemical mechanical polishing method (or dry etching).

Next, CVD is performed on the silicon oxide film 10.
After depositing a silicon oxide film 14 (having a thickness of about 150 nm) by a method, as shown in FIGS. 17 to 19, the silicon oxide film 14 above the contact hole 11 is formed using a photoresist film (not shown) as a mask. By dry etching, a through hole 15 for connecting a bit line (BL) formed in a later step and the contact hole 11 is formed.
To form

Next, as shown in FIGS. 20 and 21,
A plug 16 is formed inside the through hole 15. In order to form the plug 16, a barrier metal film made of TiN is deposited on the silicon oxide film 14 by, for example, a sputtering method, and then W is deposited on the barrier metal film by a CVD method.
After embedding these films inside the through holes 15 by depositing films, these films outside the through holes 15 are removed by chemical mechanical polishing.

Next, as shown in FIGS. 23 to 25, a bit line BL is formed on the silicon oxide film 14. In order to form the bit line BL, for example, a TiN film (about 10 nm thick) is deposited on the silicon oxide film 14 by a sputtering method, and then a W film (about 50 nm thick) is formed on the TiN film by a CVD method. Are deposited, these films are dry-etched using the photoresist film as a mask. The bit line BL is connected to the source / drain (n-type semiconductor region 8) of the memory cell selection MISFET Qs via the plug 16 embedded in the lower through hole 15 and the plug 13 embedded in the lower contact hole 11. Is electrically connected to one of them.

Next, as shown in FIGS. 26 to 29, a silicon oxide film 17 having a thickness of about 300 nm and a silicon nitride film 18 having a thickness of about 200 nm are deposited on the bit line BL by CVD. Resist film (not shown)
The silicon nitride film 18 and the silicon oxide film 17 are dry-etched using
A through hole 19 is formed above the contact hole 11 in which is embedded.

The through hole 19 is formed such that its diameter is smaller than the diameter of the contact hole 11 thereunder. Specifically, the CVD is performed on the silicon nitride film 18.
After a polycrystalline silicon film 20 is deposited by a method and a hole is formed by dry-etching the polycrystalline silicon film 20 in a region where a through hole 19 is to be formed, the polycrystalline silicon film 20 is formed.
A polycrystalline silicon film (not shown) is further deposited on the upper surface. Next, a sidewall spacer 21 is formed on the side wall of the hole by anisotropically etching the polycrystalline silicon film on the polycrystalline silicon film 20. Subsequently, the polycrystalline silicon film 20 and the sidewall spacer 21 are masked. The silicon nitride film 18 and the silicon oxide film 17 at the bottom of the hole are dry-etched.

As shown in FIGS. 26 and 29,
The center of the through hole 19 is offset from the center of the lower contact hole 11 in a direction away from the bit line BL. As described above, the diameter of the through hole 19 is made smaller than the diameter of the contact hole 11 thereunder, and the center thereof is offset in a direction away from the bit line BL, so that even when the memory cell size is reduced, self-alignment is achieved. Contact (Self Align Contac
t; SAC) without using the through hole 19
(A plug 22 embedded inside) and the bit line BL can be prevented from being short-circuited. Further, by making the diameter of the through hole 19 smaller than the diameter of the contact hole 11 therebelow, a sufficient contact area between them can be ensured even if their centers are shifted.

Next, after the mask (polycrystalline silicon film 20 and side wall spacer 21) used to form through hole 19 is removed by dry etching, FIGS.
As shown in FIG. 32, a plug 22 is formed inside the through hole 19. In order to form the plug 22, first, an n-type polycrystalline silicon film doped with P is deposited on the silicon nitride film 18 by a CVD method, so that the n-type polycrystalline silicon film is buried in the through hole 19. Subsequently, the n-type polycrystalline silicon film outside the through hole 19 is removed by a chemical mechanical polishing method (or dry etching).

Next, as shown in FIGS. 33 and 34,
The thickness of 1500 n is formed on the silicon nitride film 18 by the CVD method.
An about m silicon oxide film 24 is deposited. The lower electrode 28 of the information storage capacitor C is formed inside the groove 27 formed in the silicon oxide film 24 in the next step. Therefore,
Since the thickness of the silicon oxide film 24 is the height of the lower electrode 28, the silicon oxide film 24 is deposited with a large thickness in order to increase the surface area of the lower electrode 28 and increase the amount of accumulated charges. The silicon oxide film 24 is deposited by a plasma CVD method using, for example, oxygen and tetraethoxysilane (TEOS) as a source gas, and then, if necessary, its surface is flattened by a chemical mechanical polishing method.

Next, as shown in FIGS. 35 to 37, the silicon oxide film 24 is dry-etched using a photoresist film (not shown) as a mask, so that the bottom of the plug 22 in the through hole 19 is formed. Groove 2 with exposed surface
7 is formed. As shown in FIG. 35, the groove 27 is formed of a rectangular planar pattern having a long side in the extending direction of the word line WL and a short side in the extending direction of the bit line BL.

Next, as shown in FIG. 38, a TaN film 28 is deposited on the silicon oxide film 24 on which the deep groove 27 is formed by a sputtering method, and then, as shown in FIG.
An R film having a thickness of about 20 nm is formed on the TaN film 28 by CVD.
A u film 29 is deposited. The Ru film 29 is made of, for example, ethylcyclopentadienyl ruthenium (hereinafter referred to as Ru (EtC) dissolved in an organic solvent such as tetrahydrofuran (THF).
p) ₂ ) is vaporized at about 250 ° C. and decomposed with oxygen.

Next, as shown in FIG. 40, after the insulating film 30 is embedded in the groove 27, the TaN film 28 and the Ru film 29 outside the groove 27 not covered with the insulating film 30 are dry-etched. By the removal, the lower electrode 31 of the information storage capacitor composed of the TaN film 28 and the Ru film 29 is formed inside the groove 27. Insulating film 30
Is made of an insulating material having a large etching selectivity to the silicon oxide film 24, for example, a photoresist or a spin-on glass. When the insulating film 30 is formed of a photoresist, a positive photoresist film is spin-coated on the inside of the groove 27 and on the silicon oxide film 24, and then the entire surface is exposed and developed to expose the exposed portion outside the groove 27. It may be removed, and an unexposed portion may be left inside the groove 27.

Next, after removing the insulating film 31 inside the groove 27, as shown in FIG. 41, a film having a thickness of 5 is formed on the inner wall of the groove 27 where the lower electrode 31 is formed and the surface of the silicon oxide film 24.
A tantalum oxide film 32a of about 10 to 10 nm is deposited. The tantalum oxide film 32a is formed, for example, by using C as a source gas using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) and oxygen.
Deposition by the VD method, and then heat treatment at 300 to 400 ° C. in an atmosphere containing oxygen and heat treatment at about 700 ° C. in a non-oxidizing atmosphere in order to improve crystallization and film quality of the film. Do.

Next, as shown in FIG. 42, a film thickness of 5 to 10 nm is formed on the surface of the tantalum oxide film 32a by the same method as described above.
After depositing the tantalum oxide film 32b to the extent, the upper electrode 33 made of a Ru film is formed on the tantalum oxide film 32b. The heat treatment is not necessarily required for the tantalum oxide film 32b deposited on the surface of the crystallized tantalum oxide film 32a because the crystallization has already been completed (homoepitaxial growth) when the film formation is completed. Also, the upper electrode 3
In order to form 3, for example, a Ru film deposited by the CVD method is buried in the trench 27, and then a Ru film is deposited thereon by a sputtering method. The upper electrode material is not limited to Ru, and may be made of, for example, a metal such as W, Ru, Pt, Ir, or a laminate of these metals and TiN.

By the steps so far, the lower electrode 31 and
An information storage capacitor C composed of a dielectric film composed of two layers of tantalum oxide films 32a and 32b and an upper electrode 33
Is completed, and a memory cell composed of the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to this is substantially completed. Thereafter, the information storage capacitor C
, An Al wiring of about two layers is formed with an interlayer insulating film interposed therebetween, and a passivation film is formed on the uppermost Al wiring, but these are not shown.

When a barrier layer is provided on the surface of the plug 22 made of polycrystalline silicon, and a lower electrode made of Ru is formed on the barrier layer, the tantalum oxide film 32a is formed in an atmosphere containing oxygen. When performing heat treatment,
An oxide layer is formed on the surface of the barrier layer. This oxide film
Even if the film thickness is extremely small, the surface area of the plug 22 is extremely small, and as a result, the resistance at the interface between the barrier layer and the lower electrode becomes large, and there is a possibility that conduction failure may occur.

On the other hand, in this embodiment, since the lower electrode 31 including the TaN film 28 is formed on the plug 22 made of polycrystalline silicon, the tantalum oxide film 3
When the heat treatment of 2a is performed, no oxide layer is formed on the surface of the plug 22. On the other hand, the tantalum oxide film 32
When the heat treatment a is performed, an oxide layer is formed at the interface between the TaN film 28 and the Ru film 29 constituting the lower electrode 31, and the area of this interface is as large as the surface area of the information storage capacitive element C. Therefore, this is equivalent to connecting two capacitive elements having the same area in series.

Further, Ta constituting a part of the lower electrode 31 is
The N film 28 also functions as an adhesive layer between the Ru film 29 and the silicon oxide film 24 that constitute another part. Ru film 29
Has a poor adhesion to the silicon oxide film 24, and when deposited directly on the silicon oxide film 24, peeling may occur due to heat treatment. However, a TaN film is formed between the Ru film 29 and the silicon oxide film 24. With the interposition of, such a problem can be prevented.

(Embodiment 2) In the manufacturing method of this embodiment, the steps (the steps of FIGS. 1 to 37) until the groove 27 is formed in the silicon oxide film 24 are the same as those of the first embodiment. Therefore, the description thereof will be omitted, and only the subsequent steps will be described.

First, following the step shown in FIG. 37, as shown in FIG. 43, a TaN film 28 is deposited on the silicon oxide film 24 in which the groove 27 is formed by a sputtering method. Subsequently, as shown in FIG. 44, after the insulating film 30 is embedded in the groove 27, the TaN film 28 outside the groove 27 not covered with the insulating film 30 is removed by dry etching. TaN film 28 remaining inside groove 27
Constitutes the lower electrode of the information storage capacitor.

Next, after removing the insulating film 30 inside the groove 27, as shown in FIG.
By performing a heat treatment at 700 ° C. and oxidizing the surface of the TaN film (lower electrode) 28, the TaN film (lower electrode) 28
Tantalum oxide film 32 having a thickness of about 10 to 15 nm
Form c. The tantalum oxide film 32c forms a dielectric film of the information storage capacitor. The oxidation of the TaN film 28 can arbitrarily select the thickness of the tantalum oxide film 32c by controlling the type, concentration, oxidation temperature, and the like of the oxidizing agent.

Next, as shown in FIG. 46, a second tantalum oxide film 32 is formed on the surface of the tantalum oxide film 32c by the CVD method.
Deposit d. This tantalum oxide film 32d is deposited as needed, but may be omitted in some cases.

Next, as shown in FIG. 47, the upper electrode 3 made of a Ru film is formed on the surface of the tantalum oxide film 32c (or the tantalum oxide film 32d) in the same manner as in the first embodiment.
Form 3 By the steps so far, the information storage capacitor composed of the lower electrode made of the TaN film 28, the dielectric film made of the tantalum oxide film 32c (or the two tantalum oxide films 32c and 32b), and the upper electrode 33 Element C
Is completed, and a memory cell composed of the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to this is substantially completed.

In the present embodiment, the lower electrode T
The aN film 28 is oxidized to form a tantalum oxide film 32c on its surface.
Is formed. The tantalum oxide film 32c formed by this method has a feature of extremely high crystallinity. That is, a tantalum oxide film crystallized by performing a heat treatment after being deposited by a CVD method shows various crystal orientations when observed by an X-ray diffraction method, but a tantalum oxide film obtained by oxidizing a TaN film is: It is strongly oriented to (001) and has little variation in crystallinity. Therefore, by using such a tantalum oxide film as a dielectric film, it is possible to realize an information storage capacitor C having a smaller leak current and a large charge capacity. Also in the present embodiment, similarly to the first embodiment, it is possible to avoid a problem that a high-resistance oxide layer is formed on the surface of the plug 22 made of polycrystalline silicon.

As described above, the dielectric film may have a two-layer structure of the tantalum oxide film 32c and the tantalum oxide film 32d deposited thereon by the CVD method.
The tantalum oxide film 32d deposited by the CVD method has a property of being amorphous when the base is amorphous and being crystalline when the base is crystalline. In the case of the present embodiment, since the underlying tantalum oxide film 32c has high crystallinity and is strongly oriented to (001), the tantalum oxide film 32d also has high crystallinity, and
It is oriented strongly in 1). Therefore, the dielectric film is formed by such a method.
With the layered structure, the information storage capacitor C with less leakage current can be realized. The dielectric film is
It is also possible to have a multilayer structure of three or more layers.

(Embodiment 3) In the manufacturing method of the present embodiment, the steps up to forming the groove 27 in the silicon oxide film 24 (the steps of FIGS. 1 to 37) are the same as those of the first embodiment. Therefore, the description thereof will be omitted, and only the subsequent steps will be described.

First, following the step shown in FIG. 37, as shown in FIG. 48, a TaN film 28 is deposited on the silicon oxide film 24 in which the groove 27 is formed by a sputtering method. After the insulating film 30 is embedded therein, the TaN outside the trench 27 not covered with the insulating film 30 is formed.
By removing the film 28 by dry etching, a lower electrode made of the TaN film 28 is formed inside the groove 27.

Next, as shown in FIG. 49, the lower electrode (T
A Ru film 34 is deposited by sputtering or CVD inside the trench 27 where the aN film 28) is formed and on the silicon oxide film 24. This Ru film 34 constitutes a part of the upper electrode.

Next, as shown in FIG. 50, a heat treatment is performed in an oxidizing atmosphere to form a dielectric film made of a tantalum oxide film 32d on the interface between the lower electrode (TaN film 28) and the upper electrode (Ru film 34). To form Since the Ru film 34 has a property of extremely high oxygen permeability, the surface of the underlying TaN film 28 can be oxidized by using this property to form the tantalum oxide film 32d constituting the dielectric film.

Various oxidation conditions for the TaN film 28 can be selected, but if the temperature is 600 ° C. or more, the tantalum oxide film 32 d
Can be crystallized. At this time, since the Ru film 34 is also oxidized to some extent, the heat treatment may be performed in a reducing atmosphere containing hydrogen, ammonia, or the like. Also, R
In order to prevent oxidation of the u film 34, 30
After performing the heat treatment at about 0 to 400 ° C. to form the tantalum oxide film 32 d on the surface of the TaN film 28, the heat treatment may be performed at 600 ° C. or more in a non-oxidizing atmosphere for crystallization.

Next, as shown in FIG. 51, a second Ru film 36 is deposited on the Ru film 34. Through the steps so far, the information storage capacitor C composed of the lower electrode made of the TaN film 28, the dielectric film made of the tantalum oxide film 32d, and the upper electrode made of the Ru films 34 and 36 is completed. A memory cell composed of the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to this is substantially completed.

As described above, by using the Ru film for the upper electrode, a dielectric can be formed after the upper electrode is formed.

(Embodiment 4) In the manufacturing method of the present embodiment, the steps up to the formation of the groove 27 in the silicon oxide film 24 (the steps of FIGS. 1 to 37) are the same as those of the first embodiment. Therefore, the description thereof will be omitted, and only the subsequent steps will be described.

First, following the step shown in FIG. 37, as shown in FIG. 52, a polycrystalline silicon film 37 is deposited on the silicon oxide film 24 in which the groove 27 is formed by the CVD method. The polycrystalline silicon film 37 has the same conductivity type (for example, n-type) as the polycrystalline silicon film forming the plug 22 thereunder.

Next, as shown in FIG. 53, a Ru film 29 is deposited on the polycrystalline silicon film 37 by the CVD method, and subsequently, as shown in FIG. 54, the insulating film 30 is embedded in the trench 27. After that, the Ru film 29 and the polycrystalline silicon film 37 outside the groove 27 not covered with the insulating film 30 are removed by dry etching, so that the R
A lower electrode composed of the u film 29 and the polycrystalline silicon film 37 is formed.

Next, as shown in FIG. 55, T is formed inside the groove 27 where the lower electrode is formed and on the silicon oxide film 24.
After depositing the aN film 35, as shown in FIG. 56, a heat treatment is performed in an oxidizing atmosphere to turn the TaN film 35 into a tantalum oxide film 35a.

Next, as shown in FIG. 57, a second tantalum oxide film 35 is formed on the tantalum oxide film 35a by CVD.
After depositing b, an upper electrode 33 made of a Ru film is formed on the tantalum oxide film 35b. Through the steps so far, the information storage capacitance element C is completed, and the memory cell composed of the memory cell selection MISFET Qs and the information storage capacitance element C connected in series to this is substantially completed.

The CVD is performed on the Ru film deposited by the CVD method.
When a tantalum oxide film is deposited by a method and crystallized by heat treatment of the tantalum oxide film, it is difficult to orient (001) strongly. However, as in this embodiment, the Ru film 2
When the TaN film 35 deposited on the substrate 9 is oxidized, (0
Since the tantalum oxide film 35a oriented to (01) is obtained, the second tantalum oxide film 35b deposited on the surface can also be oriented to (001).

As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described first to fourth embodiments, and does not depart from the gist of the invention. It goes without saying that various changes can be made.

In the first to fourth embodiments, the case where the present invention is applied to a DRAM manufacturing process has been described.
The present invention can be applied not only to the RAM but also to a logic embedded DRAM.

[0068]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the representative configuration of the above-described embodiment, it is possible to avoid a problem that a high-resistance layer is formed between the lower electrode of the information storage capacitor and the plug therebelow, so that the MIM structure is provided. Having information storage capacitance element
AM reliability and manufacturing yield can be improved.

By oxidizing the TaN film,
By forming a (001) -oriented tantalum oxide film and using it as a dielectric of an information storage capacitor,
A DRAM with less leakage current can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a plan view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a plan view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 17 is a fragmentary plan view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 22 is a plan view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 26 is a main-portion plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 27 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 32 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 35 is an essential part plan view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 37 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 39 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 40 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 41 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 42 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 44 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 45 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 46 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 47 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to another embodiment of the present invention;

FIG. 48 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 49 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to another embodiment of the present invention;

FIG. 50 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 51 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 52 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 53 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 54 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 55 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 56 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 57 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 silicon oxide film 5 gate insulating film 6 gate electrode 7 silicon oxide film 8 n-type semiconductor region (source, drain) 9 silicon nitride film 10 silicon oxide film 11, 12 contact hole 13 Plug 14 Silicon oxide film 15 Through hole 16 Plug 17 Silicon oxide film 18 Silicon nitride film 19 Through hole 20 Polycrystalline silicon film 21 Side wall spacer 22 Plug 24 Silicon oxide film 27 Groove 28 TaN film 29 Ru film 30 Insulating film 31 Lower electrode 32a, 32b, 32c, 32d Tantalum oxide film 33 Upper electrode 34 Ru film 35 TaN film 35a, 35b Tantalum oxide film 36 Ru film 37 Polycrystalline silicon film BL Bit line C Information storage capacitor Qs MISFET for memory cell selection

Continued on the front page (72) Inventor Hiroshi Sakuma 2-2-1 Yaesu, Chuo-ku, Tokyo Inside Elpida Memory Co., Ltd. (72) Inventor Masahiko Hiratani 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central 5F083 AD21 AD48 AD49 JA06 JA38 JA39 JA40 MA06 MA18 MA19 MA20 NA01 PR03 PR09 PR12 PR21 PR22 PR33 PR40

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a capacitive element comprising a pair of electrodes and a dielectric film sandwiched between the pair of electrodes, wherein the inner wall of a groove formed in an insulating film is a main capacitive region. (A) forming a lower electrode composed of a tantalum nitride film and a ruthenium film formed on the inner surface of a groove formed in the insulating film; (b) the insulating film including a surface of the lower electrode A step of depositing a tantalum oxide film thereon by a CVD method and then performing a heat treatment in an atmosphere containing oxygen; and (c) a step of forming an upper electrode on the tantalum oxide film after the step (b). A method for manufacturing a semiconductor integrated circuit device, comprising: 2. A method for manufacturing a semiconductor integrated circuit device having a capacitive element comprising a pair of electrodes and a dielectric film sandwiched between the pair of electrodes, wherein a main capacitive region is an inner wall of a groove formed in an insulating film. (A) forming a lower electrode composed of a tantalum nitride film and a ruthenium film formed on the inner surface of a groove formed in the insulating film; (b) the insulating film including a surface of the lower electrode Depositing a first tantalum oxide film thereon by a CVD method, and then performing a heat treatment in an atmosphere containing oxygen in order to achieve crystallization of the first tantalum oxide film and improve film quality, (c). Forming a second tantalum oxide film on the first tantalum oxide film by a CVD method;
(D) after the step (c), a step of forming an upper electrode on the second tantalum oxide film. 3. A method for manufacturing a semiconductor integrated circuit device having a capacitive element including a pair of electrodes and a dielectric film sandwiched between the pair of electrodes, wherein a main capacitive region is an inner wall of a groove formed in an insulating film. (A) forming a lower electrode made of a tantalum nitride film on the inner surface of a groove formed in the insulating film; and (b) performing heat treatment in an oxidizing atmosphere to form a tantalum oxide film on the surface of the tantalum nitride film. Forming a film, and (c) depositing a second tantalum oxide film on the surface of the tantalum oxide film, if necessary, by a CVD method, and then forming an upper electrode on the tantalum oxide film. A method for manufacturing a semiconductor integrated circuit device, comprising: 4. A method of manufacturing a semiconductor integrated circuit device having a capacitive element including a pair of electrodes and a dielectric film sandwiched between the pair of electrodes, wherein a main capacitive region is an inner wall of a groove formed in an insulating film. (A) forming a lower electrode made of a tantalum nitride film on the inner surface of a groove formed in the insulating film;
(B) a step of forming a ruthenium film constituting a part of the upper electrode on the TaN film; and (c) performing a heat treatment in an oxidizing atmosphere to form a tantalum nitride film constituting the lower electrode and the upper part. Forming a tantalum oxide film at an interface with a ruthenium film forming a part of the electrode; (d) after the step (c), forming a conductive part forming another part of the upper electrode on the ruthenium film; A method for manufacturing a semiconductor integrated circuit device, comprising: forming a film. 5. A method for manufacturing a semiconductor integrated circuit device having a capacitive element including a pair of electrodes and a dielectric film sandwiched between the pair of electrodes, wherein the inner wall of a groove formed in the insulating film is a main capacitive region. (A) forming a lower electrode including a ruthenium film on the inner surface of a groove formed in the insulating film; (b) depositing a tantalum nitride film on the insulating film including on the surface of the lower electrode; A step of converting the tantalum nitride film into a tantalum oxide film by performing a heat treatment in an oxidizing atmosphere;
Forming a tantalum oxide film and then forming an upper electrode on the second tantalum oxide film.