JP2004071759A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Provided is a semiconductor device capable of suppressing deterioration of capacitor characteristics and preventing the storage electrode from falling or jumping when a capacitor having a storage electrode is formed, and a method for manufacturing the same.
A memory cell transistor including a pair of source / drain diffusion layers formed on a semiconductor substrate, a gate electrode formed on the semiconductor substrate, and an insulating film formed on the memory cell transistor 58, a contact hole formed in the insulating film, a conductive plug 62 filled in the contact hole and electrically connected to one of the source / drain diffusion layers, and a conductive plug formed on the conductive plug. A film 74, an oxide 85 partially formed on the surface of the conductive film, a storage electrode 84 formed on the conductive film via the oxide, and a dielectric formed on the surface of the storage electrode. A semiconductor device having a body film 86 and a counter electrode 88 formed on the surface of the dielectric film.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device characterized by a bonding structure of an adhesion layer used for a storage capacitor provided in a DRAM (Dynamic Random Access Memory) or a DRAM mixed Logic LSI and a method of manufacturing the same. It is about.
[0002]
[Prior art]
A DRAM is a semiconductor memory device that can be configured with one transistor and one capacitor, and various structures and manufacturing methods for manufacturing a high-density and highly integrated semiconductor memory device have been studied. In particular, since the structure of a capacitor in a DRAM greatly affects high integration, it is important how to secure a desired storage capacity without hindering high integration of the device.
[0003]
In order to achieve high integration, it is essential to reduce the area of the memory cell, and it is necessary to reduce the area in which the capacitor is formed. Therefore, by forming a three-dimensional structure such as a columnar, cylindrical, or concave type capacitor structure, the surface area of the capacitor is increased in the height direction, and desired storage without increasing the area of the region where the capacitor is formed. It has been proposed to reserve capacity.
[0004]
However, even if the above method is adopted, the conventional silicon oxide film (SiO ₂ : Relative dielectric constant of 3.8) and silicon nitride film (Si ₃ N ₄ : In the case of a capacitor dielectric film having a relative dielectric constant of 7 to 8), device dimensions are becoming smaller and smaller, and it is difficult to obtain a capacitance value required for element operation in a capacitor of a design rule generation having a line width of 0.13 μm or less. .
[0005]
Therefore, in order to solve such a problem, a tantalum oxide film (Ta) is formed on the capacitor dielectric film. ₂ O ₅ : Relative dielectric constant of 20 to 25). Further, barium strontium titanate having a relative permittivity of 100 or more: (Ba, Sr) TiO ₃ (BSTO), strontium titanate: SrTiO ₃ (STO), lead zirconate titanate: PbZrTiO ₃ The use of an oxide high dielectric such as (PZT) is being studied. In this specification, a high dielectric refers to a dielectric having a relative dielectric constant of 20 or more.
[0006]
When these oxide high dielectrics are used as a capacitor dielectric film, when a conventionally used silicon material is used for a storage electrode of a capacitor, a silicon oxide film having a lower dielectric constant than the capacitor dielectric film is used. It is formed on the contact surface of the dielectric film and causes a reduction in the capacitance of the capacitor.
[0007]
Therefore, it is desired that the storage electrode of the capacitor be formed of a metal that is not oxidized, a metal that is a conductor even if oxidized, or a conductive metal oxide. The use of an electrode made of such a material makes it easy to obtain a capacitor dielectric film having good dielectric properties.
[0008]
Rare metals including noble metals such as ruthenium (Ru) and platinum (Pt) are known as metals that are not oxidized or have a property of maintaining conductivity even when oxidized. Ruthenium oxide (RuO) is used as the conductive metal oxide. ₂ ), SrRuO ₃ (SRO) and the like are known. These are formed using a CVD process such as MOCVD (metal organic chemical vapor deposition).
[0009]
In a method of manufacturing a cylinder-type or concave-type capacitor using the above materials, first, an interlayer insulating film is formed on a semiconductor substrate, and an opening is formed in the interlayer insulating film. Thereafter, Ru is formed in the opening by the MOCVD method following the sputtering method and the storage electrode is formed.
[0010]
At this time, as disclosed in Japanese Patent Application Laid-Open No. 2000-156483, the bonding strength of the portion where the side wall of the interlayer insulating film exposed through the opening and the storage electrode are in contact with each other is weak, so that the bonding force is reduced during the subsequent polishing process or heat treatment. During the process, development occurs in which the storage electrode is lifted from the interlayer insulating film. When such lifting development occurs, stress is applied to the entire structure of the capacitor, which may adversely affect the capacitor dielectric film and the storage electrode. May be deteriorated.
[0011]
Therefore, a conductive adhesion layer such as TiN, WN, TaN or Ta is formed on the surface of the opening by sputtering or CVD, and then Ru is formed by sputtering and MOCVD to form the storage electrode. Has formed.
[0012]
Next, with reference to Japanese Patent Application Laid-Open No. 2002-76307, a conventional method of manufacturing a cylindrical capacitor in which an adhesion layer is formed on the surface of an opening and then a storage electrode is formed will be described with reference to FIGS. This will be described with reference to FIG.
[0013]
As shown in FIG. 22A, first, a memory cell transistor having a gate electrode 202 and a source / drain diffusion layer 204 on a silicon substrate 200 in the same manner as in a normal MOS transistor manufacturing method, and a gate electrode 208 Then, a transistor for a peripheral circuit having the source / drain diffusion layer 210 is formed.
[0014]
Next, the bit line 214 electrically connected to the source / drain diffusion layer 204 via the plug 212 and the source / drain via the plug 215 are formed on the interlayer insulating film 218 covering the memory cell transistor and the transistor for the peripheral circuit. The wiring layer 216 electrically connected to the diffusion layer 210 is formed. Since the bit line 214 does not appear in the illustrated cross section, the bit line 214 is indicated by a dotted line.
[0015]
Next, an interlayer insulating film 220 is formed over the interlayer insulating film 218 on which the bit lines 214 and the wiring layers 216 are formed.
[0016]
Next, as shown in FIG. 22B, a tungsten (W) plug 224 electrically connected to the source / drain diffusion layer 204 via the plug 222 is buried in the interlayer insulating films 220 and 218.
[0017]
Next, as shown in FIG. 22C, an etching stopper film 226 made of a silicon nitride film and an interlayer insulating film 228 made of a silicon oxide film are formed on the interlayer insulating film 220 in which the W plugs 224 are embedded by CVD. Then, an etching stopper film 230 made of a silicon nitride film, an insulating film 232 made of a silicon oxide film, and a hard mask 234 made of an amorphous silicon film are sequentially formed.
[0018]
Next, the hard mask 234, the insulating film 232, the etching stopper film 230, the interlayer insulating film 228, and the etching stopper film 226 are patterned by a normal lithography technique and an etching technique to form an opening 236 reaching the W plug 224.
[0019]
Next, as shown in FIG. 23A, an adhesion layer 237 made of a 10-nm-thick titanium nitride film is formed on the entire surface by a CVD method. Next, a Ru film with a thickness of 10 nm is formed as a seed layer on the adhesion layer 237 by a sputtering method, and a Ru film with a thickness of 30 nm is deposited by MOCVD to form a Ru film 238 with a total thickness of 40 nm. I do.
[0020]
Next, as shown in FIG. 23B, a photoresist film 239 is applied on the entire surface, and the inside of the opening 236 in which the adhesion layer 237 and the Ru film 238 are formed is filled with the photoresist film 239.
[0021]
Next, as shown in FIG. 24A, the photoresist film 239, the Ru film 238, and the hard mask 234 are polished by a CMP method until the surface of the adhesion layer 237 is exposed, and thereafter, the surface of the insulating film 232 is exposed. Until the contact layer 237 is removed by a reactive ion etching method. An adhesion layer 237 made of a titanium nitride (TiN) film and a storage electrode 248 made of a Ru film are formed along the inner wall and bottom of the opening 236 and electrically connected to the W plug 224.
[0022]
Next, as shown in FIG. 24B, the insulating film 232 is isotropically etched using the etching stopper film 230 as a stopper by wet etching using a hydrofluoric acid aqueous solution. Next, the photoresist film 239 in the storage electrode 248 is removed by a chemical solution treatment or a plasma ashing treatment.
[0023]
Next, as shown in FIG. 25A, the adhesion layer 237 is selectively formed on the storage electrode 248, the interlayer insulating films 220 and 228, and the etching stopper films 226 and 230 by wet etching using a sulfuric acid / peroxide solution. Etch. This etching is performed to prevent the deterioration of the capacitor characteristics due to the direct contact between the adhesion layer 237 and the capacitor dielectric film 240 formed later. Ta to be the capacitor dielectric film 240 ₂ O ₅ Are in direct contact with TiN or the like serving as the adhesion layer 237, ₂ O ₅ Oxygen diffuses to the TiN side to cause oxygen deficiency. Ta ₂ O ₅ When oxygen deficiency occurs, the film becomes conductive, a leak current flows in the film, and information of the capacitor is lost. The etching of the adhesion layer 237 is for preventing the deterioration of the capacitor characteristics. ₂ O ₅ It is necessary to etch the adhesion layer 237 to at least a position lower than the height of the etching stopper film 230 so that the conductive layer has no effect even if it has conductivity.
[0024]
Next, as shown in FIG. ₂ O ₅ The film is deposited to form a capacitor dielectric film 240 over the storage electrode 248. Next, a Ru film is deposited and patterned by MOCVD to form a counter electrode 242 on the capacitor dielectric film 240.
[0025]
Thus, a cylindrical capacitor having the storage electrode 248, the capacitor dielectric film 240, and the counter electrode 242 and electrically connected to the source / drain diffusion layer 204 of the memory cell transistor can be provided.
[0026]
[Problems to be solved by the invention]
However, in the conventional method for manufacturing a semiconductor device, it is difficult to perform the etching of the adhesion layer 237 shown in FIGS. 24B to 25A with good controllability.
[0027]
As shown in FIG. 26A, the storage electrode 248 made of a Ru film locally has a crystal gap called a pinhole. In the etching of the adhesion layer 237 in FIG. 25A, when wet etching using a sulfuric acid / peroxide solution is performed, the sulfuric acid / peroxide solution entering the cylinder from the opening of the storage electrode 248 soaks into the pinhole of the storage electrode 248. Then, the contact reaches the adhesion layer 237 between the storage electrode 248 and the W plug 224, and the adhesion layer 237 is etched to increase the contact resistance.
[0028]
Further, as shown in FIG. 26B, in the worst case, even the W plug 224 is etched, the electrical connection between the transfer transistor and the capacitor is lost, and the storage electrode falls or jumps, and the yield is reduced. The problem of reduction occurs.
[0029]
An object of the present invention is to provide a semiconductor device capable of preventing deterioration of a capacitor characteristic due to etching of an adhesion layer and preventing a storage electrode from falling or jumping, and a method of manufacturing the same.
[0030]
[Means for Solving the Problems]
The above object is achieved by forming an oxide 85 between the storage electrodes (84, 94) and the conductive film (the adhesion layers 74, 92). When the oxide 85 is etched into the conductive films (the adhesion layers 74 and 92), the aqueous solution of sulfuric acid permeated into the pinholes 77 of the storage electrodes (84 and 94) is removed from the conductive films (the adhesion layers 74 and 92). By stopping at the interface, it is possible to prevent the conductive film (the adhesion layers 74 and 92) and the underlying conductive plug 62 from being etched.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
[First embodiment]
The semiconductor device according to the first embodiment of the present invention and the method for fabricating the same will be described with reference to FIGS.
[0032]
FIG. 1 is a plan view of the memory cell of the semiconductor device according to the present embodiment. In the figure, a gate electrode 20 also serving as a word line is arranged in a vertical direction, a bit line 48 is arranged in a horizontal direction thereon, and a storage electrode 84 is arranged thereon.
[0033]
FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and the left side of the drawing is a cross-section of the memory cell portion, which shows a cross-section along line AA ′ in FIG. The right side shows a cross section of the peripheral circuit section.
[0034]
3A to 12 are sectional views of the semiconductor device according to the present embodiment, which illustrate the method for fabricating the semiconductor device.
[0035]
As shown in FIG. 3A, an element isolation film 12 is formed on the main surface of the p-type silicon substrate 10 by STI (Shallow Trench Isolation).
[0036]
First, a 100-nm-thick silicon nitride film (not shown) is formed on the silicon substrate 10, and then this silicon nitride film is patterned so as to remain in a region to be an element region. Next, using the patterned silicon nitride film as a hard mask, the silicon substrate 10 is etched to form an element isolation groove having a depth of 200 nm in the silicon substrate 10.
[0037]
Next, after depositing a silicon oxide film on the entire surface by the CVD method, the silicon oxide film is polished by a CMP (Chemical Mechanical Polishing) method until the silicon nitride film is exposed, and is selected in the element isolation groove. The silicon oxide film is left as it is. Thereafter, the silicon nitride film is removed, and an element isolation film 12 made of a silicon oxide film buried in the element isolation trench of the silicon substrate 10 is formed.
[0038]
Next, as shown in FIG. 3B, a P well (not shown) is formed in the silicon substrate 10 in the memory cell region, and ion implantation for controlling a threshold voltage is performed.
[0039]
Next, as shown in FIG. 3C, a gate insulating film 14 made of a silicon oxide film having a thickness of 5 nm is formed on the plurality of device regions defined by the device isolation films 12 by a thermal oxidation method. Note that as the gate insulating film 14, another insulating film such as a silicon oxynitride film may be used.
[0040]
Next, on the gate insulating film 14, a polysilicon film 16 having a thickness of 70 nm, a tungsten nitride (WN) film (not shown) having a thickness of 5 nm, a tungsten (W) film 18 having a thickness of 40 nm, and a film A silicon nitride film 22 having a thickness of 200 nm is sequentially deposited. Thereafter, these films are patterned by a lithography technique and an etching technique to form a gate electrode 20 having a polymetal structure in which an upper surface is covered with a silicon nitride film 22 and a polysilicon film 16 and a W film 18 are laminated via a WN film. I do.
[0041]
Next, as shown in FIG. 3D, ion implantation is performed using the gate electrode 20 as a mask to form a source / drain diffusion layer 24 in the silicon substrate 10 on both sides of the gate electrode 20. Thus, a memory cell transistor having the gate electrode 20 and the source / drain diffusion layers 24 on the silicon substrate 10 is formed.
[0042]
Next, a silicon nitride film having a film thickness of 35 nm is deposited on the entire surface by the CVD method and then etched back to form a sidewall insulating film 28 made of the silicon nitride film on the side walls of the gate electrode 20 and the silicon nitride film 22.
[0043]
Next, as shown in FIG. 3E, a borophosphosilicate glass (BPSG) film is deposited on the entire surface by the CVD method, and then the surface is etched by the reflow method and the CMP method until the silicon nitride film 22 is exposed. Polishing is performed to form an interlayer insulating film 30 made of a BPSG film having a planarized surface.
[0044]
Next, contact holes 32, 33, and 34 reaching the source / drain diffusion layers 24 are formed in the interlayer insulating film 30 in a self-aligned manner with the gate electrode 20 and the sidewall insulating films 28 by lithography and etching. .
[0045]
Next, as shown in FIG. 4A, an arsenic-doped polycrystalline silicon film is deposited by a CVD method, and then polished by a CMP method until the silicon nitride film 22 is exposed. Are selectively embedded with plugs 36, 37, and 38 made of a polycrystalline silicon film.
[0046]
Next, as shown in FIG. 4B, an interlayer insulating film 40 of a 200 nm-thickness silicon oxide film is formed on the entire surface by a CVD method. Next, a contact hole 42 reaching the plug 36 and a contact hole 43 reaching the plug 37 are formed in the interlayer insulating film 40 by lithography and etching.
[0047]
Next, as shown in FIG. 4C, an adhesion layer 50 having a laminated structure of titanium nitride (TiN) / titanium (Ti) having a thickness of 45 nm and a tungsten (W) film 51 having a thickness of 250 nm are formed by sputtering. Are sequentially deposited. The adhesion layer 50 is for improving the adhesion between the side wall of the interlayer insulating film 40 made of a silicon oxide film and the W film 51.
[0048]
Next, the W film 51 is polished by the CMP method, and plugs made of the W film 51 are embedded in the contact holes 42 and 43. Next, a W film 52 having a thickness of 30 nm is deposited by a sputtering method. Next, a 200-nm-thick silicon nitride film 54 is deposited on the W film 52 by the CVD method.
[0049]
Next, the silicon nitride film 54, the W film 52, and the adhesion layer 50 are patterned by lithography and etching techniques, and the upper surface is covered with the silicon nitride film 54, and is formed of the adhesion layer 50 and the W film 52. A bit line connected to the source / drain diffusion layer is formed. Similarly, a wiring layer 44 connected to the source / drain diffusion layer 24 via the plug 37 is formed. Since the bit line 48 does not appear in the illustrated cross section, it is shown by a dotted line.
[0050]
Next, a silicon nitride film having a thickness of 20 nm is deposited on the entire surface by the CVD method and then etched back, and a sidewall insulating film 56 made of a silicon nitride film is formed on the side walls of the bit line 48, the wiring layer 44 and the silicon nitride film 54. To form Next, a 400-nm-thick silicon oxide film is deposited on the entire surface by the CVD method, and the surface thereof is polished by the CMP method to form an interlayer insulating film 58 of a silicon oxide film having a flattened surface.
[0051]
Next, as shown in FIG. 5A, a contact hole 60 reaching the plug 38 is formed in the interlayer insulating films 58 and 40 by lithography and etching. At this time, the silicon oxide film is etched under an etching condition having a high selectivity with respect to the silicon nitride film, so that the silicon nitride film 54 covering the bit line 48 and the sidewall insulating film formed on the side wall of the bit line 48 are formed. A contact hole 60 can be opened at 56 (not shown) by self-alignment.
[0052]
Next, as shown in FIG. 5B, an adhesion layer having a laminated structure of titanium nitride / titanium having a thickness of 25 nm and a W film having a thickness of 250 nm are deposited on the entire surface by a sputtering method. Polishing is performed by a CMP method until the surface of the film 58 is exposed to form a conductor plug 62 embedded in the contact hole 60. As the conductor plug 62, TiN or polysilicon can be used instead of the W film.
[0053]
Next, as shown in FIG. 6A, an etching stopper film 64 made of a silicon nitride film with a thickness of about 40 nm, an interlayer insulating film 66 made of a silicon oxide film with a thickness of 100 nm, An etching stopper film 68 made of a silicon nitride film having a thickness of about 40 nm and an insulating film 70 made of a silicon oxide film having a thickness of 850 nm are sequentially formed.
[0054]
Next, as shown in FIG. 6B, the insulating film 70, the etching stopper film 68, the interlayer insulating film 66, and the etching stopper film 64 are patterned by a lithography technique and an etching technique. An opening 72 penetrating the film and reaching the conductor plug 62 is formed.
[0055]
Next, as shown in FIG. 7, a film forming temperature is set to 580 ° C., a pressure is set to 0.3 Torr, and a gas flow rate is set to TiCl ₄ At / NH = 30/400 sccm, an adhesion layer 74 made of a titanium nitride (TiN) film having a thickness of 10 nm is formed.
[0056]
Next, a 10 nm-thick ruthenium (Ru) film is formed as a seed layer on the adhesion layer 74 by a sputtering method, and a 30 nm-thick Ru film is deposited by a MOCVD method, so that a total 40 nm-thick Ru film is formed. 76 is formed. In the film formation by MOCVD, the film formation temperature is 300 ° C., the pressure is 0.05 Torr, and Ru (EtCp) is used as a Ru source. ₂ Flow rate of 0.06 sccm, O ₂ A Ru film is formed at a gas flow rate of 160 sccm. Further, Pt, Ir, IrOx, and RuOx can be used instead of the Ru film.
[0057]
Next, as shown in FIG. 8, an oxide 85 made of TiOx is formed at the interface between the Ru film 76 and the adhesion layer 74 by wet processing. With a wet device, water and an aqueous HCl solution are simultaneously flown into the treatment tank for 2 minutes, and then O ₃ Due to the wet process in which the water is kept flowing, the chemical solution permeates into the pinhole 77 in the Ru film 76 and reacts with the adhesion layer 74 made of TiN, and TiOx is generated at the interface between the Ru film 76 and the adhesion layer 74. This oxide 85 stops the aqueous solution of sulfuric acid permeated into the pinhole 77 of the Ru film 76 at the interface with the adhesion layer 74 when etching the adhesion layer 74 in a later step. Of the conductive plug 62 is prevented from being etched. Dry processing such as ashing and annealing may be used to generate the oxide 85. As the adhesion layer 74, TiN / Ti, TiAlN, WN, TiW, NbN, TaN, Ta, TaSiN can be used instead of the TiN film. In this case, oxides generated at the interface between the Ru film and the titanium nitride film are TiOx, WOx, NbOx, and TaOx.
[0058]
Next, as shown in FIG. 9A, a photoresist film 78 is applied to the entire surface, and the inside of the opening 72 in which the adhesion layer 74 and the Ru film 76 are formed is filled with the photoresist film 78.
[0059]
Next, as shown in FIG. 9B, the photoresist film 78 and the Ru film 76 are polished by the CMP method until the surface of the adhesion layer 74 is exposed, and then the reaction is performed until the surface of the insulating film 70 is exposed. The adhesion layer 74 is removed by a reactive ion etching method.
[0060]
Next, as shown in FIG. 10A, the insulating film 70 is selectively etched by isotropic etching such as wet etching using a hydrofluoric acid aqueous solution, using the etching stopper film 68 as a stopper. Next, the photoresist film 78 is removed by a chemical solution process or a plasma ashing process, and a cylindrical storage electrode 84 made of a Ru film 76 is formed.
[0061]
Next, as shown in FIG. 10B, the adhesion layer 74 is selectively etched with respect to the Ru film 76, the etching stopper film 68, and the interlayer insulating film 66 using an aqueous solution containing sulfuric acid and hydrogen peroxide. This etching is for preventing the deterioration of the capacitor characteristics due to the direct contact between the adhesion layer 74 and the capacitor dielectric film 86 to be formed later. Ta to be the capacitor dielectric film 86 ₂ O ₅ Are in direct contact with TiN or the like, which becomes ₂ O ₅ Oxygen diffuses to the TiN side to cause oxygen deficiency. Ta ₂ O ₅ When oxygen deficiency occurs, the film becomes conductive, a leak current flows in the film, and information of the capacitor is lost. Therefore, the etching of the adhesion layer 74 is performed by Ta ₂ O ₅ Is preferably performed at least until a gap is formed between the etching stopper film 68 and the Ru film 76 so that the conductive film has no influence even if it has conductivity.
[0062]
At the time of etching the adhesion layer 74, even if the aqueous solution of sulfuric acid enters the cylinder through the opening of the storage electrode 84 and penetrates into the pinhole 77 (shown in FIG. 8) of the Ru film 76, it is formed at the interface with the adhesion layer 74 The impregnated oxide 85 stops the permeation, so that the adhesion layer 74 and the lower conductive plug 62 are not etched.
[0063]
Next, as shown in FIG. 11A, oxygen and pentoethoxytantalum (Ta (O (C ₂ H ₅ )) ₅ A tantalum oxide film (Ta) having a film thickness of 10 to 30 nm is formed by using a mixed gas of ₂ O ₅ ) Is formed.
[0064]
Next, heat treatment is performed at 480 ° C. for 2 minutes in UV-O 3 to fill oxygen vacancies in the tantalum oxide film. This heat treatment can further reduce the leakage current of the capacitor.
[0065]
In addition, Ta ₂ O ₅ Instead, (Ba, Sr) TiO ₃ (BSTO), SrTiO ₃ (STO), PbZrTiO ₃ An oxide high dielectric such as (PZT) can also be used.
[0066]
Next, a Ru film with a thickness of 10 nm is formed as a seed layer on the entire surface by sputtering, and a Ru film is deposited by MOCVD to form a Ru film 87 with a total thickness of 30 to 50 nm. For the film formation by MOCVD, the same film formation conditions as for the Ru film 76 serving as the storage electrode 84 can be used.
[0067]
Next, a 10 to 20 nm-thick titanium nitride film 89 is deposited on the Ru film 87 by a sputtering method. The titanium nitride film is formed by sputtering a titanium target at a substrate temperature of 150 ° C., a power of 5 kW, an argon gas flow rate of 5 sccm, and a nitrogen gas flow rate of 50 sccm. The titanium nitride film 89 is an adhesion layer for improving the adhesion between the Ru film 87 serving as a counter electrode and an interlayer insulating film formed thereover. Therefore, it is not always necessary when the adhesion between the counter electrode and the interlayer insulating film is good.
[0068]
Then, the pressure was 0.1 Torr, the power was 500 W, and the gas flow rate was Cl. ₂ / O ₂ = 50/500 sccm, the titanium nitride film 89 and the Ru film 87 are patterned by etching to form a counter electrode 88 made of a Ru film and covered with the titanium nitride film 89.
[0069]
Then, as shown in FIG. 11B, a silicon oxide film having a thickness of 1000 nm is deposited on the entire surface by the CVD method, and the surface is polished by the CMP method, and the surface is made of a silicon oxide film having a flat surface. An interlayer insulating film 90 is formed.
[0070]
Next, a contact hole 104 that reaches the wiring layer 44 through the interlayer insulating film 90, the etching stopper film 68, the interlayer insulating film 66, the etching stopper film 64, and the interlayer insulating film 58 is formed by lithography and etching.
[0071]
Next, as shown in FIG. 12, an adhesion layer having a laminated structure of titanium nitride / titanium having a thickness of 25 nm and a W film having a thickness of 250 nm are deposited on the entire surface by sputtering, and then an interlayer insulating film is formed. Polishing is performed by a CMP method until the surface of the plug 90 is exposed to form a plug 108 embedded in the contact hole 104.
[0072]
Next, a 10-nm-thick titanium nitride film serving as a barrier metal and a 300-nm-thick aluminum film or copper film were deposited and patterned on the entire surface by a sputtering method, and connected to the lower wiring via a plug 108. The wiring layer 100 is formed.
[0073]
Next, a silicon oxide film having a thickness of 1000 nm is deposited on the entire surface by the CVD method, and the surface thereof is polished by the CMP method, thereby forming an interlayer insulating film 102 made of a silicon oxide film having a planarized surface.
[0074]
Thus, a DRAM having a memory cell including one transistor and one capacitor is manufactured.
[0075]
As described above, according to the present embodiment, even when the sulfuric acid / peroxide solution enters the cylinder of the storage electrode and penetrates into the electrode layer through the pinhole of the Ru film during the etching of the adhesion layer after the formation of the storage electrode, Since the penetration is stopped by the oxide (TiOx) generated at the interface between the adhesion layer and the storage electrode, it is possible to prevent the adhesion layer and the lower conductive plug from being etched. This prevents deterioration of capacitor characteristics such as an increase in contact resistance due to the etching of the adhesion layer and an etching of the conductor plug, which prevents electrical connection between the transfer transistor and the capacitor. And flying can be prevented.
[0076]
[Modification]
FIG. 13 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a modification of the first embodiment. The left side of the drawing is a cross-section of a memory cell unit, and shows a cross-section along line AA ′ in FIG. I have. The right side shows a cross section of the peripheral circuit section.
[0077]
In the first embodiment, as shown in FIG. 10, the etching stopper film 68 and the interlayer insulating film 66 prevent the Ru film 76 from falling down. It is not necessary to support with the film 68 and the interlayer insulating film 66, and the number of steps can be reduced as compared with the first embodiment.
[0078]
[Second embodiment]
Next, a second embodiment will be described with reference to the drawings.
[0079]
In the first embodiment, a cylinder type capacitor using a tantalum oxide film as a capacitor dielectric film has been described in order to secure a capacitor capacity.
[0080]
Japanese Unexamined Patent Application Publication No. 2002-83880 discloses that in the case of a cylinder type capacitor as in the first embodiment, since a capacitor dielectric film is also formed on the outer surface of the cylinder, it may be difficult to maintain step coverage in some cases. Has been described. Since the cylinder opening is polished by the CMP method in the process of forming the storage electrode, the bending from the opening to the outer surface of the cylinder becomes an acute angle. Since it is difficult to deposit the capacitor dielectric film on this portion, the film thickness of the capacitor dielectric film becomes thin, and in some cases, a leakage current occurs between the storage electrode and the counter electrode. As described above, the yield of the cylinder type capacitor is low, and there is a problem in reliability.
[0081]
Therefore, in the present embodiment, a description will be given of a semiconductor device to which the present invention is applied, which prevents deterioration of capacitor characteristics due to etching of an adhesion layer, and a method of manufacturing the same in a concave capacitor in which a capacitor dielectric film is not formed on the outer surface of a cylinder.
[0082]
FIG. 14 is a schematic cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The left side of the drawing is a cross-section of the memory cell section, and shows a cross-section along the line AA ′ in FIG. The right side shows a cross section of the peripheral circuit section. 15 to 21 are process sectional views for explaining the method for fabricating the semiconductor device according to the present embodiment. In the drawing, reference numeral 92 denotes an adhesion layer, 94 denotes a storage electrode, 96 denotes a capacitor dielectric film, 98 denotes a counter electrode, and other reference numerals are the same as those in FIGS. 2 to 12 described in the first embodiment. And
[0083]
First, in the same manner as in the first embodiment, as shown in FIGS. 3A to 5B, a memory cell transistor is formed on a semiconductor substrate, and a plug 38 connected to the source / drain diffusion layer 24 is formed. The conductor plug 62 is formed in the contact hole 60 that reaches.
[0084]
Next, as shown in FIG. 15A, an etching stopper film 64 made of a silicon nitride film having a thickness of about 40 nm and an interlayer insulating film 67 made of a silicon oxide film having a thickness of 800 nm are sequentially formed on the entire surface by the CVD method. I do.
[0085]
Next, as shown in FIG. 15B, an opening 72 reaching the conductor plug 62 is formed in the region where the storage electrode is to be formed in the same manner as in the first embodiment.
[0086]
Next, as shown in FIG. 16, an adhesion layer 92 made of a 10-nm-thick titanium nitride film and a 40-nm-thick ruthenium (Ru) film 76 are sequentially formed on the entire surface in the same manner as in the first embodiment.
[0087]
Next, as shown in FIG. 17, an oxide 85 made of TiOx is formed at the interface between the Ru film 76 and the adhesion layer 92 by annealing. At an annealing temperature of 400 ° C, N containing a small amount of entrained oxygen ₂ By annealing in a furnace in an atmosphere for 30 minutes, gas penetrates into the pinhole 77 in the Ru film 76 and reacts with the adhesion layer 92 made of TiN to generate TiOx at the interface between the Ru film 76 and the adhesion layer 92. . The oxide 85 stops the aqueous solution of sulfuric acid permeated into the pinhole 77 of the Ru film 76 at the interface with the adhesion layer 92 at the time of etching the adhesion layer 92 in a later step. Is prevented from being etched. Dry processing such as ashing or wet processing may be used to generate the oxide 85.
[0088]
Next, as shown in FIG. 18A, a photoresist film 78 is applied to the entire surface, and the inside of the opening 72 where the adhesion layer 92 and the Ru film 76 are formed is filled with the photoresist film 78.
[0089]
Next, as shown in FIG. 18B, the photoresist film 78 and the Ru film 76 are polished by the CMP method until the surface of the adhesion layer 92 is exposed, and thereafter, until the surface of the interlayer insulating film 67 is exposed. The adhesion layer 92 is removed by a reactive ion etching method. Next, the photoresist film 78 in the opening 72 is removed by a chemical solution process or a plasma ashing process.
[0090]
Next, as shown in FIG. 19, the adhesion layer 92 is etched with an aqueous solution containing sulfuric acid and hydrogen peroxide. This etching is performed until at least a gap is formed between the interlayer insulating film 67 and the Ru film 76 so that the capacitor characteristics do not deteriorate due to the contact between the capacitor dielectric film 96 formed later and the adhesion layer 92. It is desirable to do. At the time of etching the adhesion layer 92, even though the sulfuric acid / peroxide solution enters the opening of the Ru film 76 and penetrates into the pinhole 77 (shown in FIG. 17) of the Ru film 76, it is generated at the interface with the adhesion layer 92. The permeation is stopped by the oxide 85, and the adhesive layer 92 and the lower conductive plug 62 are not etched.
[0091]
Referring to FIG. 20A, in the first embodiment, a tantalum oxide film (Ta) is formed on the capacitor dielectric film. ₂ O ₅ However, in the concave capacitor of the present embodiment, since the area of the capacitor dielectric film is smaller than that of the cylinder type capacitor, the capacitor dielectric film is formed of a tantalum oxide film rather than a tantalum oxide film in order to secure the capacitor capacity. A BSTO film having a high relative dielectric constant is formed. Solid raw material Ba (THD) ₂ , Sr (THD) ₂ , Ti (i-OC ₃ H ₇ ) ₂ (THD) ₂ Is mixed with tetrahydrofuran (THF) as a solvent, and the mixture is vaporized to form a capacitor dielectric film 96.
[0092]
Next, in the same manner as in the first embodiment, a Ru film 97 having a total thickness of 30 to 50 nm and a titanium nitride film 99 having a thickness of 10 to 20 nm are sequentially formed on the entire surface. The titanium nitride film 99 is an adhesion layer for improving the adhesion between the Ru film serving as the counter electrode and the interlayer insulating film formed thereover. Therefore, it is not always necessary when the adhesion between the counter electrode and the interlayer insulating film is good.
[0093]
Next, in the same manner as in the first embodiment, the titanium nitride film 99 and the Ru film 97 are patterned to form a counter electrode 98 made of a Ru film, the upper surface of which is covered with the titanium nitride film 99.
[0094]
Next, as shown in FIG. 20B, an interlayer insulating film 90 made of a silicon oxide film is formed in the same manner as in the first embodiment, and then an interlayer insulating film 90, an interlayer insulating film 67, and an etching stopper film are formed. A contact hole 104 that penetrates the wiring layer 44 through the gate insulating film 64 and the interlayer insulating film 58 is formed.
[0095]
Next, as shown in FIG. 21, a plug 108, a wiring layer 100, and an interlayer insulating film 102 are sequentially formed in the same manner as in the first embodiment.
[0096]
Thus, a DRAM having a memory cell including one transistor and one capacitor is manufactured.
[0097]
As described above, also in the present embodiment, at the time of etching the adhesion layer after the formation of the storage electrode, the permeation of the aqueous solution of sulfuric acid and peroxide is stopped by the oxide (TiOx) generated at the interface between the adhesion layer and the storage electrode. In addition, it is possible to prevent the adhesion layer and the lower conductive plug from being etched. Accordingly, it is possible to prevent deterioration of the capacitor characteristics such as an increase in the contact resistance due to the etching of the adhesion layer and an interruption of the electrical connection between the transfer transistor and the capacitor due to the etching of the conductor plug. In addition, the concave type capacitor facilitates the maintenance of the step coverage of the capacitor dielectric film, and does not generate a leak current between the storage electrode and the counter electrode, thereby improving the yield and improving the reliability of the semiconductor device. Can be provided.
[0098]
As described above in detail, the features of the semiconductor device and the method of manufacturing the same according to the present invention are summarized as follows.
[0099]
(Supplementary Note 1) A memory cell transistor including a pair of source / drain diffusion layers formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate; an insulating film formed on the memory cell transistor;
A contact hole formed in the insulating film;
A conductive plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
A conductive film formed on the conductive plug,
An oxide partially formed on the surface of the conductive film;
Via the oxide, a storage electrode formed on the conductive film,
A dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the surface of the dielectric film;
A semiconductor device comprising: (1)
(Supplementary Note 2) A memory cell transistor including a pair of source / drain diffusion layers formed on a semiconductor substrate and a gate electrode formed on the semiconductor substrate, and a first insulating layer formed on the memory cell transistor Membrane and
A contact hole formed in the first insulating film;
A conductive plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
A second insulating film formed on the conductor plug and the first insulating film;
An opening formed in the second insulating film and reaching the conductor plug;
A conductive film formed on the conductor plug in the opening,
A storage electrode electrically connected to the conductive film and formed on the inner wall of the opening via the conductive film;
A dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the surface of the dielectric film,
A pinhole is formed in the storage electrode, and an oxide selectively formed at an interface between the pinhole and the conductive film;
A semiconductor device comprising: (2)
(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the conductive film is any one of TiN, TiN / Ti, TiAlN, WN, TiW, NbN, TaN, Ta, and TaSiN.
[0100]
(Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the storage electrode is any one of Ru, Pt, Ir, IrOx, and RuOx.
[0101]
(Supplementary Note 5) The semiconductor according to any one of Supplementary Notes 1 to 4, wherein the oxide formed between the conductive film and the storage electrode is any of TiOx, WOx, NbOx, and TaOx. apparatus.
[0102]
(Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the conductor plug is any one of W, TiN, and polysilicon.
[0103]
(Supplementary Note 7) A step of forming a memory cell transistor including a pair of source / drain diffusion layers on a semiconductor substrate and a gate electrode on the semiconductor substrate;
Forming an insulating film on the memory cell transistor;
Forming a contact hole in the insulating film;
Forming a conductor plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
Forming a conductive film on the conductive plug;
Forming a storage electrode having a pinhole on the conductive film;
Forming an oxide on the conductive film surface under the pinhole;
Removing a part of the conductive film;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film;
A method for manufacturing a semiconductor device, comprising: (3)
(Supplementary Note 8) A step of forming a memory cell transistor including a pair of source / drain diffusion layers on a semiconductor substrate and a gate electrode on the semiconductor substrate;
Forming a first insulating film on the memory cell transistor;
Forming a contact hole in the first insulating film;
Forming a conductor plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
Forming a second insulating film on the conductor plug and the first insulating film;
Forming an opening in the second insulating film that reaches the conductor plug;
Forming a conductive film electrically connected to the conductor plug on the bottom surface and the inner wall of the opening;
Forming a storage electrode having a pinhole on the bottom surface and the inner wall of the opening via the conductive film;
Forming an oxide on the conductive film surface under the pinhole;
Removing a part of the conductive film from the upper surface of the second insulating film;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film;
A method for manufacturing a semiconductor device, comprising: (4)
(Supplementary note 9) The method for manufacturing a semiconductor device according to supplementary note 7 or 8, wherein the storage electrode is formed by a metal organic chemical vapor deposition method.
[0104]
(Supplementary note 10) The method of manufacturing a semiconductor device according to any one of Supplementary notes 7 to 9, wherein the step of removing a part of the conductive film is performed by selectively etching the storage electrode. (5)
[0105]
【The invention's effect】
As described above, according to the present invention, in the formation of the storage capacitor of the DRAM, when the adhesion layer is etched after the formation of the storage electrode, the oxide locally formed at the interface between the adhesion layer and the storage electrode accumulates. Since the permeation of the etching solution permeating into the pinholes of the electrodes is stopped at the interface of the adhesive layer, it is possible to prevent the underlying adhesive layer and the conductive plug from being etched. As a result, deterioration of the capacitor characteristics such as falling or jumping of the storage electrode and contact failure is prevented, and the yield is improved.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;
FIG. 5 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;
FIG. 6 is a process sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 7 is a process sectional view (part 5) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a process sectional view (part 6) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a process sectional view (part 7) showing the method for fabricating the semiconductor device according to the first embodiment of the present invention;
FIG. 10 is a process sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 11 is a process sectional view (part 9) showing the method for fabricating the semiconductor device according to the first embodiment of the present invention;
FIG. 12 is a process sectional view (part 10) showing the method for fabricating the semiconductor device according to the first embodiment of the present invention;
FIG. 13 is a schematic sectional view showing the structure of a semiconductor device according to a modification of the first embodiment of the present invention.
FIG. 14 is a schematic sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 15 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.
FIG. 16 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.
FIG. 17 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.
FIG. 18 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.
FIG. 19 is a process sectional view (part 5) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.
FIG. 20 is a process sectional view (part 6) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.
FIG. 21 is a process sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 22 is a process sectional view (part 1) for illustrating the conventional method of manufacturing a semiconductor device.
FIG. 23 is a process sectional view (2) showing the conventional method of manufacturing the semiconductor device;
FIG. 24 is a process sectional view (part 3) for illustrating the conventional method of manufacturing a semiconductor device.
FIG. 25 is a process sectional view (part 4) illustrating the conventional method for manufacturing a semiconductor device.
FIG. 26 is a diagram illustrating a problem in a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
10 ... Silicon substrate
12… Element isolation film
14 ... Gate insulating film
16 ... Polysilicon film
18, 51, 52 ... tungsten film
20 ... Gate electrode
22, 54: silicon nitride film
24 ... Source / drain diffusion layer
28, 56 ... sidewall insulating film
30, 40, 58, 66, 67, 90, 102 ... interlayer insulating film
32, 33, 34, 42, 43, 60, 104 ... contact holes
36, 37, 38, 108 ... plug
48 ... Bit line
50 ... adhesion layer
62 ... conductor plug
64, 68: Etching stopper film
70 ... insulating film
72 ... opening
74, 92 ... adhesion layer
76, 87, 97 ... ruthenium film
77… Pinhole
84, 94 ... storage electrode
85 ... oxide
86, 96: capacitor dielectric film
88, 98: Counter electrode
89, 99 ... titanium nitride film
100 ... wiring layer

Claims (5)

A memory cell transistor including a pair of source / drain diffusion layers formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate;
An insulating film formed on the memory cell transistor;
A contact hole formed in the insulating film;
A conductive plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
A conductive film formed on the conductive plug,
An oxide partially formed on the surface of the conductive film;
Via the oxide, a storage electrode formed on the conductive film,
A dielectric film formed on the surface of the storage electrode;
And a counter electrode formed on the surface of the dielectric film. A memory cell transistor including a pair of source / drain diffusion layers formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate;
A first insulating film formed on the memory cell transistor;
A contact hole formed in the first insulating film;
A conductive plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
A second insulating film formed on the conductor plug and the first insulating film;
An opening formed in the second insulating film and reaching the conductor plug;
A conductive film formed on the conductor plug in the opening,
A storage electrode electrically connected to the conductive film and formed on the inner wall of the opening via the conductive film;
A dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the surface of the dielectric film,
A pinhole is formed in the storage electrode, and an oxide selectively formed at an interface between the pinhole and the conductive film is provided. Forming a memory cell transistor including a pair of source / drain diffusion layers on a semiconductor substrate and a gate electrode on the semiconductor substrate;
Forming an insulating film on the memory cell transistor;
Forming a contact hole in the insulating film;
Forming a conductor plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
Forming a conductive film on the conductive plug;
Forming a storage electrode having a pinhole on the conductive film;
Forming an oxide on the conductive film surface under the pinhole;
Removing a part of the conductive film;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film. Forming a memory cell transistor including a pair of source / drain diffusion layers on a semiconductor substrate and a gate electrode on the semiconductor substrate;
Forming a first insulating film on the memory cell transistor;
Forming a contact hole in the first insulating film;
Forming a conductor plug filled in the contact hole and electrically connected to one of the source / drain diffusion layers;
Forming a second insulating film on the conductor plug and the first insulating film;
Forming an opening in the second insulating film that reaches the conductor plug;
Forming a conductive film electrically connected to the conductor plug on the bottom surface and the inner wall of the opening;
Forming a storage electrode having a pinhole on the bottom surface and the inner wall of the opening via the conductive film;
Forming an oxide on the conductive film surface under the pinhole;
Removing a part of the conductive film from the upper surface of the second insulating film;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film. 5. The method according to claim 3, wherein the step of removing a part of the conductive film is performed by selectively etching the storage electrode.

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