JP2002270618A - GaN field effect transistor - Google Patents

Abstract

(57) [Problem] To provide a GaN-based FET which has a small on-resistance, easily realizes a pinch-off state, and can perform a large current switching operation even at a high temperature. SOLUTION: On a semi-insulating substrate 1, a lower gate electrode 2A made of the same material as a gate electrode 2B to be formed.
Is formed directly in the same pattern as the gate electrode 2B, the lower gate electrode 2A is buried to form at least one active layer 3 made of a GaN-based compound semiconductor, and on the upper surface of the active layer 3, the gate electrode 2B is formed. Is formed, and the gate electrodes 2A and 2B are arranged vertically above and below the active layer 3.
aN-based field-effect transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaN-based field effect transistor (FET), and more particularly, to a switching element which has a small on-resistance, easily realizes a pinch-off state, and can operate at a high temperature and drive a large current. The present invention relates to a GaN-based FET having a useful new structure.

[0002]

2. Description of the Related Art Recently, MIS (metal-insulating layer-semiconductor) has been proposed.
Research and development of FETs having a structure are being advanced, but in that case, GaAs-based compound semiconductors are mainly used. The GaAs-based FET is generally manufactured as follows. First, on a substrate such as a sapphire substrate, a non-doped Ga
A semi-insulating layer made of As is formed, and an active layer made of Si-doped n-AlGaAs is formed thereon. Then, on this active layer, for example, Si
An O ₂ film is formed, an opening of a desired pattern is formed by photolithography and etching, and a predetermined electrode material is deposited from the opening to form an active layer (Si-doped n-AlGaAs). Layer) on top of the gate electrode,
Working electrodes such as a source electrode and a drain electrode are formed.

[0003] Recently, the use of FETs as switching elements mounted on automobiles, for example, has begun to spread. In addition to demands for weight reduction and miniaturization, FETs in such application fields are required to be able to operate at high temperatures in consideration of the temperature in the engine room and to be capable of driving a large current. I have. In relation to the latter requirement, the above-mentioned GaAs-based FET does not always exhibit satisfactory characteristics.

On the other hand, GaN, AlGaN, InGaAl
Since a GaN-based compound semiconductor such as N can operate at a higher temperature than GaAs or Si, and has a wide discontinuous band gap at a heterojunction interface, it can be used as an active layer on which a gate electrode is formed. Thus, it is possible to obtain an FET that operates at a high temperature and can apply a high voltage.

[0005] For these reasons, research and development of FETs using GaN-based compound semiconductors have been promoted. However, the GaN-based FETs obtained up to now have a smaller size than conventional Si and GaAs-based FETs. The on-resistance during operation is 1
Although it has the advantage of being reduced by about three orders of magnitude, considerable on-resistance still exists due to the immature crystal growth technology and the immature electrode formation technology.

Further, even when a considerably high electric field is applied to the active layer located immediately below the gate electrode, a depletion layer for completely blocking the channel is not formed in the gate portion. A leak current may flow between the source electrode and the drain electrode without realizing an appropriate pinch-off state.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a GaN-based FE.
Solving the above-mentioned problem at T, the on-resistance is small,
It is another object of the present invention to provide a GaN-based FET having a structure in which a pinch-off state is easily obtained without generating a leak current, and designed to make full use of the characteristics of the GaN-based material.

[0008]

According to the present invention, a lower gate electrode made of the same material as a gate electrode to be formed is directly provided on a semi-insulating substrate. Forming at least one active layer made of a GaN-based compound semiconductor by burying the lower gate electrode, and forming the active layer on the upper surface of the active layer; A GaN-based field-effect transistor is provided in which gate electrodes are arranged above and below a layer.

[0009]

FIG. 1 shows a basic structure A of a GaN-based FET according to the present invention. In this GaN-based FET (A), a lower gate electrode 2A is directly wired on a semi-insulating substrate 1, and an active layer 3 made of a GaN-based compound semiconductor is disposed by burying the lower gate electrode 2A. A gate electrode 2B is formed on the upper surface of the substrate.

Here, the gate electrode 2B is wired on the upper surface of the active layer 3 in a certain design pattern, and the lower gate electrode 2A is provided at the corresponding surface position of the semi-insulating substrate 1 in the same design as the gate electrode 2B. It is wired in a pattern, and its lower gate electrode 2 </ b> A is embedded in the active layer 3. Therefore, as shown as the dashed area in FIG.
The gate portion G is formed by sandwiching the active layer 3 between the lower gate electrode 2A and the gate electrode 2B which are wired up and down.

Then, on both sides of the active layer 3, specifically, the semi-insulating substrate 1 in a region excluding the gate portion G described above.
The contact layers 4 and 4 are arranged directly on the source electrode 5 and the drain electrode 6 respectively.
Are formed. In the case of this FET (A), the gate portion G is composed of an active layer 3 and two gate electrodes 2 sandwiching the active layer 3 from above and below.
A and 2B, when these gate electrodes are operated to apply an electric field to the active layer 3, first, a depletion layer 7B that spreads downward is formed in the channel of the active layer 3 by the gate electrode 2B. A depletion layer 7B extending upward is formed in the channel of the active layer 3 by the lower gate electrode 2A.

Therefore, even if one of the gate electrodes alone cannot make the entire channel of the active layer 3 a depletion layer, the channel is eventually depleted due to the depletion layer which spreads due to the action of the other gate electrode. A depletion layer that blocks the channel will be formed with the layers combined. This is in contrast to the fact that a conventional FET is trying to realize a pinch-off state with one gate electrode.
In the case of (A), it means that the pinch-off state can be realized more easily.

In the FET (A) shown in FIG. 1, as the semi-insulating substrate 1, for example, a sapphire substrate, Si substrate, AlN substrate, GaAs substrate, SiC substrate, GaP substrate or the like can be used. Further, various oxide substrates or glass substrates such as quartz glass can be used. The lower gate electrode 2A wired on the semi-insulating substrate 1 and the gate electrode 2B wired on the active layer 3 need to be made of the same material. For example, Pt, W, P
d, Ag, Au, and Ni can be used.

As a material of the source electrode 5 and the drain electrode 6, a material that can form an ohmic junction with the contact layers 4 and 4 is used.
Al / T having a structure formed by sequentially depositing l, Ti, and Au
i / Au and Al / Ti can be mentioned. Besides these, for example, silicide alloys such as Ti-Si, Al-Si, and Ta-Si can also be used.

The active layer 3 can be formed by applying a molecular beam epitaxial growth method (MBE method) or a metal organic chemical vapor deposition method (MOCVD method) to a GaN-based compound semiconductor. Further, a halide vapor deposition method (HVPE method) may be employed. To form a high-quality active layer, MB
It is preferable to apply the E method. As the GaN-based compound semiconductor to be used, for example, GaN, AlGaN, InG
aN, AlInGaN, InGaNAs, InGaNP
And so on.

In the case of the GaN-based FET (A), when the active layer 3 is formed, the conductivity type of the active layer is changed to n-type by doping n-type impurities such as Si, Te, and Sn. . Next, the contact layer 4 is preferably formed as a layer having as low a resistance as possible because a source electrode and a drain electrode for ohmic junction are formed thereon. In the case of being made of GaN, it is preferable to form a Si-doped n-GaN layer formed by, for example, doping Si, which is an n-type impurity, at a high concentration. In addition, GaAs, InGaAs, and the like having a smaller band gap than GaN can also be used as a material for the contact layer.

The GaN-based FET (A) of the present invention can be manufactured as follows. The manufacturing method will be described in the order of steps with reference to the drawings. First, as shown in FIG. 2, the semi-insulating surface of the substrate 1, for example an insulating film by plasma CVD, for example, by forming a the SiN _x film 8A producing starting material A _0. Next, after applying and patterning a photoresist 9A on the surface of the SiN _x film 8A of the material A ₀ , R
The SiN _x film 8A is removed by etching to the surface of the semi-insulating substrate 1 by a dry etching method such as IE to form an opening 10A in which a lower gate electrode is to be formed (FIG. 3). The material of the lower gate electrode is sputtered from the opening 10A to the exposed surface of the semi-insulating substrate 1 by ECR using plasma gas, and then the SiN _x film 8A is removed.

[0018] As a result, as shown in FIG. 4, material A ₁ of the lower gate electrode 2A in a predetermined position of the semi-insulating substrate 1 are wired in a pattern of design criteria can be obtained. In this step, the openings 1 formed in the SiN _x film 8A are formed.
0A needs to be formed in the same pattern as the pattern of the gate electrode 2B of the GaN-based FET (A) shown in FIG.

[0019] then, again plasma C on the entire surface of the material A ₁
The the SiN _x film 8B formed with VD method, further After patterning a photoresist is applied 9B, to the material A ₂ shown in FIG. 5 performs dry etching such as RIE. In this material A _2, portions 8B, 9 indicated by dashed lines
B is a region for forming the active layer 3 of the GaN-based FET (A) shown in FIG. 1, and portions 8B and 9B shown by solid lines.
Are regions for forming the contact layer 4.

Next, after a predetermined GaN-based compound semiconductor is selectively grown on the entire surface of the raw material A ₂ , all of the SiN _x 9B is removed by etching. As a result, as shown in FIG. 6, a material A3 in which the lower gate electrode 2A is embedded in the active layer ₃ is obtained. Then, as shown in FIG. 7, a SiN _x film 8C is formed on the entire surface of the material A ₃ , and a photoresist 9C is further applied thereon to form an SiN _x film for covering the active layer 3.
After patterning so that the film 8C (the portion indicated by the solid line) remains, the surface of the semi-insulating substrate 1 and the side portion of the active layer 3 are removed by performing a dry etching method such as RIE to remove the portion indicated by the broken line. Express.

[0021] Then, perform crystal growth of a given GaN-based compound semiconductor, as shown in FIG. 8, to produce a material A ₄ in which the contact layers 4 and 4 are formed in the portions that are exposed. Then, the photoresist 9C of this material A ₄
And the SiN _x film 8C are removed by a dry etching method, and then the SiN _x film 8D is again formed as a protective film on the entire surface,
Further, a photoresist 9D is applied, the portions where the source electrode and the drain electrode are to be formed are removed by dry etching, and the upper surfaces of the contact layers 4 and 4 are exposed there. by sputtering in ECR to form a source electrode 5 and drain electrode 6, to produce a material a ₅ shown in FIG.

[0022] Next, after removing the photoresist 9D, a new photoresist is applied to the entire surface of the material A _5,
The portion corresponding to the gate electrode to be formed on the active layer 3 is opened by dry etching to remove the photoresist mixture was allowed to expose the top surface 3a, to produce a material A ₆ shown in FIG. 10. Finally, a photoresist is applied to the entire surface of the material A ₆ and patterned so as to remain all except for the portion where the gate electrode 2 B is to be formed. Then, the same material as the lower gate electrode 2 A is coated on the upper surface 3 a of the active layer 3. The gate electrode 2B is formed by vapor deposition, and the GaN-based FET shown in FIG.
(A).

FIG. 11 shows another example GaN-based FET B of the present invention. This GaN-based FET (B) is the same as the GaN-based FET (A) shown in FIG. 1 except that the active layer 3 is composed of a layer 3 ′ composed of a plurality of layers (three layers in the figure). Here, each layer of the active layer 3 'is formed of a GaN-based compound semiconductor, but the upper and lower layers 3A, 3A
Are made of the same material, and the intermediate layer 3B is composed of upper and lower layers 3A and 3A.
By being made of a material different from A, the overall structure has a layer structure having a heterojunction interface between the layers. Specifically, the upper and lower layers 3A. 3A is, for example, non-doped AlGaN, and the intermediate layer 3B can be formed of non-doped GaN.

The upper and lower layers 3A, 3A are non-doped G
aN, the intermediate layer 3B may be made of non-doped InGaN, and the upper and lower layers 3A, 3A may be made of non-doped AlGaN.
The intermediate layer 3B is made of non-doped GANA with InGaNAsP.
It may be composed of sP. In the case of the active layer 3 ', when a voltage is applied between the lower gate electrode 2A and the gate electrode 2B, a two-dimensional electron gas layer is generated at the heterojunction interface of the active layer 3'.

As a result, the electron mobility of the channel increases, and a large current flows between the source electrode 5 and the drain electrode 6. That is, the on-resistance decreases.

[0026]

EXAMPLE A GaN-based FET (A) was manufactured as follows. First, S is applied to the sapphire substrate 1 by plasma CVD.
It was produced material A ₀ shown in FIG. 2 by forming a iN _x film 8A. Next, a photoresist 9A was applied to the SiN _x film 8A, followed by patterning, and the SiN _x film was removed by RIE to form an opening 10A (FIG. 3).

Next, an EC using Ar plasma gas is used.
Au and Pt are sequentially sputtered by an R apparatus to form a lower gate electrode 2A in the opening 10A, and then SiN _x
The film was removed by etching with HF to obtain the material A ₁ shown in FIG.
Was manufactured. On the entire surface of the material A _1, after forming a re the SiN _x film 8B by plasma CVD, to pattern the further portion to form the active layer 3 by applying a photoresist 9B thereon, open at RIE and the material a ₂ (Fig. 5).

Then, nitrogen (3 × 10 ⁻⁶ Tor) was added to the material A _2.
r), Ga (5 × 10 ⁻⁷ Torr), Si (5 × 10 ⁻⁹ Torr)
Using r), a 1 μm-thick n-GaN active layer 3 burying the lower gate electrode 2A is formed by molecular beam epitaxial growth at a growth temperature of 850 ° C., and the entire SiN _x film is etched away with HF. It was produced material a ₃ shown in. Note that Si in the active layer 3 made of n-GaN
Has a doping concentration of 2 × 10 ¹⁷ cm ⁻³ .

An SiN _x film 8C is formed again on the entire surface of the material A ₃ , and a photoresist 9C is further applied thereon.
The SiN _x film 8C on the active layer 3 was patterned so as to remain, and the surface of the sapphire substrate 1 was exposed by RIE by opening a portion where a contact layer was to be formed (FIG. 7). Next, radical nitrogen (3
× 10 ⁻⁶ Torr), Ga (5 × 10 ⁻⁷ Torr), Si (8 ×
10 ⁻⁸ Torr) at a growth temperature of 850 ° C.
1 μm thick contact layer 4 made of doped-GaN
4 formed by the prepared material A ₄ shown in FIG. In addition,
The doping concentration of Si in the contact layers 4 and 4 is 2
× 10 ¹⁹ cm ^-3 .

After the photoresist 9C and the SiN _x film 8C are all removed, a SiN _x film 8D is formed again on the entire surface, and further the photoresist 9D is applied and then patterned to form a source electrode and a drain electrode. A desired portion is opened by RIE, and Al, Ti, and Au are sequentially sputtered there by ECR using an Ar plasma gas to form a source electrode 5 and a drain electrode 6, and the material A ₅ shown in FIG.
Was manufactured.

Next, after removing the photoresist 9D, a new photoresist is applied and patterned, and a portion where a gate electrode is to be formed is opened by RIE to form an active layer 3D.
To expose the upper surface 3a and the material A ₆ shown in FIG. 10. Finally, the source electrode and the drain electrode are masked, patterned with a photoresist to open an area where the upper gate electrode is to be formed, and Pt and Au are sequentially sputtered there by ECR vapor deposition using an Ar plasma gas. Pt / Au deposited on unnecessary portions is removed with an organic solvent to form a gate electrode, and the MES-FET type Ga shown in FIG.
An N-based FET (A) was manufactured.

The source-drain voltage of this MES-FET was saturated at 10A. Also, the breakdown voltage exceeded 100V. And the on-resistance was 10 mΩcm ⁻² or less. In addition, the FET operated at a temperature of 300 ° C.

[0033]

As apparent from the above description, the GaN-based FET of the present invention has a low on-resistance and can realize a large current switching operation. At the same time, a gate portion is formed above and below the active layer to form a gate portion sandwiching the channel of the active layer from above and below, whereby a pinch-off state in the gate portion can be easily realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example A of a GaN-based FET of the present invention.

FIG. 2 is a sectional view showing a starting material A ₀ of a GaN-based FET (A).

FIG. 3 is a cross-sectional view showing a state where a formation location of a lower gate electrode is opened.

4 is a sectional view showing the material A ₁ of the lower gate electrode is formed.

5 is a cross-sectional view showing the material A _2.

FIG. 6 is a sectional view showing a state where an active layer 3 is formed.

FIG. 7 is a cross-sectional view showing a state where a formation location of a contact layer is opened.

8 is a sectional view showing the material A ₄ in which the contact layer is formed.

9 is a sectional view showing the material A ₅ in a state where the top surface of the active layer is exposed.

10 is a cross-sectional view showing the material A ₆ in which the source electrode and the drain electrode are formed.

FIG. 11 is a sectional view showing Example B of another GaN-based FET of the present invention.

[Explanation of symbols]

Reference Signs List 1 semi-insulating substrate (sapphire substrate) 2A lower gate electrode 2B gate electrode 3, 3 ', 3A, 3B active layer 3a upper surface of active layer 4 contact layer 5 source electrode 6 drain electrode 7A, 7B depletion layer 8A, 8B, 8C, 8D Protective film (SiN _x film) 9A, 9B, 9C, 9D Photoresist 10A Opening

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F102 FA02 GB01 GC01 GC02 GJ03 GJ04 GJ05 GJ10 GL04 GM08 GN04 GQ03 GS03 GT03 HC01 HC15

Claims (2)

[Claims] 1. A lower gate electrode made of the same material as a gate electrode to be formed is directly formed on a semi-insulating substrate in the same pattern as the gate electrode, and the lower gate electrode is embedded. At least one active layer made of a GaN-based compound semiconductor is formed, the gate electrode is formed on an upper surface of the active layer, and gate electrodes are arranged above and below the active layer. GaN field effect transistor. 2. The GaN-based field effect transistor according to claim 1, wherein said active layer has a three-layer structure, and has a heterojunction structure between the layers.