JP2003188190A - Heterojunction field-effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a III nitride heterojunction field-effect transistor (HFET) having a recess structure. <P>SOLUTION: A method for manufacturing a heterojunction field-effect transistor comprises the steps of forming a contact layer 22 having the recess structure by utilizing an etching selection ratio of a carrier supply layer 20 to a precursor contact layer 22' of a first laminate 30 obtained by sequentially providing a buffer layer 14 made of a GaN, a channel layer 16 made of a GaN containing an undoped or n-type impurity, a carrier supply layer 20 having a forbidden band width larger than that of the channel layer and made of an Al<SB>x</SB>In<SB>y</SB>Ga<SB>1-(x+y)</SB>N (0<x<0, 0<y<1, x+y≤1) containing an n-type impurity, and a precursor contact layer 22' made of a GaN containing an n-type impurity of a higher concentration than that of the carrier supply layer on a substrate. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor, and more particularly to a group III nitride (III-Nitrid
e) Field-effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art A heterojunction field effect transistor (HFET: Heterojunction) using a heterojunction made of different kinds of semiconductors.
ction Feild Effect Transisitor Hereinafter, it may be referred to as HFET. ), The importance is increasing year by year as a high output device such as microwave.

While GaAs HFETs and the like have come to practical use at present, group III nitride HFETs have been actively researched due to the development of group III nitride materials associated with the production of blue / green LEDs and the like. There is.

[0004] For example, in a document by Kawai et al. (Materials of the 49th Research Meeting of the 151st Committee of the Society for the Limitation of Electronic Structure, Japan Society for the Promotion of Science), the group III nitride material is 6-8 compared to GaAs (gallium arsenide). It has been reported that the group III nitride-based HFET as a high-speed power device is significant because it has excellent characteristics such as a double breakdown electric field and a 2-3 times saturation speed.

[0005]

Group III nitride HFET
For example, as shown in the literature, GaN-based HFETs in which carriers run in a GaN channel layer having a small forbidden band width and a gate electrode is provided via an AlGaN electron supply layer having a larger forbidden band width than the channel layer There is (normal type).

In this GaN-based HFET, the source and drain electrodes must be formed on the electron supply layer which is the gate contact layer (or also referred to as Schottky layer) on which the gate electrode is formed.

In this (normal type) GaN-based HFET (more specifically, GaN / AlGaN-based HFET), reactive ion etching (RIE: Reactive Ion E) using chlorine gas is used.
Hereinafter referred to as tRIE. ) Method is a reliable etching means, it is difficult to form the recess structure with good reproducibility because there is almost no etching selection ratio between AlGaN and GaN.

On the other hand, for example, a GaAs-based HF having a GaAs layer as a channel layer and an AlGaAs layer as an electron supply layer.
In ET, the etching selectivity between AlGaAs and GaAs is used to make Ga on the AlGaAs electron supply layer.
A recess structure is formed by the As contact layer.
As a result, the contact layer in which the source and drain electrodes are formed and the layer in which the gate electrode is formed can be separated, and the contact resistance between the source and drain electrodes can be reduced.

However, conventional III-nitride HFE
In T, for example, a GaN-based HFET, it was difficult to improve the device characteristics by such a recess structure.

In the GaN-based HFET, AlGaN
It is known that when forming a layer, a high quality crystal cannot be obtained if the Al composition ratio is large. Therefore, A
Although Al _0.2 Ga _0.8 N having an l composition ratio of about _0.2 is used, the contact resistance of the source and drain electrodes on the AlGaN layer is as high as about 10 ⁻⁵ Ωcm. Moreover, since the source resistance increases with the increase of the contact resistance, the device characteristics are deteriorated.

Ga in which the recess structure is not formed
In the N-type HFET, a vast surface depletion layer is formed. As a result, this undesired surface depletion layer also increases the source resistance.

Therefore, the advent of a technique for technically solving the above-mentioned various problems has been desired.

[0013]

Therefore, the heterojunction field effect transistor of the present invention has the following structural features.

That is, a GaN buffer layer and GaN containing undoped or n-type impurities are formed on a substrate.
And a channel layer of Al _x In _y Ga having a band gap larger than that of the channel layer and containing an n-type impurity.
_{1- (x + y)} N (0 <x <1,0 <y <1, x + y ≦ 1) and a GaN containing a higher concentration of n-type impurities than the carrier supply layer. , A contact layer formed as two regions separated from each other, and on the carrier supply layer between the two regions,
A gate electrode is provided separately from the two regions, a source electrode is provided on one region of the two regions, and a drain electrode is provided on the other region.

The heterojunction field effect transistor (HFET) manufactured in this manner is, for example, a GaN-based HFET.
It is suitable to be applied to a FET. According to the structure of the HFET of the present invention, the recess structure is formed by the contact layer. Therefore, for example, the increase in the source resistance due to the surface depletion layer as described above can be reduced as compared with the conventional GaN-based HFET.

Further, according to the structure of the HFET of the present invention described above, the impurity concentration in the contact layer where the source electrode and the drain electrode are formed can be made higher than that of the conventional GaN-based HFET. Therefore, the barrier against electrons (potential barrier) can be lowered, and the contact between the source electrode and the drain electrode (contact)
The resistance can be reduced.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIGS.
An embodiment of the present invention will be described. 1 to 1
FIG. 0 is a process drawing showing a cross section of a structural example of a method for manufacturing a heterojunction field effect transistor according to the present invention. It should be noted that the respective drawings merely schematically show the shapes, sizes and arrangement relationships of the respective constituent components to the extent that the present invention can be understood, and the present invention is not limited to the illustrated examples. Further, hatching (diagonal line) showing a cross section is omitted except for a part for the sake of easy understanding of the drawing. Further, in the following description, specific materials and conditions may be used, but these materials and conditions are only one of the preferred examples, and are not limited thereto. Further, in each drawing, the same constituent components are denoted by the same reference numerals, and the duplicated description thereof may be omitted.

<First Embodiment> Referring to FIGS. 1 to 3, manufacture of a heterojunction field effect transistor (hereinafter also referred to as an HFET) according to a first embodiment of the present invention. The method will be explained. Here, HFET
As an example, a high electron mobility transistor (HEMT) using a two-dimensional electron gas (2DEG) quantized at a heterojunction surface (HEMT: High Electron Mobility Transistor, HEMT
Called. ), Which is the manufacturing method of the normal HEMT.

According to the first embodiment, first, in a first step, a buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and undoped Al _x In are formed on a substrate. _y Ga _{1- (x + y)} N (0 <
x <1,0 <y <1, x + y ≦ 1) and an Al _x In _y Ga _{1- (x + y)} having a forbidden band width larger than that of the channel layer and containing an n-type impurity. N (0 <x <
1, 0 <y <1, x + y ≦ 1), and a contact layer made of GaN containing an n-type impurity at a concentration higher than that of the carrier supply layer are sequentially provided to form a first stacked body. To do. Therefore, the first step will be described below.

In this embodiment, in forming the first laminated body, each layer of the first laminated body is formed by metal organic chemical vapor deposition (MOCVD) using ammonia (NH ₃ ) as a nitrogen (N ₂ ) source. ) Is used.

First, sapphire (Al ₂ O ₃ ) was used as a substrate.
The (0001) substrate 12 is set in a crystal growth apparatus. Then, under the condition that the substrate temperature is heated to 600 ° C., Ga
The N low-temperature buffer layer (hereinafter, also simply referred to as a buffer layer) 14 is formed with a film thickness of 50 nm. Then, under the condition that the substrate temperature is heated to 1050 ° C., the undoped GaN channel layer 16 is formed to a thickness of 2000 nm on the GaN buffer layer 14. Then, under the same conditions, the undoped Al _0.2 In _0.05 Ga _0.75 N spacer layer 18 is formed on the undoped GaN channel layer 16.
Is formed with a film thickness of 3 nm. Then, on this undoped Al _0.2 In _0.05 Ga _0.75 N spacer layer 18, silicon (Si) was added at 5 × 10 ¹⁸ cm ⁻³ , n-type Al _0.2
The In _0.05 Ga _0.75 N carrier supply layer 20 is formed with a film thickness of 50 nm. Then, this n-type Al _0.2 In _0.05 Ga
Si of 1 × 10 ¹⁹ cm on the _0.75 N carrier supply layer 20.
^-3- added n ⁺ (which is referred to as n ⁺ because it has a higher impurity concentration than the carrier supply layer 20) type GaN precursor contact layer (etched to be the contact layer 22 in a later step) 22 ′. It is formed with a film thickness of 50 nm.

The first laminated body 30 thus obtained is shown in FIG.
It shows in (A). In this embodiment, the first laminated body 3
In forming 0, the buffer layer 14 and the channel layer 1
6, the crystal layers to be the spacer layer 18, the carrier supply layer 20, and the precursor contact layer 22 ′ are lattice-matched, that is, these crystal layers (14, 1) are grown on the substrate 12.
6, 18, 20, 22 ') are formed so that the lattice constants thereof match (match). The lattice matching can reduce the internal stress generated in each layer due to the lattice constant mismatch.

The composition ratio of the Al _x In _y Ga _{1- (x + y)} N layer is not limited to only Al _0.2 In _0.05 Ga _0.75 N, and the band gap (= forbidden band width) shown in FIG. It is assumed that it has a composition within a triangle having AlN-InN-GaN as the apex in the relationship diagram with the bond length ("Nitride Semiconductor Starting from Here" p.5, edited by Japan Society of Applied Physics). Also,
More preferably, the composition of the points on the thick solid line in the triangle,
That is, the bond length is equal to that of GaN and Ga is
Al _x In _y Ga having a composition with a forbidden band width larger than N
_The present invention can be more suitably implemented by arbitrarily and suitably using _{1- (x + y)} N (0 <x <1,0 <y <1, x + y ≦ 1).

Further, in this embodiment, the channel layer 1
Although 6 is an undoped GaN layer, the present invention can be appropriately applied to an n-type GaN layer containing n-type impurities.

Next, in a second step, the precursory contact layer 22 'is formed on the precursory contact layer 22' as two regions separated in parallel to the substrate surface, for example, an island region (or a strip region). ) For forming (processing)
Form a mask.

Specifically, a recess structure is formed by the precursor contact layer 22 '. For that purpose, the precursor contact layer 22' is spaced (width) on the precursor contact layer 22 'shown in FIG. 1 (A). Only a, for example, a resist pattern 42 that is exposed in a stripe shape is formed by arbitrary suitable photolithography. This resist pattern 42 is used as a first mask. Then, this resist pattern 42 is used as an etching mask (see FIG. 1B).

Next, as a third step, anisotropic etching is performed from above the first mask 42 to selectively remove the precursor contact layer 22 ′ exposed from the first mask 42 to remove the carrier supply layer 20. Expose. By this etching, the remaining region of the precursor contact layer 22 'becomes two island-shaped regions 22a and 22b. After that, the first mask 42
To remove.

Specifically, in this embodiment, as an etching method in the third step, reactive ion etching (RIE: Reactive Ion Etchi), which is one of dry etching, is performed.
Hereinafter referred to as RIE. ) Method is used. In the RIE method,
For example, the first laminated body 30 is kept warm at 23 ° C. and high frequency (R
F) Under a reduced pressure of 1.5 mTorr and a power of 50 W, chlorine gas (Cl ₂ ) and argon gas (Ar) have a gas flow rate of 5 sccm and 10 sccm, respectively.

At this time, since the vapor pressure of the chloride of indium (In) is lower than the vapor pressure of the chloride of gallium (Ga), the carrier supply layer 20 which is an Al _0.2 In _0.05 Ga _0.75 N layer containing In is , The GaN layer is less likely to be etched than the precursor contact layer 22 '.

As a result, as shown in FIG. 1C, substantially only a part of the precursory contact layer 22 'can be etched easily and with good reproducibility. Then, the remaining regions of the precursor contact layer 22 'form island-shaped regions 22a and 22b which are separated by a substantial distance a. The island-shaped regions 22a and 22b are respectively formed in the contact layer 22.
Becomes In addition, the two contact layers 22 (22a,
The carrier supply layer 20 is exposed in a portion sandwiched by 22b), that is, in the stripe-shaped opening 28. After that, the resist pattern 42 is removed by any suitable method to obtain the second stacked body 60 (see FIG. 2A).

Next, as a fourth step, two regions (22
a, 22b) so as to expose at least a part of the carrier supply layer 20 exposed in the opening 28 which is a portion sandwiched between the second laminated body 60 and the second laminated body 60 obtained in the third step.
Form a mask.

Therefore, the second laminated body 6 shown in FIG.
On the exposed carrier supply layer 20 of 0, a resist pattern 44 is formed by any suitable photolithography so as to expose the carrier supply layer 20 at intervals b, for example, in a stripe shape (see FIG. 2B). ). This resist pattern 44 is used as a second mask.

Next, in a fifth step, a first metal is vapor-deposited from above the second mask 44 to form a gate electrode made of the first metal on the carrier supply layer 20, and then the first metal is deposited. The second mask 44 being removed is removed.

Specifically, rhenium (Re) as the first metal is vapor-deposited from above the resist pattern 44 so as to have a film thickness of 100 nm (not shown). After that, the resist pattern 44 on which the first metal is formed is removed by a lift-off method, and the stripe-shaped gate electrode 46 made of the first metal and having a substantial width b is formed on the carrier supply layer 20. Get the body 70 (Fig. 2 (C))
reference).

Next, in a sixth step, the third laminated layer obtained in the fifth step is exposed so that at least a part of each of the two island-shaped regions 22a and 22b exposed in the fifth step is exposed. A third mask is formed on the body 70.

Specifically, the contact layers are exposed on the respective contact layers 22 formed in the island-shaped regions 22a and 22b shown in FIG. 2C by a distance c, for example, in a stripe shape. The resist pattern 48 is formed by any suitable photolithography (FIG. 3).
(See (A)). This resist pattern 48 is used as a third mask.

Next, as a seventh step, a second metal is vapor-deposited from above the third mask 48 to form the source electrode 50 made of the second metal on one of the two regions and the other of the two regions. After forming the drain electrode 52 made of the second metal on the region, the third mask 48 on which the second metal is deposited is removed.

Specifically, titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au) as the second metal are sequentially deposited from above the resist pattern 48 to form a laminated metal. More specifically, vapor deposition is performed so that the film thickness of titanium is 15 nm, the film thickness of aluminum is 220 nm, the film thickness of nickel is 40 nm, and the film thickness of gold is 50 nm (not shown). After that, the resist pattern 4 on which this laminated metal is formed by the lift-off method
Remove 8. Then, the third laminated body 70 including the remaining laminated metal portions (regions) 50 and 52 is replaced with nitrogen (N
₂ ) Anneal at a temperature of 450 ° C or higher for several minutes in an atmosphere.

Thus, the two island regions 22a and 22b are formed.
Heterojunctions are formed by forming striped laminated metal layers 50 and 52 each having a substantial width c on the contact layer 22 formed in the above. One of them is the source electrode 50 and the other is the drain electrode 52. The field effect transistor 10 is obtained (see FIG. 3B).

As is clear from the above description, in the heterojunction field effect transistor manufactured in this embodiment, the recess structure is formed by the island regions 22a and 22b which are the contact layers on the carrier supply layer 20. Therefore, the source resistance can be reduced.

Further, the source electrode 50 and the drain electrode 5
2 is formed on the surface of the contact layer 22 with n
Since the type impurities are contained at a high concentration, the barrier against electrons (potential barrier) can be lowered. As a result, the contact resistance between the source electrode 50 and the drain electrode 52 and the contact layer 22 (22a, 22b) can be reduced, and a good GaN-based HFET can be obtained.

Also, a GaN / AlInGaN system HFET
The etching rate in RIE of conventional GaN-based H
It is sufficiently slower than the etching rate of the FET (GaN / AlGaN system). Therefore, the recess structure can be designed with good controllability and reproducibility.

<Second Embodiment> A method for manufacturing a heterojunction field effect transistor according to a second embodiment of the present invention will be described with reference to FIGS.

In the second embodiment, the gate electrode 46 is first formed in the first embodiment, and then the source electrode 50 and the drain electrode 52 are formed in the reverse order. The difference is that they are doing.

First, the first step to the third step are carried out in the same manner as the first step to the third step of the first embodiment. Then, the second laminated body 6 obtained by going through the third step
0 is shown in FIG.

Next, in this embodiment, as the fourth step, the third step is performed so that at least a part of the pair of contact layers 22a and 22b exposed in the third step is exposed. On the second stacked body 60, the second
Form a mask.

Specifically, a second mask for exposing the contact layer 22 by a distance c on each contact layer 22 formed in the island regions 22a and 22b shown in FIG. 4A. Forming a resist pattern 54 (see FIG. 4B).

Next, as a fifth step, a second metal is vapor-deposited from above the second mask 54 to form the source electrode 50 made of the second metal on one of the two regions and the other of the two regions. After forming the drain electrode 52 made of the second metal on the region, the second mask 54 on which the second metal is deposited is removed.

Specifically, the laminated metal described in the first embodiment is vapor-deposited as the second metal from above the resist pattern 54 (not shown). Then, the resist pattern 54 is removed by the lift-off method. And
The second laminated body 60 including the remaining laminated metal portions (regions) 50 and 52 is annealed at a temperature of 450 ° C. or higher in a nitrogen (N ₂ ) atmosphere for several minutes.

Thus, the two island regions 22a and 22b are formed.
A third stacked body 80 is obtained in which the striped source electrode 50 and the drain electrode 52 each having a substantial width c are formed on the contact layer 22 formed in FIG.
(See (C)).

Next, as a sixth step, two island regions 2 are formed.
The third portion obtained in the fifth step so as to expose at least a part of the carrier supply layer 20 exposed in the stripe-shaped opening 28, that is, the portion sandwiched between 2a and 22b.
A third mask is formed on the stacked body 80.

Concretely, the third carrier 80 is exposed on the exposed carrier supply layer 20 of the third laminated body 80 shown in FIG. A resist pattern 56 as a mask is formed (see FIG. 5A).

Next, as a seventh step, a first metal is vapor-deposited from above the third mask 56 to form a gate electrode made of the first metal on the carrier supply layer 20, and then the first metal is deposited. The third mask 56 that has been removed is removed.

Specifically, the rhenium described in the first embodiment is vapor-deposited as the first metal from above the resist pattern 56. After that, the resist pattern 56 is removed by the lift-off method. Thus, the gate electrode 46 made of the first metal is formed on the carrier supply layer 20 to obtain the heterojunction field effect transistor 10 (see FIG. 5B).

As is clear from the above description, the heterojunction field effect transistor manufactured in this embodiment can obtain the same effect as that of the first embodiment.

Further, in this embodiment, the source electrode and the drain electrode are formed before forming the gate electrode. Therefore, the gate electrode (Schottky contact portion) is not exposed to the annealing atmosphere. Therefore, it is possible to form a good quality Schottky contact as compared with the first embodiment.

<Third Embodiment> A method of manufacturing a heterojunction field effect transistor according to a third embodiment of the present invention will be described with reference to FIGS.

In the third embodiment, the carrier supply layer 2
This is different from the first embodiment in that the precursor contact layer 22 'is provided after the cap layer 24 is provided on the O.O.

According to the third embodiment, first, as the first step, similarly to the method described in the first embodiment,
On the sapphire substrate 12, the GaN buffer layer 14, the undoped GaN channel layer 16, and the undoped Al _0.2 In
_0.05 Ga _0.75 N spacer layer 18, n-type Al _0.2 In _0.05
A Ga _0.75 N carrier supply layer 20 is sequentially formed.

In this embodiment, n-type Al _0.2 In
_{Between the 0.05} Ga _0.75 N carrier supply layer 20 and the n ⁺ -type GaN precursor contact layer 22 ′ formed later, undoped Al _x In _y Ga _{1- (x + y)} N (0 <x <1, 0 <y <
1, a cap layer 24 of x + y ≦ 1) is provided.

Specifically, in this embodiment, as shown in FIG.
As shown in (A), the cap layer 2 made of undoped Al _0.2 In _0.05 Ga _0.75 N is formed on the carrier supply layer 20.
4 with a film thickness of 2 nm, the precursor contact layer 2
To form 2 '. The laminated body thus obtained is referred to as a first laminated body 90.

In forming the first laminated body 90,
Channel layer 16, spacer layer 18, carrier supply layer 2
0, the crystal layers to be the cap layer 24 and the precursor contact layer 22 ′ are lattice-matched, that is, these crystal layers (16, 18, 20, 24, 22 ′) grown on the substrate 12
It is provided so that the lattice constants of are the same.

Then, the second step is performed in the same manner as the second step of the first embodiment to form a resist pattern 58 on the precursor contact layer 22 'shown in FIG. 6A (FIG. 6).
(See (B)).

Next, the third step is carried out in the same manner as the third step of the first embodiment. In this embodiment, the precursor contact layer 22 'remaining by etching is striped by a substantial distance a. Island-shaped regions 22a spaced apart from each other
And 22b to be the contact layer 22.

Further, in this embodiment, the portion (opening 28) sandwiched between the two contact layers 22 (22a and 22b) remains based on the etching selection ratio with the material of the contact layer 22 as described above. The cap layer 24 to be exposed is exposed (see FIG. 6C). Then, the resist pattern 58 is removed to obtain the second stacked body 95 (FIG. 7).
(See (A)).

Next, the fourth step is carried out in the same manner as the fourth step of the first embodiment, but in this embodiment, as shown in FIG.
As shown in (B), a resist pattern 62 is formed so as to expose the cap layer 24 exposed in the portion sandwiched by the contact layer 22, that is, the opening 28, in stripes by the distance b.

Next, the fifth step is carried out in the same manner as the fifth step of the first embodiment. In this embodiment, the first step is performed.
A third stacked body 97 including the gate electrode 46 made of a metal layer on the cap layer 24 is formed (see FIG. 7C).

Subsequently, by performing the sixth step and the seventh step in the same manner as the sixth step and the seventh step in the first embodiment, the source electrode 50 and the other electrode are formed on one contact layer 22 and the other, respectively. Drain electrode 52 on contact layer 22
Are formed to obtain the heterojunction field effect transistor 10 (see FIG. 8).

As is clear from the above description, the heterojunction field effect transistor manufactured in this embodiment can obtain the same effect as that of the first embodiment.

Further, in this embodiment, the gate electrode is formed on the undoped cap layer. Therefore,
Although the series resistance on the source and drain sides is higher than that in the first embodiment, the Schottky barrier can be kept high. As a result, the gate leakage current can be reduced.

Therefore, it is possible to reduce the contact resistance without lowering the breakdown voltage of the gate electrode, and to obtain good H
FET is obtained.

Also, a GaN / AlInGaN system HFET
Since the etching rate in RIE is sufficiently slow,
The recess structure can be designed with good controllability and reproducibility.

<Fourth Embodiment> A method for manufacturing a heterojunction field effect transistor according to a fourth embodiment of the present invention will be described with reference to FIGS.

In the fourth embodiment, the gate electrode 46 in the third embodiment is formed first, and then the source electrode 50 and the drain electrode 52 are formed in the reverse order. The difference is that they are doing.

First, the first step to the third step are carried out in the same manner as the first step to the third step of the third embodiment. And the 2nd laminated body 9 obtained by performing to a 3rd process
5 is shown in FIG.

Next, a fourth step is performed by the same method as described in the fourth step of the second embodiment, and a resist pattern 64 is formed on the contact layer 22 shown in FIG. See FIG. 9B).

Next, the fifth step is carried out in the same manner as the fifth step of the second embodiment.

Specifically, the laminated metal described in the first embodiment is vapor-deposited as the second metal from above the resist pattern 64 (not shown). Then, the resist pattern 64 is removed by the lift-off method. And
The second laminated body 95 including the remaining laminated metal portions (regions) 50 and 52 is annealed at a temperature of 450 ° C. or higher in a nitrogen (N ₂ ) atmosphere for several minutes. Thus, the contact layer 22 formed on the two island-shaped regions 22a and 22b
On top, a striped source electrode 50 having a substantial width c
A third stacked body 97 in which the drain electrode 52 and the drain electrode 52 are formed is obtained (see FIG. 9C).

Next, the sixth step is carried out in the same manner as the sixth step of the second embodiment. In this embodiment, the contact layer 2 formed on the two island regions 22a and 22b.
The resist pattern 66 is formed on the third stacked body 97 so that at least a part (space b) of the cap layer 24 exposed at the portion sandwiched by 2 is exposed in a stripe shape (see FIG. 10A). ).

Next, the seventh step is performed in the same manner as the seventh step of the second embodiment. In this embodiment, the gate electrode 46 is formed on the cap layer 24 to obtain the heterojunction field effect transistor 10 (see FIG. 10B).

As is apparent from the above description, the heterojunction field effect transistor manufactured in this embodiment can obtain the same effects as those in the third embodiment.

Further, in this embodiment, as in the second embodiment, the gate electrode is not exposed to the annealing treatment because the source electrode and the drain electrode are first formed. Therefore, it is possible to form a good quality Schottky contact as compared with the third embodiment.

As described above, the present invention is not limited to the combination of the above-described embodiments. Therefore, the present invention can be applied by combining suitable conditions at any suitable stage.

For example, in each of the above-described embodiments, the hetero interface, which is the interface between the channel layer and the carrier supply layer, is
By providing a spacer layer having the same electron affinity as the carrier supply layer and containing no impurities, the electron mobility in the channel layer is increased.

However, although the electron mobility is increased by providing the spacer layer, the two-dimensional electron concentration is decreased. Therefore, it is not always necessary to provide the spacer layer, and the spacer layer may not be provided depending on the design and purpose.

Further, the present invention can be appropriately applied to semiconductor devices other than HFETs (including semiconductor devices having a double recess structure).

In each embodiment, the sapphire (A
l ₂ O ₃ ) substrate was used, but a silicon carbide (SiC) substrate,
A gallium nitride (GaN) substrate or the like may be used. When silicon carbide is used as the substrate, the buffer layer is preferably made of aluminum nitride (AlN).

Further, as a nitrogen source for crystal growth,
Nmonia (NH₃) Was used, but tert-butylhydrazine
((CH₃)₃CHNNH₂) Can be used. So
In the case of, the formation of the laminated film above the low temperature buffer layer,
The substrate temperature can be set to 670 ° C. 3rd spot
In addition to luhydrazine, dimethylhydrazine ((C
H ₃)₂NNH₂) Etc. are available.

Further, the concentration distribution of the n-type impurities does not necessarily have to be uniform, and may be a distribution which locally changes according to the purpose and design.

As the n-type impurity (dopant), tin (Sn), tellurium (Te), or the like can be used in addition to silicon.

[0091]

As is apparent from the above description, according to the present invention, the recess structure is formed by the contact layer. Therefore, the conventional Ga having no recess structure
The source resistance can be made smaller than that of the N-type HFET.

Further, the impurity concentration in the contact layer forming the island region where the source electrode and the drain electrode are formed can be increased as compared with the conventional GaN-based HFET.

Therefore, the barrier against electrons (potential barrier) can be lowered, and the contact resistance of the source electrode and the drain electrode can be reduced.

Therefore, a group III nitride HFET having better device characteristics than before can be obtained.

[Brief description of drawings]

1A to 1C are cross-sectional views provided for explaining a manufacturing process of a heterojunction field effect transistor according to a first embodiment of the present invention.

2A to 2C are cross-sectional views provided for explaining a manufacturing process of the heterojunction field effect transistor according to the first embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views provided for explaining a manufacturing process of the heterojunction field effect transistor according to the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views provided for explaining a manufacturing process of a heterojunction field effect transistor according to a second embodiment of the present invention.

5 (A) and 5 (B) are cross-sectional views provided for explaining a manufacturing process of the heterojunction field effect transistor of the second embodiment of the present invention.

6 (A) to 6 (C) are cross-sectional views for explaining the manufacturing process of the heterojunction field effect transistor of the third embodiment of the present invention.

7 (A) to 7 (C) are cross-sectional views for explaining a manufacturing process of the heterojunction field effect transistor of the third embodiment of the present invention.

FIG. 8 is a sectional view for explaining a manufacturing process for a heterojunction field effect transistor according to a third embodiment of the present invention.

9A to 9C are cross-sectional views provided for explaining a manufacturing process of a heterojunction field effect transistor according to a fourth embodiment of the present invention.

10A and 10B are cross-sectional views provided for explaining a manufacturing process of a heterojunction field effect transistor according to a fourth embodiment of the present invention.

FIG. 11 is an Al _x In _y Ga _{1- (x + y)} N according to the present invention.
It is a figure with which the composition ratio of a (0 <x <1,0 <y <1, x + y <= 1) layer is demonstrated.

[Explanation of symbols]

10: heterojunction field effect transistor 12: sapphire substrate 14: buffer layer 16: channel layer 18: spacer layer 20: carrier supply layers 22a, 22b, 22: contact layer 22 ': precursor contact layer 24: cap layer 28: opening 30 , 90: first laminated body 42, 44, 48, 54, 56, 58, 62, 64, 6
6: resist pattern 46: gate electrode 50: source electrode 52: drain electrode 60, 95: second laminated body 70, 80, 97: third laminated body

Continued front page    F-term (reference) 4M104 AA04 AA07 BB04 BB14 CC01                       CC03 DD34 DD68 DD78 FF27                       GG11 GG12 HH15 HH17                 5F102 FA03 GB01 GC01 GD01 GJ02                       GJ04 GJ10 GK04 GL04 GM04                       GM08 GN04 GQ01 GR10 HC11                       HC16 HC19 HC21

Claims (19)

[Claims] 1. A buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and a band gap larger than the channel layer and containing n-type impurities on a substrate. Al _x In _y Ga _{1- (x + y)}
N (0 <x <1, 0 <y <1, x + y ≦ 1), a carrier supply layer, and GaN containing a higher concentration of n-type impurities than the carrier supply layer, separated from each other by 2
Sequentially comprising a contact layer formed as one region,
A gate electrode is provided on the carrier supply layer between the two regions and apart from the two regions, and a source electrode is provided on one of the two regions. And a drain electrode is provided on the other region of the heterojunction field effect transistor. 2. The heterojunction field effect transistor according to claim 1, wherein the lattice constants of the buffer layer, the channel layer, the carrier supply layer and the contact layer are matched. Effect transistor. 3. The heterojunction field effect transistor according to claim 1, wherein undoped Al _x In _y Ga is provided between the channel layer and the carrier supply layer.
A heterojunction field effect transistor, characterized in that a spacer layer made of _{1- (x + y)} N (0 <x <1, 0 <y <1, x + y ≦ 1) is provided. 4. The heterojunction field effect transistor according to claim 3, wherein the lattice constants of the buffer layer, the channel layer, the spacer layer, the carrier supply layer, and the contact layer are matched. Heterojunction field effect transistor. 5. A buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and an Al containing n-type impurities having a larger forbidden band width than the channel layer on a substrate. _x In _y Ga _{1- (x + y)}
N (0 <x <1,0 <y <1, x + y ≦ 1) and a carrier supply layer and undoped Al _x In _y Ga _{1- (x + y)} N
(0 <x <1, 0 <y <1, x + y ≦ 1) and a GaN layer containing an n-type impurity at a higher concentration than the carrier supply layer, and the two regions are separated from each other. And a contact layer formed on the cap layer, and a gate electrode is provided between the two regions on the cap layer so as to be separated from the two regions.
A heterojunction field effect transistor, wherein a source electrode is provided on one of the two regions and a drain electrode is provided on the other region. 6. The heterojunction field effect transistor according to claim 5, wherein the lattice constants of the buffer layer, the channel layer, the carrier supply layer, the cap layer and the contact layer are matched. Heterojunction field effect transistor. 7. The heterojunction field effect transistor according to claim 5, wherein undoped Al _x In _y Ga is provided between the channel layer and the carrier supply layer.
A heterojunction field effect transistor, characterized in that a spacer layer made of _{1- (x + y)} N (0 <x <1, 0 <y <1, x + y ≦ 1) is provided. 8. The heterojunction field effect transistor according to claim 7, wherein the lattice constants of the buffer layer, the channel layer, the spacer layer, the carrier supply layer, the cap layer, and the contact layer are matched. A heterojunction field effect transistor characterized by the above. 9. A buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and a band gap larger than the channel layer and containing n-type impurities on the substrate. Al _x In _y Ga _{1- (x + y)}
A carrier supply layer made of N (0 <x <1, 0 <y <1, x + y ≦ 1) and a contact layer made of GaN containing a higher concentration of n-type impurities than the carrier supply layer are sequentially provided. A first step of forming a first laminated body, a second step of forming a first mask on the contact layer for forming the contact layer in two regions separated from each other, the first mask Etching from above the first
A third step of selectively removing the contact layer exposed from the mask, exposing the carrier supply layer to form the contact layer into the two regions, and then removing the first mask; A fourth step of forming a second mask on the second laminated body obtained in the third step so as to expose at least a part of the carrier supply layer exposed between the two regions; A second metal is vapor-deposited from above the second mask to form a gate electrode made of the first metal on the carrier supply layer, and then the second mask on which the first metal is deposited is removed. A sixth step of forming a third mask on the third laminate obtained in the fifth step, so as to expose at least a part of each of the two regions exposed in the fifth step. Steps, and on the third mask The second metal is vapor-deposited from
A source electrode made of the second metal is formed on one of the two regions, and a drain electrode made of the second metal is formed on the other region, and then the second metal is deposited. A seventh step of removing the mask, and a method for manufacturing a heterojunction field effect transistor. 10. A buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and a band gap larger than that of the channel layers and containing n-type impurities on a substrate. Al _x In _y Ga _{1- (x + y)}
A carrier supply layer made of N (0 <x <1, 0 <y <1, x + y ≦ 1) and a contact layer made of GaN containing a higher concentration of n-type impurities than the carrier supply layer are sequentially provided. A first step of forming a first laminated body, a second step of forming a first mask on the contact layer for forming the contact layer in two regions separated from each other, the first mask Etching from above the first
A third step of selectively removing the contact layer exposed from the mask, exposing the carrier supply layer to form the contact layer into the two regions, and then removing the first mask; A fourth step of forming a second mask on the second laminated body obtained in the third step so as to expose at least a part of each of the two regions exposed in the third step; The second metal is deposited from above the second mask to
The source electrode made of the second metal is formed on one of the two regions, and the drain electrode made of the second metal is formed on the other region, and then the second metal is deposited. 2) a fifth step of removing the mask; and a third step on the third laminate obtained in the fifth step so as to expose at least a part of the carrier supply layer exposed between the two regions. A sixth step of forming a mask, and depositing a first metal from above the third mask to form a gate electrode of the first metal on the carrier supply layer, and then depositing the first metal. And a seventh step of removing the third mask that is present, thereby manufacturing a heterojunction field effect transistor. 11. The method for manufacturing a heterojunction field effect transistor according to claim 9, wherein the first
A method of manufacturing a heterojunction field effect transistor, wherein a laminated body is formed so that lattice constants of the buffer layer, the channel layer, the carrier supply layer, and the contact layer are matched. 12. The method for manufacturing a heterojunction field effect transistor according to claim 9, wherein between the channel layer and the carrier supply layer,
Undoped Al _x In _y Ga _{1- (x + y)} N (0 <x <1,0
A method of manufacturing a heterojunction field effect transistor, characterized in that a spacer layer of <y <1, x + y ≦ 1) is provided. 13. The method of manufacturing a heterojunction field effect transistor according to claim 12, wherein the first stacked body is formed by a lattice of the buffer layer, the channel layer, the spacer layer, the carrier supply layer, and the contact layer. A method for manufacturing a heterojunction field effect transistor, characterized in that the constant junctions are formed. 14. A buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and Al containing an n-type impurity having a band gap larger than that of the channel layer on a substrate. _x In _y Ga _{1- (x + y)}
N (0 <x <1,0 <y <1, x + y ≦ 1) and a carrier supply layer and undoped Al _x In _y Ga _{1- (x + y)} N
A cap layer made of (x <1, y <1, x + y ≦ 1) and a contact layer made of GaN containing a higher concentration of n-type impurities than the carrier supply layer are sequentially provided to form a first stacked body. A first step of forming, a second step of forming a first mask on the contact layer for forming the contact layer in two regions separated from each other, and etching from above the first mask , The first
The third step of selectively removing the contact layer exposed from the mask, exposing the cap layer to form the contact layer into the two regions, and then removing the first mask; Fourth step of forming a second mask on the second laminate obtained in the third step so as to expose at least a part of the cap layer exposed between two regions, and the second mask A fifth step of depositing a first metal from above to form a gate electrode made of the first metal on the cap layer, and then removing the second mask on which the first metal is deposited; A sixth step of forming a third mask on the third stacked body obtained in the fifth step so as to expose at least a part of each of the two regions exposed in the fifth step, From above the third mask, the second gold Metal vapor deposition, the above 2
The source electrode made of the second metal is formed on one of the two regions, and the drain electrode made of the second metal is formed on the other region, and then the second metal is deposited. And a seventh step of removing the mask, the method for manufacturing a heterojunction field effect transistor. 15. A buffer layer made of GaN, a channel layer made of GaN containing undoped or n-type impurities, and an Al containing n-type impurities having a band gap larger than that of the channel layers on a substrate. _x In _y Ga _{1- (x + y)}
N (0 <x <1,0 <y <1, x + y ≦ 1) and a carrier supply layer and undoped Al _x In _y Ga _{1- (x + y)} N
A cap layer made of (x <1, y <1, x + y ≦ 1) and a contact layer made of GaN containing a higher concentration of n-type impurities than the carrier supply layer are sequentially provided to form a first layer.
A first step of forming a laminated body; a second step of forming a first mask on the contact layer for forming the contact layer in two regions separated from each other; Etching the first
The third step of selectively removing the contact layer exposed from the mask, exposing the cap layer to form the contact layer into the two regions, and then removing the first mask; 2 exposed by three steps
To expose at least a portion of each of the two areas,
A fourth step of forming a second mask on the second stack obtained in the third step, and a step of depositing a second metal from above the second mask,
The source electrode made of the second metal is formed on one of the two regions, and the drain electrode made of the second metal is formed on the other region, and then the second metal is deposited. Second step of removing the second mask, and a third mask on the third laminate obtained in the fifth step so as to expose at least a part of the cap layer exposed between the two regions. Forming a gate electrode made of the first metal on the cap layer by vapor-depositing a first metal from above the third mask, and then depositing the first metal. And a seventh step of removing the third mask, the method for manufacturing a heterojunction field effect transistor. 16. The method of manufacturing a heterojunction field effect transistor according to claim 14, wherein the buffer layer, the channel layer, the carrier supply layer, the cap layer, and the contact layer are formed in the first stacked body. A method for manufacturing a heterojunction field effect transistor, which is characterized in that the lattice constants are matched. 17. The method for manufacturing a heterojunction field effect transistor according to claim 14, wherein an undoped Al _x In _y Ga _{1- (is formed} between the channel layer and the carrier supply layer. _{x + y)} N (0 <x <
1. A method for manufacturing a heterojunction field effect transistor, characterized in that a spacer layer of 1,0 <y <1, x + y ≦ 1) is provided. 18. The method for manufacturing a heterojunction field effect transistor according to claim 17, wherein the buffer layer, the channel layer, the spacer layer, the carrier supply layer, the cap layer, and the first stacked body are formed. A method for manufacturing a heterojunction field effect transistor, which is characterized in that the contact layers are formed so that the lattice constants thereof match. 19. The method for manufacturing a heterojunction field effect transistor according to claim 9, wherein the etching is reactive ion etching. Method.