JP2002246848A - Power amplifier and communication equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the size of a power amplifier for amplifying signals in two frequency bands and to increase the efficiency at low output. SOLUTION: An input terminal 501, an input terminal connected to the input terminal 501, a branch circuit 102 having one input and a plurality of outputs, and a branch circuit 102 connected to some other outputs, respectively. Amplifying means 104 and 106 operating at mutually different signal frequencies, a transmission line 108 connected to another output of the branch circuit 102, and respective outputs of the amplifying means and the output from the transmission line are connected. Controls the combining circuit 110, the switch 109 provided between the transmission line and the combining output device, the conduction of the branch circuit 102 and others, the conduction and amplification operations of the amplifying means 104 and 106, and the conduction of the switch 109. Control circuit 112
And

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier and a communication device mainly used in mobile communication.

[0002]

2. Description of the Related Art In mobile communication, there are applications of various systems and frequency bands, and it is desired that a radio device also supports a plurality of applications. Some applications, such as the CDMA system, need to control the output power of a wireless device, and low power consumption is required over a wide dynamic range. There is also a demand for smaller and lighter wireless devices.

Hereinafter, a conventional power amplifier will be described with reference to the drawings.

FIG. 7 shows a block diagram of a conventional power amplifier 700. In the figure, reference numeral 701 denotes a first input terminal;
2 is a first input side matching circuit, 703 is a first input side DC bias supply circuit, 704 is a first transistor, 70
5 is a first output side DC bias supply circuit, and 706 is a first output side DC bias supply circuit.
707, a first output terminal, 708, a second input terminal, 709, a second input side matching circuit, 71
0 is the second input side DC bias supply circuit, and 711 is the second input side DC bias supply circuit.
712 is a second output side DC bias supply circuit, 713 is a second output side matching circuit, and 714 is a second output side
Output terminal.

[0005] The conventional power amplifier having the above configuration operates on signals of two kinds of frequencies, and the operation is as follows. That is, when operating at the first frequency, the first input terminal 702
Are amplified by the first transistor 704 and output to the first output terminal 707. In the case of operating at the second frequency, the signal input to the second input terminal 708 is amplified by the second transistor 712 and output to the second output terminal 714.

Also, when a low-output signal is obtained with respect to the above-described two types of signal inputs, the signal is passed through the first transistor 704 or the second transistor 712 to perform an amplification operation.

[0007]

However, in such a configuration, the power amplifier is completely independent for each frequency, and the number of parts (not shown) between the power amplifier and the antenna is required for two systems. There has been a problem that the size of the wireless device has also been increased.

Further, in the use in a multi-stage amplifier or the like, the power amplifier is generally adjusted so that the efficiency is highest at the maximum output. Therefore, even when the output decreases and a low output signal is required, However, since the power amplifier is operated, there is a problem that the efficiency is deteriorated as a whole.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a single input and output system of a power amplifier operating at a plurality of mutually different frequencies, and switches a signal path according to the output power. It is an object of the present invention to provide a power amplifier which consumes low power even at low output.

[0010]

In order to achieve the above object, a first aspect of the present invention (corresponding to claim 1) comprises a branch output means having an input terminal and a plurality of output terminals, and the branch output means. A plurality of amplifying units connected to a part of the output terminals and operating at different signal frequencies from each other; a bypass unit connected to another output terminal of the branch output unit; and the plurality of amplifying units. A combined output device having an output terminal to the outside, each output of which and an output from the bypass unit being input, a switch unit for switching on / off of conduction of the bypass unit, conduction of the branch output unit, Control means for controlling conduction and amplification operations of the plurality of amplification means and conduction of the switch means, wherein the control means adjusts the signal frequency and the required output power. First, the input to the branch output means is amplified through any one of the plurality of amplifying means and output to the combined output device, or the combined output device is not amplified through the bypass means. This is a power amplifier that controls so as to output to the power amplifier.

Further, the second invention (corresponding to claim 2)
A branch output unit having an input terminal and a plurality of output terminals, a plurality of amplifying units connected to a part of the output of the branch output unit, each operating at a signal frequency different from each other, A bypass transmission line group having a plurality of bypass transmission lines connected in series to each other connected to the other output terminals, and a combined output in which respective outputs of the plurality of amplifying means and outputs from the transmission line group are connected; A first grounding means provided at a first connection point between the transmission line group and the branch output means for controlling conduction, and a second grounding means between each of the bypass transmission lines of the transmission line group. A plurality of second grounding means provided at a connection point of which conduction is controlled, conduction of the branch output means, conduction and amplification operations of the plurality of amplification means, and conduction of the first grounding means When, Serial and control means for controlling the conduction of the second grounding means, said transmission line group as viewed from the combined output-side, partial length of up to each of the second connection point,
And the total length of the transmission line group corresponds to each signal frequency of the plurality of amplifying means, and the partial lengths are, in order from the shortest, from the highest signal frequency of the plurality of amplifying means to the low signal frequency. Corresponding, the overall length corresponds to the lowest signal frequency of the plurality of amplifying means, the control means, depending on the signal frequency and the required output power, input to the branch output means, A power amplifier that performs control such that the signal is amplified through any one of the plurality of amplifying means and output to the combined output device, or is output to the combined output device without being amplified through the transmission line group. .

Further, a third aspect of the present invention (corresponding to claim 3)
A branch output unit having an input terminal and a plurality of output terminals, a plurality of amplifying units connected to a part of the output of the branch output unit, each operating at a signal frequency different from each other, A transmission line connected to the remaining other outputs, and a combined output device to which outputs of the plurality of amplifying units and outputs from the transmission lines are connected,
Ground means provided on the branch output means side of the transmission line, the conduction of which is controlled, and conduction of the branch output means,
Control means for controlling conduction and amplification operations of the plurality of amplifying means and conduction of the ground means, wherein the signal frequencies are different from each other by an even number, and the control means includes the signal frequency and Depending on the required output power, the input to the branch output means is amplified through any of the plurality of amplifying means and output to the combined output device, or amplified through the transmission line. A power amplifier that controls output to the combined output device in a state where the power is not output.

Further, the fourth invention (corresponding to claim 4)
The amplifying means includes a first matching circuit provided on the branch input means side and a second matching circuit provided on the combined output device side.
, A transistor provided between the first matching circuit and the second matching circuit, a transistor provided between the first matching circuit and the transistor, and / or
A DC bias supply circuit provided between the first matching circuit and the transistor, wherein the impedance of at least one of the first matching circuit and the second matching circuit is variable. 3 is a power amplifier of the present invention.

Further, the fifth invention (corresponding to claim 5)
The control means may be configured to output any one of the first matching circuit and the second matching circuit of the one amplifying means in operation in response to an output of one of the plurality of amplifying means in operation. A fourth power amplifier of the present invention that changes the impedance of one or both.

Further, a sixth aspect of the present invention (corresponding to claim 6)
The first matching circuit and / or the second matching circuit may include an input terminal connected to the branch input means or the output side of the transistor, and an output terminal connected to the input side of the transistor or the combined output device. And at least one
One series matching circuit element connected between the input terminal and the output terminal, and at least one between the input terminal and the series matching circuit element, or between the two series matching circuit elements, or A fourth switch connected between the series matching circuit element and the output terminal, the switch being controlled on and off by the control means, and a parallel matching circuit element connected to the other end of the switch. 3 is a power amplifier of the present invention.

A seventh aspect of the present invention (corresponding to claim 7)
The branch input unit includes an amplification unit input switch for conducting each of the plurality of amplification units, and a bypass input switch for conducting any one of the bypass unit, the transmission line, and the transmission line group. The amplifying means input switch is the power amplifier according to any one of the first to third aspects of the present invention that operates as a predistortion compensation circuit.

Further, an eighth aspect of the present invention (corresponding to claim 8)
The seventh aspect of the present invention is the power amplifier according to the seventh aspect of the present invention, wherein the amplifying means input switch has a diode whose on / off is controlled by an input side DC bias to the amplifying means.

A ninth aspect of the present invention (corresponding to claim 9).
Further comprises a multi-frequency DC bias supply circuit connected to a connection point between the output combiner and the output terminal,
The multi-frequency DC bias supply circuit is a power amplifier according to a fourth aspect of the present invention, which operates according to the signal frequency corresponding to the operating amplifying means among the plurality of amplifying means.

According to a tenth aspect of the present invention (corresponding to claim 10), the multi-frequency DC bias supply circuits are provided in series with each other and provided so as to correspond to the corresponding signal frequencies of the plurality of amplifying means. A transmission line group having a plurality of bias transmission lines, and one end side of the transmission line group,
A first bypass capacitor having one end connected to the connection point and connected to the other end of the highest frequency bias transmission line corresponding to the highest signal frequency;
A first sub-switch, which is connected in series with a bypass capacitor of which on / off is controlled by the control means, and at least one second sub-switch, which is connected between a plurality of bias transmission lines of the transmission line group. A bypass capacitor, a second sub-switch connected in series with the second bypass capacitor, and the other end of the transmission line group connected to a side not connected to another bias transmission line; A bias terminal to which a DC bias supplied from a control means is applied; the other end of the highest frequency bias transmission line is grounded via the first bypass capacitor and the first sub-switch; Between the plurality of bias transmission lines of the transmission line group other than the other end of the frequency bias transmission line, the second bypass capacitor and the second sub Grounded via a switch, the first bypass capacitors, among the signal frequency,
The ninth invention of the ninth invention, wherein the short circuit occurs at the highest signal frequency and the second bypass capacitor short-circuits at the signal frequency associated with the sum of the transmission line lengths from the connection position to the connection point. Power amplifier.

According to an eleventh aspect of the present invention (corresponding to claim 11), in a power amplifier having a multi-stage configuration, at least one or more stages of the power amplifier according to any one of the first to tenth aspects is provided with the power amplifier of the present invention. This is a power amplifier having a multi-stage configuration used in combination.

According to a twelfth aspect of the present invention (corresponding to claim 12), all or a part of each part of the power amplifier according to any one of the first to tenth aspects is formed on the same semiconductor substrate. Power amplifier.

According to a thirteenth aspect of the present invention (corresponding to claim 13), all or a part of each part of the power amplifier according to any one of the first to tenth aspects is provided on a plurality of different semiconductor substrates. It is a configured power amplifier.

According to a fourteenth aspect of the present invention (corresponding to claim 14), a signal processing circuit, a transmitting circuit having a power amplifier for transmitting a signal from the signal processing circuit, and an output of the transmitting circuit are provided. A communication device including an antenna for transmitting and receiving a received signal, and a receiving circuit for processing the received signal, wherein the power amplifier is any one of the first to thirteenth power amplifiers of the present invention.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of a power amplifier according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a power amplifier 100 according to Embodiment 1 of the present invention. Figure 1
, 101 is an input terminal, 102 is a branch circuit, 10
3 is a first switch, 104 is first amplifying means operating at a first frequency, 104a is an input-side matching circuit, 104b
Is an output-side matching circuit; 104c is an input-side DC bias supply circuit; 104d is an output-side DC bias supply circuit;
e is a transistor, 105 is a second switch, 106 is second amplifying means operating at a second frequency, 106a is an input side matching circuit, 106b is an output side matching circuit, 106c is an input side DC bias supply circuit, 106d Is an output side DC bias supply circuit, 106e is a transistor, 107 is a third switch, 108 is a transmission line, 109 is a fourth switch, 110 is a combining circuit, 111 is an output terminal, and 112 is a control circuit.

The operation of the power amplifier 100 according to the present embodiment having the above-described configuration is as follows.

The power amplifier 100 operates at a first frequency, and in a first mode requiring an amplification operation, the control circuit 11
2, the first switch 103 is turned on, and the second to fourth switches are turned on.
Switches 105, 107, and 109 are turned off,
A DC bias for obtaining a desired initial current is supplied to the transistor 104e of the amplifying means 104 through the DC bias supply circuits 104c and 104d, and the DC bias is supplied to the transistor 106e of the second amplifying means 106. A DC bias that does not perform the amplification operation is supplied via the circuits 106c and 106d.

At this time, at the first frequency, the control circuit 112 controls the impedance of the combining circuit 110 so that the impedance seen from the input of the second amplifying means 106 to the second amplifying means 106 becomes high. By
Input side and output side matching circuit 106 of the second amplifying means 106
a and 106b are changed. However, output side matching circuit 1
06b may be changed, and the input matching circuit 106a may not be changed.

As a result, the signal input from the input terminal 101 is amplified by the first amplifying means 104, and the output signal is output from the output terminal 111.

In the second mode, which operates at the first frequency and does not require the amplification operation, the control circuit 112 turns off the first and second switches 103 and 105, and turns off the third and fourth switches.
Switches 107 and 109 are turned on, and the transistors 10 of the first and second amplifying units 104 and 106 are turned on.
4e and 106e, a DC bias supply circuit 104c, 1
A direct current bias that does not perform the amplification operation is supplied via 04d, 106c, and 106d.

At this time, at the first frequency, the control circuit 112 controls the impedance of the control circuit 112 so that the impedance seen from the input to which the first amplifying means 104 is connected to the first amplifying means 104 becomes high. By
Input side and output side matching circuit 104 of first amplifying means 104
a, 104b are changed, and the input of the synthesis circuit 110 to which the second amplification means 106 is connected is changed from the input of the second amplification means 10
The control circuit 112 changes the input side and output side matching circuits 106a and 106b of the second amplifying means 106 so that the impedance seen from the 6 side becomes high. However, only the output side matching circuit 106b may be changed, and the input side matching circuit 106a may not necessarily be changed.

As a result, the signal input from the input terminal 101 passes through the transmission line 108, and the output signal is output from the output terminal 111.

In the third mode, which operates at the second frequency and requires an amplifying operation, the control circuit 112 turns on the second switch 105 and turns on the first, third, and fourth switches 10.
3, 107 and 109 are turned off, and the second amplifying means 10
DC bias supply circuit 1
A direct current bias for obtaining a desired initial current is supplied via the first amplification means 104c and 106d.
DC bias supply circuit 1
A DC bias that does not perform an amplification operation is supplied via the terminals 04c and 104d.

At this time, at the second frequency, the control circuit 112 controls the impedance of the combining circuit 110 so that the impedance seen from the input of the first amplifier 104 to the first amplifier 104 becomes higher. By
Input side and output side matching circuit 104 of first amplifying means 104
a and 104b are changed. However, output side matching circuit 1
Only the input side matching circuit 104a may be changed without changing the input side matching circuit 104a.

As a result, the signal input from the input terminal 101 is amplified by the second amplifying means 106, and the output signal is output from the output terminal 111.

In the fourth mode, which operates at the second frequency and does not require the amplification operation, the control circuit 112 turns off the first and second switches 103 and 105, and turns off the third and fourth switches.
Switches 107 and 109 are turned on, and the transistors 10 of the first and second amplifying units 104 and 106 are turned on.
4e and 106e, a DC bias supply circuit 104c, 1
A direct current bias that does not perform the amplification operation is supplied via 04d, 106c, and 106d.

At this time, at the second frequency, the control circuit 112 controls the input of the combining circuit 110 to the first amplifier 104 so that the impedance seen from the input to the first amplifier 104 becomes high. By
Input side and output side matching circuit 104 of first amplifying means 104
a, 104b are changed, and the input of the synthesis circuit 110 to which the second amplification means 106 is connected is changed from the input of the second amplification means 10
The control circuit 112 changes the input side and output side matching circuits 106a and 106b of the second amplifying means 106 so that the impedance seen from the 6 side becomes high. However, only the output side matching circuits 104b and 106b may be changed, and the input side matching circuits 104a and 106a may not necessarily be changed.

Thus, the signal input from the input terminal 101 passes through the transmission line 108, and the output signal is output from the output terminal 111.

The control circuit 112 performs control so that the above four modes are switched according to the operating frequency and the output power.

As described above, according to the present embodiment, the signal path is switched in accordance with the operating frequency and the output power, and in particular, in the second and fourth modes, the output signal is bypassed from the amplifying means. By supplying a bias voltage that does not operate the amplifying unit, the current consumption of the amplifier when the output power is reduced is reduced, so that the efficiency can be improved in a wide output range. In addition, by sharing a signal path in the case where an amplification operation is not required by two frequencies and using a single amplifier output, the circuit can be downsized.

In the above description, the power amplifier 100 includes the first amplifying unit 104 for amplifying the signal of the first frequency and the second amplifying unit 106 for amplifying the signal of the second frequency. The power amplifier of the present invention has been described as having two amplifying units. However, the power amplifier of the present invention is not limited to this, and has a configuration including three or more amplifying units that amplify signals of mutually different frequencies. It is good. In this case, a signal path when no amplification operation is required can be shared by three or more frequencies.

(Embodiment 2) A second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram of a power amplifier 200 according to Embodiment 2 of the present invention. FIG.
, 201 is an input terminal, 202 is a branch circuit, 20
3 is a first switch, 204 is first amplifying means operating at a first frequency, 204a is an input side matching circuit, 204b
Is an output-side matching circuit; 204c is an input-side DC bias supply circuit; 204d is an output-side DC bias supply circuit;
e is a transistor, 205 is a second switch, 206 is a second amplifier operating at a second frequency which is an even multiple of the first frequency, 206a is an input side matching circuit, 206b is an output side matching circuit, 206c Is an input side DC bias supply circuit, 206d is an output side DC bias supply circuit, 206e
Is a transistor, 207 is a third switch, 208 is a transmission line, 209 is a fourth switch, 210 is a combining circuit,
211 is an output terminal, and 212 is a control circuit.

Here, the line length of the transmission line 208 is the first
It is desirable to make the wavelength of the signal having the frequency of 1/4.

The operation of the power amplifier 200 according to the present embodiment having the above-described configuration is as follows.

The power amplifier 200 operates at the first frequency, and in the first mode requiring the amplification operation, the control circuit 21
2, the first and fourth switches 203 and 209 are turned on, the second and third switches 205 and 207 are turned off, and the transistor 204e of the first amplifying means 204
A DC bias for obtaining a desired initial current is supplied through the DC bias supply circuits 204c and 204d, and the transistor 206e of the second amplifying means 206 is amplified through the DC bias supply circuits 206c and 206d. A DC bias that does not perform an operation is supplied.

At this time, at the first frequency, the control circuit 212 is controlled so that the impedance seen from the input of the combining circuit 210 to which the second amplifying means 206 is connected to the second amplifying means 206 becomes high. By
Input side and output side matching circuit 206 of second amplifying means 206
a and 206b are changed. However, the output side matching circuit 2
06b may be changed, and the input matching circuit 206a may not be changed.

Further, when the fourth switch 209 is turned on, the impedance seen from the input of the combining circuit 210 to which the transmission line 208 is connected to the transmission line 208 becomes high impedance at the first frequency, and The impedance becomes low at the frequency of 2.

As a result, the signal input from the input terminal 201 is amplified by the first amplifying means 204, and the output signal is output from the output terminal 211.

In the second mode, which operates at the first frequency and does not require an amplification operation, the control circuit 112 turns off the first, second, and fourth switches 203, 205, and 209 and turns off the third switch. 207 is turned on, and the transistor 20 of each of the first and second amplifying units 204 and 206 is turned on.
4e and 206e, a DC bias supply circuit 204c,
A direct current bias that does not perform an amplification operation is supplied via 04d, 206c, and 206d.

At this time, at the first frequency, the control circuit 212 controls the impedance of the combining circuit 210 from the input to which the first amplifying means 204 is connected to the impedance of the first amplifying means 204 so as to be high. By
Input side and output side matching circuit 204 of first amplifying means 204
a and 204b are changed, and the input of the combining circuit 210 to which the second amplifying means 206 is connected is changed to the second amplifying means 20.
The control circuit 112 changes the input side and output side matching circuits 206a and 206b of the second amplifying means 206 so that the impedance seen from the 6 side becomes high. However, only the output-side matching circuits 204b and 206b may be changed, and the input-side matching circuits 204b and 206a may not necessarily be changed.

Thus, the signal input from the input terminal 201 passes through the transmission line 208, and the output signal is output from the output terminal 211.

In the third mode, which operates at the second frequency and requires an amplifying operation, the control circuit 212 turns on the second switch 205 and turns on the first, third, and fourth switches 20.
3, 207 and 209 are turned off, and the second amplifying means 20
DC bias supply circuit 2
06c and 206d, a DC bias for obtaining a desired initial current is supplied, and the first amplifying means 204
DC bias supply circuit 2
A DC bias that does not perform an amplification operation is supplied via the terminals 04c and 204d.

At this time, at the second frequency, the control circuit 212 controls the impedance of the combining circuit 210 so that the impedance seen from the input of the first amplifying means 204 to the first amplifying means 204 becomes high. By
Input side and output side matching circuit 204 of first amplifying means 204
a and 204b are changed. However, the output side matching circuit 2
Only the input side matching circuit 204a may be changed without changing the input side matching circuit 204a.

Further, third and fourth switches 207, 2
09 is turned off, the transmission line 2 of the synthesis circuit 210 is turned off.
The impedance seen from the input connected to the transmission line 208 toward the transmission line 208 becomes high impedance at the second frequency.

As a result, the signal input from the input terminal 201 is amplified by the second amplifying means 206, and the output signal is output from the output terminal 211.

In the fourth mode operating at the second frequency and requiring no amplifying operation, the control circuit 212 turns off the first, second, and fourth switches 203, 205, and 209 and turns off the third switch. 207 is turned on, and the transistor 20 of each of the first and second amplifying units 204 and 206 is turned on.
4e and 206e, a DC bias supply circuit 204c,
A direct current bias that does not perform an amplification operation is supplied via 04d, 206c, and 206d.

At this time, at the second frequency, the control circuit 212 controls the impedance of the combining circuit 210 such that the impedance seen from the input of the first amplifying means 204 to the first amplifying means 204 becomes high. By
Input side and output side matching circuit 204 of first amplifying means 204
a and 204b are changed, and the input of the combining circuit 210 to which the second amplifying means 206 is connected is changed to the second amplifying means 20
The control circuit 212 changes the input-side and output-side matching circuits 206a and 206b of the second amplifying means 206 so that the impedance seen from the sixth side becomes high. However, only the output-side matching circuits 204b and 206b may be changed, and the input-side matching circuits 204a and 206a may not necessarily be changed.

Thus, the signal input from the input terminal 201 passes through the transmission line 208, and the output signal is output from the output terminal 211.

The control circuit 212 performs control so as to switch the first to fourth modes according to the operating frequency and the output power.

As described above, according to the present embodiment, when one operating frequency is an even multiple of the other operating frequency, the same operation as in the first embodiment can be performed even when the circuit configuration is changed. Further, when the amplifying means operates at a low frequency, the transmission line 208 has a low impedance at a high frequency, which is a harmonic of the output signal at a low frequency, and suppresses the harmonic component. A harmonic processing circuit can be realized without adding a circuit for the above.

Further, compared to the first embodiment, since no switch is provided between the transmission line 208 and the combining circuit 210, internal loss can be reduced, and efficient signal transmission can be achieved. Can be realized.

In the above description, the power amplifier 200 amplifies the signal of the first frequency and the signal of the second frequency which is an even multiple of the first frequency. Although the description has been given assuming that the second amplification means 206 includes two amplification means, the power amplifier of the present invention is not limited to this, and amplifies signals having frequencies different from each other by even-number times. Alternatively, a configuration having three or more amplifying means may be provided.

(Embodiment 3) A third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram of a power amplifier 900 according to the third embodiment of the present invention. FIG.
In FIG. 2, the same or corresponding parts as those in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted. However, the first amplifying means 2
04 operates in a relationship between the first frequency at which the second amplifying means 206 operates and the second frequency at which the second amplifying means 206 operates.
, And need not be an even multiple of the first frequency.

Reference numeral 230 is a first transmission line, and 231 is a second transmission line. One end of each of the first transmission line 230 and the second transmission line 231 is connected to the second connection point 2.
34b, the first transmission line 23
0 is the third switch 207 and the fourth switch 20
9, a second transmission line 2 is connected to a first connection point 234a.
The other end of 31 is connected to the synthesizing circuit 210 to form the group of bypass transmission lines of the present invention. The second connection point 234b is provided with a fifth switch 232 whose conduction is controlled by the control of the control means 212. The second connection point 234b is connected to the fifth switch 232b.
Through the ground.

Here, the line length of the second transmission line 231 is set to １ ／ of the wavelength of the signal of the second frequency on the second amplifying means 206 side, and the line length of the first transmission line 230 and the 2
Of the transmission line 231 of the first amplification unit 2
It is set to be 1/4 of the wavelength of the signal of the first frequency on the 04 side.

The operation of power amplifier 900 according to the present embodiment having the above-described configuration is as follows.

The power amplifier 900 operates at the first frequency, and in the first mode requiring the amplification operation, the control circuit 21
2, the first and fourth switches 203 and 209 are turned on, and the second, third and fifth switches 205, 207 and 23 are turned on.
2 is turned off, and the DC bias supply circuits 204c and 204d are connected to the transistor 204e of the first amplifying means 204.
Is supplied through the transistor 2 so that a desired initial current can be obtained.
06e includes DC bias supply circuits 206c and 206d.
, A DC bias that does not perform the amplification operation is supplied.

At this time, at the first frequency, the control circuit 212 has a high impedance from the input of the synthesis circuit 210 to which the second amplification means 206 is connected, as viewed from the second amplification means 206 side. By
Input side and output side matching circuit 206 of second amplifying means 206
a and 206b are changed. However, the output side matching circuit 2
06b may be changed, and the input matching circuit 206a may not be changed.

Further, when the fourth switch 209 is turned on and the fifth switch 232 is turned off, the input of the combining circuit 210 to which the first transmission line 230 and the second transmission line 231 are connected becomes The impedance seen from the first transmission line 230 and the second transmission line 231 becomes high impedance at the first frequency.

As a result, the signal input from the input terminal 201 is amplified by the first amplifying means 204, and the output signal is output from the output terminal 211.

In the second mode, which operates at the first frequency and does not require an amplification operation, the control circuit 112 controls the first, second, fourth, and fifth switches 203, 205, and 20.
9 and 232 are turned off, the third switch 207 is turned on, and the transistors 204e and 206e of the first and second amplifying means 204 and 206 are supplied to the respective transistors 204e and 206e via the DC bias supply circuits 204c, 204d, 206c and 206d. A DC bias that does not perform the amplification operation is supplied.

At this time, at the first frequency, the control circuit 212 controls the input of the combining circuit 210 from the input to which the first amplifying means 204 is connected so that the impedance seen from the input to the first amplifying means 204 becomes high. By
Input side and output side matching circuit 204 of first amplifying means 204
a and 204b are changed, and the input of the combining circuit 210 to which the second amplifying means 206 is connected is changed to the second amplifying means 20
The control circuit 112 changes the input side and output side matching circuits 206a and 206b of the second amplifying means 206 so that the impedance seen from the 6 side becomes high. However, only the output-side matching circuits 204b and 206b may be changed, and the input-side matching circuits 204b and 206a may not necessarily be changed.

Thus, the signal input from the input terminal 201 passes through the first transmission line 230 and the second transmission line 231, and the output signal is output from the output terminal 211.

In the third mode, which operates at the second frequency and requires an amplifying operation, the control circuit 212 turns on the second switch 205 and the fifth switch 232 and turns on the first and second switches.
The third and fourth switches 203, 207 and 209 are turned off, and the transistor 206e of the second amplifying means 206 is turned off.
Is supplied with a DC bias to obtain a desired initial current through the DC bias supply circuits 206c and 206d.
Is supplied with a DC bias via the DC bias supply circuits 204c and 204d such that the amplification operation is not performed.

At this time, at the second frequency, the control circuit 212 controls the impedance of the combining circuit 210 so that the impedance seen from the input of the first amplifying means 204 to the first amplifying means 204 becomes high. By
Input side and output side matching circuit 204 of first amplifying means 204
a and 204b are changed. However, the output side matching circuit 2
Only the input side matching circuit 204a may not be changed.

Further, third and fourth switches 207, 2
09 is turned off and the fifth switch 232 is turned on, so that the impedance seen from the input of the combining circuit 210 to which the second transmission line 231 is connected to the second transmission line 231 side becomes the second frequency. At high impedance.

As a result, the signal input from the input terminal 201 is amplified by the second amplifying means 206, and the output signal is output from the output terminal 211.

In the fourth mode, which operates at the second frequency and does not require an amplification operation, the control circuit 212 causes the first, second, fourth, and fifth switches 203, 205, 20
9 and 232 are turned off, the third switch 207 is turned on, and the transistors 204e and 206e of the first and second amplifying means 204 and 206 are supplied to the respective transistors 204e and 206e via the DC bias supply circuits 204c, 204d, 206c and 206d. A DC bias that does not perform the amplification operation is supplied.

At this time, at the second frequency, the control circuit 212 controls the impedance of the combining circuit 210 from the input to which the first amplifying means 204 is connected, so that the impedance seen from the first amplifying means 204 becomes high. By
Input side and output side matching circuit 204 of first amplifying means 204
a and 204b are changed, and the input of the combining circuit 210 to which the second amplifying unit 206 is connected is changed from the input of the second amplifying unit 20.
The control circuit 212 changes the input-side and output-side matching circuits 206a and 206b of the second amplifying means 206 so that the impedance seen from the sixth side becomes high. However, only the output-side matching circuits 204b and 206b may be changed, and the input-side matching circuits 204a and 206a may not necessarily be changed.

Thus, the signal input from the input terminal 201 passes through the first transmission line 230 and the second transmission line 231, and the output signal is output from the output terminal 211.

The control circuit 212 performs control so as to switch the first to fourth modes according to the operating frequency and the output power.

As described above, according to the present embodiment, similarly to the first embodiment, the output signal is reduced by bypassing the output signal from the amplifying unit and supplying the bias voltage that does not operate the amplifying unit. By reducing the current consumption of the amplifier in this case, efficiency can be improved in a wide output range. In addition, by sharing the signal path in the case where the amplification operation is not required by two frequencies and using one amplifier output, the circuit can be downsized, and the first transmission line 230 and the second transmission line can be used. Line 231 and combining circuit 21
Since no switch is provided between 0 and 0, internal loss can be reduced and efficient signal transmission can be realized.

In the above description, power amplifier 900 comprises first amplifying means 204 for amplifying a signal of the first frequency and second amplifying means for amplifying a signal of a second frequency higher than the first frequency. Although the description has been given assuming that the amplifying means 206 includes two amplifying means, the power amplifier of the present invention is not limited to this, and three or more amplifying signals having different frequencies are used. A configuration including an amplifying unit may be adopted. At this time, the number of transmission lines connected in series is also prepared according to the number of amplifying means, and each transmission line is grounded via a switch whose conduction can be controlled by the control means, like the fifth switch 232. To do.

The partial length of each of the plurality of transmission lines as viewed from the combining circuit 210 up to the respective connection point and the overall length of each of the transmission lines connected in series correspond to each signal frequency of the plurality of amplifying means. The partial length preferably corresponds to the highest signal frequency to the lowest signal frequency of the plurality of amplifying means in order from the shortest, and the entire length may be a length corresponding to the lowest signal frequency of the plurality of amplifying means. The control means controls the conduction of the switches between the transmission lines in accordance with the frequency of the operating amplifying means, respectively.
Even when three or more amplifying units are provided, the same operation as in the above embodiment can be performed. Also at this time, it is desirable that the length corresponding to the partial length and the entire length is such that each signal frequency is １ ／ of the corresponding wavelength.

In the first to third embodiments, the first,
By operating the second switch as a predistortion compensation circuit, it is possible to improve the efficiency particularly in a system requiring linearity.

The efficiency can be improved by changing the DC bias of the operating amplifying means according to the output power and reducing the current consumption while satisfying the desired characteristics.

Further, the input side of the operating amplifying means,
Efficiency can also be improved by changing one or both of the output-side matching circuits according to the output power and using an optimum load at the output power.

FIG. 3 is a block diagram showing an example of the configuration of the matching circuit of the amplifying means in the first to third embodiments. In the matching circuit 300, 301 is an input terminal, and 302 is a first terminal.
, 303 is a first parallel matching circuit element, 304
Is a series matching circuit element, 305 is a second switch, 306
Is a second parallel matching circuit element, and 307 is an output terminal.
The series matching circuit element is realized by, for example, a coil, a capacitor, or a transmission line.
The first parallel matching circuit element 303 and the second parallel matching circuit element 306 are realized as coils respectively connected to the output terminal 307, and are realized as, for example, capacitors having one ends grounded.

The impedance of the matching circuit 300 is changed by switching on and off the first and second switches 302 and 305 according to control signals from the control circuits 112 and 212. First and second switches 302 and 30
5 and the first and second parallel matching circuit elements 303 and 306 increase the number of circuits, so that the matching circuit can be adjusted more finely. When there is no need to switch the matching circuit, a matching circuit having a constant impedance is eliminated by eliminating the circuit including the first and second switches 302 and 305 and the first and second parallel matching circuit elements 303 and 306. Can also be realized. Thus, the operations described in the first to third embodiments can be realized.

(Embodiment 4) FIG. 4 shows Embodiments 1 to
3 is a block diagram showing an example in which the input-side switches of the amplifying means 104 and 106 (204 and 206) are each configured by a diode whose on / off is controlled by an input-side DC bias of a transistor. FIG. 4 shows a circuit in which the transistors of the amplifying means 104 and 106 require a positive voltage for the input DC bias necessary for performing the amplifying means. The switch 400
The first switch 103 and the second switch 10 shown in FIG.
5. The switch used as 5 and comprising a switch 400
, 401 is an input terminal, 402 is a DC / AC separation circuit, 402a is an AC signal path, 402b is a DC signal path, 403 is a diode, and 404 is an output terminal. FIG. 8A shows a case where the switch 400 is used for the first switch 103 of the first embodiment (400a in the figure) and a case where the switch 400 is used for the second switch 105 (400 in the figure).
FIG. 3b shows a partial view of the power amplifier of FIG. Since the operation of the entire circuit is the same as in the first and second embodiments, the first circuit is used here.
Only the operation of the input side switch section of the amplifying means 104 and the second amplifying means 106 will be described.

When the amplifying means 104 or 106 operates, the DC bias supplied to the input side of the transistor 104e or 106e is also applied to the anode of the diode 403, and the DC / AC separation circuit 402 changes the cathode of the diode 403 to DC. Grounded. As a result, a current flows through the diode 403, and the switch 400 is turned on. When the first amplifying means 104 or the second amplifying means 106 is not operated, the transistor 104e
Alternatively, a DC bias is supplied so that both 106e and the diode 403 are turned off.

Thus, while realizing the operations of the first and second embodiments, the control terminals of the amplifying means 104 and 106 and the input side switches 103 and 105 can be shared, and the number of control lines from the control circuit can be reduced.

Further, as shown in FIG. 8B, a DC / AC separation circuit 402 provided in each of the switch 400a serving as the first switch 103 and the switch 400b serving as the second switch 105 is shared. Input terminal 101
And the branch circuit 102, and the first and second switches are realized as 400a '400b' each including only the diode 403, whereby the circuit can be further reduced in size.

It is apparent that the effect of improving the efficiency shown in the second embodiment can be obtained by operating the switch using the diode 403 as a predistortion compensation circuit.

(Embodiment 5) A fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a power amplifier 500 according to Embodiment 5 of the present invention. FIG.
Since the configuration of the circuit is almost the same as that of the first embodiment, only the differences will be described. The first and second amplifying units 504 and 506 are respectively connected to the input side matching circuit 50.
4a, 506a, output side matching circuits 504b, 506b
DC bias supply circuits 504c, 50
It is composed of transistors 504d and 506d having 6c. Transistor 504 of amplifying means 504, 506
The output side DC bias of d and 506d is supplied by a two-frequency DC bias supply circuit 512. The two-frequency DC bias supply circuit 512 includes a combination circuit 510 and an output terminal 51.
1 is connected to a connection point 514 provided between the first and the second. At this time, the output-side matching circuit 504 of the first and second amplifying means
Both b and 506b must be configured to apply a DC bias to the transistors 504d and 506d, respectively. If necessary, a DC cutoff circuit may be provided between the connection point 514 and the output terminal 511.

In the two-frequency DC bias supply circuit 512, one end of the first bias transmission line 512a is directly connected between the combining circuit 510 and the output terminal 511 via the connection point 514, and the other end is connected to the first bias transmission line 512a. 2 is connected to one end of the bias transmission line 512d. The other end of the second bias transmission line 512d is connected to a DC bias supply terminal 512g.
And is supplied with a DC bias from the control circuit 513. A first bypass capacitor 512b and a first sub-switch 512c are provided between the first bias transmission line 512a and the second bias transmission line 512d.
And the second bias transmission line 51
2d and the DC bias supply terminal 512g, a second bypass capacitor 512e and a second sub-switch 51
2f is grounded. The line length of the first bias transmission line 512a is a quarter wavelength of a high-frequency signal corresponding to the first amplification means 504, and the line length of the first bias transmission line 512a and the second bias The sum of the transmission line 512d and the line length is determined by the second amplifying unit 506.
Is a quarter wavelength of the corresponding low frequency.

The operation of the present embodiment having such a configuration is as follows.

When operating at the higher frequency of the two frequencies, the control circuit 513 controls the first sub-switch 512
c is controlled to be turned on, and a necessary DC bias is supplied to the DC bias supply terminal 512g.

Thus, at a high frequency, a quarter
Since the first bypass capacitor 512b connected to the first bias transmission line 512a having the wavelength length is grounded, the impedance at a high frequency as seen from the connection point 514 to the two-frequency DC bias supply circuit 512 is high impedance. Become.

When operating at the lower frequency of the two frequencies, the control circuit 513 controls the first sub-switch 512
Control is performed so that c is turned off and the second sub-switch 512f is turned on, and a necessary DC bias is supplied to the DC bias supply terminal 512g.

Thus, the sum of the lengths of the first and second bias transmission lines 512a and 512d has a length of a quarter wavelength at a low frequency and is connected to the second bias transmission line 512d. Second bypass capacitor 512
e is a signal from the control circuit 513 to the second sub-switch 512f.
Is turned on, the connection point 51 is grounded.
The impedance at a low frequency as seen from the 4-to-2 frequency DC bias supply circuit 512 becomes a high impedance.

Thus, a DC bias can be applied by the DC bias supply circuit common to the two transistors without affecting the high-frequency signal. Note that the same operation can be performed without the second sub-switch 512f (or the sub-switch closest to the DC bias supply terminal 152g), and the number of switches requiring control can be reduced.

Here, the case of the circuit configuration shown in the first embodiment has been described. However, even if a two-frequency DC bias supply circuit is applied to the circuit configurations shown in the second and third embodiments,
The operation described in Embodiment 2 is possible.

In the above description, the first sub-switch 512c and the first sub-switch 512f have been described as being provided between the bypass capacitor and the ground. May be set in such a manner that a bypass capacitor is provided between the switch and the ground.

In the above description, the power amplifier 500 includes the first amplifier 504 for amplifying the signal of the first frequency and the second amplifier 506 for amplifying the signal of the second frequency. The power amplifier of the present invention has been described as being provided with two amplifying means. However, the power amplifier of the present invention is not limited to this. May be provided. At this time, the two-frequency DC bias supply circuit 512 becomes a multi-frequency DC bias supply circuit corresponding to the same number of signals as the signals to be processed by the number of amplifying means. As the bias transmission line, one end of the quarter wavelength bias transmission line at the highest frequency is connected to the connection point 514, and the connection point 5
It is sufficient to increase the number of bias transmission lines connected in series between the power transmission line 14 and the DC bias supply terminal 512g. At this time, the length from the connection point 514 to the connection point of each of the added bias transmission lines is 1/1 of the wavelength of the corresponding signal of the amplification means corresponding to each of the added bias transmission lines.
It is desirable to set it to 4.

Further, in the case of a configuration according to the second embodiment, a configuration may be employed in which three or more amplifying means for amplifying signals having frequencies different from each other by even-number times are provided. Also in this case, the two-frequency DC bias supply circuit 512
Is a multi-frequency DC bias supply circuit corresponding to the same number of signals as the number of amplifying means processes, and in this multi-period wave DC bias supply circuit, as the highest frequency bias transmission line of the present invention, at the highest frequency 4
One end of the one-wavelength bias transmission line is connected to the connection point 514, and the number of bias transmission lines connected in series between the connection point 514 and the DC bias supply terminal 512g is increased. Good. At this time, the length from the connection point 514 to the connection point of each additional bias transmission line is set to be 1/4 of the wavelength of the signal corresponding to the amplification means corresponding to each additional bias transmission line. Is desirable.

Further, by connecting the power amplifiers shown in the first to fifth embodiments in multiple stages, it is possible to achieve higher efficiency in finer output power steps.

Further, by configuring the power amplifiers of the first to fifth embodiments or the multi-stage power amplifier using them on the same semiconductor substrate, it is possible to further reduce the size of the circuit.

A part is formed on the same semiconductor substrate,
By forming other parts on a semiconductor substrate of a different material and process, the respective excellent characteristics can be shared.

By using the power amplifier shown in the first to fifth embodiments to construct a portable radio as shown in FIG. 6, it is possible to use at least two frequencies and to use a portable radio with small size and high efficiency. Communication equipment can be realized.

In each of the above embodiments, the input terminals 101, 201, 501, the first switch 103,
203, 503, second switches 105, 205, 50
5 and the third switches 107, 207, 507 correspond to the branch output means of the present invention, and furthermore, the first switches 103, 203, 503, and the second switches 105, 20
5,505 correspond to the amplifying means input switch of the present invention, the third switches 107,207,507 correspond to the bypass input switch of the present invention, and the transmission line 108 corresponds to the bypass means of the present invention. Also, the input side DC bias supply circuits 104c, 204c, 106c, 206
c, 504c and output side DC bias supply circuit 104
d, 106d, 204d, and 206d correspond to the DC bias supply circuit of the present invention. Also, the synthesis circuits 110 and 2
Reference numerals 10 and 510 correspond to the combined output device of the present invention. Also,
The fourth switches 109 and 509 correspond to the transmission line output switch of the present invention. Further, the fourth switch 209 is included in the grounding means of the present invention. Also, the input side matching circuit 10
4a, 204a, 504a and 106a, 206a,
Reference numeral 506a corresponds to the first matching circuit of the present invention, and the output-side matching circuits 104b, 204b, 504b and 106b,
206b and 506b correspond to the second matching circuit of the present invention. The control circuits 113, 213, and 513 correspond to control means of the present invention. Also, the first bias transmission line 5
Reference numeral 12a corresponds to the highest frequency bias transmission line of the present invention, and the first bias transmission line 512a and the second bias transmission line 512d correspond to the transmission line group of the present invention.

Further, in the second embodiment, the first transmission line 230 and the second transmission line 231 correspond to the bypass transmission line of the second invention, and the fourth switch 209 corresponds to the bypass transmission line of the second invention. The fifth switch 209 is included in the second grounding means of the second invention, and is included in the first grounding means.

[0113]

As is apparent from the above description, according to the present invention, a power amplifier having a plurality of amplifying means for amplifying signals in mutually different frequency bands can be reduced in size and increased in efficiency at low output. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a matching circuit according to the first to third embodiments of the present invention;

FIG. 4 is a block diagram showing an input switch according to a fourth embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing one embodiment of the mobile radio device of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional power amplifier.

FIG. 8 is a partial configuration diagram for explaining a case where the input switch according to the fourth embodiment of the present invention is used in the first embodiment;

FIG. 9 is a block diagram showing a configuration of a third embodiment of the present invention.

[Explanation of symbols]

100, 200, 500, 603 Power amplifier 101, 201, 301, 401, 501, 701, 7
08 Input terminal 102, 202, 502 Branch circuit 103, 105, 107, 109, 203, 205, 2
07, 209, 302, 305, 503, 505, 50
7, 509, switches 104, 106, 204, 206, 504, 506 amplifying means 104a, 104b, 106a, 106b, 204a,
204b, 206a, 206b, 300, 504a, 5
04b, 506a, 506b, 702, 706, 70
9, 713 matching circuits 104c, 104d, 106c, 106d, 204c,
204d, 206c, 206d, 504c, 506c,
703, 705, 710, 711 DC bias supply circuits 104c, 106c, 204c, 206c, 504d,
506d, 704, 712 Transistors 108, 208, 508, 512a, 512d Transmission lines 110, 210, 510 Combining circuits 111, 211, 307, 404, 511, 707, 7
14 Output terminal 112, 212, 513 Control circuit 303, 306 Parallel matching circuit element 304 Series matching circuit element 402 DC / AC separation circuit 402a AC signal path 402b DC signal path 403 Diode 512c, 512f Sub-switch 512b, 512e Bypass capacitor 512g DC bias Supply terminal 514 Connection point 600 Portable wireless device 601 Signal processing unit 602 Transmitting circuit 604 Antenna 605 Receiving circuit

Continuing from the front page (72) Inventor Keishi Isono 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. In-house F-term (reference) 5J069 AA01 AA21 AA41 CA36 CA92 FA11 FA18 HA02 HA19 HA29 HA38 KA12 KA29 KA68 TA01 5J091 AA01 AA21 AA41 CA36 CA92 FA11 FA18 HA02 HA19 HA29 HA38 KA12 KA29 KA68 TA01 UW01 5A092A HA29 HA38 KA12 KA29 KA68 TA01 5K060 CC04 HH06 HH09 HH39 JJ08

Claims (14)

[Claims] 1. A branch output unit having an input terminal and a plurality of output terminals; and a branch output unit connected to the output terminal of a part of the branch output unit.
A plurality of amplifying units each operating at a signal frequency different from each other, a bypass unit connected to another output terminal of the branch output unit, and an output of each of the plurality of amplifying units and an output from the bypass unit. A combined output device having an output terminal to the outside as an input, a switch means for switching on / off of conduction of the bypass means, conduction of the branch output means, conduction and amplification operations of the plurality of amplifying means, And control means for controlling conduction of the switch means, wherein the control means sets an input to the branch output means to one of the plurality of amplifying means according to the signal frequency and required output power. Control to output the signal to the combined output device through the bypass means or to output the signal to the combined output device without amplification through the bypass means. Cormorant power amplifier. 2. A branch output unit having an input terminal and a plurality of output terminals; a plurality of amplifying units connected to a part of the output of the branch output unit and operating at mutually different signal frequencies; A bypass transmission line group having a plurality of bypass transmission lines connected in series to each other and connected to another output terminal remaining on the output means; and an output of each of the plurality of amplifying means and an output from the transmission line group are connected. A combined output device, a first grounding means provided at a first connection point between the transmission line group and the branch output means, the conduction of which is controlled, between each of the bypass transmission lines of the transmission line group. A plurality of second grounding means provided at a second connection point of which conduction is controlled; a conduction of the branch output means; a conduction and amplifying operation of the plurality of amplifying means; hand Control means for controlling conduction of a stage and conduction of the second grounding means, a partial length of the transmission line group as viewed from the combined output device side to each of the second connection points, and The entire length of the transmission line group corresponds to each signal frequency of the plurality of amplifying means, and the partial lengths correspond to the signal frequencies from the highest signal frequency to the low signal frequency of the plurality of amplifying means in order from the shortest one. The total length corresponds to the lowest signal frequency of the plurality of amplifying units, and the control unit sets the plurality of inputs to the branch output unit according to the signal frequency and required output power. And a power amplifier that controls so as to amplify and output to the combined output device via any one of the amplifying means, or to output to the combined output device without amplification through the transmission line group. 3. A branch output unit having an input terminal and a plurality of output terminals; a plurality of amplification units connected to a part of the output of the branch output unit and operating at mutually different signal frequencies; A transmission line connected to the remaining output of the output unit, a combined output unit to which the output of each of the plurality of amplifying units and the output from the transmission line are connected; and a branch output unit side of the transmission line. Control means for controlling conduction provided, ground means whose conduction is controlled, conduction of the branch output means, conduction and amplification operations of the plurality of amplifying means, and conduction of the ground means. The frequencies are different from each other by an even number, and the control means outputs an input to the branch output means to the plurality of amplifying means according to the signal frequency and required output power. Any amplified through to output to the synthesis output unit, or the power amplifier to control to output the to composite output device while no amplified through the transmission line. 4. The amplifying unit includes: a first matching circuit provided on the branch input unit side; a second matching circuit provided on the combining output unit side; A transistor provided between the second matching circuit and the first matching circuit and / or between the first matching circuit and the transistor;
Or a DC bias supply circuit provided between the second matching circuit and the transistor, wherein the impedance of at least one of the first matching circuit and the second matching circuit is variable. The power amplifier according to any one of the above. 5. The first matching circuit of the amplifying means in operation according to an output of any one of the plurality of amplifying means in operation, and the second matching means, 5. The power amplifier according to claim 4, wherein the impedance of one or both of the circuits is changed. 6. The first matching circuit and / or the second matching circuit.
An input terminal connected to the branch input means or the output side of the transistor; an output terminal connected to the input side of the transistor or the combined output device; at least one of the input terminal and the output terminal A series matching circuit element connected between at least one of the input terminal and the series matching circuit element, or between two of the series matching circuit elements;
Or a switch connected between the series matching circuit element and the output terminal, the switch being turned on and off by the control means, and a parallel matching circuit element connected to the other end of the switch. 5. The power amplifier according to 4. 7. The branching input means, an amplifying means input switch for conducting each of the plurality of amplifying means, and a bypass input switch for conducting any one of the bypass means, the transmission line and the transmission line group. The power amplifier according to any one of claims 1 to 3, further comprising: amplifying means input switches that operate as a predistortion compensation circuit. 8. The power amplifier according to claim 7, wherein the amplification unit input switch has a diode whose on / off is controlled by an input side DC bias to the amplification unit. 9. A multi-frequency direct current bias supply circuit connected to a connection point between the output combiner and the output terminal, wherein the multi-frequency direct current bias supply circuit is provided in the plurality of amplifying means. 5. The power amplifier according to claim 4, wherein said power amplifier operates corresponding to said signal frequency corresponding to said operating amplifier means. 10. The multi-frequency DC bias supply circuit,
A transmission line group having a plurality of bias transmission lines connected in series with each other, the transmission line group being provided so as to correspond to the corresponding signal frequencies of the plurality of amplifying means; A first connected to the other end of the highest frequency bias transmission line corresponding to the highest signal frequency connected to a point.
A first sub-switch connected in series with the first bypass capacitor, the first sub-switch being turned on and off by the control unit; and a first sub-switch connected between the plurality of bias transmission lines of the transmission line group. And at least one second bypass capacitor; and a second bypass capacitor connected in series with the second bypass capacitor.
And a bias terminal connected to the other end of the transmission line group, which is not connected to another bias transmission line, to which a DC bias supplied from the control unit is applied. The other end of the highest frequency bias transmission line is grounded via the first bypass capacitor and the first sub-switch, and a plurality of bias transmissions of the transmission line group other than the other end of the highest frequency bias transmission line The lines are grounded via the second bypass capacitor and the second sub-switch, and the first bypass capacitor is short-circuited at the highest signal frequency among the signal frequencies, From the connection position of the
10. The power amplifier according to claim 9, wherein a short circuit occurs at the signal frequency associated with the sum of the transmission line lengths to the connection point. 11. A power amplifier having a multi-stage configuration, wherein at least one or more stages of amplifiers are connected to one another.
A power amplifier having a multi-stage configuration using a combination of the power amplifiers according to any one of the above. 12. A power amplifier according to claim 1, wherein all or a part of each part of the power amplifier according to claim 1 is formed on the same semiconductor substrate. 13. A power amplifier according to claim 1, wherein all or a part of each part of the power amplifier according to claim 1 is configured on a plurality of different semiconductor substrates. 14. A signal processing circuit, a transmission circuit having a power amplifier for transmitting a signal from the signal processing circuit, an antenna transmitting an output of the transmission circuit and receiving a reception signal, and the reception signal 14. A communication device, comprising: a receiving circuit configured to process the power amplifier, wherein the power amplifier is the power amplifier according to claim 1.