JP2002244588A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture display device in which sufficient display luminance is obtained by suppressing the reduction of an opening ratio and the area of a pixel electrode to the minimum and also in which a problem is never generated in the stability of an emission current in a light emission maintaining type display having a transistor for selecting a pixel, a transistor for controlling a pixel current and a capacitor for holding a signal voltage. SOLUTION: In this display device, the gate and the source of a transistor 6a for selecting a pixel are connected respectively to the scanning line 1a of one side and a signal line 2a and the drain of the transistor 6a is connected to the electrode of one side of a capacitor 5a and the gate of a transistor 7a for controlling a pixel current. The drain of the transistor 7a is connected to a pixel electrode 4a and the source of the transistor 7a is connected to the electrode of the other side of the capacitor 5a and also the scanning line 1a' of the other side. As a result, the wiring area of a voltage supplying line is unnecessitated by making an adjacent scanning line 1a' have the role of the voltage supplying line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type image display, and more particularly to a light emitting display which emits light by injecting electrons or holes. The present invention relates to technology that can extend the life. The present invention relates to an ELD (ElectroLuminescence).
Display) and FED (Field Emission Display).

[0002]

2. Description of the Related Art Currently, flat panel displays include liquid crystal displays, plasma displays, and ELs.
Display (ELD), FE display (FED) and the like have been put to practical use. Among them, ELD and FED are self-luminous displays and can achieve high definition.
Development is underway as a next-generation television receiver replacing the CRT. However, when these displays are driven by a simple matrix, there has been a problem that as the display becomes higher definition, the duty ratio becomes smaller and sufficient luminance cannot be obtained. Further, when the current is increased to obtain a sufficient luminance, there is a problem that the light emitting element and the light emitting material (such as a phosphor) are deteriorated. Therefore, an active matrix driven display has been proposed to improve these problems. In active matrix driven displays, MIS
(Metal Insulator Semiconductor) A field effect transistor is used as a switching element of a pixel. Here, a device in which silicon oxide is formed as a gate insulating film is called a MOS (Metal Oxide Semiconductor) field effect transistor.

FIG. 6 shows a conventional FED (Field Emission Diode).
splay) pixel driving circuit, and in a circuit described in Japanese Patent No. 2668443, a pixel (i
j) 13 is illustrated. This drive circuit is a pixel selection NMOS transistor 1 arranged for each pixel.
6, a current driving NMOS transistor 17 and a signal voltage holding capacitor 15. The gate of the pixel selecting NMOS transistor 16 is connected to the i-th scanning line 11. Reference numeral 11 'denotes a scanning line on the (i + 1) th row for an adjacent pixel. One of the source and the drain of the pixel selecting NMOS transistor 16 is connected to the signal line 12 in the j-th column, and the other of the source and the drain is connected to the capacitor 15 and the current driving NMOS transistor 1.
7 is connected to the gate. One of the source and the drain of the current driving NMOS transistor 17 is connected to the constant voltage line 18, and the other of the source and the drain is connected to the pixel electrode 14.

According to this configuration, even after the pixel selecting NMOS transistor 16 is turned off, the current driving NMOS transistor 17 continues to supply a current corresponding to the signal. Therefore, it is possible to maintain light emission even when the pixels are not selected, and a display with high luminance can be formed.
In this case, sufficient luminance can be obtained without passing a large emission current as in the case of simple matrix driving, so that the lifetime of the emitter and the lifetime of the phosphor are prolonged.

FIG. 7 shows a pixel driving circuit of a conventional organic EL display, which illustrates a pixel (ij) 23 at an i-th row and a j-th column in a circuit described in Japanese Patent No. 2784615. This circuit uses a driving method similar to the FED active matrix driving method shown in FIG. 7 includes an NMOS transistor 26 for selecting a pixel, a PMOS transistor 29 for driving a current,
And a capacitor 25 for holding a signal voltage. The gate of the pixel selection NMOS transistor 26 is connected to the scanning line 21 in the i-th row. Reference numeral 21 'denotes a scanning line on the (i + 1) th row for an adjacent pixel. One of the source and the drain of the pixel selecting NMOS transistor 26 is connected to the signal line 22 of the j-th column, and the other of the source and the drain is connected to the capacitor 25 and the gate of the current driving PMOS transistor 29. P for current drive
One of a source and a drain of the MOS transistor 29 is connected to the voltage supply line 28, and the other of the source and the drain is connected to the pixel electrode 24.

According to this configuration, even after the NMOS transistor 26 is turned off, a current corresponding to the signal can continue to flow through the PMOS transistor 29. Also, N
By connecting the capacitor 25 to one of the source and the drain of the MOS transistor 26, a stable P
The current of the MOS transistor 29 is obtained. Therefore, it is possible to stabilize pixel light emission.

[0007]

However, in the case of the active matrix drive, there is a problem that the number of transistors and the number of wirings are large. In the case of a conventional active matrix drive FED or ELD,
A constant voltage line or a voltage supply line is required in addition to a scanning line and a signal line, and a current driving transistor is required in addition to a pixel selection transistor and a signal voltage holding capacitor. Therefore, in the case of the active matrix driving, there is a problem that the pixel electrode area decreases and the aperture ratio decreases due to an increase in the number of transistors and the number of wirings. In particular, since the constant voltage line is a wiring for passing a current, it is necessary to sufficiently reduce the resistance, and the ratio of the constant voltage line to the pixel area is large. For example, if the pixel size is 100 μm × 300 μm,
Assuming that the wiring width is 10 μm and the wiring length is 300 μm, the ratio of the constant voltage line to the pixel area is 10%, which is a very large ratio. As a result, in the case of the organic ELD, the aperture ratio is reduced, resulting in a dark display. In the case of the FED, the display luminance is reduced due to the reduction in the area of the pixel electrode forming the emitter, and the stability of the emission current is reduced. And the problem that the uniformity between pixels is reduced.

According to the present invention, in an active matrix type display such as an organic ELD or FED, a sufficient display luminance can be obtained by minimizing a decrease in an aperture ratio and a decrease in a pixel electrode area, and a stability of an emission current. It is an object of the present invention to provide an image display device that does not cause a problem in uniformity between pixels or between pixels.

[0009]

The image display device according to the present invention is an active matrix type display device having a plurality of pixels, a plurality of scanning lines, and a plurality of signal lines. Each pixel has a pixel selection transistor, a pixel current control transistor, a capacitor, and a pixel electrode in one pixel. The pixel selection transistor has a gate connected to a scanning line or a signal line, and one of a source or a drain connected to a signal line or a scanning line not connected to the gate,
The other of the source and the drain is connected to one electrode of the capacitor and the gate of the transistor for controlling pixel current. The pixel current control transistor has a drain connected to the pixel electrode, and a source connected to the other electrode of the capacitor to a scanning line located adjacent to the scanning line with the pixel interposed therebetween. According to this configuration, the image signal input from the signal line is held as the gate voltage of the capacitor and the pixel current control transistor. That is, even when the pixel is in the non-selection state, the pixel current corresponding to the signal can continue to flow through the pixel current control transistor.

When the source or the drain of the pixel selection transistor is connected to the signal line, the magnitude of the voltage is input as a signal, and when the gate of the pixel selection transistor is connected to the signal line. , A signal as the ON time of the transistor is input, and the pixel current corresponding to the signal can be controlled by the pixel current controlling transistor. The current path flowing at this time does not flow through a constant voltage line or a voltage supply line as in the related art, but instead of flowing a current through a scanning line adjacent to a pixel, which is different from a scanning line to which a pixel selection transistor is connected. Shed. Therefore, in the pixel current control transistor, the drain is connected to the pixel electrode, and the other electrode of the source and the capacitor is connected to the scanning line located adjacent to the scanning line to which the pixel selection transistor is connected, with the pixel interposed therebetween. Connecting. Thereby, it is possible to operate without providing a constant voltage line or a voltage supply line for flowing a pixel current.

Here, considering the case of line-sequential driving, assuming that the number of scanning lines is n, each scanning line is 1 / frame / frame time.
The voltage fluctuates for n hours. Therefore, since the potential of the scanning line to which the pixel current control transistor is connected also changes, the gate voltage of the pixel current control transistor and the voltage of the pixel electrode also change due to capacitive coupling, and as a result, the pixel current also changes. However, this voltage fluctuation is only 1 / n hour per frame time, and there is no problem in a high-definition panel of VGA or higher because the number of scanning lines is n = 480 or more.

However, when the scanning line connected to the pixel current control transistor is selected and the voltage rises, not only does the gate voltage of the pixel current control transistor rise, but also the source-drain potential of the pixel selection transistor increases. The voltage also increases. When the scanning line to which the pixel current control transistor is connected is selected, the scanning line to which the pixel selection transistor is connected is in a non-selected state, that is, the pixel selection transistor is in an off state, but the source and drain are not connected. As the voltage increases, the off-leak current increases. As a result, a problem occurs that the signal voltage input from the signal line and held in the capacitor fluctuates.

Therefore, in the present invention, it is preferable to perform line-sequential scanning in the direction from the scanning line connected to the pixel current control transistor to the scanning line connected to the pixel selection transistor in one pixel. Thus, the effect of the signal voltage fluctuation due to the off-leak current can be reduced to 1 / n, and the effect on the image display can be reduced to a negligible level.

Further, by making the pixel selection transistor have a multi-gate structure, the off-leak current can be further reduced.

When a high voltage of 10 to 20 V is applied between the source and the drain of the pixel current control transistor as in the case of the FED, the pixel current control transistor also has a multi-gate structure, so that the off-leakage current is reduced. The resulting power consumption can be reduced.

As described above, according to the present invention, the conventional constant voltage line or voltage supply line is not required, and as a result, the aperture ratio or the pixel electrode area increases, and the image display of the high definition panel becomes bright. It is possible to do.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 show the configuration of a pixel circuit in an image display device according to an embodiment of the present invention. Figure 1
The circuits (a) and (b) include two NMOS transistors, one capacitor, and a pixel electrode, and are used when a light emitting element or a light emitting material emits light by emitting electrons from the pixel electrode. Specifically, it can be used for FED. The circuits shown in FIGS. 2A and 2B are composed of two PMOS transistors, one capacitor, and a pixel electrode, and emit light from a light emitting element or a light emitting material by emitting holes from the pixel electrode. Used for Specifically, it can be used for an organic EL display. Here, the release of the charge from the pixel electrode can be applied to the case of recombination with a different charge.

The circuit shown in FIG. 1A or FIG.
1B or FIG. 2B is different from the circuit of FIG. 1B in connection with the wiring of the pixel selection transistor.

In the circuit of FIG. 1A, the gate of the pixel selecting transistor 6a is connected to the i-th scanning line 1a,
One of the source and the drain is connected to the signal line 2a in the j-th column. Similarly, in the circuit of FIG. 2A, the gate of the pixel selection transistor 8c is connected to the i-th scanning line 1c, and one of the source and the drain is connected to the j-th column signal line 2c. The pixel signal in this case may be a gate voltage of the pixel current driving transistors 7a and 9c, or may be a temporal gradation control signal based on the number of times a signal is written to a pixel in one frame. Good.

In the circuit of FIG. 1B, the gate of the transistor 6b for pixel selection is connected to the signal line 2b of the j-th column.
One of the source and the drain is connected to the i-th scanning line 1b. Similarly, in the circuit of FIG. 2B, the gate of the pixel selection transistor 8d is connected to the signal line 2d in the j-th column, and one of the source and the drain is connected to the scanning line 1d in the i-th row. In this case, the pixel signal is preferably a temporal gradation control signal based on the number of times a signal is written to a pixel in one frame.

(Embodiment 1) Hereinafter, an embodiment in which an FED is driven will be described with reference to FIG. FIG. 1A shows a pixel unit at an i-th row and a j-th column of a display composed of n rows and m columns of pixels. The pixel (ij) 3a includes a pixel selection NMOS transistor 6a,
It comprises an emission current control NMOS transistor 7a, a signal voltage holding capacitor 5a, and a pixel electrode 4a. An emitter (not shown) serving as an electron current source for causing the phosphor to emit light is formed in the pixel electrode 4a.

The pixel selecting NMOS transistor 6a is
The gate is connected to the i-th scanning line 1a, one of the source and the drain is connected to the j-th signal line 2a, and the other of the source and the drain is connected to the emission current controlling NMO.
The gate of the S transistor 7a is connected to one electrode of the capacitor 5a. Here, the source and the drain of the pixel selection NMOS transistor 6a are switched by the voltage applied to the signal line 2a in the j-th column. Therefore, the source and the drain of the transistor 6a cannot be distinguished from each other, but the transistor 6a connected to the signal line 2a in the j-th column is referred to as a source, and the transistor 6a connected to the capacitor 5a is referred to as a drain. I do. NM for emission current control
The drain of the OS transistor 7a is connected to the pixel electrode 4a on which the emitter is formed, and the source is connected to the other electrode of the capacitor 5a and the (i-1) th scanning line 1a '.

In the case of performing the line-sequential driving, when the scanning line 1a of the i-th row is selected and a voltage of, for example, 10 V is applied,
The m transistors connected to the row scanning line 1a are turned on. In FIG. 1A, the NMOS transistor 6a is turned on, and the signal voltage output from the external drive circuit to the j-th signal line 2a is applied to the capacitor 5a and the NM.
The voltage is applied to the gate of the OS transistor 7a. The magnitude of the signal voltage is adjusted such that the saturation drain current of the NMOS transistor 7a has a desired current value to be emitted from the emitter. For example, when a desired luminance can be obtained from the phosphor at an emission current of 1 μA, a signal voltage such that the saturation drain current of the transistor 7a becomes 1 μA may be applied. Here, the gradation of each pixel can be controlled by changing the saturation drain current value of the transistor 7a by changing the signal voltage. Further, it is also possible to control the saturation drain current value of the transistor 7a at a constant signal voltage and to change the number of selections or the selection time of each pixel in one frame period. Selection or non-selection of a pixel is performed based on a signal voltage equal to or higher than the threshold voltage of the transistor 7a and 0 V, or a signal voltage equal to or higher than the threshold voltage and a negative voltage.

Next, the reason why the current corresponding to the signal voltage can be maintained for about one frame period will be described. While the i-th scanning line 1a is selected and a positive voltage is applied,
Other scanning lines are in a non-selected state. That is, while the i-th scanning line 1a is selected, the (i-1) -th scanning line 1a 'is set to 0.
V or negative voltage. Therefore, pixel (ij) 3a
Is selected and the transistor 7a is on, the emission current flows from the pixel electrode 4a to the (i-1) th scanning line 1a 'via the transistor 7a. When the i-th scanning line 1a is in the non-selected state, the transistor 6a is turned off, so that the signal voltage supplied to the capacitor 5a is held. Therefore, the transistor 7a can continue to flow a current corresponding to the held signal voltage until the next signal is input to the capacitor 5a after one frame.

Here, the phenomenon in the case where the (i-1) th scanning line 1a 'is selected will be described with reference to FIGS. FIG.
FIG. 4 shows that the selected state of the scanning line is 10 V and the non-selected state is 0 V.
And an emission current of 1.0 at a signal voltage of 4V.
The simulation result when 4 μA flows is shown. Although not shown in the figure, the simulation was performed by increasing the electric field strength at the tip of the emitter, fixing the voltage of the extraction gate electrode to 80 V to facilitate electron emission from the emitter, and setting the threshold voltage of the emission current to 60 V. .

FIG. 3 shows that the time is changed from 370 μs to 400 μs after the signal voltage of 4 V is held in the capacitor 5a.
It shows the fluctuation of the voltage Vcapa of the gate of the transistor 7a and the capacitor 5a and the voltage Vemitter of the pixel electrode 4a on which the emitter is formed when the scanning line 1a 'in the (i-1) th row is in the selected state and 10 V is applied. ing. The emitter voltage Vemitter also fluctuates from 9.8V to 11.2V due to the fluctuation of the gate-side capacitor voltage Vcapa. As a result, as shown in FIG. 4, the emission current decreases. As described above, the emission current also fluctuates due to the voltage fluctuation of the (i-1) th scanning line 1a '. However, this fluctuation time is limited to the period during which the (i-1) th scanning line 1a' is selected as shown in FIG. Since this period is 1 / n or less of one frame, it is 1/480 or less for a high-definition panel of VGA or more, and the influence on an image is very small, and it is found that there is no problem.

On the other hand, since the drain of the transistor 6a is equal to the gate voltage Vcapa of the transistor 7a, when the voltage of the signal line 2a is 0 V, the transistor 6a
Is 14 V between the source and the drain. as a result,
In the transistor 6a, an off-leak current easily flows,
The voltage of Vcapa fluctuates. In the case where a transistor is formed using a thin film transistor, 10 to 10
Since an off-leak current of about 0 pA / μm may occur, the voltage of Vcapa may fluctuate by about 0.1 V. This voltage fluctuation is 25 at a voltage amplitude of 2.56V.
When performing 6 gradations, this is a problem because it corresponds to 10 gradations.

Therefore, in the present invention, in order to reduce the influence of the off-leak current as described above, the selection order of the scanning lines is changed as follows.
It is set so as to select sequentially from the (i-1) th scanning line 1a 'to the i-th scanning line 1a. Thereby, the transistor 6 during the (n-1) / n period in one frame
The source-drain voltage of a is a signal voltage at the maximum, which is 4 V in the present embodiment.
It can be easily controlled to 0 pA / μm or less, and good gradation control can be performed.

Incidentally, in order to suppress the off-leak current,
It is effective that the transistor 6a has a multi-gate structure. When the transistor 7a is also an FED,
Since the voltage between the source and the drain is about 10 to 20 V, it is effective to adopt a multi-gate structure in order to suppress power consumption due to off-leakage current. Further, in addition to the multi-gate structure, the diffusion layer of the transistor is formed by an LDD (Lig
By using an htly doped drain structure, it was possible to further suppress the off-leak current and suppress the variation in transistor characteristics due to hot carrier deterioration.

FIG. 5 shows an FED 1 according to the present embodiment.
FIG. 3 shows a layout diagram corresponding to pixels. Although the extraction gate electrode 51 in the figure is not always necessary, it is for facilitating the emission of electrons from the emitter, and is common to all pixels or a plurality of pixels. Further, the extraction gate electrode 51 is formed at a distance of 1 μm or less from the emitter, and is formed in a self-aligned manner with respect to the emitter. As a method of forming the emitter and the extraction gate electrode 51,
Spindt type method can be applied.

As can be seen from FIG. 5, it is no longer necessary to arrange a constant voltage line or a voltage supply line as in the prior art, so that the emitter forming region 52 can be made large. The transistor dimensions and capacitor area depend on the characteristics of the transistor.
Although it is necessary to change it in accordance with it, in the present embodiment, it can be formed in a region of 36% of the pixel area. Conventionally, a constant voltage line or a voltage supply line occupies several% to 10% of a pixel area. Therefore, when a layout similar to that of the present embodiment is performed, the emitter formation region 52 becomes 30% or less of the pixel area. Was. Based on this embodiment,
It was confirmed that by forming the FED panel, the emission current was stabilized and the luminance of the screen was improved.

(Embodiment 2) An embodiment in which an organic EL display is driven will be described with reference to FIG. FIG. 2A shows a pixel portion at the i-th row and the j-th column of the display composed of the pixels of the n-th row and the m-th column. The pixel (ij) 3c includes a pixel selection PMOS transistor 8c,
It comprises a pixel current control PMOS transistor 9c, a signal voltage holding capacitor 5c, and a pixel electrode 4c for injecting holes into the organic light emitting layer. The driving method is exactly the same as the FED driving of the first embodiment except that the polarity of the transistor is changed. It is only necessary to change the voltages of the scanning lines and the signal lines to the negative voltage with respect to the positive voltage of the FED.

The display pixel portion has a structure in which a pixel selecting transistor 8c, a pixel current controlling transistor 9c, and a capacitor 5c are formed by thin film transistors formed on a glass substrate. The pixel electrode 4c is formed of a transparent electrode such as ITO, an organic thin film serving as a light emitting layer is formed thereon, and a cathode is formed on the uppermost layer. Light emitted from the organic light emitting layer is used through a transparent electrode and a glass substrate. In this case, the aperture ratio of the pixel greatly affects the luminance. In the present invention, by eliminating the voltage supply line, the aperture ratio can be reduced from several% to
The improvement was 10%, so that a high-luminance organic EL display could be formed.

[0035]

According to the image display device of the present invention, the light emitting sustaining type display having the pixel selection transistor, the pixel current control transistor, and the signal voltage holding capacitor is provided, but the voltage supply line is not provided. Since the role is given to the scanning line and the voltage supply line is eliminated, the opening efficiency or the pixel electrode formation area can be increased, and higher brightness can be achieved as compared with the conventional method.

In addition, the method of selecting a scanning line is such that one pixel is sequentially selected in a direction from the scanning line to which the pixel current control transistor is connected to the scanning line to which the pixel selection transistor is connected, as viewed from one pixel. Is caused by giving the role of the voltage supply line to the scanning line,
Eliminates the effect of voltage fluctuations of the signal voltage holding capacitor,
Good gradation control becomes possible.

Further, by making the pixel selecting transistor have a multi-gate structure, it is possible to improve the signal voltage holding characteristic and to perform good gradation control.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a pixel in an image display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a pixel in the image display device according to the second embodiment of the present invention;

FIG. 3 is a diagram showing a variation characteristic of a signal voltage in the FED according to the embodiment of the present invention;

FIG. 4 is a diagram showing a variation characteristic of an emission current in the FED according to the embodiment of the present invention.

FIG. 5 is a layout diagram of a pixel region in the FED according to the embodiment of the present invention;

FIG. 6 is a circuit diagram of a pixel in a conventional FED.

FIG. 7 is a circuit diagram of a pixel in another conventional ELD.

[Explanation of symbols]

1a, 1b, 1c, 1d, 11, 21 i-th scanning line 1a ', 1b', 1c ', 1d' i-1th scanning line 11 ', 21' i + 1th scanning line 2a, 2b , 2c, 2d, 12, 22 signal lines 3a, 3b, 3c, 3d, 13, 23 pixels (ij) 4a, 4b, 4c, 4d, 14, 24 pixel electrodes 5a, 5b, 5c, 5d, 15, 25 Signal holding capacitor 6a, 6b, 16, 26 Pixel selecting NMOS transistor 7a, 7b, 17 Pixel current controlling NMOS transistor 8c, 8d Pixel selecting PMOS transistor 9c, 9d, 29 Pixel current controlling PMOS transistor 51 Extraction gate electrode 52 Emitter formation area

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme coat II (reference) H01J 29/96 H01J 29/96 31/12 31/12 CF term (reference) 5C032 AA01 5C036 EE04 EE14 EF01 EF06 EF09 EG48 EH05 EH26 5C080 AA01 AA06 BB05 DD01 DD23 EE29 FF11 FF12 JJ03 JJ04 JJ05 JJ06 5C094 AA10 AA15 BA03 BA29 CA19 EA04 EA07

Claims (5)

[Claims] 1. An active matrix type image display device having a plurality of pixels, a plurality of scanning lines, and a plurality of signal lines, wherein each of the pixels includes a pixel selection transistor and a pixel current control A transistor, a capacitor, and a pixel electrode, wherein the pixel selection transistor has a gate connected to the scanning line or the signal line, and one of a source and a drain not connected to the gate. The other of the source or the drain is connected to one electrode of the capacitor and the gate of the pixel current control transistor. The pixel current control transistor has a drain connected to the pixel electrode, and a source connected to the capacitor. Connected to a scanning line located adjacent to the scanning line with the pixel in between with the other electrode of An image display device characterized in that: 2. The image display device according to claim 1, wherein at least one of the pixel selection transistor and the pixel current control transistor is a multi-gate transistor. 3. The pixel selection transistor and the pixel current control transistor are both N-type MIS field effect transistors, and emit light from a light emitting element or a light emitting material by emitting electrons from the pixel electrode. The image display device according to claim 1 or 2, wherein 4. The method according to claim 1, wherein the pixel selection transistor and the pixel current control transistor are both P-type MIS field-effect transistors, and emit light from the pixel electrode by emitting holes from the pixel electrode. 3. The image display device according to claim 1, wherein: 5. The method for driving an image display device according to claim 1, wherein the pixel selection is performed from a scanning line in one pixel, which connects a source of the pixel current control transistor and one electrode of a capacitor. A line-sequential scan in an order toward a scanning line to which a transistor for connection is connected.