JP2002124664A - Compound field effect semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A field-effect semiconductor device and a method for manufacturing the same, in a compound field-effect semiconductor device, a gate-channel is insulated, a gate breakdown voltage is improved, and a deep mesa etching is caused. To prevent disconnection of the gate. SOLUTION: An i-InAlAs buffer layer 22 laminated and formed on a semi-insulating InP substrate 21 and formed into a mesa is provided.
i-InGaAs channel layer 23, n-InAlAs carrier supply layer 24, i-InAlAs protective layer 25, n ⁺
By applying the liquid phase oxidation method to the -InGaAs cap layer 26, at least the i-InGaAs channel layer 2 is formed.
An oxide insulating film is formed on the side wall of No. 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an InP-based HEM expected to be applied to an integrated circuit for a high-speed optical communication system.
T (high electron mobility)
Transistor), MESFET (metal
semiconductor fielddefect
(transistor), MISFET (metal
insulator semiconductor
The present invention relates to a compound field-effect semiconductor device including a field effect transistor and the like and an improvement in a manufacturing method thereof.

[0002]

2. Description of the Related Art In an InP-based high-In composition InGaAs channel HEMT, the energy band gap of InGaAs is small, and isolation by oxygen implantation is impossible. Therefore, isolation by mesa formation is performed. .

In such a case, since the side surface of the channel layer made of InGaAs is exposed, when the gate comes into contact with the side surface, the gate breakdown voltage is significantly reduced.

FIGS. 10A and 10B are main part explanatory views showing a HEMT in which elements are separated by mesa formation, wherein FIG. 10A is a main part plane, and FIG. 10B is a line shown in FIG. The cutaway side of the main part along XX is shown.

In FIG. 1A, reference numeral 1 denotes an active region, 2 denotes a source electrode, 3 denotes a drain electrode, 4 denotes a metal gate, 5 denotes a gate pad, and in FIG.
1 is an InP substrate, 12 is an i-InAlAs buffer layer,
13 is an InGaAs channel layer, 14 is n-InAlA
Reference numeral 15 denotes an i-InAlAs protective layer, and reference numeral 16 denotes a metal gate.

As is apparent from the figure, the I contained in the mesa
The side surface of the channel layer 13 made of nGaAs is exposed, and the metal gate 16 crawls and contacts the side surface of the channel layer 3.

The reason why the gate breakdown voltage is reduced in the above-mentioned state is that InGaAs cannot form a Schottky barrier, and various proposals have been made to solve this problem.

FIG. 11 is a cutaway side view of a main part of a conventional HEMT in which a measure for preventing a reduction in gate withstand voltage has been taken. The same symbols as used in FIG. 10 indicate the same parts or have the same meanings. Shall have.

In FIG. 1A, reference numeral 17 denotes a side wall made of SiON.
Isolation of the side surface of the channel layer 13 made of As is performed.

In FIG. 2B, reference numeral 18 denotes a void formed by side-etching the InGaAs channel layer. With this structure, the metal gate 16 is
3 is prevented from contacting. H indicates the height of the mesa.

However, in the conventional example in which the side wall 17 is formed as shown in FIG. 11A, although the anisotropic etching technique which is frequently used is applied, the control of the processing is not easy. Since the dry etching method is applied, there is a problem that damage is introduced to the semiconductor layer.

In the conventional example in which the gap 18 is formed as shown in FIG. 11 (B), if distortion occurs due to etching of an upper layer or formation of a gate metal layer due to a process defect, the gap 18 is formed. Is lost, and In
There is a possibility that the GaAs channel layer 13 and the metal gate 16 come into contact.

Further, as will be recognized from the above-mentioned conventional examples, 150 [n] is required for isolation.
m] to 200 [nm], deep metal mesa etching is performed, and there is a concern about disconnection of the metal gate 16. This point is that the current sub-micron order gate length is reduced to nano order. If that happens, it becomes a bigger problem.

[0014]

SUMMARY OF THE INVENTION In a compound field-effect semiconductor device, the gate and the channel are insulated from each other, the gate breakdown voltage is improved, and the disconnection of the gate due to deep mesa etching is prevented.

[0015]

According to the present invention, a compound semiconductor is oxidized by applying a liquid phase oxidation method and a steam oxidation method to a side wall of a compound field effect semiconductor device which is isolated by mesa etching. The basic principle is to improve the gate breakdown voltage by generating the gate voltage, and to suppress the gate disconnection by suppressing the height of the mesa.

Here, the liquid phase oxidation method refers to ammonia (N
H ₃ ) G in a potassium nitrate solution whose pH has been adjusted with water, etc.
oxidizing the GaAs surface by immersing aAs,
Ga oxide, i.e., a technique for generating a Ga ₂ O _3, H. H. Developed by Wang.

The technical achievements known to date in connection with the liquid phase oxidation process are that when GaAs is oxidized to produce Ga ₂ O ₃ ,
The interface state density at the Ga ₂ O ₃ / GaAs interface can be reduced. When the GaAs surface is selectively oxidized by using a resist mask, the oxidized GaAs portion has a high resistance. Not oxidized, GaAs-MOS using Ga ₂ O ₃ gate oxide film
It is known that the FET is realized (if necessary, “Jpn.J.Appl.Phy.
s. 37 (1998) L67 "," Jpn. J. App.
l. Phys. 37 (1998) L988 "," J.E.
electrochem. Soc. 146 (1999) 2
328 "," IEEE EDL-20 (1999) 1
8), etc.), and the present inventors have invented a recess oxidation type HEMT to which a liquid phase oxidation method is applied (if necessary,
See Japanese Patent Application No. 2000-147902), and in the present invention, besides GaAs, AlGaAs and InGa
It discloses that As is oxidized and InGaP is not oxidized.

Next, the steam oxidation method refers to AlAs, Al
This is a technique in which a compound semiconductor layer having a high Al composition, such as AsSb or InAlAs, is exposed to water vapor (steam) at a substrate temperature of 350 ° C. to 500 ° C. to transform into an (In) Al ₂ O ₃ insulating layer. Of a current confining layer in a semiconductor laser, or high reflection D in a surface emitting laser.
BR (distributed Bragg refl)
(See, Appl. Phys. Lett. 72, if necessary.)
(1998) 135. ", Appl. Phys. Le
tt. 70 (1997) 1781. "," Appl.P
hys. Lett. 75 (1999) 1264. ).)

In the compound field-effect semiconductor device according to the present invention, a compound oxide layer, for example, In, obtained by a simple means of subjecting a compound semiconductor, for example, InGaAs, to liquid phase oxidation.
The presence of the Ga oxide layer insulates between the gate and the channel to improve the gate breakdown voltage, and also provides a simple method of steam-oxidizing at least a part of the side wall in the compound semiconductor, for example, the InAlAs layer. The gate breakdown voltage can be further improved by making the insulation by means.

In addition, since the compound semiconductor can be easily insulated by liquid-phase oxidation, the step due to the mesa can be reduced, and therefore, the disconnection of the gate due to the step of the mesa can be reduced. it can.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 (HEMT in which channel layer is oxidized and insulated by applying a liquid phase oxidation method) FIGS. 1 and 2 show a HEMT in a process for explaining Embodiment 1. It is a principal part cut side view showing, It demonstrates below, referring these figures.

FIG. 1 (A) 1- (1) MOVPE (metalorganic vapor)
By applying a phase epitaxy method, a buffer layer 22, a channel layer 23, a carrier supply layer (here, an electron supply layer) 24, and a protective layer 2 are formed on a substrate 21.
5. The cap layer 26 is grown.

The main data in each of the above-mentioned semiconductor portions is exemplified as follows. (1) About the substrate 21 Material: semi-insulating InP (2) About the buffer layer 22 Material: i-InAlAs Thickness: 100 [nm] (3) About the channel layer 23 Material: i-InGaAs Thickness: 25 [nm] (4) Carrier supply layer 24 Material: n-InAlAs Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 10 [nm] (5) Protective layer 25 Material: i-InAlAs Thickness: 15 [nm] (6) Cap layer 26 Material: n ⁺ -InGaAs Impurity concentration: 1 × 10 ¹⁹ [cm ⁻³ ] Thickness: 50 [nm]

1- (2) A resist film 2 forming a mesa plane pattern by applying a resist process in lithography technology.
7 is formed.

1- (3) By applying a wet etching method using an H ₃ PO ₄ / H ₂ O ₂ etchant as an etchant, a mesa layer reaching the surface of the substrate 21 from the surface of the cap layer 26.
Perform etching.

1- (4) By applying the liquid phase oxidation method, the side surfaces of the i-InGaAs channel layer 23 are oxidized to form an InGaAs oxide film 28.
Is generated. Note that the HEMT shown is a cap layer 26.
Is also made of InGaAs.
An s oxide film 28 is generated.

The liquid phase oxidation will be described in more detail. Preparation of Solution for Liquid Phase Oxidation Gallium nitrate is dissolved in pure water at a rate of 0.1 [g / cc], and diluted ammonia water is added to adjust the pH to 4.5. Since white particles are generated in the solution, the solution is filtered through a filter to remove the white particles. Oxidation The temperature of the solution is 70 ° C., the wafer is immersed, and the oxidation rate is 130 nm / hour to oxidize the side surface of InGaAs. The oxidation rates for liquid phase oxidation are as shown in Table 1 below.

[Table 1] The thickness of the oxide film is controlled by the oxidation time.
An oxide film of 20 [nm] could be formed in an oxidation time of [minute]. In order to improve the gate breakdown voltage, the effect is remarkable when the thickness of the oxide film is 10 nm or more.

When the liquid phase oxidation is performed, InAlAs
, That is, i-InAlAs buffer layer 2
2, n-InAlAs carrier supply layer 24, i-InA
Since the side surface of the lAs protective layer 25 is also slightly oxidized, the oxide film is represented by a symbol 29 as a representative.

In the case of liquid-phase oxidation, there is no problem of difficulty in processing and introduction of damage unlike the side wall, and there is no need to form voids, so that a stable process can be performed.

See FIG. 2 2- (1) Although not shown, a source and a drain are formed.
Note that the source and the drain cannot be represented in FIG. 2 because they are formed with the gate 30 as the center in the direction perpendicular to the paper surface.

2- (2) Resist process in lithography technology, and
By applying a wet etching method using a mixture of citric acid + hydrogen peroxide + water as an etchant, n ⁺
A gate recess is formed by etching the InGaAs cap layer 26;

2- (3) Ti / Pt / Au by sequentially applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology
Is formed.

As is apparent from the figure, since the metal gate 29 and the InGaAs channel layer 23 are completely insulated, the gate breakdown voltage of the InP-based HEMT shown in the figure is surely improved.

By the way, the n-
If the sidewalls of the InAlAs carrier supply layer 24 can be sufficiently oxidized and insulated to offset the carriers, the gate breakdown voltage can be further improved.

However, it is difficult to oxidize InAlAs at the same oxidation rate as that of InGaAs only by applying the liquid phase oxidation method. In that case, the second embodiment described below may be implemented. Thereby, the insulation between the metal gate 30 and the InGaAs channel layer 23 can be further stabilized as compared with the first embodiment.

Embodiment 2 (HEM in which channel layer and others are oxidized and insulated by using both steam oxidation method and liquid phase oxidation method)
T) FIG. 3 and FIG. 4 are cutaway side views of a main part showing a HEMT in the middle of a process for explaining the second embodiment, which will be described below with reference to these drawings.

3 (A) 3- (1) Chemical vapor deposition (chemical vapor deposition) using a wafer having the same semiconductor lamination structure as in the first embodiment.
By applying a deposition (CVD) method, the surface of the n ⁺ -InGaAs cap layer 26 is
An N film 31 is formed.

3- (2) A resist film forming a mesa plane pattern is formed by applying a resist process in the lithography technique, and then the resist film is formed by applying a dry etching method. The SiN film 31 is etched using the film as a mask.

3- (3) The surface of the cap layer 26 is formed by using the patterned SiN film 31 as a mask by applying a wet etching method using an etchant as an H ₃ PO ₄ / H ₂ O ₂ based etchant. Is performed to reach the surface of the substrate 21 from above.

3 (B) 3- (4) InAlAs with steam obtained by bubbling water at a substrate temperature of 500 ° C., a nitrogen flow rate of 1 liter / minute, and a temperature of 80 ° C. Oxidation of InAlAs
An oxide film 29 is generated.

In this case, the oxidation rate of InAlAs is 7
50 [nm / hour] and 25 [n] between 2 [minutes]
m] could be formed. The thickness of the oxide film is at least 10 [nm], which is sufficient to achieve the object.

Here, the semiconductor layer whose mesa side surface is oxidized includes an i-InAlAs buffer layer 22, an n-InAl
As carrier supply layer 24, i-InAlAs protective layer 25
It is.

Referring to FIG. 4A, 4- (1) the i-InGaAs channel layer 23 and the In-InGaAs channel layer 23 are formed by applying the liquid phase oxidation method under exactly the same conditions as in the first embodiment.
The side surface of the GaAs cap layer 26 is oxidized to a thickness of 20 [n
m] of the InGaAs oxide film 28 is generated.

As is clear from the above description, the side surfaces of the mesa are all covered with oxide films 28 and 29, and especially n-In
The thickness of the oxide film 29 on the side surface of the AlAs carrier supply layer 24 (and the buffer layer 22 and the protective layer 25) can be made thicker than in the first embodiment.

In the case of the second embodiment as well, similar to the first embodiment, there is no difficulty in processing and no damage is introduced as in the case of the side wall, and there is no need to form voids, so that a stable process is performed. can do.

Referring to FIG. 4B, 4- (2) After forming the source and the drain in the same manner as in the first embodiment, the resist and the resist in the lithography technique are formed.
The process and the application of a wet etching method in which the etchant is citric acid + H ₂ O ₂ make n
^The gate recess is formed by etching the ⁺ -InGaAs cap layer 26.

4- (3) Ti / Pt / Au by sequentially applying a resist process, a vacuum deposition method, and a lift-off method in the lithography technique
Is formed.

In the first and second embodiments and the conventional example, in order to reliably avoid contact between the channel and the gate, the step H of the mesa (see FIG. 11B) is set to 150 [n].
m] or more.

The reason will be described with reference to FIG. 11B, for example. If the electron supply layer 14 is formed into a mesa in order to reduce the step of the mesa,
When a part close to the substrate 11 is left on the channel layer 13 outside the mesa, or when the gap 18 is formed, the etchant hardly seeps into the channel layer 13 from the side and forms a sufficient gap. The problem of being unable to do so also arises.

However, in order to further increase the speed of the field-effect semiconductor device, it is essential at present that the gate length on the order of submicrons must be on the order of nanometers. Since a problem of disconnection occurs, in this case, a third embodiment described below may be employed.

Embodiment 3 and Embodiment 4 (HEMT in which disconnection of a metal gate is prevented by forming an oxide film on a side surface of a mesa to be insulated) FIG. 5 shows Embodiment 3 and Embodiment H in the middle of the process for explaining the form 4
It is a principal part cut-away side view showing EMT, and it demonstrates below, referring these figures. Note that FIG. 5A shows Embodiment 3
FIG. 5B shows the fourth embodiment.

FIG. 5A (Embodiment 3) 5 (A)-(1) Using a wafer having the same semiconductor lamination structure as in Embodiments 1 and 2, Similarly, Mesa
Etching is performed, but in Embodiment 3, the depth is different.

First, the etchants are InAlAs and In
H ₃ PO ₄ that can etch GaAs together
By applying a wet etching method using a / H ₂ O ₂ -based etchant, mesa etching from the surface of the n ⁺ -InGaAs cap layer 26 to the surface of the i-InGaAs channel layer 23 is performed.

5 (A)-(2) By applying a wet etching method using a citric acid / H ₂ O ₂ -based etchant capable of selectively etching InAlAs and InGaAs as an etchant,
The i-InGaAs channel layer 23 is etched.
Incidentally, the height H of the mesa is 50 [nm].

5 (A)-(3) The same liquid phase oxidation solution as in the first embodiment
[° C.], immerse the wafer, and set the oxidation rate to 100 [n].
m / hour], the side surface of the i-InGaAs channel layer 23 is oxidized to generate an InGaAs oxide film 28. In this case, an oxide film having a thickness of 20 [nm] was formed in an oxidation time of 12 [minutes].

5 (A)-(4) In the same manner as in the first embodiment, after forming the source and the drain, a resist process in lithography and an etchant are citric acid + H ₂ O ₂ etching solution By applying the wet etching method described above, the n ⁺ -InGaAs cap layer 26 is etched to form a gate recess.

5 (A)-(5) Ti / Pt / Au by sequentially applying a resist process, a vacuum deposition method, and a lift-off method in the lithography technique.
Is formed.

FIG. 5B (Embodiment 4) 5 (B)-(1) i-In from the surface of the n ⁺ -InGaAs cap layer 26
The process until the mesa etching reaching the surface of the GaAs channel layer 23 is performed is the same as that of the third embodiment. At the stage where the mesa etching is completed, the i-InGaAs channel layer 23 extends to the lower side of the mesa. It is in the state of being displayed. By the way, the height H of the mesa is 25 [n
m].

5 (B)-(2) The same solution for liquid phase oxidation as in the first embodiment
[° C.], immerse the wafer, and set the oxidation rate to 100 [n].
m / hour], the exposed surface of the i-InGaAs channel layer 23 is oxidized to form an InGaAs oxide film 28. still,
In this case, the oxidation time was 20 [minutes].

5 (B)-(3) In the same manner as in the first embodiment, after forming the source and the drain, the resist process in the lithography technique and the etchant are mixed with citric acid + H ₂ O ₂ By applying the wet etching method described above, n
^The gate recess is formed by etching the ⁺ -InGaAs cap layer 26.

5 (B)-(4) Ti / Pt / Au by sequentially applying a resist process, a vacuum deposition method, and a lift-off method in the lithography technique.
Is formed.

The step of the mesa in the HEMT obtained according to the third or fourth embodiment is a conventional HEMT.
, The disconnection of the metal gate 30 hardly occurs. In Embodiments 3 and 4, it is optional to use steam oxidation in combination.

Although the above-described first to fourth embodiments are directed to HEMTs, the present invention relates to a MES.
It can be easily applied to FETs and MISFETs.

Fifth Embodiment (MESFET in which Channel Layer is Oxidized and Insulated by Applying Liquid-Phase Oxidation Method) FIGS. 6 and 7 are cutaway views showing a MESFET during a process for explaining a fifth embodiment. It is a side view, and it demonstrates below with reference to these figures.

6A. 6- (1) A buffer layer 42, a channel layer 43, and a barrier layer 44 are grown on a substrate 41 by applying the MOVPE method.

The main data in each of the above-mentioned semiconductor portions is exemplified as follows. (1) About the substrate 41 Material: semi-insulating InP (2) About the buffer layer 42 Material: i-InAlAs Thickness: 100 [nm] (3) About the channel layer 43 Material: n-InGaAs Impurity concentration: 1 × 10 ¹⁸ [Cm ^-3 ] Thickness: 18 [nm] (4) About the barrier layer 44 Material: i-InAlAs Thickness: 10 [nm]

Here, the reason why the i-InAlAs barrier layer 44 is provided is that a high Schottky barrier cannot be generated in the n-InGaAs channel layer 43.

6- (2) A resist film 4 forming a mesa plane pattern by applying a resist process in the lithography technique.
5 is formed.

6- (3) Mesa etching from the surface of the barrier layer 44 to the surface of the substrate 41 by applying a wet etching method using an etchant as an H ₃ PO ₄ / H ₂ O ₂ type etching solution. I do.

6 (B) 6- (4) By applying the liquid phase oxidation method, the side surface of the n-InGaAs channel layer 43 is oxidized to form an InGaAs oxide film 46.
Is generated.

For the liquid-phase oxidation, the same liquid-phase oxidation solution as in the first embodiment is used, the temperature of the solution is set to 70 ° C., the wafer is immersed, and the oxidation rate is set to 130 nm / hour.
To oxidize the side surface of InGaAs.

The thickness of the oxide film was controlled by the oxidation time. In this case, an oxide film 46 of 20 nm could be formed in an oxidation time of 10 minutes.

When the liquid phase oxidation is performed, InAlAs
A layer consisting of: i-InAlAs buffer layer 42,
Since the side surface of the n-InAlAs barrier layer 44 is also slightly oxidized, the oxide film is represented by a symbol 47.

Also in the fifth embodiment, there is no problem of difficulty in processing and introduction of damage unlike the side wall.
In addition, since there is no need to generate voids, a stable process can be performed.

7- (1) Although not shown, after forming a source and a drain, a resist process in lithography technology, a vacuum deposition method, and a lift-off method are sequentially applied to form Ti / Pt /
A metal gate 48 made of Au is formed.

As is apparent from the figure, since the metal gate 48 and the InGaAs channel layer 43 are completely insulated, the gate breakdown voltage in the illustrated MESFET is surely improved.

Sixth Embodiment (MISFET in which Channel Layer is Oxidized and Insulated by Applying Liquid Phase Oxidation Method) FIGS. 8 and 9 are cutaway views showing a MISFET during a process for explaining the sixth embodiment. It is a side view, and it demonstrates below with reference to these figures.

Referring to FIG. 8A, the buffer layer 42 and the channel layer 43 are grown on the substrate 41 by applying the MOVPE method.

The main data in each of the above-mentioned semiconductor parts is exemplified as follows. (1) About the substrate 41 Material: semi-insulating InP (2) About the buffer layer 42 Material: i-InAlAs Thickness: 100 [nm] (3) About the channel layer 43 Material: n-InGaAs Impurity concentration: 2 × 10 ¹⁷ [Cm ^-3 ] Thickness: 100 [nm]

8- (2) Gas Source Molecular Beam Epitaxial Growth (gas so
urce molecular beam epita
By applying the xy: GSMBE method, a gate insulating film 51 having a thickness of 30 [nm] is formed on the channel layer 43.

The gate insulating film 51 is made of gallium sulfide (G
aS), gallium oxide (gadolinium) [(Ga _x Gd
_An insulating material such as _1-x ) ₂ O ₃ ] that can reduce interface states is used.

Here, the gate insulating film 5 made of GaS is used.
The case of forming 1 will be specifically described.

8- (3) The wafer is set in the GSMBE apparatus and the substrate temperature is set to 400
After heating to [° C.], the wafer surface is irradiated with trisdimethylaminoarsenic to remove the natural oxide film.

8- (4) A gate insulating film 51 made of GaS and having a thickness of 30 [nm] is formed on the channel layer 43 by using tertiary butyl gallium sulfacupene as a raw material at a substrate temperature of 350 [° C]. .

8- (5) A resist film 4 having a mesa plane pattern is formed by applying a resist process in the lithography technique.
5 is formed.

8- (6) By applying a wet etching method using an etchant of H ₃ PO ₄ / H ₂ O ₂ based etchant, a mesa reaching the surface of the substrate 41 from the surface of the gate insulating film 51. Perform etching.

Referring to FIG. 8B, 8- (4) the side surface of the n-InGaAs channel layer 43 is oxidized by applying the liquid phase oxidation method to form the InGaAs oxide film 46.
Is generated.

For the liquid-phase oxidation, the same liquid-phase oxidation solution as in the first embodiment is used, the temperature of the solution is set to 70 ° C., the wafer is immersed, and the oxidation rate is set to 130 nm / hour.
Then, the side surface of the n-InGaAs channel layer 43 is oxidized.

The oxide film thickness was controlled depending on the oxidation time. In this case, an oxide film 46 of 20 nm was formed in an oxidation time of 10 minutes.

When the liquid phase oxidation is performed, InAlAs
, That is, the side surface of the i-InAlAs buffer layer 42 is also slightly oxidized.

Also in the sixth embodiment, there is no problem of difficulty in processing and introduction of damage unlike the side wall.
In addition, since there is no need to generate voids, a stable process can be performed.

See FIG. 9 7- (1) Although not shown, after forming a source and a drain, a resist process, a vacuum deposition method, and a lift-off method in a lithography technique are sequentially applied to Ti / Pt /
A metal gate 48 made of Au is formed.

As is clear from the figure, since the metal gate 48 and the n-InGaAs channel layer 43 are completely insulated, the gate breakdown voltage in the illustrated MISFET is surely improved.

In each of the above embodiments, InGaAs and InAlAs have been described as compound semiconductors to be oxidized. However, other materials include InAlGaAs and InAlGaAs.
GaAsSb and the like can be similarly oxidized.

[0095]

In the compound field effect semiconductor device according to the present invention and the method of manufacturing the same, it is fundamental that an oxide insulating film is formed on the side walls of the laminated and mesaized compound semiconductor layers.

According to the present invention, the presence of the compound oxide layer obtained by a simple means of subjecting a part of the compound semiconductor layer constituting the compound field-effect semiconductor device to liquid phase oxidation causes a gap between the gate and the channel. Are insulated to improve the gate breakdown voltage, and similarly, a part of the compound semiconductor layer is insulated by a simple means of steam oxidation to further improve the gate breakdown voltage.

In addition, since the compound semiconductor can be easily insulated by liquid-phase oxidation, the step due to the mesa can be reduced, and therefore, an accident that the gate is disconnected due to the step of the mesa can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a HEMT during a process for explaining a first embodiment;

FIG. 2 is a fragmentary side view showing a HEMT during a process for explaining the first embodiment;

FIG. 3 is a fragmentary side view showing a HEMT during a process for explaining a second embodiment;

FIG. 4 is a fragmentary side view showing a HEMT during a process for explaining a second embodiment;

FIG. 5 is a fragmentary side view showing a HEMT in the middle of a process for explaining a third embodiment and a fourth embodiment;

FIG. 6 is a fragmentary side view showing a MESFET during a process for explaining a fifth embodiment;

FIG. 7 is a fragmentary side view showing a MESFET during a process for explaining a fifth embodiment;

FIG. 8 is a fragmentary side view showing a MISFET during a process for explaining a sixth embodiment;

FIG. 9 is a fragmentary side view showing a MISFET during a process for describing a sixth embodiment;

FIG. 10 shows a HEM in which the elements are separated by forming a mesa.
FIG. 9 is an explanatory diagram of a main part representing T.

FIG. 11 is a fragmentary side view showing a conventional HEMT in which a measure for preventing a reduction in gate withstand voltage is taken.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Substrate 22 Buffer layer 23 Channel layer 24 Carrier supply layer 25 Protective layer 26 Cap layer 27 Resist film 28 InGaAs oxide film 29 InAlAs oxide film 30 Metal gate

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F102 FA01 GB01 GC01 GD01 GJ06 GK04 GL04 GM04 GR04 GS02 GT03 HC00 HC01 HC16 HC18

Claims (5)

[Claims] 1. A compound field effect semiconductor device comprising an oxide insulating film formed on a side wall of a laminated and mesaized compound semiconductor layer. 2. The compound field effect semiconductor device according to claim 1, wherein the compound semiconductor layer having the oxide insulating film formed on the side wall is an InGaAs channel layer. 3. The compound field effect semiconductor device according to claim 1, wherein the compound semiconductor layer having the oxide insulating film formed on the side wall is an InAlAs layer in addition to the InGaAs channel layer. 4. An InGa film between a substrate and a substrate through a buffer layer.
A step of laminating a compound semiconductor layer including an As channel layer; and a step of mesa-etching from a surface of the laminated compound semiconductor layer to at least a surface of the InGaAs channel layer. Immerse at least InG
oxidizing the side wall of the aAs channel layer. 5. The semiconductor device according to claim 1, wherein In is contained in the compound semiconductor layer.
5. The method according to claim 4, further comprising the step of oxidizing the AlAs layer with water vapor.