JP2002124524A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JP2002124524A JP2002124524A JP2000315379A JP2000315379A JP2002124524A JP 2002124524 A JP2002124524 A JP 2002124524A JP 2000315379 A JP2000315379 A JP 2000315379A JP 2000315379 A JP2000315379 A JP 2000315379A JP 2002124524 A JP2002124524 A JP 2002124524A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- brazing material
- material layer
- alloy
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】
【課題】半導体素子を配線基板にＡｕ−Ｓｎ合金等から
成るロウ材層を介して接着固定するにあたり、ロウ材層
のＳｎが第２の拡散防止層に拡散してロウ材層の融点が
上昇し、接着時にロウ材層を溶融させて半導体素子を確
実、強固に接着固定することが困難であった。
【解決手段】絶縁基板１の上面に密着金属層２、第１の
拡散防止層３、Ａｕより成る主導体層４、Ｐｔより成る
第２の拡散防止層５、Ｓｎ層６およびＡｕ−Ｍ（ＭはＳ
ｎ，ＳｉまたはＧｅ）合金より成るロウ材層７が順次積
層された配線導体層が形成されている。
(57) Abstract: In bonding and fixing a semiconductor element to a wiring board via a brazing material layer made of an Au-Sn alloy or the like, the Sn of the brazing material layer diffuses into the second diffusion preventing layer to form a solder. The melting point of the material layer has risen, and it has been difficult to reliably and firmly bond and fix the semiconductor element by melting the brazing material layer during bonding. An adhesion metal layer, a first diffusion prevention layer, a main conductor layer made of Au, a second diffusion prevention layer made of Pt, a Sn layer, and an Au-M are formed on an upper surface of an insulating substrate. M is S
A wiring conductor layer is formed in which a brazing material layer 7 made of an n, Si or Ge) alloy is sequentially laminated.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体レーザ等の
半導体素子を搭載するサブマウント等として用いられる
配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used as a submount for mounting a semiconductor device such as a semiconductor laser.
【０００２】[0002]
【従来の技術】従来の半導体素子を搭載するための配線
基板を図２に示す。同図において、１１は窒化アルミニ
ウムセラミックス等から成る絶縁基板、１２はＴｉ等か
ら成る密着金属層、１３はＰｔ等から成る第１の拡散防
止層、１４はＡｕから成る主導体層であり、１５はＰｔ
から成る第２の拡散防止層であり、１６は半導体素子の
電極等を接着するためのＡｕ−Ｓｎ合金から成るロウ材
層である。2. Description of the Related Art FIG. 2 shows a conventional wiring board for mounting a semiconductor element. In the figure, 11 is an insulating substrate made of aluminum nitride ceramics or the like, 12 is an adhesion metal layer made of Ti or the like, 13 is a first diffusion prevention layer made of Pt or the like, 14 is a main conductor layer made of Au, 15 Is Pt
Reference numeral 16 denotes a brazing material layer made of an Au-Sn alloy for bonding electrodes and the like of a semiconductor element.
【０００３】絶縁基板１１の上面に被着されたＡｕから
成る主導体層１４と半導体素子を接着固定するＡｕ−Ｓ
ｎ合金から成るロウ材層１６との間に、Ｐｔから成る第
２の拡散防止層１５を配した構造にすることで、半導体
素子をロウ材層１６を介して接着固定する際、主導体層
１４のＡｕがロウ材層１６のＡｕ−Ｓｎ合金中に拡散す
るのを第２の拡散防止層１５によって有効に防止するも
のである。また、ロウ材層１６は組成および組成比が変
化することにより融点が高くなることはなく、接着時の
所定の温度で完全に溶解して半導体素子を配線基板上に
確実、強固に接着できることができるものである（特開
平１１−３０７６９２号公報参照）。[0003] Au-S for bonding and fixing a semiconductor element to a main conductor layer 14 made of Au adhered on the upper surface of an insulating substrate 11.
With the structure in which the second diffusion prevention layer 15 made of Pt is arranged between the brazing material layer 16 made of n alloy and the semiconductor element, the main conductor layer is used when the semiconductor element is bonded and fixed via the brazing material layer 16. The second diffusion prevention layer 15 effectively prevents the Au of No. 14 from diffusing into the Au—Sn alloy of the brazing material layer 16. Further, the melting point of the brazing material layer 16 does not increase due to a change in the composition and composition ratio, and the brazing material layer 16 can be completely melted at a predetermined temperature at the time of bonding and can securely and firmly bond the semiconductor element onto the wiring board. It is possible (see Japanese Patent Application Laid-Open No. H11-307792).
【０００４】[0004]
【発明が解決しようとする課題】近年、上記従来の配線
基板において、ロウ材層１６を薄くすることが要求され
ており、これは、半導体レーザ（レーザダイオード：Ｌ
Ｄ）やフォトダイオード（ＰＤ）等の光半導体素子等の
半導体素子を搭載する配線基板の場合、ロウ材層１６の
厚みが厚いと半導体素子を接着固定させた際、ロウ材層
１６が半導体素子の接着面（下面）から側面へ這い上が
り、半導体素子の側面に設けられたレーザ発光部がロウ
材層１６により塞がれるという不具合が生じ易いためで
ある。また、ロウ材層１６の厚みが厚いと半導体素子を
接着固定させた際、半導体素子と配線基板とが平行に接
着されず、傾いた状態で接着され易いので、半導体素子
のレーザが絶縁基板１１の上面に対して平行に出射され
ないという不具合が生じていた。In recent years, in the above-mentioned conventional wiring board, it is required to make the brazing material layer 16 thin, and this is because a semiconductor laser (laser diode: L
In the case of a wiring board on which a semiconductor element such as an optical semiconductor element such as D) or a photodiode (PD) is mounted, if the thickness of the brazing material layer 16 is large, when the semiconductor element is bonded and fixed, the brazing material layer 16 This is because the laser light-emitting portion provided on the side surface of the semiconductor element is likely to be closed by the brazing material layer 16 from the adhesive surface (lower surface) of the semiconductor device. When the thickness of the brazing material layer 16 is large, when the semiconductor element is bonded and fixed, the semiconductor element and the wiring board are not bonded in parallel but are easily bonded in an inclined state. Has not been emitted parallel to the upper surface of the.
【０００５】一方、ロウ材層１６が厚いことによる上記
の不具合を解消するために、ロウ材層１６の厚みを薄く
すると、半導体素子を接着するために配線基板を加熱し
た際、第２の拡散防止層１５を構成するＰｔ中に、その
上部のロウ材層１６を構成するＡｕ−Ｓｎ合金中のＳｎ
が急速に拡散し、その結果、ロウ材層１６を構成するＡ
ｕ−Ｓｎ合金の組成がＡｕ過多（Ａｕリッチ）となり、
融点の上昇を招き易いことがわかった。その場合、接着
時の所定の温度でロウ材層１６のＡｕ−Ｓｎ合金を完全
に溶融させることができず、半導体素子と配線基板とが
強固に接着され難いという問題点があった。On the other hand, if the thickness of the brazing material layer 16 is reduced in order to solve the above-mentioned problem caused by the thick brazing material layer 16, the second diffusion layer is formed when the wiring board is heated to bond the semiconductor elements. Sn contained in the Au—Sn alloy constituting the brazing material layer 16 above the Pt constituting the prevention layer 15
Rapidly diffuses, and as a result, A
The composition of the u-Sn alloy becomes Au-rich (Au-rich),
It was found that the melting point was easily increased. In this case, there is a problem that the Au—Sn alloy of the brazing material layer 16 cannot be completely melted at a predetermined temperature at the time of bonding, and it is difficult for the semiconductor element and the wiring substrate to be firmly bonded.
【０００６】また、ロウ材層１６の融点上昇という問題
点を解消するために、ロウ付け温度を上げ、ロウ材層１
６を完全に溶融させることも考えられるが、ロウ付け温
度を上げると半導体素子に不要な熱的負荷が加わり半導
体素子に熱破壊が生じたり、発光特性等の動作特性が劣
化し、半導体素子が誤作動するという問題を誘発してい
た。In order to solve the problem that the melting point of the brazing material layer 16 rises, the brazing temperature is increased and the brazing material layer 1 is heated.
Although it is conceivable to completely melt the semiconductor element 6, if the brazing temperature is increased, an unnecessary thermal load is applied to the semiconductor element, causing thermal destruction of the semiconductor element or deteriorating operating characteristics such as light emission characteristics. This has caused the problem of malfunction.
【０００７】従って、本発明は上記事情に鑑みて完成さ
れたものであり、その目的は、半導体素子を配線基板
に、Ａｕ−Ｓｎ合金から成るロウ材層を介して接着固定
するにあたり、Ａｕ−Ｓｎ合金から成るロウ材層のＳｎ
が第２の拡散防止層に拡散し、Ａｕ−Ｓｎ合金の融点が
上昇するのを有効に防止し、接着時の所定の温度でＡｕ
−Ｓｎ合金を完全に溶融させ、半導体素子を確実、強固
に接着固定することができる配線基板を提供することに
ある。Accordingly, the present invention has been completed in view of the above circumstances. It is an object of the present invention to provide a method for bonding and fixing a semiconductor element to a wiring board via a brazing material layer made of an Au-Sn alloy. Sn of brazing material layer composed of Sn alloy
Effectively diffuses into the second diffusion prevention layer to increase the melting point of the Au—Sn alloy, and Au is bonded at a predetermined temperature during bonding.
An object of the present invention is to provide a wiring board that can completely and securely fix a semiconductor element by melting an Sn alloy completely.
【０００８】[0008]
【課題を解決するための手段】本発明の配線基板は、絶
縁基板の上面に、密着金属層、第１の拡散防止層、Ａｕ
より成る主導体層、Ｐｔより成る第２の拡散防止層、Ｓ
ｎ層およびＡｕ−Ｍ（ＭはＳｎ，ＳｉまたはＧｅ）合金
より成るロウ材層が順次積層された配線導体層が形成さ
れていることを特徴とする。According to the present invention, there is provided a wiring board comprising an adhesion metal layer, a first diffusion preventing layer, and an Au layer on an upper surface of an insulating substrate.
Main conductive layer made of Pt, second diffusion prevention layer made of Pt, S
It is characterized in that a wiring conductor layer is formed in which an n layer and a brazing material layer made of an Au-M (M is Sn, Si or Ge) alloy are sequentially laminated.
【０００９】本発明は、Ｐｔより成る第２の拡散防止層
とＡｕ−Ｍ合金より成るロウ材層との間にＳｎ層を設け
たことにより、配線基板をロウ付け温度まで加熱した
際、第２の拡散防止層のＰｔとＳｎ層との界面において
Ｐｔ3Ｓｎ，ＰｔＳｎで表される高融点のＰｔ−Ｓｎ合
金層を形成する。このＰｔ−Ｓｎ合金層が、ロウ材層中
のＳｎ等が多量に第２の拡散防止層に拡散することを防
ぐ。また、ロウ材層がＡｕリッチになることによるロウ
材層の融点上昇を防ぐことができる。つまり、ロウ材層
中のＡｕとＳｎとの組成比が大きく変化することがない
ため、接着時の所定の温度によってロウ材層を完全に溶
融させることができ、半導体素子を確実、強固に接着固
定することができる。According to the present invention, an Sn layer is provided between a second diffusion preventing layer made of Pt and a brazing material layer made of an Au-M alloy. A high melting point Pt—Sn alloy layer represented by Pt 3 Sn and PtSn is formed at the interface between the Pt and Sn layers of the second diffusion prevention layer. This Pt—Sn alloy layer prevents a large amount of Sn and the like in the brazing material layer from diffusing into the second diffusion prevention layer. Further, it is possible to prevent the melting point of the brazing material layer from rising due to the Au material becoming Au-rich. In other words, since the composition ratio of Au and Sn in the brazing material layer does not change significantly, the brazing material layer can be completely melted at a predetermined temperature during bonding, and the semiconductor element can be securely and firmly bonded. Can be fixed.
【００１０】[0010]
【発明の実施の形態】本発明の配線基板について以下に
説明する。図１は、本発明の配線基板の断面図である。
同図において、１は絶縁基板、２は密着金属層、３は第
１の拡散防止層、４はＡｕより成る主導体層、５はＰｔ
より成る第２の拡散防止層、６はＳｎ層、７はＡｕ−Ｍ
（ＭはＳｎ，ＳｉまたはＧｅ）合金より成るロウ材層で
ある。絶縁基板１は、例えば酸化アルミニウム（Ａｌ2
Ｏ3）質焼結体、窒化アルミニウム（ＡｌＮ）質焼結
体、炭化珪素（ＳｉＣ）質焼結体、ガラスセラミック焼
結体、窒化珪素（Ｓｉ3Ｎ4）質焼結体、石英、ダイヤモ
ンド、サファイア、立方晶窒化硼素、または熱酸化膜を
形成したシリコンのうち少なくとも１種より成るのがよ
く、これらは体積抵抗率ρが１０10Ωｍ以上で絶縁性が
良好である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A wiring board according to the present invention will be described below. FIG. 1 is a sectional view of a wiring board of the present invention.
In the figure, 1 is an insulating substrate, 2 is a close contact metal layer, 3 is a first diffusion prevention layer, 4 is a main conductor layer made of Au, and 5 is Pt.
6 is a Sn layer, 7 is Au-M
(M is a brazing material layer made of Sn, Si or Ge) alloy. The insulating substrate 1 is made of, for example, aluminum oxide (Al 2
O 3 ) sintered body, aluminum nitride (AlN) based sintered body, silicon carbide (SiC) based sintered body, glass ceramic sintered body, silicon nitride (Si 3 N 4 ) based sintered body, quartz, diamond , Sapphire, cubic boron nitride, or silicon on which a thermal oxide film is formed, which has a volume resistivity ρ of 10 10 Ωm or more and good insulation.
【００１１】なお、絶縁基板１は、窒化アルミニウム質
焼結体、炭化珪素質焼結体、ダイヤモンド、シリコンで
形成するのがより好ましく、これらの熱伝導率は４０Ｗ
／ｍ・Ｋ以上と高いため、配線基板の上面に接着固定さ
れる半導体素子が駆動時に熱を発しても、その熱は配線
基板を介して良好に外部に伝達されるため、半導体素子
を長時間にわたり正常かつ安定に作動させることが可能
となる。The insulating substrate 1 is more preferably formed of an aluminum nitride sintered body, a silicon carbide sintered body, diamond or silicon, and has a thermal conductivity of 40 W.
/ M · K or more, even if the semiconductor element bonded and fixed to the upper surface of the wiring board generates heat during driving, the heat is transmitted well to the outside via the wiring board. It is possible to operate normally and stably over time.
【００１２】また、絶縁基板１としてガラスセラミック
焼結体や石英を用いることもより好ましく、これらの比
誘電率は６以下（１ＭＨｚでの測定）と小さいために、
絶縁基板１が浮遊容量を持たず、その結果半導体素子に
電気信号を高速で伝達させることが可能となる。Further, it is more preferable to use a glass ceramic sintered body or quartz as the insulating substrate 1. Since the relative permittivity of these materials is as small as 6 or less (measured at 1 MHz),
The insulating substrate 1 has no stray capacitance, and as a result, it is possible to transmit an electric signal to the semiconductor element at high speed.
【００１３】絶縁基板１の上面に被着される配線導体層
の成膜は、蒸着法、スパッタリング法、ＣＶＤ法等の薄
膜形成法によりなされ、パターン加工が必要な場合は、
フォトリソグラフィ法、エッチング法、リフトオフ法等
によってパターン加工される。The wiring conductor layer deposited on the upper surface of the insulating substrate 1 is formed by a thin film forming method such as a vapor deposition method, a sputtering method, a CVD method, and the like.
Pattern processing is performed by a photolithography method, an etching method, a lift-off method, or the like.
【００１４】密着金属層２は、例えばＴｉ，Ｃｒ，Ｔ
ａ，Ｎｂ，Ｎｉ−Ｃｒ合金またはＴａ 2Ｎ等のうち少な
くとも１種類より成るのがよく、第１の拡散防止層３
は、例えばＰｔ，Ｐｄ，Ｒｈ，Ｒｕ，Ｎｉ，Ｎｉ−Ｃｒ
合金またはＴｉ−Ｗ合金等のうち少なくとも１種類より
成るのがよい。The adhesion metal layer 2 is made of, for example, Ti, Cr, T
a, Nb, Ni-Cr alloy or Ta TwoLess than N
It is preferable that the first diffusion prevention layer 3
Is, for example, Pt, Pd, Rh, Ru, Ni, Ni-Cr
Alloy or Ti-W alloy
Should consist of
【００１５】密着金属層２の厚さは０．０１〜０．２μ
ｍ程度が良い。０．０１μｍ未満では、強固に密着する
ことが困難となる傾向にあり、０．２μｍを超えると、
成膜時の内部応力によって剥離が生じ易くなる。The thickness of the adhesion metal layer 2 is 0.01 to 0.2 μm.
m is good. If it is less than 0.01 μm, it tends to be difficult to firmly adhere, and if it exceeds 0.2 μm,
Separation easily occurs due to internal stress during film formation.
【００１６】また、第１の拡散防止層３の厚さは０．０
５〜１μｍ程度が良く、０．０５μｍ未満ではピンホー
ル等の欠陥が発生して第１の拡散防止層３としての機能
を果たしにくい傾向にあり、１μｍを超えると成膜時の
内部応力により剥離が生じ易くなる。The thickness of the first diffusion preventing layer 3 is 0.0
If the thickness is less than 0.05 μm, defects such as pinholes tend to occur and it is difficult to function as the first diffusion prevention layer 3. If the thickness exceeds 1 μm, peeling is caused by internal stress during film formation. Is more likely to occur.
【００１７】さらに、Ａｕより成る主導体層４の厚さは
０．１〜５μｍ程度が良い。０．１μｍ未満では、電気
抵抗が大きくなる傾向にあり、５μｍを超えると成膜時
の内部応力により剥離を生じ易くなる。また、Ａｕは貴
金属で高価であることから、低コスト化の点で薄く形成
することが好ましい。The thickness of the main conductor layer 4 made of Au is preferably about 0.1 to 5 μm. If it is less than 0.1 μm, the electrical resistance tends to increase, and if it exceeds 5 μm, peeling tends to occur due to internal stress during film formation. Further, since Au is a noble metal and expensive, it is preferable to form it thinly from the viewpoint of cost reduction.
【００１８】Ｐｔより成る第２の拡散防止層５の厚みは
０．０１〜１μｍ程度が良い。また、第２の拡散防止層
５の上部に形成されるＳｎ層の厚みは０．０１〜１μｍ
程度がよい。半導体素子を接着固定するために配線基板
をロウ付け温度まで加熱した際、第２の拡散防止層５を
形成するＰｔとその上に形成されたＳｎ層６とによって
Ｐｔ3Ｓｎ，ＰｔＳｎで表される高融点のＰｔ−Ｓｎ合
金層が形成される。第２の拡散防止層５の厚みおよびＳ
ｎ層６の厚みがそれぞれ０．０１μｍ未満では、両者に
よって形成されるＰｔ−Ｓｎ合金層が、主導体層４を形
成するＡｕのロウ材層７内への拡散を十分に抑えること
ができない。それぞれの厚みが１μｍを超えると成膜時
の内部応力により剥離を生じ易くなる。The thickness of the second diffusion prevention layer 5 made of Pt is preferably about 0.01 to 1 μm. The thickness of the Sn layer formed on the second diffusion prevention layer 5 is 0.01 to 1 μm.
Good degree. When the wiring board is heated to a brazing temperature for bonding and fixing the semiconductor element, the wiring board is represented by Pt 3 Sn and PtSn by the Pt forming the second diffusion prevention layer 5 and the Sn layer 6 formed thereon. A high melting point Pt—Sn alloy layer is formed. Thickness of second diffusion prevention layer 5 and S
If the thickness of each of the n-layers 6 is less than 0.01 μm, the Pt—Sn alloy layer formed by both layers cannot sufficiently suppress the diffusion of Au forming the main conductor layer 4 into the brazing material layer 7. If each thickness exceeds 1 μm, separation easily occurs due to internal stress during film formation.
【００１９】さらに、Ｐｔより成る第２の拡散防止層５
とＳｎ層６のＰｔとＳｎについて、ＰｔとＳｎのモル比
が１：２〜６：１の範囲内になるようにすることが好ま
しい。Further, a second diffusion preventing layer 5 made of Pt
It is preferable that the molar ratio of Pt to Sn in the Sn layer 6 be in the range of 1: 2 to 6: 1.
【００２０】モル比においてＰｔ／Ｓｎが１／２未満の
場合、即ちＰｔが３３．３モル％未満の含有量の場合、
Ｓｎがリッチな状態となり、このＳｎが第２の拡散防止
層５の下層の主導体層４のＡｕ中へ拡散し、Ａｕ−Ｓｎ
化合物が形成される。その際に生じる体積収縮によって
カーケンダールボイドと呼ばれる脆いＡｕ−Ｓｎ合金層
が、主導体層４中の上側（第２の拡散防止層５側）にで
きてしまい、その結果この脆いＡｕ−Ｓｎ合金層から剥
離が発生する危険性がある。When the molar ratio of Pt / Sn is less than 1/2, that is, when the content of Pt is less than 33.3 mol%,
Sn becomes a rich state, and this Sn diffuses into Au of the main conductor layer 4 under the second diffusion prevention layer 5, and Au-Sn
A compound is formed. A fragile Au-Sn alloy layer called Kirkendale void is formed on the upper side (the second diffusion prevention layer 5 side) in the main conductor layer 4 due to volume shrinkage generated at that time, and as a result, this fragile Au-Sn There is a risk that peeling will occur from the alloy layer.
【００２１】また、モル比においてＰｔ／Ｓｎが６／１
を超える場合、即ちＰｔが８５．７モル％を超える含有
量の場合、Ｐｔがリッチな状態となり、ロウ材層７中の
Ｓｎ等が第２の拡散防止層５へ拡散してしまい、ロウ材
層７の融点の上昇を招く。その結果、接着時の所定の温
度（２８０〜３３０℃程度）でロウ材層７を完全に溶融
させることができず、半導体素子と配線基板とが強固に
接続され難くなる。In a molar ratio, Pt / Sn is 6/1.
When the Pt content exceeds 85.7 mol%, Pt is in a rich state, and Sn and the like in the brazing material layer 7 diffuse into the second diffusion preventing layer 5, and the brazing material is This causes an increase in the melting point of the layer 7. As a result, the brazing material layer 7 cannot be completely melted at a predetermined temperature (approximately 280 to 330 ° C.) at the time of bonding, and it is difficult to firmly connect the semiconductor element and the wiring board.
【００２２】半導体素子を接着固定するロウ材層７の厚
みは、０．５〜３μｍ程度が良く、０．５μｍ未満で
は、半導体素子を強固に接着することが困難となり、３
μｍを超えると半導体素子を接着固定させた際、ロウ材
層７が半導体素子の接着面から側面へ這い上がり、半導
体素子が半導体レーザの場合、その側面に設けられたレ
ーザ発光部が塞がれるという不具合が生じ易い。また、
Ａｕ−Ｍ合金を構成するＡｕは貴金属で高価であること
から、薄く形成する方が低コスト化の点で好ましい。The thickness of the brazing material layer 7 for adhering and fixing the semiconductor element is preferably about 0.5 to 3 μm. If the thickness is less than 0.5 μm, it becomes difficult to firmly adhere the semiconductor element.
If the thickness exceeds μm, when the semiconductor element is bonded and fixed, the brazing material layer 7 rises from the bonding surface of the semiconductor element to the side face, and when the semiconductor element is a semiconductor laser, the laser light emitting portion provided on the side face is closed. The problem described above is likely to occur. Also,
Since Au that constitutes the Au-M alloy is a noble metal and is expensive, it is preferable to form it thinly in terms of cost reduction.
【００２３】また、ロウ材層７の上面に０．１μｍ程度
の厚さのＡｕ層を被着して、ロウ材層７の表面酸化を防
ぐ構造としてもよい。Further, an Au layer having a thickness of about 0.1 μm may be formed on the upper surface of the brazing material layer 7 to prevent the surface of the brazing material layer 7 from being oxidized.
【００２４】ロウ材層７としては、Ａｕ−Ｓｎ合金、Ａ
ｕ−Ｇｅ合金またはＡｕ−Ｓｉ合金を用いるものであ
り、それぞれ同様の作用効果が得られる。これらのなか
で、特にＡｕ−Ｓｎ合金が好適であり、その場合Ａｕ−
Ｓｎ合金は溶融温度が最も低いので搭載する半導体素子
への熱的影響が小さくなる。As the brazing material layer 7, an Au—Sn alloy, A
A u-Ge alloy or an Au-Si alloy is used, and the same operation and effect can be obtained. Among these, an Au-Sn alloy is particularly preferable, in which case the Au-Sn alloy is used.
Since the Sn alloy has the lowest melting temperature, the thermal effect on the mounted semiconductor element is reduced.
【００２５】配線基板に形成する配線導体層は、配線基
板の上面だけでなく、下面や側面に形成してもよい。ま
た、その層構成を上面と同様にしても、または異なるも
のとしても構わない。The wiring conductor layer formed on the wiring substrate may be formed not only on the upper surface but also on the lower surface and side surfaces of the wiring substrate. Further, the layer configuration may be the same as or different from the upper surface.
【００２６】かくして、本発明は、配線基板をロウ付け
温度まで加熱した際、第２の拡散防止層５のＰｔとＳｎ
層６との界面においてＰｔ3Ｓｎ，ＰｔＳｎで表される
高融点のＰｔ−Ｓｎ合金層を形成し、このＰｔ−Ｓｎ合
金層がロウ材層中のＳｎが多量に第２の拡散防止層に拡
散することを防ぐ。また、ロウ材層がＡｕリッチになる
ことによるロウ材層の融点上昇を防ぐことができる。従
って、ロウ材層中のＡｕとＳｎとの組成比が大きく変化
しないため、接着時の所定の温度によってロウ材層を完
全に溶融させることができ、半導体素子を確実、強固に
接着固定することができる。Thus, according to the present invention, when the wiring substrate is heated to the brazing temperature, the Pt and Sn
A high melting point Pt—Sn alloy layer represented by Pt 3 Sn and PtSn is formed at the interface with the layer 6, and this Pt—Sn alloy layer is used as a second diffusion prevention layer with a large amount of Sn in the brazing material layer. Prevent spreading. Further, it is possible to prevent the melting point of the brazing material layer from rising due to the Au material becoming Au-rich. Therefore, since the composition ratio of Au and Sn in the brazing material layer does not change significantly, the brazing material layer can be completely melted at a predetermined temperature during bonding, and the semiconductor element can be securely and firmly bonded and fixed. Can be.
【００２７】[0027]
【実施例】本発明の実施例を以下に説明する。Embodiments of the present invention will be described below.
【００２８】（実施例）図１の配線基板を以下の工程
［１］、［２］により作製した。(Example) The wiring board of FIG. 1 was manufactured by the following steps [1] and [2].
【００２９】［１］絶縁基板１として、寸法が縦３ｍｍ
×横３ｍｍ×高さ０．４ｍｍで窒化アルミニウム質焼結
体から成るものを用意し、絶縁基板１を洗浄後、真空蒸
着法により、厚さが０．１μｍのＴｉより成る密着金属
層２、厚さが０．２μｍのＰｔより成る第１の拡散防止
層３、厚さが０．５μｍのＡｕより成る主導体層４を順
次積層した。[1] The dimensions of the insulating substrate 1 are 3 mm in length.
An aluminum nitride sintered body having a width of 3 mm and a height of 0.4 mm was prepared, and after washing the insulating substrate 1, an adhesion metal layer 2 made of Ti having a thickness of 0.1 μm was formed by vacuum evaporation. A first diffusion prevention layer 3 made of Pt having a thickness of 0.2 μm and a main conductor layer 4 made of Au having a thickness of 0.5 μm were sequentially laminated.
【００３０】［２］この主導体層４上に、厚さが０．２
μｍのＰｔより成る第２の拡散防止層５、厚さが０．２
μｍのＳｎ層６、厚さが２μｍのＡｕ−Ｓｎ合金より成
るロウ材層７をスパッタリング法により順次形成した。[2] On the main conductor layer 4, a thickness of 0.2
Second anti-diffusion layer 5 made of Pt having a thickness of 0.2 μm
A Sn layer 6 having a thickness of μm and a brazing material layer 7 made of an Au—Sn alloy having a thickness of 2 μm were sequentially formed by a sputtering method.
【００３１】上記のようにして作製した配線基板と、Ｓ
ｎ層６が形成されていない以外は上記実施例と同様にし
て作製した配線基板とを用いて、ロウ材層７の濡れ性を
比較した。３３０℃の温度に保持したヒータブロック上
に配線基板を置き、表面に酸化膜ができないように不活
性ガス（Ａｒガス）を吹き付け、３０秒後にロウ材層７
表面の光沢の有無を調べた。Ｓｎ層６を有する本発明の
配線基板では光沢があったが、Ｓｎ層６のない配線基板
では、高融点相の析出により光沢のないざらついた表面
状態となった。この結果から、Ｓｎ層６を設けた方がロ
ウ材層７の濡れ性が良好であることがわかった。The wiring board manufactured as described above,
The wettability of the brazing material layer 7 was compared using a wiring board manufactured in the same manner as in the above example except that the n-layer 6 was not formed. The wiring substrate is placed on a heater block maintained at a temperature of 330 ° C., and an inert gas (Ar gas) is blown thereon so as not to form an oxide film on the surface.
The surface was examined for gloss. The wiring board of the present invention having the Sn layer 6 was glossy, but the wiring board without the Sn layer 6 had a glossy and rough surface due to precipitation of the high melting point phase. From this result, it was found that the Sn layer 6 provided better brazing material layer 7 wettability.
【００３２】また、ロウ材層７としてＡｕ−Ｓｉ合金，
Ａｕ−Ｇｅ合金を用いた場合についても、上記実施例と
同様にしてそれぞれロウ材層７表面の光沢について調べ
たが、上記実施例と同様の結果が得られた。An Au—Si alloy,
Also in the case where the Au-Ge alloy was used, the gloss of the surface of the brazing material layer 7 was examined in the same manner as in the above-described embodiment, and the same result as in the above-described embodiment was obtained.
【００３３】なお、本発明は上記実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲内において
種々の変更を行なうことは何等差し支えない。It should be noted that the present invention is not limited to the above embodiment, and that various changes may be made without departing from the spirit of the present invention.
【００３４】[0034]
【発明の効果】本発明は、絶縁基板の上面に、密着金属
層、第１の拡散防止層、Ａｕより成る主導体層、Ｐｔよ
り成る第２の拡散防止層、Ｓｎ層およびＡｕ−Ｍ（Ｍは
Ｓｎ，ＳｉまたはＧｅ）合金より成るロウ材層が順次積
層された配線導体層が形成されていることにより、半導
体素子を配線基板にロウ材層を介して接着固定するにあ
たり配線基板を加熱する際に、第２の拡散防止層のＰｔ
とＳｎ層とがそれらの界面において高融点のＰｔ−Ｓｎ
合金層を形成するため、ロウ材層のＳｎが第２の拡散防
止層に拡散してロウ材層の融点が上昇するのを有効に防
止し、接着時の所定の温度でロウ材層を完全に溶融さ
せ、その結果半導体素子を確実、強固に接着固定するこ
とができる。According to the present invention, an adhesion metal layer, a first diffusion prevention layer, a main conductor layer made of Au, a second diffusion prevention layer made of Pt, a Sn layer and an Au-M ( M denotes a heating of the wiring board when the semiconductor element is bonded and fixed to the wiring board via the brazing material layer because the wiring conductor layer in which the brazing material layers made of Sn, Si or Ge) alloy are sequentially laminated is formed. In doing so, the Pt of the second diffusion prevention layer
And the Sn layer at their interface with high melting point Pt-Sn
Since the alloy layer is formed, Sn of the brazing material layer is effectively prevented from diffusing into the second diffusion preventing layer to increase the melting point of the brazing material layer, and the brazing material layer is completely formed at a predetermined temperature during bonding. As a result, the semiconductor element can be securely and firmly adhered and fixed.
【図１】本発明の配線基板の断面図である。FIG. 1 is a sectional view of a wiring board of the present invention.
【図２】従来の配線基板の断面図である。FIG. 2 is a cross-sectional view of a conventional wiring board.
１：絶縁基板 ２：密着金属層 ３：第１の拡散防止層 ４：主導体層 ５：第２の拡散防止層 ６：Ｓｎ層 ７：ロウ材層 1: Insulating substrate 2: Adhesive metal layer 3: First diffusion preventing layer 4: Main conductor layer 5: Second diffusion preventing layer 6: Sn layer 7: Brazing material layer
フロントページの続き Ｆターム(参考） 4E351 AA06 BB01 BB23 BB24 BB29 BB38 CC00 DD06 DD12 DD20 DD21 GG01 GG08 5F047 AA17 BA12 CA08 Continued on the front page F term (reference) 4E351 AA06 BB01 BB23 BB24 BB29 BB38 CC00 DD06 DD12 DD20 DD21 GG01 GG08 5F047 AA17 BA12 CA08
Claims (1)
散防止層、Ａｕより成る主導体層、Ｐｔより成る第２の
拡散防止層、Ｓｎ層およびＡｕ−Ｍ（ＭはＳｎ，Ｓｉま
たはＧｅ）合金より成るロウ材層が順次積層された配線
導体層が形成されていることを特徴とする配線基板。1. An adhesion metal layer, a first diffusion prevention layer, a main conductor layer made of Au, a second diffusion prevention layer made of Pt, a Sn layer, and an Au-M (M is Sn, A wiring substrate, comprising: a wiring conductor layer in which brazing material layers made of Si or Ge) alloy are sequentially laminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000315379A JP4605883B2 (en) | 2000-10-16 | 2000-10-16 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000315379A JP4605883B2 (en) | 2000-10-16 | 2000-10-16 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002124524A true JP2002124524A (en) | 2002-04-26 |
| JP4605883B2 JP4605883B2 (en) | 2011-01-05 |
Family
ID=18794492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000315379A Expired - Fee Related JP4605883B2 (en) | 2000-10-16 | 2000-10-16 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4605883B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005091351A1 (en) * | 2004-03-24 | 2005-09-29 | Tokuyama Corporation | Substrate for device bonding and method for manufacturing same |
| JP2005285966A (en) * | 2004-03-29 | 2005-10-13 | Kyocera Corp | Submount and light emitting device using the same |
| JP2006269751A (en) * | 2005-03-24 | 2006-10-05 | Toshiba Corp | Semiconductor device manufacturing method and semiconductor device |
| JP2006286958A (en) * | 2005-03-31 | 2006-10-19 | Toshiba Corp | Ceramic circuit board and semiconductor device using the same |
| EP1695382A4 (en) * | 2001-05-24 | 2007-10-10 | Fry Metals Inc | THERMAL INTERFACE MATERIAL AND LOT-PREFORMS |
| JPWO2005020315A1 (en) * | 2003-08-26 | 2007-11-01 | 株式会社トクヤマ | Element bonding substrate, element bonding substrate and manufacturing method thereof |
| US7663242B2 (en) | 2001-05-24 | 2010-02-16 | Lewis Brian G | Thermal interface material and solder preforms |
| US8836119B2 (en) | 2012-08-09 | 2014-09-16 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| JP2021150464A (en) * | 2020-03-18 | 2021-09-27 | シチズンファインデバイス株式会社 | Electrode structure and junction structure including the same |
| JP7526116B2 (en) | 2021-03-04 | 2024-07-31 | シチズンファインデバイス株式会社 | How to calculate the duration of solder melting |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260671A (en) * | 1989-03-31 | 1990-10-23 | Nec Corp | Optical semiconductor device |
| JPH04263432A (en) * | 1991-02-19 | 1992-09-18 | Nec Corp | Bump electrode of semiconductor element |
| JPH11307692A (en) * | 1998-04-23 | 1999-11-05 | Kyocera Corp | Semiconductor element support member and semiconductor element storage package using the same |
| JP2000288770A (en) * | 1999-03-31 | 2000-10-17 | Kyocera Corp | AuSn multilayer solder |
| JP2002151629A (en) * | 2000-08-28 | 2002-05-24 | Kyocera Corp | Wiring board |
-
2000
- 2000-10-16 JP JP2000315379A patent/JP4605883B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260671A (en) * | 1989-03-31 | 1990-10-23 | Nec Corp | Optical semiconductor device |
| JPH04263432A (en) * | 1991-02-19 | 1992-09-18 | Nec Corp | Bump electrode of semiconductor element |
| JPH11307692A (en) * | 1998-04-23 | 1999-11-05 | Kyocera Corp | Semiconductor element support member and semiconductor element storage package using the same |
| JP2000288770A (en) * | 1999-03-31 | 2000-10-17 | Kyocera Corp | AuSn multilayer solder |
| JP2002151629A (en) * | 2000-08-28 | 2002-05-24 | Kyocera Corp | Wiring board |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1695382A4 (en) * | 2001-05-24 | 2007-10-10 | Fry Metals Inc | THERMAL INTERFACE MATERIAL AND LOT-PREFORMS |
| US7663242B2 (en) | 2001-05-24 | 2010-02-16 | Lewis Brian G | Thermal interface material and solder preforms |
| JP4979944B2 (en) * | 2003-08-26 | 2012-07-18 | 株式会社トクヤマ | Element bonding substrate, element bonding substrate and manufacturing method thereof |
| JPWO2005020315A1 (en) * | 2003-08-26 | 2007-11-01 | 株式会社トクヤマ | Element bonding substrate, element bonding substrate and manufacturing method thereof |
| CN100428432C (en) * | 2004-03-24 | 2008-10-22 | 德山株式会社 | Substrate for bonding device and method for manufacturing the same |
| WO2005091351A1 (en) * | 2004-03-24 | 2005-09-29 | Tokuyama Corporation | Substrate for device bonding and method for manufacturing same |
| US7626264B2 (en) | 2004-03-24 | 2009-12-01 | Tokuyama Corporation | Substrate for device bonding and method for manufacturing same |
| JP2005285966A (en) * | 2004-03-29 | 2005-10-13 | Kyocera Corp | Submount and light emitting device using the same |
| JP2006269751A (en) * | 2005-03-24 | 2006-10-05 | Toshiba Corp | Semiconductor device manufacturing method and semiconductor device |
| JP2006286958A (en) * | 2005-03-31 | 2006-10-19 | Toshiba Corp | Ceramic circuit board and semiconductor device using the same |
| US8836119B2 (en) | 2012-08-09 | 2014-09-16 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| JP2021150464A (en) * | 2020-03-18 | 2021-09-27 | シチズンファインデバイス株式会社 | Electrode structure and junction structure including the same |
| JP7406417B2 (en) | 2020-03-18 | 2023-12-27 | シチズンファインデバイス株式会社 | Electrode structure and bonded structure equipped with the electrode structure |
| JP7526116B2 (en) | 2021-03-04 | 2024-07-31 | シチズンファインデバイス株式会社 | How to calculate the duration of solder melting |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4605883B2 (en) | 2011-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3509809B2 (en) | Submount and semiconductor device | |
| JP3882712B2 (en) | Submount and semiconductor device | |
| JP3918858B2 (en) | Light-emitting element mounting member and semiconductor device using the same | |
| JP3982284B2 (en) | Submount and semiconductor device | |
| JP2013016838A (en) | Ceramics wiring substrate and semiconductor device using the same | |
| JP4605883B2 (en) | Wiring board | |
| WO2005020315A1 (en) | Substrate for device bonding, device bonded substrate, and method for producing same | |
| WO2004107438A1 (en) | Submount and semiconductor device using same | |
| JP4363761B2 (en) | Wiring board | |
| JP4822155B2 (en) | Submount and manufacturing method thereof | |
| JP2008034581A (en) | Submount | |
| JP2002252316A (en) | Wiring board | |
| JP2003318475A (en) | Optical semiconductor device mounting structure | |
| JP4637495B2 (en) | Submount | |
| JP3987765B2 (en) | Subcarrier of optical semiconductor element and optical semiconductor device | |
| JP4014867B2 (en) | Heat sink submount and manufacturing method thereof | |
| JP4549103B2 (en) | Method for manufacturing light emitting device | |
| JP2003101120A (en) | Wiring board | |
| JP2003068929A (en) | Semiconductor element mounting substrate and semiconductor device | |
| JP2006216766A (en) | Ceramic circuit board and semiconductor device using the same | |
| JP2001127370A (en) | Submount for mounting semiconductor elements | |
| JP2004111770A (en) | Wiring board | |
| JP2006041156A (en) | Submount and light emitting device using the same | |
| JP2006203051A (en) | Submount and semiconductor device | |
| JPWO2020138278A1 (en) | Joining method and joining structure of electronic parts |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070907 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091023 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091029 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091221 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100907 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101005 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4605883 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131015 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |