JP2002118264A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabricating method in which floating effect of a substrate incident to impact ionization can be suppressed sufficiently in an SOI device while suppressing increase in the occupation area of the SOI device. SOLUTION: The semiconductor device comprises a supporting substrate 2, an SOI substrate 1 having an insulation film 3 formed on the substrate and a single crystal Si layer 4 formed on the insulation film, a gate oxide film 6 formed on the surface of the single crystal Si layer 4, a gate electrode 7 formed on the gate oxide film, diffusion layers 16 and 17 of source-drain formed beneath the gate electrode 7 on the side wall side, and a pinhole 3a made in the insulation film 3 beneath the gate electrode 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an SOI structure and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device capable of sufficiently suppressing a substrate floating effect and a method for manufacturing the same.

[0002]

2. Description of the Related Art A method of forming a transistor in a single crystal semiconductor layer on an insulating film is known as an SOI (Silicon On Insulator) structure. Hereinafter, the MO formed on the SOI substrate will be described.
The S transistor will be described.

FIGS. 3A and 3B are cross-sectional views showing a conventional method for manufacturing a semiconductor device. First, the SOI substrate 10
Prepare 1 The SOI substrate 101 includes a support substrate 102 made of single crystal silicon, an insulating film 103 formed on the support substrate 102, and a single crystal Si layer 104 formed on the insulating film 103. I have. The SOI substrate 101 can be manufactured by various manufacturing methods.
It can also be manufactured by X (separation by Implanted oxygen) or the like. The bonding method is a method for preparing an SOI substrate by preparing two silicon substrates each having an insulating film on the surface and bonding the insulating films of the silicon substrates to each other. SIMOX is a method for manufacturing an SOI substrate by implanting oxygen at a high concentration into a single crystal silicon substrate to form an oxide film inside the silicon substrate.

[0004] Next, as shown in FIG.
A trench is formed in the i-layer 104, and a silicon oxide film is embedded in the trench. Thus, the element isolation film 1 made of a silicon oxide film is formed in the element isolation region on the insulating film 103.
05 is formed. Next, a P-type impurity is ion-implanted into the single-crystal Si layer 104.

Thereafter, a gate oxide film 106 is formed on the surface of the single crystal Si layer 104 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the gate oxide film 106, and the polysilicon film is patterned to form a gate electrode 107 on the gate oxide film.

Next, while rotating the SOI substrate 101, high-energy Ar ions 109 are obliquely implanted under the condition that the concentration becomes maximum at the bottom of the single-crystal Si layer 104. As a result, a damage layer 111 including a crystal defect is formed at the bottom of the single crystal Si layer 104 located below the gate electrode. This damage layer 111 is made of SO
This is for suppressing the substrate floating effect due to impact ionization in the I device. In other words, when there is no damage layer, the single-crystal Si layer 104 is insulated from the support substrate 102, so that minority carriers (holes) generated by a strong drain electric field or the like are transiently accumulated in the single-crystal Si layer. Although the threshold voltage fluctuates as a result, when the damage layer 111 is present, the recombination of holes generated in the single crystal Si layer is promoted, and the lifetime of the holes is shortened. The accumulation of holes in the substrate can be suppressed, and the floating effect of the substrate can be suppressed.

Then, as shown in FIG. 3B, low concentration N-type impurity ions are implanted using the gate electrode 107 as a mask. Next, a silicon oxide film is deposited on the entire surface including the gate electrode 107 by a CVD (Chemical Vapor Deposition) method, and the silicon oxide film is etched on the entire surface. A wall 113 is formed.

Next, N-type impurity ions are implanted using the side wall 113 and the gate electrode 107 as a mask. Thereafter, the SOI substrate 101 is annealed, so that the single-crystal Si layer 104 has a low-concentration N-type diffusion layer 1.
15 and N-type diffusion layers 116, 1 of source / drain regions
17 are formed.

In the conventional method of manufacturing a semiconductor device, when the Ar ions 109 are implanted, the conditions are such that the concentration is maximized at the bottom of the single-crystal Si layer 104. A damage layer 111 made of a crystal defect is formed at the bottom. Therefore, the concentration of crystal defects is highest at the bottom of the single crystal Si layer. However, although this crystal defect has a lower concentration than the bottom of the single-crystal Si layer, it is also formed in the diffusion layers 116 and 117 in the source / drain regions where the crystal defect is not desired to be formed. Thereby, for example, N channel M
In the case of the OS transistor, majority carriers (electrons) are trapped by crystal defects (damage portions) in the source / drain regions, so that desired transistor performance cannot be exhibited.

FIG. 4 is a plan view showing another conventional semiconductor device. This semiconductor device suppresses a substrate floating effect by extracting minority carriers (holes) generated by a strong drain electric field or the like from a body contact portion connected to a single crystal Si layer.

A semiconductor device has an SOI substrate.
The I substrate includes a support substrate made of single-crystal silicon, an insulating film formed on the support substrate, and a single-crystal Si layer 104 formed on the insulating film.

An element isolation film 105 is formed on the single crystal Si layer 104.
Are formed. The element isolation film 105 is located in an element isolation region on the insulating film. P-type impurities are introduced into the single crystal Si layer 104. A gate oxide film (not shown) is formed on the surface of the single crystal Si layer 104, and a gate electrode 107 is formed on the gate oxide film.
N-type diffusion layers 116 and 117 of source / drain regions are formed in the single crystal Si layer. Single crystal Si layer 1
04 has body contact portions 121 to 123 formed therein.

In the other conventional method of manufacturing a semiconductor device described above, holes generated in the single-crystal Si layer are pulled out of the body contact portions 121 to 123, so that the single-crystal S
It is possible to suppress the accumulation of holes in the i-layer and suppress the substrate floating effect.

However, when the body contact portions 121 to 123 are formed in the single crystal Si layer 104, the substrate floating effect can be suppressed, but a region for forming the body contact portion is required as shown in FIG. Therefore, the area occupied by the device increases.

[0015]

In the above-described conventional method for manufacturing a semiconductor device, the crystal defects are also formed in the diffusion layers 116 and 117 in the source / drain regions where the formation of crystal defects is not desired. Majority carriers are trapped by crystal defects in the source / drain regions.
As a result, desired transistor performance cannot be exhibited. Further, the other conventional semiconductor device requires a region for forming a body contact portion, and thus has a problem that the area occupied by the device increases.

The present invention has been made in consideration of the above circumstances, and has as its object to sufficiently suppress the floating effect of a substrate accompanying impact ionization in an SOI device while suppressing an increase in the area occupied by the SOI device. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0017]

In order to solve the above problems, a semiconductor device according to the present invention is an SOI substrate having a supporting substrate, an insulating film formed thereon, and a single-crystal Si layer formed thereon. A gate insulating film formed on the surface of the single crystal Si layer; a gate electrode formed on the gate insulating film; and a source formed on the single crystal Si layer and formed below the side wall of the gate electrode. / Drain region, and a pinhole formed in the insulating film below the gate electrode.

According to the above semiconductor device, a transistor comprising a gate electrode and a diffusion layer of a source / drain region is formed on an SOI substrate, and a pinhole located below the gate electrode is provided in an insulating film of the SOI substrate. . Thereby, holes due to impact ionization generated in the single crystal Si layer can be efficiently extracted from the pinhole to the support substrate side. Therefore, the lifetime of holes is shortened, and the accumulation of holes in the single crystal Si layer can be suppressed,
The substrate floating effect can be sufficiently suppressed.

In the semiconductor device according to the present invention, a plurality of the pinholes may be formed. As a result, it is possible to further increase the efficiency of extracting holes accompanying the impact ionization generated in the single-crystal Si layer from the pinhole to the support substrate side.

Further, the semiconductor device according to the present invention may further include a pinhole formed in the insulating film below the diffusion layer of the source / drain region. As a result, it is possible to further increase the efficiency of extracting holes accompanying the impact ionization generated in the single-crystal Si layer from the pinhole to the support substrate side.

In the method of manufacturing a semiconductor device according to the present invention, a first substrate having a first insulating film formed on a supporting substrate and a first pinhole formed in the first insulating film is prepared. A step, a second insulating film formed on the single crystal Si layer,
Preparing a second substrate having a second pinhole formed in the second insulating film; and aligning the first pinhole and the second pinhole so that the first pinhole and the second pinhole are connected to each other. By bonding the insulating film, the supporting substrate, the insulating film formed thereon, and the single crystal Si formed thereon are formed.
Forming an SOI substrate having a layer, forming a gate insulating film on the surface of the single crystal Si layer, and forming a gate on the gate insulating film above the first pinhole and the second pinhole. Forming an electrode, implanting impurity ions into the single-crystal Si layer using the gate electrode as a mask, and annealing the single-crystal Si layer to form a diffusion layer of source / drain regions in the single-crystal Si layer And a step of performing

A method of manufacturing a semiconductor device according to the present invention is directed to a first method having a first insulating film formed on a supporting substrate, and a first pinhole and a second pinhole formed in the first insulating film. Preparing a second substrate having a second insulating film formed on the single crystal Si layer, and a third pinhole and a fourth pinhole formed in the second insulating film. And bonding the first insulating film and the second insulating film by aligning the first pinhole and the third pinhole and connecting the second pinhole and the fourth pinhole and bonding the first insulating film and the second insulating film. Forming an SOI substrate having an insulating film formed thereon and a single crystal Si layer formed thereon, forming a gate insulating film on the surface of the single crystal Si layer, Above, the first pinhole and the third pin Forming a gate electrode that is located above the Lumpur, single crystal S of the gate electrode as a mask
By implanting impurity ions into the i-layer and annealing the single-crystal Si layer, the diffusion layers of the source / drain regions located above the second pinhole and the fourth pinhole are formed in the single-crystal Si layer. And a step of forming.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

The semiconductor device has an SOI substrate 1, and the SOI substrate 1 has a support substrate 2 made of single crystal silicon,
An insulating film (BOX layer) 3 formed on the support substrate 2;
And a single-crystal Si layer 4 formed on the insulating film 3. The BOX layer 3 has a pinhole 3a located below the gate electrode 7, which will be described later. The inner diameter of the pinhole 3a is preferably about 1 to 10 nm.
The reason is that if the inner diameter is too large, the leak current becomes large, and if it is too small, holes cannot be efficiently extracted.

An element isolation film 5 is formed on the single crystal Si layer 4. The element isolation film 5 is located in an element isolation region on the BOX layer 3. P-type impurities are introduced into the single crystal Si layer 4. A gate oxide film 6 is formed on the surface of the single crystal Si layer 4.
Is formed, and a gate electrode 7 is formed on the gate oxide film 6. In the single-crystal Si layer, a low-concentration N-type diffusion layer 15 and N-type diffusion layers 16 and 17 in source / drain regions are formed.

Next, a method for manufacturing the semiconductor device will be described. First, an SOI substrate 1 is prepared. This SOI
The substrate 1 includes a support substrate 2 made of single crystal silicon, an insulating film (BOX layer) 3 formed on the support substrate 2, and a single crystal Si layer 4 formed on the insulating film 3. Have been. A pinhole 3a is formed in the BOX layer 3, and this pinhole 3a is located below the gate electrode described later. The SOI substrate 1 can be manufactured by various manufacturing methods.
It can also be manufactured by IMOX or the like. In the case of the bonding method, a silicon substrate having an insulating film on its surface is
A pinhole is formed in both insulating films in advance, and the two insulating films (BOX layer) 3 are pinned by aligning the two pinholes so that the two insulating films are bonded to each other. SOI substrate 1 having hole 3a
To manufacture.

Next, as shown in FIG.
A trench is formed on the entire surface including the inside of the trench.
A silicon oxide film is deposited by the VD method. Thereafter, the silicon oxide film existing on the single crystal Si layer 4 is removed by etch back or CMP (Chemical Mechanical Polishing) polishing. Thereby, the silicon oxide film is buried in the trench, and an element isolation film 5 made of the silicon oxide film is formed in the element isolation region on the BOX layer 3. Next, a P-type impurity is ion-implanted into the single-crystal Si layer 4.

Thereafter, a gate oxide film 6 is formed on the surface of the single crystal Si layer 4 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the gate oxide film 6 by a CVD method, and the polysilicon film is patterned to form a gate electrode 7 on the gate oxide film. The gate electrode 7 is located above the pinhole 3a.

Next, low concentration N-type impurity ions are implanted using the gate electrode 7 as a mask. Next, a silicon oxide film is deposited on the entire surface including the gate electrode 7 by the CVD method, and the silicon oxide film is etched over the entire surface, so that a sidewall 13 made of the silicon oxide film is formed on the side wall of the gate electrode 7. You.

Thereafter, N-type impurity ions are implanted using the side wall 13 and the gate electrode 7 as a mask.
The SOI substrate 1 is annealed. Thereby, the single crystal S
In the i-layer 4, a low-concentration N-type diffusion layer 15 and N-type diffusion layers 16 and 17 of source / drain regions are formed.

According to the first embodiment, the gate electrode 7 and the N-type diffusion layers 16 and 17 in the source / drain regions are formed.
Is formed on the SOI substrate 1 and the S
The BOX layer 3 of the OI substrate 1 is provided with a pinhole 3 a located below the gate electrode 7. Thereby, the substrate floating effect due to impact ionization in the SOI device can be efficiently suppressed. That is, the BOX layer 3
When the pinhole 3a is not provided, the single-crystal Si layer 4 is insulated from the support substrate 2, so that the minority carriers (holes) generated by the strong electric field of the drain, etc.
Although the threshold voltage fluctuates transiently in the layer, the threshold voltage fluctuates.
Holes generated in the layer due to impact ionization can be efficiently extracted from the pinhole 3a to the support substrate 2 side. Therefore, the lifetime of holes is shortened, the accumulation of holes in the single crystal Si layer can be suppressed, and the floating effect of the substrate can be suppressed.

In the present embodiment, the floating effect of the substrate is suppressed by providing the pin holes 3a in the BOX layer 3 as described above. Therefore, majority carriers, unlike the conventional semiconductor device described above, are not trapped by crystal defects in the source / drain regions. Further, the area occupied by devices such as the other conventional semiconductor devices described above does not increase.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. The same portions as those in FIG. 1 are denoted by the same reference numerals, and only different portions will be described.

The insulating film (BOX layer) 3 has a gate electrode 7
, And pin holes 3b and 3c located below the N-type diffusion layers 16 and 17 in the source / drain regions, respectively.

When an SOI substrate is manufactured by a bonding method, two silicon substrates having an insulating film on the surface are prepared, and pinholes are formed in both insulating films in advance, and a position is set so that both pinholes are connected. By bonding the two insulating films to each other, the SOI substrate 1 having the BOX layer 3 having the pinholes 3a to 3c is manufactured.

In the second embodiment, the same effects as those of the first embodiment can be obtained, and the BO
Since the pinholes 3a to 3c are partially formed in the X layer 3, the efficiency of extracting holes accompanying the impact ionization generated in the single crystal Si layer from the pinholes 3a to 3c to the support substrate 2 side can be further increased. .

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
The shape and size of the pinhole can be changed as appropriate.

[0038]

As described above, according to the present invention, a transistor including a gate electrode and a diffusion layer of a source / drain region is formed on an SOI substrate, and is located below the gate electrode in an insulating film of the SOI substrate. A pinhole is provided. Therefore, it is possible to provide a semiconductor device capable of sufficiently suppressing the substrate floating effect accompanying impact ionization in the SOI device while suppressing an increase in the area occupied by the SOI device, and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

3A and 3B are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

FIG. 4 is a plan view showing another conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 SOI substrate 2,102 Support substrate 3,103 Insulating film (BOX layer) 3a-3c Pinhole 4,104 Single crystal Si layer 5,105 Element isolation film 6,106 Gate oxide film 7,107 Gate electrode 13, 113 Side wall 15, 115 Low concentration N-type diffusion layer 16, 116 Source diffusion layer 17, 117 Drain diffusion layer 109 Ar ion 111 Damage layer 121 to 123 Body contact portion

Claims (5)

[Claims] An SOI substrate having a supporting substrate, an insulating film formed thereon and a single-crystal Si layer formed thereon, a gate insulating film formed on the surface of the single-crystal Si layer, A gate electrode formed on the insulating film; a diffusion layer of a source / drain region formed on a single-crystal Si layer below the side wall of the gate electrode; and a gate electrode formed on the insulating film. A semiconductor device comprising: a pinhole located below; 2. The semiconductor device according to claim 1, wherein a plurality of said pinholes are formed. 3. The method according to claim 1, wherein the source / source formed on the insulating film is
3. The semiconductor device according to claim 1, further comprising a pinhole located below the diffusion layer in the drain region. 4. A first insulating film formed on a supporting substrate,
Preparing a first substrate having a first pinhole formed in the first insulating film; a second insulating film formed on the single-crystal Si layer; and a second substrate formed on the second insulating film. A step of preparing a second substrate having two pinholes; and supporting the first and second insulating films by aligning the first and second pinholes so as to be connected to each other. Forming a SOI substrate having a substrate, an insulating film formed thereon and a single-crystal Si layer formed thereon, forming a gate insulating film on the surface of the single-crystal Si layer, Forming a gate electrode located above the first pinhole and the second pinhole on the film; implanting impurity ions into the single crystal Si layer using the gate electrode as a mask; By performing annealing, Crystal Si
Forming a diffusion layer of a source / drain region in a layer. 5. A first insulating film formed on a supporting substrate,
Preparing a first substrate having a first pinhole and a second pinhole formed in the first insulating film; a second insulating film formed on the single-crystal Si layer; and a second insulating film. Preparing a second substrate having a third pinhole and a fourth pinhole formed in the second substrate; and connecting the first and third pinholes to the second substrate.
By bonding the first insulating film and the second insulating film while aligning them so that the pinhole and the fourth pinhole are connected, the supporting substrate, the insulating film formed thereon, and the single crystal formed thereon A step of forming an SOI substrate having a Si layer; a step of forming a gate insulating film on the surface of the single-crystal Si layer; and a step of forming a gate insulating film over the first pinhole and the third pinhole. Forming a gate electrode; implanting impurity ions into the single crystal Si layer using the gate electrode as a mask; and annealing the single crystal Si layer to form the single crystal Si layer.
Forming a diffusion layer in the source / drain region located above the second pinhole and the fourth pinhole in the layer.