JP2002118267A - Method for fabricating semiconductor device and semiconductor device - Google Patents

Abstract

(57) [Problem] To achieve simultaneously a low capacitance and low on-resistance of a pin diode and a reduction in inductance of a package. SOLUTION: The pin diode 1 is mounted on a mounting substrate with bump electrodes 8 formed on the respective surfaces of ap ⁺ type diffusion layer 5 and an n ⁺ type diffusion layer 6, thereby realizing a reduction in the capacity of the pin diode 1. Further, pin by forming a p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6 as p ⁺ -type diffusion layer 5 and the n ⁺ -type distance W between the diffusion layer 6 is smaller
A low on-resistance of the diode 1 is realized. Furthermore, p ⁺
By reducing the product of the width D of the diffusion layer 5 and the n ⁺ -type diffusion layer 6 and the thickness t of the epitaxial layer (i-layer) 4, the capacitance of the pin diode 1 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for manufacturing a semiconductor device and a semiconductor device, and more particularly to a technique for manufacturing a semiconductor device having a pin junction structure and a technique effective when applied to the semiconductor device.

[0002]

2. Description of the Related Art In recent years, mobile communication terminals such as digital cellular phones have been rapidly becoming smaller, have lower power consumption, have higher frequencies, and have more multibands. Therefore, transmission of radio waves
For a pin diode used as an antenna switch module for switching reception, a reduction in capacity is required from the viewpoint of improving the off characteristic (separation characteristic). Further, from the viewpoint of improving the ON characteristics (insertion loss characteristics), a reduction in ON resistance is required. Further, from the viewpoint of improving the operation in a high frequency region in the GHz band, it is required to reduce the inductance of the package in which the pin diode is packaged.

In a pin diode, a back electrode of a vertical (planar or mesa) structure pin diode is bonded to a tab side of a lead frame, and a front electrode is connected to a post side of the lead frame by an Au (gold) wire or the like. After the wires are connected to each other, the outer peripheral portion of the vertical structure pin diode is molded with a resin.

In a pin diode, a p-layer and an n-layer are formed on the surface of an intrinsic layer (i-layer) grown on a main surface of a semiconductor substrate, and electrodes are formed on the p-layer and the n-layer. There is also a beam lead structure (horizontal structure) formed.

[0005] The above-mentioned pin diode is described in, for example, "(a) March 20, 1999, published by Nikkan Kogyo Shimbun Co., Ltd.," Dictionary of Semiconductor Terms ", p12.
3-p124, (b) Published by QC Publishing Co., Ltd., December 1, 1985, Joseph F. White, "Microwave Semiconductor Applied Engineering", p. 307 to p. 312, and the like.

[0006]

However, when the above-mentioned pin diode is considered from the viewpoints of low capacitance, low on-resistance, and reduction of package inductance, the present invention has the following problems. They found.

That is, the back electrode of the vertical pin diode is bonded to the tab side of the lead frame, and the front electrode is wire-connected to the post side of the lead frame by Au (gold) wire or the like. The technique of molding the outer periphery of the pin diode has a problem that it is difficult to reduce the package capacitance because the surface electrode and the lead frame are connected by wire and molded with resin. Further, since the inductance of the Au wire and the lead is large, there is a problem that the operation in a high frequency region is limited.

In a pin diode having a beam lead structure, electrodes are arranged in a lateral direction. for that reason,
The pin diode having the beam lead structure is different from the pin diode having the vertical (planar or mesa) structure.
There is a problem that on-resistance increases. As a result, since the on-resistance is increased, the insertion resistance is increased. When the pin diode having the beam lead structure is used as an antenna switch module of a digital mobile phone or the like, a problem such as noise or other signal distortion occurs. .

An object of the present invention is to provide a technique capable of simultaneously realizing low capacitance, low on-resistance, and low package inductance of a pin diode.

Another object of the present invention is to provide a technique capable of improving the operation of a pin diode in a high frequency range.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a step of forming a first insulating film by oxidizing a surface of a semiconductor substrate of a first conductivity type, and growing a first semiconductor layer made of an intrinsic semiconductor on the first insulating film. Forming a second insulating film by oxidizing the surface of the first semiconductor layer, forming a first masking layer on the surface of the second insulating film, and using the first masking layer as a mask. Selectively removing an unnecessary portion of the second insulating film, and introducing a first conductivity type impurity into the first semiconductor layer using the first masking layer as a mask, thereby forming a first conductivity type second impurity. Forming a second semiconductor layer and removing the first masking layer, forming a second masking layer on the surface of the second insulating film, and using the second masking layer as a mask to remove the second insulating film. Selectively remove parts Performing a second conductive type third semiconductor layer by introducing a second conductive type impurity into the first semiconductor layer using the second masking layer as a mask; Forming a first electrode on each surface of the second semiconductor layer and the third semiconductor layer after removing the film, wherein the second semiconductor layer and the third semiconductor layer are the first insulating film. , And the distance between the second semiconductor layer and the third semiconductor layer is formed to be a predetermined distance, and the opposing area of the second semiconductor layer and the third semiconductor layer is set to a predetermined distance. It is formed in the size of.

The present invention also provides (a) a first conductive type second semiconductor layer and a second conductive type third semiconductor layer on a surface of a first insulating film formed on a surface of a first conductive type semiconductor substrate. A first semiconductor layer made of an intrinsic semiconductor electrically connected to the first semiconductor layer and the second semiconductor layer and the third semiconductor layer; and (b)
A first electrode formed on each surface of the second semiconductor layer and the third semiconductor layer, wherein a distance between the second semiconductor layer and the third semiconductor layer is a predetermined distance; The facing area of the second semiconductor layer and the third semiconductor layer is a predetermined size.

According to the present invention, the semiconductor device has the second
Since the semiconductor device is mounted on the mounting substrate by the first electrodes formed on the respective surfaces of the third semiconductor layer of the conductivity type and the second semiconductor layer of the first conductivity type, the lead inductance of the semiconductor device can be reduced. .

Further, according to the present invention, since the on-resistance of the semiconductor device can be reduced, the on-characteristic (insertion loss characteristic) of the semiconductor device can be improved.

Further, according to the present invention, since the capacity of the semiconductor device can be reduced, the off characteristic (separation characteristic) of the semiconductor device can be improved.

Further, according to the present invention, the spread of the depletion layer in the first semiconductor layer of the semiconductor device can be structurally controlled, so that the deviation of the terminal capacitance of the semiconductor device can be reduced. It becomes possible.

Further, according to the present invention, since the lead inductance of the semiconductor device can be reduced, and the capacitance and the on-resistance of the semiconductor device can be reduced, the operation of the semiconductor device in a high frequency region can be improved. Becomes

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

The semiconductor device of the present embodiment is, for example, a pin diode 1 as shown in FIG.

As shown in FIG. 1A, a pin diode (semiconductor device) 1 of the present embodiment has an insulating film (first insulating type) formed on the surface of an n-type (first conductivity type) semiconductor substrate 2. Intrinsic epitaxial layer (i layer (first semiconductor layer)) 4 grown on film 3) and p ⁺ type (second conductivity type)
A horizontal pin junction is formed by the diffusion layer (third semiconductor layer) 5 and the n ⁺ type (first conductivity type) diffusion layer (second semiconductor layer) 6. Further, the p ⁺ type diffusion layer 5 and n ⁺
Type diffusion layer 6 has a thickness t of epitaxial layer (i-layer) 4.
Is diffused to a depth that reaches.

On the surface of the epitaxial layer (i-layer) 4,
A surface protection film (second insulating film) 7 formed by oxidizing the surface of the epitaxial layer (i-layer) 4 is formed. Further, as shown in FIG. 1B, the n ⁺ -type guard ring layer 6A is formed so as to surround the surface protective film 7 on a plane.

As shown in FIGS. 1 (a) and 1 (b), the pin diode 1 of the present embodiment is provided on the surface of each of the above-mentioned p ⁺ -type diffusion layer 5 and n ⁺ -type diffusion layer 6. A bump electrode (first electrode) 8 is formed. Since the pin diode 1 is mounted on a mounting substrate (not shown) with the bump electrode 8, a lead in the vertical pin diode and an Au wire for electrically wire-connecting the surface electrode and the lead are required. do not do. In the vertical type pin diode, the inductance of the lead and the Au wire is large. However, in the pin diode 1 of the present embodiment, the inductance of the lead and the Au wire is not used because the lead and the Au wire are not used. (Lead inductance) becomes the same state as when it becomes zero. That is, p in the present embodiment
When the in-diode 1 is used as an antenna switch module for switching between transmission and reception of radio waves, it is possible to improve the operation in a high frequency region of a GHz band or more in a wide band. Note that, regarding the antenna switching circuit configured using the pin diode 1 of the present embodiment,
This will be described later with reference to FIG.

Further, the pin diode 1 of the present embodiment
, The distance W between the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6
, The on-resistance can be made smaller than that of the pin diode having the beam lead structure. As a result, the ON characteristic (insertion loss characteristic) of the pin diode 1
Can be improved more than the ON characteristic of the pin diode having the beam lead structure.

The p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6
Of the width D and the thickness t of the epitaxial layer (i-layer) 4 (the opposing areas of the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6)
Is reduced, the junction capacitance between p ⁺ -type diffusion layer 5 and n ⁺ -type diffusion layer 6 can be reduced. further,
In the case of the pin diode 1, for example, molding with resin is not performed.
Package capacity can be reduced. As a result, the capacitance of the pin diode 1 can be reduced.
Can be improved in the off characteristic (separation degree characteristic).

Further, as shown in FIG. 1, the pin diode of the present embodiment has a structure in which the pin diode is formed on the insulating film 3. Therefore, it is possible to structurally control the expansion of the depletion layer in the epitaxial layer (i-layer) 4. As a result, the deviation of the terminal capacitance of the pin diode 1 can be reduced.

When the pin diode 1 of the present embodiment is used as an antenna switch module, the operating frequency of the pin diode 1 is f, and
Assuming that the inductance of the diode 1 is L and the capacitance of the pin diode 1 is C, it is expressed by Expression 1.

[0029]

(Equation 1)

As shown in Equation 1, the smaller the product of the inductance L and the capacitance C, the higher the operating frequency f of the pin diode 1 becomes. As described above, the pin diode 1 of the present embodiment does not use an Au wire or the like that electrically connects the lead and the surface electrode to the lead by wire. It can be reduced by the minute. Further, the junction capacitance between the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6 can be reduced, and the package capacitance of the pin diode 1 can be reduced.
The capacitance of the entire diode 1 can be reduced. As a result, in Equation 1, the inductance L and the capacitance C
And the product of the inductance L and the capacitance C also decreases. That is, the pin diode 1 of the present embodiment
In the case of, the product of the inductance L and the capacitance C is also small, so that the operating frequency f is large. That is, since the operating frequency f of the pin diode 1 increases, the operation of the pin diode 1 in a high-frequency region can be improved.

The present inventor has proposed a vertical structure pin diode,
Experiments were conducted on the beam lead type pin diode and the pin diode 1 of the present embodiment, and the capacitance, lead inductance, and on-resistance were examined. As a result, as shown in Table 1, it was found that the pin diode 1 of the present embodiment had a lower capacity than the vertical pin diode and could be equivalent to the beam lead pin diode. Further, since the pin diode 1 does not use a lead like the beam lead type pin diode, it was found that the lead inductance was zero. Further, it was found that the on-resistance of the pin diode 1 was lower than that of the beam lead type pin diode, and could be equivalent to that of the vertical structure pin diode. That is, it can be confirmed from experimental values that the pin diode 1 of the present embodiment can achieve lower capacitance, lower on-resistance, and lower lead inductance than the vertical pin diode and the beam lead pin diode. It was confirmed from the experimental values that the operation in the high frequency region of No. 1 can be improved.

[0032]

[Table 1]

Next, FIG. 2 shows that p of the present embodiment described above.
FIG. 3 shows a circuit diagram when the in-diode 1 is used in an antenna switching circuit.

In the antenna switching circuit shown in FIG. 2, the antenna connected to the terminal ANT is shared by a transmitting circuit (not shown) connected to the terminal TX and a receiving circuit (not shown) connected to the terminal RX. ing.

The antenna switching circuit shown in FIG.
, The switching current is input from the terminal VC and the pin
Turn on Ide 1 Also microstrip wire
Road Z ₀Indicates the impedance with the receiving circuit during reception.
The same as the antenna impedance so that
And the line length is about 1/4 of the transmission wavelength.
To do. When receiving, turn off the input from terminal VC.
To turn off the replacement current and turn off the pin diode 1
Thus, the transmission circuit is separated from the antenna.

Next, a method of manufacturing the above-described pin diode according to the present embodiment will be described in the order of steps with reference to FIGS.

FIG. 3 is a flowchart showing an example of a method for manufacturing the above-described pin diode of the present embodiment.

First, in step P1, the n-type semiconductor substrate 2
Is oxidized to form an insulating film 3 (FIG. 4).

Next, in step P2, an intrinsic epitaxial layer (i-layer) 4 is formed on the insulating film 3 (FIG. 5). Subsequently, in step P3, the surface of the above-described epitaxial layer (i-layer) 4 is oxidized to form a surface protective film 7 (FIG. 6).

Next, in step P4, a photoresist film (first masking layer (not shown)) is formed on the surface of the surface protection film 7 by photolithography. At this time, the photoresist film forms an n ⁺ type diffusion layer 6 described later.
And, the surface of the surface protection film 7 in the region where the n ⁺ -type guard ring layer 6A is formed is exposed. continue,
The surface protective film 7 is etched using the photoresist film as a mask, and an opening is formed in the surface protective film 7 for forming the n ⁺ -type diffusion layer 6 and the n ⁺ -type guard ring layer 6A (FIG. 7).

Next, in step P5, the epitaxial layer (i-layer) 4 is formed using the photoresist film as a mask.
Is doped with an n-type impurity (for example, P (phosphorus)). Subsequently, heat treatment is performed on the n-type semiconductor substrate 2 to thermally diffuse the n-type impurities, thereby forming the n ⁺ -type diffusion layer 6 and the n ⁺ -type guard ring layer 6A (FIG. 8). At this time, as described above with reference to FIG. 1, the n ⁺ -type diffusion layer 6
And n ⁺ -type guard ring layer 6A is diffused to a depth reaching the thickness of epitaxial layer (i-layer) 4.

Next, the above-mentioned photoresist film is removed.
After that, in step P6, the surface of the
A photoresist film (second mask
Forming layer (not shown). At this time,
The photoresist film is formed by p ⁺Mold diffusion layer 5 is formed
It is formed such that the surface of the surface protection film 7 in the region is exposed.
Next, use the photoresist film as a mask to protect the surface.
The film 7 is etched, and p⁺Type diffusion layer 5
An opening for formation is made (FIG. 9).

Next, in step P7, the epitaxial layer (i-layer) 4 is formed using the photoresist film as a mask.
Is doped with a p-type impurity (for example, B (boron)). Subsequently, heat treatment is performed on the n-type semiconductor substrate 2 to thermally diffuse the p-type impurities, thereby forming the p ⁺ -type diffusion layer 5 (FIG. 10). At this time, as described above with reference to FIG. 1, the p ⁺ type diffusion layer 5 is formed as an epitaxial layer (i-layer).
4 to a depth reaching the thickness of 4.

[0044] In forming the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6 as described above is described above with reference to FIG. 1, the interval W between the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6 Is reduced, the on-resistance of pin diode 1 of the present embodiment can be reduced. As a result, the ON characteristics (insertion loss characteristics) of the pin diode 1 can be improved. The width D of the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6
And the thickness t of the epitaxial layer (i-layer) 4 can reduce the junction capacitance between the p ⁺ -type diffusion layer 5 and the n ⁺ -type diffusion layer 6.

Next, in step P8, the exposed p
Bump electrode 8 is formed on each surface of ⁺ type diffusion layer 5 and n ⁺ type diffusion layer 6. Subsequently, by separating the n-type semiconductor substrate 2 into individual semiconductor chips by dicing, the pin diode 1 of the present embodiment shown in FIG.
Is manufactured (step P9).

As described above with reference to FIG. 1, the pin diode 1 of the present embodiment is mounted on a mounting substrate with the bump electrodes 8 formed in the above-described step P8. That is, in the pin diode 1, the lead for mounting on the mounting substrate and the Au wire for electrically connecting the surface electrode of the pin diode and the lead are not used, so that the inductance (lead) of the lead and the Au wire is not used. (Inductance) becomes zero.

Further, as described above with reference to FIG. 1, the pin diode 1 of the present embodiment is mounted on a mounting board in a state of being separated into individual semiconductor chips in the above-described process P9. That is, since the pin diode 1 is not molded with resin, for example, the package capacity of the pin diode 1 can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, n
An example in which an insulating film is formed by oxidizing the surface of a die-shaped semiconductor substrate and an intrinsic epitaxial layer is formed on the insulating film, but a sapphire insulating substrate (insulating substrate) is used. An intrinsic epitaxial layer may be formed thereon.

[0050]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) According to the present invention, the pin diode is mounted on the mounting substrate by the bump electrodes formed on the respective surfaces of the p ⁺ -type diffusion layer and the n ⁺ -type diffusion layer, so that the lead inductance of the pin diode is reduced. be able to. (2) According to the present invention, since the ON resistance of the pin diode can be reduced, the ON characteristics (insertion loss characteristics) of the pin diode can be improved. (3) According to the present invention, since the capacity of the pin diode can be reduced, the off characteristic (isolation characteristic) of the pin diode can be improved. (4) According to the present invention, the spread of the depletion layer in the epitaxial layer (i-layer) of the pin diode can be structurally controlled, so that the deviation of the terminal capacitance of the pin diode can be reduced. (5) According to the present invention, the lead inductance of the pin diode can be reduced, and the capacitance and the on-resistance of the pin diode can be reduced, so that the operation of the pin diode in a high-frequency region can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are a main part cross-sectional view and a main part plan view of a semiconductor device according to an embodiment of the present invention, respectively.

FIG. 2 is a circuit diagram of an antenna switching circuit configured using the semiconductor device of the present invention.

FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;

7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;

[Explanation of symbols]

Reference Signs List 1 pin diode (semiconductor device) 2 n-type (first conductivity type) semiconductor substrate 3 insulating film (first insulating film) 4 epitaxial layer (i-layer (first semiconductor layer)) 5 p ⁺ type (second conductivity type) Diffusion layer (third semiconductor layer) 6 n ⁺ -type (first conductivity type) diffusion layer (second semiconductor layer) 6A n ⁺ -type guard ring layer 7 Surface protective film (second insulating film) 8 Bump electrode (first electrode) ) ANT terminal Dp ⁺ -type diffusion layer 5 and width of n ⁺ -type diffusion layer 6 P1 to P9 Step RX terminal t Thickness of epitaxial layer (i-layer) 4 TX terminal VC terminal Wp ⁺ -type diffusion layer 5 and n ⁺ Distance from Diffusion Layer 6 Z ₀ Microstrip Line

Claims (4)

[Claims] 1. A step of forming a first insulating film by oxidizing a surface of a semiconductor substrate of a first conductivity type, and
Growing a first semiconductor layer made of an intrinsic semiconductor on the first insulating film; (c) forming a second insulating film by oxidizing a surface of the first semiconductor layer; and (d) forming the second insulating film. Forming a first masking layer on the surface of the insulating film, and selectively removing unnecessary portions of the second insulating film using the first masking layer as a mask; (e) using the first masking layer as a mask, Forming a second semiconductor layer of the first conductivity type by introducing an impurity of the first conductivity type into the first semiconductor layer; (f) removing the first masking layer, Forming a second masking layer on the surface, and selectively removing unnecessary portions of the second insulating film using the second masking layer as a mask;
Using the masking layer as a mask, a second layer is formed on the first semiconductor layer.
Forming a third semiconductor layer of the second conductivity type by introducing impurities of the conductivity type; and (h) removing the second insulating film, and then forming the second semiconductor layer and the third semiconductor layer, respectively. Forming a first electrode on the surface of the semiconductor device, wherein the second semiconductor layer and the third semiconductor layer are formed to a depth reaching the first insulating film, and the second semiconductor layer and the third
A method for manufacturing a semiconductor device, comprising: forming an interval between the semiconductor layer and the semiconductor layer so as to be a predetermined distance; and forming an area where the second semiconductor layer and the third semiconductor layer face each other with a predetermined size. (A) growing a first semiconductor layer made of an intrinsic semiconductor on an insulating substrate; (b) forming a second insulating film by oxidizing a surface of the first semiconductor layer; (C) forming a first masking layer on the surface of the second insulating film, and selectively removing unnecessary portions of the second insulating film using the first masking layer as a mask; (d) the first masking Forming a second semiconductor layer of the first conductivity type by introducing impurities of the first conductivity type into the first semiconductor layer using the layer as a mask; (e) removing the first masking layer; Forming a second masking layer on the surface of the second insulating film, and selectively removing unnecessary portions of the second insulating film using the second masking layer as a mask; (f) masking the second masking layer with a mask As a second conductive layer in the first semiconductor layer. Forming a third semiconductor layer of the second conductivity type by introducing a conductivity type impurity, (g).
Forming a first electrode on a surface of each of the second semiconductor layer and the third semiconductor layer after removing the second insulating film, wherein the second semiconductor layer and the third semiconductor layer are The second substrate is formed at a depth reaching the insulating substrate;
The distance between the semiconductor layer and the third semiconductor layer is formed to be a predetermined distance, and the facing areas of the second semiconductor layer and the third semiconductor layer are formed to have a predetermined size. A method for manufacturing a semiconductor device. 3. A first conductive type second semiconductor layer, a second conductive type third semiconductor layer, and the second semiconductor layer on a surface of a first insulating film formed on a surface of the first conductive type semiconductor substrate. A first semiconductor layer made of an intrinsic semiconductor electrically connected to the first semiconductor layer and the third semiconductor layer, and a first electrode formed on a surface of each of the second semiconductor layer and the third semiconductor layer. Wherein a distance between the second semiconductor layer and the third semiconductor layer is a predetermined distance, and a facing area of the second semiconductor layer and the third semiconductor layer is a predetermined size. Semiconductor device. 4. A first semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, and an intrinsic junction electrically connected to the second semiconductor layer and the third semiconductor layer on a surface of the insulating substrate. A semiconductor device in which a first semiconductor layer made of a semiconductor is formed, and a first electrode is formed on each surface of the second semiconductor layer and the third semiconductor layer, wherein the second semiconductor layer and the third semiconductor layer are formed. The distance from the layer is a predetermined distance,
The semiconductor device according to claim 1, wherein a facing area of the semiconductor layer and the third semiconductor layer is a predetermined size.